Chapter-1 Sequential logic circuits

A Sequential circuit is a combinational logic circuit that consists of inputs variable (X),
logic gates (Computational circuit), and output variable (Z).

A combinational circuit produces an output based on input variable only, but a Sequential
circuit produces an output based on current input and previous input variables. That means
sequential circuits include memory elements that are capable of storing binary information.
That binary information defines the state of the sequential circuit at that time.

A latch capable of storing one bit of information.

As shown in the figure there are two types of input to the combinational logic :
1. External inputs are which not controlled by the circuit.
2. Internal inputs are which a function of a previous output states are.

Secondary inputs are state variables produced by the storage elements, whereas secondary
outputs are excitations for the storage elements.

1. Latch

A Latch is a special type of logical circuit. The latches have low and high two stable states.
Due to these states, latches also refer to as bistable-multivibrators. A latch is a storage device
that holds the data using the feedback lane. The latch stores 1 -bit until the device set to 1.
The latch changes the stored data and constantly trials the inputs when the enable input set to
1.
Based on the enable signal, the circuit works in two states. When the enable input is high,
then both the inputs are low, and when the enable input is low, both the inputs are high.

Types of Latches

There are various types of latches used in digital circuits which are as follows:

 SR Latch
 Gated S-R Latch
 D latch
 Gated D Latch
 JK Latch
 T Latch.

i. SR Latch

The SR latch is a special type of asynchronous device which works separately for control
signals. It depends on the S-states and R-inputs. The SR latch design by connecting
two NOR gates with a cross loop connection. The SR latch can also be designed using
the NAND gate.

Block diagram Truth Table

ii. Gated SR Latch

A Gated SR Latch is a special type of SR Latch having three inputs, i.e., Set, Reset, and
Enable. The enable input must be active for the SET and RESET inputs to be effective.
The ENABLE input of gated SR Latch enables the operation of the SET and RESET
inputs. This ENABLE input connects with a switch. The Set-Reset inputs are enabled
when this switch is on. Otherwise, all the changes are ignored in the set and reset inputs.
Below are the circuit diagram and the truth table of the Gated SR latch.

Block diagram Truth Table

iii. D Latch

The only difference between these two is the ENABLE input. The output of the latch is the
same as the input passed to the Data input when the ENABLE input set to 1. At that time,
the latch is open, and the path is transparent from input to output. If the ENABLE input is
set to 0, the D latch's output is the last value of the latch, i.e., independent from the input
D, and the latch is closed. Below are the circuit diagram and the truth table of the D latch.

Block diagram Truth Table

iv. Gated D Latch

The Gated D Latch is another special type of gated latch having two inputs, i.e., DATA
and ENABLE. When the enable input set to 1, the input is the same as the Data input.
Otherwise, there is no change in output.

We can design the gated D latch by using gated SR latch. The set and reset inputs are
connected together using an inverter. By doing this, the outputs will be opposite to each
other. Below is the circuit diagram of the Gated D latch.

Circuit Diagram
 v. JK Latch

The JK Latch is the same as the SR Latch. In JK latch, the unclear states are removed, and
the output is toggled when the JK inputs are high. The only difference between SR latch
JK latches is that there is no output feedback towards the inputs in the SR latch, but it is
present in the JK latch. The circuit diagram and truth table of the JK latch are as follows:

Block diagram Truth Table

vi. T Latch

The T latch forms by shorting the JK latch inputs. The output of the T latch toggle when
the input set to 1 or high. Below is the circuit diagram of the T latch.

Circuit Diagram

2. Flip-flops
Flip flop is a sequential circuit which generally samples its inputs and changes its outputs
only at particular instants of time and not continuously. Flip flop is said to be edge sensitive
or edge triggered rather than being level triggered like latches.
 S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also called
as level triggered SR-FF. For this, circuit in output will take place if and only if the enable
input (E) is made active. In short this circuit will operate as an S-R latch if E = 1 but there
is no change in the output if E = 0.

Block diagram Truth Table

Operation

Condition Operation
S = R = 0 : No If S = R = 0 then output of NAND gates 3 and 4 are forced to
change become 1.
Hence R' and S' both will be equal to 1. Since S' and R' are the
input of the basic S-R latch using NAND gates, there will be no
change in the state of outputs.
S=0 Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of
R=1 NAND-4 i.e. S' = 0.
E=1 Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
S=1 Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.
R=0 Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0.
E=1 This is the reset condition.
S=1 As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both
R=1 are 0 i.e. S' = R' = 0.
E=1 Hence the Race condition will occur in the basic NAND latch.

 Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of second
to input of first. Master is a positive level triggered. But due to the presence of the inverter
in the clock line, the slave will respond to the negative level. Hence when the clock = 1
(positive level) the master is active and the slave is inactive. Whereas when clock = 0
(low level) the slave is active and master is inactive.
 Block diagram Truth Table

Operation

Condition Operation
J=K=0 When clock = 0, the slave becomes active and master is
(No change) inactive. But since the S and R inputs have not changed, the
slave outputs will also remain unchanged. Therefore outputs
will not change if J = K =0.
J=0 Clock = 1 − Master active, slave inactive. Therefore outputs of
K=1 the master become Q1 = 0 and Q1 bar = 1. That means S = 0 and
(Reset) R =1.
Clock = 0 − Slave active, master inactive. Therefore outputs of
the slave become Q = 0 and Q bar = 1.
Again clock = 1 − Master active, slave inactive. Therefore even
with the changed outputs Q = 0 and Q bar = 1 fed back to
master, its output will be Q1 = 0 and Q1 bar = 1. That means S
= 0 and R = 1.
Hence with clock = 0 and slave becoming active the outputs of
slave will remain Q = 0 and Q bar = 1. Thus we get a stable
output from the Master slave.
J=1 Clock = 1 − Master active, slave inactive. Therefore outputs of
K=0 the master become Q1 = 1 and Q1 bar = 0. That means S = 1 and
(Set) R =0.
Clock = 0 − Slave active, master inactive. Therefore outputs of
the slave become Q = 1 and Q bar = 0.
Again clock = 1 − then it can be shown that the outputs of the
slave are stabilized to Q = 1 and Q bar = 0.
J=K=1 Clock = 1 − Master active, slave inactive. Outputs of master will
(Toggle) toggle. So S and R also will be inverted.
Clock = 0 − Slave active, master inactive. Outputs of slave will
toggle.
These changed output are returned back to the master inputs.
But since clock = 0, the master is still inactive. So it does not
respond to these changed outputs. This avoids the multiple
toggling which leads to the race around condition. The master
slave flip flop will avoid the race around condition.
  Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter
connected between S and R inputs. It has only one input. The input data is appearing at
the output after some time. Due to this data delay between i/p and o/p, it is called delay
flip flop. S and R will be the complements of each other due to NAND inverter. Hence S
= R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by
SR = 00 and SR = 1 conditions.
Block diagram Truth Table

Operation

Condition Operation
E=0 Latch is disabled. Hence no change in output.
E=1 If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the
D=0 present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the
reset condition.
E=1 If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch
D=1 and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.

 Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected
together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for
positive edge triggered T flip flop is shown in the Block Diagram.

Block diagram Truth Table

 Operation

Condition Operation
T=0 The output Q and Q bar won't change
J=K=0
T=1 Output will toggle corresponding to every leading edge of clock
J=K=1 signal.

3. Race around condition

Before getting into the race around condition, have a look at the JK flip-flop’s truth table.

Clock Input Inputs Outputs Comments

J K Q Q’
0 X X Same as previous Same as previous No change
1 0 0 Same as previous Same as previous No change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Opposite of previous Opposite of previous Toggle

Here, Q is the present state and Q’ is the next state. As you can see, when J, K and Clock are
equal to 1, toggling takes place, i.e. The next state will be equal to the complement of the
present state.

Now, let us look at the timing diagram of JK flip-flop.

Here, T is the time period of the clock whereas delta t is the propagation delay. The delay
between input and output is called a propagation delay.

This is what was expected, but the output may not be like this all the time. This is
where Race around condition comes into the play.
Let us look at the timing diagram of JK flip-flop when the race around condition is
considered.

As you already know, when J, K and Clock are equal to 1, toggling takes place. Here,
propagation delay has also been reduced, so the output will be given out at the instant input is
given. So there is a toggling again. Therefore, whenever Clock is equal to 1 there are
consecutive toggling. This condition is called as Race around condition. To put it in words,
“For JK flip-flop if J, K and Clock are equal to 1 the state of flip-flop keeps on toggling
which leads to uncertainty in determining the output of the flip-flop. This problem is called
Race around the condition. “’ This condition also exists in T flip-flop since T flip-flop also
has toggling options.

Methods to eliminate race around condition

There are three methods to eliminate race around condition as described below:

i. Increasing the delay of flip-flop

The propagation delay (delta t) should be made greater than the duration of the clock
pulse (T). But it is not a good solution as increasing the delay will decrease the speed of
the system.

ii. Use of edge-triggered flip-flop

If the clock is High for a time interval less than the propagation delay of the flip flop then
racing around condition can be eliminated. This is done by using the edge-triggered flip
flop rather than using the level-triggered flip-flop.

iii. Use of master-slave JK flip-flop

If the flip flop is made to toggle over one clock period then racing around condition can
be eliminated. This is done by using Master-Slave JK flip-flop.