Classical and Modern Control Design
Uploaded by
Bahaa ElassyClassical and Modern Control Design
Uploaded by
Bahaa ElassyClassical and Modern Control Design:
with examples from power electronics
Richard Tymerski
Portland State University
Department of Electrical and Computer Engineering
Portland, Oregon, USA
Frank Rytkonen
Oregon Institute of Technology
Department of Electrical Engineering and Renewable Energy
Wilsonville, Oregon, USA
Acknowledgements
The authors would like to express their sincere gratitude to a number of for-
mer students who have greatly contributed to making this book possible. Of
particular note, Clint Lieser and Andrew Chuinard ... (To be expounded upon.)
ii © Richard Tymerski and Frank Rytkonen, 2017
Preface
This is the preface.
iii
iv © Richard Tymerski and Frank Rytkonen, 2017
Contents
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
I Classical Control: Fundamentals 1
1 Introduction 3
1.1 Basic Feedback Con guration . . . . . . . . . . . . . . . . . . . . 3
1.2 Stability - Absolute and Relative . . . . . . . . . . . . . . . . . . 4
1.3 Stability Analysis Example . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 Matlab Code . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 System Stability 15
2.1 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Stability Analysis by Inspection . . . . . . . . . . . . . . . . . . . 15
2.2.1 Parameterized Stability Analysis by Inspection . . . . . . 16
2.2.2 Examples of Stability Analysis by Inspection . . . . . . . 16
2.3 Routh-Hurwitz Analysis . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 Zero in First Column . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 A Row of Zeros . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.3 Parameterized Routh-Hurwitz Analysis . . . . . . . . . . 21
3 Steady State Error 23
3.1 Unity gain feedback . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Example 1: . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 Non-Unity Feedback . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.1 Example 2: . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.2 Example 3: . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.3 Example 4: . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2.4 Example 5: . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.5 Example 6: . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.6 Example 7: . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.7 Example 8: . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3 Note: partial fraction containing a complex pole pair . . . . . . . 58
v
4 Bode Plots 59
4.1 Simple Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 Pole at Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3 Zero at Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4 Pole at ωo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.5 Zero at ωo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.6 Right Half Plane Zero at ωo . . . . . . . . . . . . . . . . . . . . . 63
4.7 Complex Pole Pair with Resonant Frequency at ωo . . . . . . . . 63
4.8 Complex Zero Pair with Resonant Frequency at ωo . . . . . . . . 64
4.9 Composite Transfer Functions . . . . . . . . . . . . . . . . . . . . 65
4.10 Summary of Bode Plots . . . . . . . . . . . . . . . . . . . . . . . 70
5 Compensator Design 73
5.1 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.1.2 Uncompensated System . . . . . . . . . . . . . . . . . . . 74
5.1.3 Proportional Compensated System . . . . . . . . . . . . . 78
5.1.4 Dominant Pole Compensated System . . . . . . . . . . . . 80
5.1.5 Dominant Pole Compensated System with zero . . . . . . 82
5.1.6 Dominant Pole Compensated System with zero, improved
phase margin . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.1.7 Lead Compensated System . . . . . . . . . . . . . . . . . 85
5.1.8 Lead Compensated System with integrator and zero . . . 87
5.1.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.10 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . 103
II Classical Control: Application 109
6 Modelling - Introduction 111
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7 The System 113
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.2 The Plant: Buck Converter . . . . . . . . . . . . . . . . . . . . . 114
7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.2.2 Transfer Function Derivations . . . . . . . . . . . . . . . . 114
7.3 Pulse-width Modulator . . . . . . . . . . . . . . . . . . . . . . . . 122
7.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8 Single Loop Voltage Mode Control 127
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2 Buck Converter System Models . . . . . . . . . . . . . . . . . . . 128
8.2.1 General Model . . . . . . . . . . . . . . . . . . . . . . . . 128
8.2.2 Simpli ed System Model . . . . . . . . . . . . . . . . . . . 128
8.2.3 Design Targets . . . . . . . . . . . . . . . . . . . . . . . . 129
vi © Richard Tymerski and Frank Rytkonen, 2017
8.2.4 Buck Converter Model Analysis . . . . . . . . . . . . . . . 129
8.3 Uncompensated System . . . . . . . . . . . . . . . . . . . . . . . 130
8.4 Dominant Pole Compensation . . . . . . . . . . . . . . . . . . . . 134
8.5 Dominant Pole Compensation with Zero . . . . . . . . . . . . . . 142
8.6 Lead Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 146
8.7 Dominant Pole with Lead Compensation . . . . . . . . . . . . . . 151
8.7.1 Design 1: Zero f1 = 500Hz . . . . . . . . . . . . . . . . . 153
8.7.2 Design 2: Zero f1 = 150 Hz . . . . . . . . . . . . . . . . . 156
8.8 Extended Bandwidth Design . . . . . . . . . . . . . . . . . . . . 158
8.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
8.9.1 Compensator Circuits . . . . . . . . . . . . . . . . . . . . 170
8.10 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9 Droop and Multi-Loop Control 175
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
9.2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
9.2.1 Passive Droop Compensation . . . . . . . . . . . . . . . . 176
9.2.2 Active Droop Compensation . . . . . . . . . . . . . . . . . 183
9.2.3 Voltage Mode Compensation . . . . . . . . . . . . . . . . 188
9.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
9.4 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
III Classical Control: Laboratory 211
10 Introduction to the Labs 213
11 Lab 1 217
11.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.2 Circuit #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.2.1 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
11.3 Circuit #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
11.3.1 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.4 Circuit #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.4.1 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
12 Lab 2 223
12.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
12.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
12.3 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
12.3.1 PECS simulation . . . . . . . . . . . . . . . . . . . . . . . 226
12.3.2 Matlab simulation results check . . . . . . . . . . . . . . 227
© Richard Tymerski and Frank Rytkonen, 2017 vii
13 Lab 3 231
13.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
13.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
13.3 System Transfer Functions . . . . . . . . . . . . . . . . . . . . . . 234
13.4 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
13.5 Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
13.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
13.7 Postscript . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
14 Lab 4 249
14.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14.3 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
14.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
14.5 Notes - Buck converter components: . . . . . . . . . . . . . . . . 256
15 Lab 5 257
15.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
15.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
15.3 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
15.3.1 Pre-Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
15.3.2 In the Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
15.3.3 Post-Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
15.4 Optional Tasks - Alternative compensators . . . . . . . . . . . . 266
15.4.1 Proportional Control . . . . . . . . . . . . . . . . . . . . . 266
15.4.2 Lead Control . . . . . . . . . . . . . . . . . . . . . . . . . 266
15.5 Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
16 Lab 6 269
16.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
16.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
16.3 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
16.3.1 Pre-Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
16.3.2 In the Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
16.3.3 Post-Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Appendix A List of Parts 277
Appendix B Lab Grading Sheets 279
IV Modern Control 291
17 Introduction 293
viii © Richard Tymerski and Frank Rytkonen, 2017
18 System Analysis 297
18.1 The uk Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 297
18.2 The uk Converter Model . . . . . . . . . . . . . . . . . . . . . . 299
18.2.1 Analysis of Inductors with Mutual Coupling
and Equivalent Series Resistances . . . . . . . . . . . . . . 299
18.2.2 The State Space Averaged Model . . . . . . . . . . . . . . 300
18.2.3 Component Values . . . . . . . . . . . . . . . . . . . . . . 303
18.3 uk Converter Open Loop Performance . . . . . . . . . . . . . . 303
18.4 Controllability and Stabilizability . . . . . . . . . . . . . . . . . . 307
18.5 Observability and Detectability . . . . . . . . . . . . . . . . . . . 307
18.6 Controlling the uk Converter . . . . . . . . . . . . . . . . . . . 308
18.6.1 Time Domain Speci cations . . . . . . . . . . . . . . . . . 308
18.6.2 Frequency Domain Speci cations . . . . . . . . . . . . . . 308
18.6.3 Control Eort Constraints . . . . . . . . . . . . . . . . . . 309
18.7 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
19 Pole Placement 315
19.1 Pole Placement via Ackermann's Formula . . . . . . . . . . . . . 316
19.2 uk Converter with State Feedback Compensator . . . . . . . . . 316
19.3 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
20 Integral Action 325
20.1 Adding Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . 325
20.2 uk Converter with State Feedback and Integral Compensator . 327
20.3 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
21 State Estimation 333
21.1 Full-Order State Estimators . . . . . . . . . . . . . . . . . . . . . 333
21.2 Full-Order Estimator-Based Compensator . . . . . . . . . . . . . 334
21.3 Reduced-Order State Estimators . . . . . . . . . . . . . . . . . . 338
21.4 Reduced-Order Estimator-Based Compensator . . . . . . . . . . 341
21.5 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
22 Linear Quadratic Optimal Control 353
22.1 Linear Quadratic Regulators . . . . . . . . . . . . . . . . . . . . 353
22.2 uk Converter with LQR Compensator . . . . . . . . . . . . . . 354
22.3 Linear Quadratic Gaussian Regulators . . . . . . . . . . . . . . . 357
22.4 uk Converter with LQG Compensator . . . . . . . . . . . . . . 358
22.5 Control with LQG/LTR Compensators . . . . . . . . . . . . . . . 360
22.6 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
23 Compensator Order Reduction 369
23.1 Model Reduction of the LQGI/LTR Compensator . . . . . . . . 369
23.2 A Reduced-Order LQGI/LTR Compensator . . . . . . . . . . . . 373
23.3 MATLAB Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
© Richard Tymerski and Frank Rytkonen, 2017 ix
24 Compensator Implementation 385
24.1 MRLQGI/LTR Compensator Construction . . . . . . . . . . . . 385
24.2 MRROLQGI/LTR Compensator Construction . . . . . . . . . . 386
25 Power Electronic Circuit Simulation 391
25.1 Simulating the Controlled uk Converter in PECS . . . . . . . . 391
26 Conclusion 395
Appendix C PECS 397
C.1 PECS Overall Description . . . . . . . . . . . . . . . . . . . . . . 397
C.2 PECS Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
C.2.1 Building a circuit schematic in PECS . . . . . . . . . . . 398
C.2.2 Setting simulation parameters . . . . . . . . . . . . . . . . 400
C.2.3 Running the simulation . . . . . . . . . . . . . . . . . . . 401
C.2.4 Selecting the desired output(s) to plot . . . . . . . . . . . 401
C.3 Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
C.3.1 Basic passive elements: R (resistor), C (capacitor) and L
(inductor) . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
C.3.2 Sources: VDC (DC voltage), IDC (DC current), VAC (AC
voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
C.3.3 Ports: Vport (voltage port) and Iport (current port) . . . 407
C.3.4 Switches: Sw (controlled switch) and D (diode) . . . . . . 408
C.3.5 Switch control elements: Clk (Clock) and (MOD) PWM
Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
C.3.6 Miscellaneous: OPAMP (operational ampli er), current
sensor (no symbol name), ground node (no symbol name) 412
C.4 PECSPLOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
C.5 Terminology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
C.6 General use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
C.7 Menu items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
C.7.1 File menu commands . . . . . . . . . . . . . . . . . . . . . 416
C.7.2 Edit menu commands . . . . . . . . . . . . . . . . . . . . 417
C.7.3 Plots Menu commands . . . . . . . . . . . . . . . . . . . . 417
C.7.4 View menu commands . . . . . . . . . . . . . . . . . . . . 419
C.7.5 Options menu commands . . . . . . . . . . . . . . . . . . 419
C.7.6 Help menu commands . . . . . . . . . . . . . . . . . . . . 419
C.8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
x © Richard Tymerski and Frank Rytkonen, 2017
Part I
Classical Control:
Fundamentals
1
Chapter 1
Introduction
1.1 Basic Feedback Con guration
The standard single loop feedback block diagram con guration is shown in
Figure 1.1. There are three basic blocks G(s), Gc (s) and H(s), the plant,
compensator and feedback transfer functions, respectively. These are discussed
below. But rst a straightforward analysis leads to the overall input to output
transfer function of this con guration:
Figure 1.1: Feedback System Block Diagram
Y (s) G(s)
= (1.1)
U (s) 1 + G(s)H(s)
1 G(s)H(s)
= (1.2)
H(s) 1 + G(s)H(s)
The product G(s)H(s) (more strictly, −G(s)H(s)) is termed the loop gain as
it is the product of the gains around the feedback loop. Equation (1.3) is termed
3
the closed loop gain of the system. The advantages that feedback provides is
derived from the fact that as long as the magnitude of the loop gain is large,
that is, |G(s)H(s)| 1, then the closed loop gain is determined by H(s).
However, the price to be paid for this is the possibility that the denominator
polynomial, known as the characteristic polynomial, i.e. 1 + G(s)H(s) may
vanish at some frequency resulting in the closed loop gain becoming unbounded,
that is unstable. The purpose of the compensator Gc (s) therefore is to provide
loop shaping to avoid this instability condition.
From this discussion we can therefore summarize the purpose of each of the
three blocks: G(s) is the plant, which implements the operational function that
is desired; the feedback block H(s) (under the condition of high loop gain) sets
the value of closed loop gain
Y (s) 1
≈ for |G(s)H(s)| 1
U (s) H(s)
and the compensator Gc (s) block improves the stability and performance of the
closed loop system.
The performance of the closed loop system will be assessed by examining the
response to step inputs. Speci cally, with reference to gure 12.2 we will look at
the rise time, settling time and percentage overshoot. Rise time, tr , is de ned
as the time it takes for the step response to go from 10% to 90% of the nal
value. Settling time, ts , refers to the time it takes for the response to remain in
a band of ±5% of the nal value. The percentage overshoot (OS) is determined
by the following formula
B−A
OS = × 100 (1.3)
A
where A and B represent the largest overshoot value and nal value, respec-
tively.
1.2 Stability - Absolute and Relative
As discussed above, the question of absolute stability of a closed loop system,
that is whether it is stable or not, can be answered by whether a frequency
exists for which satis es the characteristic equation:
1 + G(s)H(s)|s=jω = 0 (1.4)
These frequencies are the 'poles' of the closed loop system. The locations of
pole frequencies can be mathematically determined by a root nding procedure.
Stability can be subsequently assessed by examining whether all of these com-
plex valued quantities have a negative real parts. If so, the system is said to be
absolutely stable.
4 © Richard Tymerski and Frank Rytkonen, 2017
Once absolute stability is assessed, then the question of how stable the system
is, that is, its relative stability may be asked. In this regard, the gain (GM) and
phase margins (PM) are used. This is generally done in the context of Bode
plots, which show the magnitude and phase response of the loop gain over a
range of frequencies which include the −180◦ phase crossover frequency and the
unity gain crossover frequency, as shown in gure 1.3. As a rule of thumb, a
gain margin of > 10 dB and phase margin of between 45◦ to 60◦ are deemed
desirable.
Note also that (under certain mild assumptions concerning the loop gain) the
phase margin may be used to determine the stability of the closed loop system.
The phase margin test for absolute stability requires that
Phase Margin Test for Stsbility: P M > 0 =⇒ stability (1.5)
The gain margin does enter into the absolute stability consideration. This
may be seen as rather unusual and so an example will be presented in the
next section demonstrating this as well as tying up a number of other concepts
presented here.
It should be emphasized that the stability of the closed loop system which
G
has transfer function
1+GH can be assessed by looking at a property the loop
gain which has transfer function GH , speci cally the phase margin.
The design of compensators may be approached in several ways. In this book
the use of Bode plots to shape the loop and obtain desirable gain and phase
margins is demonstrated.
The design of the compensator may be approached several ways. In this book
the use of Bode plots to shape the loop is demonstrated
© Richard Tymerski and Frank Rytkonen, 2017 5
Figure 1.2: Step Response
6 © Richard Tymerski and Frank Rytkonen, 2017
Figure 1.3: Gain and Phase Margins
© Richard Tymerski and Frank Rytkonen, 2017 7
1.3 Stability Analysis Example
Consider a system with the following loop gain
s s
1+ ωz 1+ ω1
T (s) = A
s3
where A = 300, ωz = 40rad/s, and ωz = 1rad/s
Using the methodology that has been developed to this point, the loop gain,
T (s) will be analyzed to determine whether the system is stable.
The stability analysis begins by constructing an asymptotic bode plot of the
given system, as shown in Figure 1.4.
Negative
Gain
| T ( s) | Margin
Phase
Margin
−180o
Figure 1.4: Bode Plot: System Loop Gain
8 © Richard Tymerski and Frank Rytkonen, 2017
Using the asymptotic bode plot, the phase margin is calculated by utilizing
the magnitude to determine the crossover frequency:
A
√
ωc2 =1 or ωc = A = 17.3rad/s
With the crossover frequency de ned, the margin is calculated by inserting
the frequency value into the loop gain phase equation:
ωc ωc
P M = 180o − 270o + tan−1 + tan−1
ωz ω1
17.3 17.3
P M = 180o − 270o + tan−1 + tan−1 = 20o
40 1
To determine the gain margin, the phase equation is used to determine the
frequency in which the phase is −180o .
ωm ωm
−180o = −270o + tan−1 + tan−1
ωz ω1
Solving the phase equation for ωm , ωm = 6.32rad/s
Inserting the computed value of ωm into the magnitude equation, the gain
margin is calculated as follows:
A 300
|T (jωm )| = 2
= = 7.5
ωm 6.322
GM = −20log10 (7.5) = −17.5dB
Using MATLAB to verify the asymptotic bode plot, Figure 1.5 con rms the
phase and gain margin analysis, with a gain margin and phase margin error
of 1.1% and 6.1% respectively, due to the approximations of the asymptotic
magnitude plot.
With a positive phase margin, and a negative gain margin, additional criterion
are necessary to determine if the system is stable. Another method used to
determine the stability of a system is the Routh-Hurwitz stability criterion.
Before the Routh-Hurwitz criterion can be applied to the presented system,
a closed loop transfer function must be derived for the system loop gain. One
possible realization of the closed loop system is presented in Figure 1.6.
© Richard Tymerski and Frank Rytkonen, 2017 9
Bode Diagram
Gm = -17.7 dB (at 6.32 rad/s) , Pm = 21.3 deg (at 18.2 rad/s)
200
150
Magnitude (dB)
100
50
-50
-90
-135
Phase (deg)
-180
-225
-270
-2 -1 0 1 2 3
10 10 10 10 10 10
Frequency (rad/s)
Figure 1.5: Matlab Analysis of phase and gain margin
Student Version of MATLAB
Figure 1.6: Closed-Loop realization of Ts
From Figure 1.6, the closed-loop transfer function is derived as follows:
1
Tcl (s) =
1 + T (s)
1
Tcl (s) =
s3 +A(1+ ωsz ) 1+ ωs
1
s3
s3
Tcl (s) =
s3 + ωzAω1 s2 + A ω1z + 1
ω1 s+A
10 © Richard Tymerski and Frank Rytkonen, 2017
With the system de ned in a closed-loop form, the denominator polynomial
can be used to determine system stability as shown in Figure 1.7
Figure 1.7: Routh Hurwitz analysis of closed loop system
Figure 1.8: Routh Hurwitz Values
Applying the system parameters, Figure 1.8 con rms that no sign changes
are present in the rst column. This con rms that the system is stable, while
having negative gain margin.
With the system con rmed as stable, the next item to explore is the possible
parameter shifting in the system that could cause the system to become unsta-
ble. From the derivations shown in Figure 1.7, the only term that could cause
a sign change in the rst column is the s1 term. Setting this term to zero and
solving for A:
A (ω1 + ωz )
− ω1 ωz = 0
ω1 ωz
1
A= = 39.024
ωz + ω1
© Richard Tymerski and Frank Rytkonen, 2017 11
Applying the shifted A parameter to the asymptotic bode plot of Figure 1.4,
the updated bode plot is shown in Figure 1.9.
| T (s) |
−180o
Figure 1.9: Bode Plot: System Loop Gain with parametric shift
A
Applying the new value of A to the magnitude equation,
ωc2 = 1 or ωc =
√
A = 6.25rad/s. With this frequency, the phase margin is calculated to be
−0.2o .
As a con rmation of the above margin estimate due to parametric value shift,
Figure 1.10 con rms the analysis, with a phase margin of −8.82 · 10−5 .
12 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm = 8.67e-05 dB (at 6.32 rad/s) , Pm = -8.82e-05 deg (at 6.32 rad/s)
200
150
Magnitude (dB)
100
50
-50
-100
-90
-135
Phase (deg)
-180
-225
-270
-2 -1 0 1 2 3
10 10 10 10 10 10
Frequency (rad/s)
Figure 1.10: Matlab Analysis of phase and gain margin with parametric shift
Summary
This chapter has shown the reader how to apply asymptotic bode plots to
determine the stability of a system. The reader has also learned that in some
scenarios it may be necessary to use asymptotic bode plot analysis in conjunction
Student Version
with the Routh-Hurwitz stability criterion to determine the stability of of
a MATLAB
system.
© Richard Tymerski and Frank Rytkonen, 2017 13
1.3.1 Matlab Code
1 clear all;
2 close all;
3
4 f = logspace(−3,3,10000);
5 w = 2*pi*f;
6 s = tf('s');
7
8 A = 300;
9 w1 = 1;
10 wz = 40;
11
12 %====================================================================
13 %System Loop Gain
14 %====================================================================
15 sys = A*(1+s/w1)*(1+s/wz)/(s^3);
16
17 figure(1)
18 [mag, phase] = bode(sys,w);
19 margin(mag, phase, w)
20
21 h = gcr;
22 xlim([10^−2 10^3]);
23 h.AxesGrid.TitleStyle.FontSize = 16;
24 h.AxesGrid.XLabelStyle.FontSize = 12;
25 h.AxesGrid.YLabelStyle.FontSize = 12;
26 %====================================================================
27
28
29 %====================================================================
30 %Plot Marginal Stability Per Routh Hurwitz
31 %====================================================================
32 A=39.024;
33
34 sys = A*(1+s/w1)*(1+s/wz)/(s^3);
35
36 figure(2)
37 [mag, phase] = bode(sys,w);
38 margin(mag, phase, w)
39
40 h = gcr;
41 xlim([10^−2 10^3]);
42 h.AxesGrid.TitleStyle.FontSize = 16;
43 h.AxesGrid.XLabelStyle.FontSize = 12;
44 h.AxesGrid.YLabelStyle.FontSize = 12;
45 %====================================================================
14 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 2
System Stability
2.1 Stability
Asymptotic stability means that, in the absence of energy coming into the sys-
tem's input, any stored energy in the system will asymptotically decay to zero
over time. A system is considered asymptotically stable if all of the proper
transfer function's poles have real components in the open left-half of the com-
plex plane (LHP). This means that the real part of any complex pole s = σ + jω
must be negative, i.e., σ < 0, for stability (since the open LHP means that the
jω axis is excluded). Therefore, a stable system cannot have poles on the jω
axis or in the right-half of the complex plane (RHP).
Bounded-input, bounded-output (BIBO) stability means that, in the absence
of stored energy in the system, any input signal that is bounded in magnitude,
i.e., −∞ < umin ≤ u(t) ≤ umax < ∞ will produce an output signal that is
bounded in magnitude, i.e., −∞ < ymin ≤ y(t) ≤ ymax < ∞. BIBO stability
exists if the integral of the absolute value of the impulse response is nite,
R∞
i.e.,
0
|g(τ )|dτ < ∞. In order to test BIBO stability, the impulse response
function g(t) must be determined for a given transfer function G(s) by applying
the inverse Laplace transform, an action that is not always trivial.
This text will focus on determining the asymptotic stability of a system, so
when a system is declared stable, it is referring to asymptotic stability.
2.2 Stability Analysis by Inspection
First-order and second-order systems can be analyzed for stability by inspecting
their characteristic equations. The following requirements must be met for
inspection to be valid:
The characteristic equation must be second-order or less
All powers of s must have non-zero coe cients
15
All coe cients of powers of s must have the same sign
If these three criteria are met, the characteristic equation is stable by inspec-
tion. If even one of these criteria is violated, the system is unstable. Third-order
and higher-order systems cannot have their stability evaluated by inspection.
2.2.1 Parameterized Stability Analysis by Inspection
The stability analysis by inspection technique can be used with parameterized
systems to determine the range over which a parameter can vary and still allow
the system to remain stable. This can be useful when considering controller
gains or uncertainty.
2.2.2 Examples of Stability Analysis by Inspection
Given a transfer function characteristic polynomial of:
s2 + 13s + 8
determine whether or not system is stable by inspection. Verify the result with
the MATLAB roots command.
The characteristic equation is second-order. The coe cients of powers of s,
in descending order, are {1, 13, 8}, and are all non-zero. The sign on all of the
coe cients of s is positive. Since all three criteria are met, the transfer function
is stable.
Check: since the characteristic polynomial was known, the roots command
was used in MATLAB to determine the poles were at [-12.3523 -0.6477], which
not only shows that all poles have real parts in the open left-half of the complex
frequency plane, but gives their locations as well.
Given a transfer function characteristic polynomial of:
s−9
determine whether or not system is stable by inspection. Verify the result with
the MATLAB roots command.
The characteristic equation is less than second-order. The coe cients of
powers of s, in descending order, are {1, −9}, and are all non-zero. The sign
on the rst coe cient is positive, but the second sign is negative indicating the
third requirement for stability by inspection is violated, therefore the transfer
function is unstable.
Check: since the characteristic polynomial was known, the roots command
was used in MATLAB to determine the poles were at [9], which shows that the
pole is real and in the right-half of the complex frequency plane.
Given a transfer function characteristic polynomial of:
4s2 + 3
determine whether or not system is stable by inspection. Verify the result with
the MATLAB roots command.
16 © Richard Tymerski and Frank Rytkonen, 2017
The characteristic equation is second-order. The coe cients of powers of
s, in descending order, are {4, 0, 3}. Since one of the coe cients is zero, the
transfer function is unstable.
Check: since the characteristic polynomial was known, the roots command
was used in MATLAB to determine the poles were at [0±j0.8660], which shows
that the poles are on the ω axis of the complex frequency plane, producing an
oscillator.
A closed-loop transfer function has a characteristic polynomial of:
s+4−K
where K is the controller gain. Determine, by inspection, the range of non-
negative values that K can assume and still have the closed-loop system remain
stable. Check the stability at the upper and lower bounds of the range deter-
mined.
The characteristic equation is rst-order. The coe cients of powers of s,
in descending order, are {1, 4 − K}. For the transfer function to be meet the
second and third criteria above, 4 − K > 0. This occurs when 0 ≥ K < 4
(remember, the question asked for the range of non-negative values K could
assume, thus establishing a lower bound on K of 0).
Check: when K = 0, the characteristic equation will be s + 4, which has a
pole at -4, and is therefore stable. When K = 4, the characteristic equation will
be s, which has a pole at the origin of the complex plane and is therefore not
stable.
2.3 Routh-Hurwitz Analysis
Given a transfer function, the Routh-Hurwitz stability analysis technique can be
performed using the characteristic equation (i.e., the denominator of the transfer
function). It is typically used as a go/no-go test - it can identify the number of
poles that exist in the right half of the complex plane or on the imaginary axis,
thus indicating stability, but it doesn't directly provide the values of the poles -
though they can be determined indirectly. Since even simple numerical analysis
software can nd the roots of the characteristic polynomial of a system, it is
easy to see if any poles are outside of the open left-half of the complex plane.
Thus, the Routh-Hurwitz stability analysis technique is no longer necessary
for systems where the transfer function characteristic equation or the system
matrix are known. However, the technique is useful when a coe cient in the
characteristic equation is unknown, or if a coe cient is known only to a degree
of uncertainty. For these cases, the stability of the system can be determined for
a range of the unknown/uncertain parameter. This section will rst show how
to develop the Routh-Hurwitz array to demonstrate the principle, then show
how it can be used to determine stability margins for uncertain systems.
Given the denominator polynomial:
d(s) = an sn + an−1 sn−1 + · · · + a1 s + a0
© Richard Tymerski and Frank Rytkonen, 2017 17
the Routh-Hurwitz array of numbers may be established:
sn an an−2 an−4
n−1
s an−1 an−3 an−5
sn−2 b1 b2 b3
sn−3 c1 c2 c3
. . . .
. . . .
. . . .
s0 h1
By examination, the rst two rows are created using by alternating the coe -
cients of the characterstic polynomial, starting with the coe cient of the highest
order of s in the rst column of the rst row. The entries in the third row and
beyond are calculated by using the coe cients of previous rows. For example,
b1 is determined using the following calculation:
an an−2
−
an−1 an−3 an−1 an−2 − an an−3
b1 = =
an−1 an−1
The entry b2 is determined by:
an an−4
−
an−1 an−5 an−1 an−4 − an an−5
b2 = =
an−1 an−1
The entry c1 is determined by:
an−1 an−3
−
b1 b2 b1 an−3 − b2 an−1
c1 = =
b1 b1
Therefore, the general rule is:
The entry in row x + 2, column y is calculated by forming the negative of
the determinant formed using the entries from the previous two rows in column
1 and the previous two rows in column y + 1, then dividing it by the entry from
the previous row in column 1.
Once the Routh-Hurwitz array has been formed, the number of sign changes
in the leftmost column of the array indicates the number of poles in the open
right-half of the complex frequency plane, i.e., the number of unstable poles.
Given a transfer function with a characteristic polynomial of s4 + 3s3 + 4s2 +
6s + 1, form the Routh-Hurwitz array and determine whether or not the system
is stable. Verify the result with the MATLAB roots command.
The initial part of the array is formed as:
s4 1 4 1
s3 3 6 0
s2
s1
s0
18 © Richard Tymerski and Frank Rytkonen, 2017
The rst element of the s2 row is calculated by:
1 4
−
3 6 3·4−1·6
b1 = = =2
3 3
The second element of the s2 row is calculated by:
1 1
−
3 0 3·1−1·0
b2 = = =1
3 3
The rst element of the s1 row is calculated by:
3 6
−
2 1 2·6−3·1
c1 = = = 4.5
2 2
The second element of the s1 row is calculated by:
3 0
−
2 0 2·0−3·0
c2 = = =0
2 2
Further calculations reveal the other s1 row elements are all zeros.
0
The rst element of the s row is calculated by:
2 1
−
4.5 0 4.5 · 1 − 2 · 0
d1 = = =1
2 4.5
Further calculations reveal the other s0 row elements are all zeros.
Thus, the full array is:
s4 1 4 1
s3 3 6 0
s2 2 1 0
s1 4.5 0 0
s0 1 0 0
Since no sign changes occur in the leftmost column, the system is stable.
Check: since the characteristic polynomial was known, the roots command
was used in MATLAB to determine the poles were at [-2.312 -0.251±j1.501,
-0.187], which not only shows that all poles have real parts in the open left-half
of the complex frequency plane, but gives their locations as well.
Once the Routh-Hurwitz array has been created, there are some special cases
that may occur that require handling.
© Richard Tymerski and Frank Rytkonen, 2017 19
2.3.1 Zero in First Column
Because the calculation of elements in the Routh-Hurwitz array requires division
by an element in the rst column, if that element happens to be zero, the
calculation breaks down. For arrays where only the leftmost element in a row
is zero, a new row must be formed with a nonzero rst element in order to
complete the array. Identifying the row with the leading zero as Row A, form
Row B by shifting Row A to the left until a zero is no longer the rst element,
padding on the right with zeros, and multiplying the row formed by -1 for each
shift. Then, add Row A and Row B to each other using element-by-element
addition to form Row C. Finally, replace Row A in the original array with Row
C and continue calculating the remainder of the original array terms.
4 3
Given a transfer function with a characteristic polynomial of 2s + 3s +
4s2 + 6s + 7, form the Routh-Hurwitz array, then determine the number of poles
in the open right-half of the complex frequency plane. Verify the result with
the MATLAB roots command.
The initial part of the array is formed as:
s4 2 4 7
s3 3 6 0
s2 0 7 0
s1
s0
The s2 row becomes Row A. Shifting this once to the left, padding with
zeros, and multiplying by -1 (due to only one shift to the left) forms Row B =
[-7 0]. Adding Rows A and B together forms Row C = [-7 7]. This now goes into
the original array in place of Row A and the remaining elements are calculated
as indicated below.
s4 2 4 7
s3 3 6 0
s2 −7 7 0
s1 9 0 0
s0 7 0 0
Since there are two sign changes in the rst column, there are two poles in
the open right-half of the complex frequency plane, and the system is unstable.
Check: since the characteristic polynomial was known, the roots command
was used in MATLAB to determine the poles were at [0.384±j1.337, -1.134±j0.722],
which not only shows two poles whose real parts are in the open right-half of
the complex frequency plane, but gives all of the pole locations as well.
2.3.2 A Row of Zeros
If a row in the Routh-Hurwitz array consists entirely of zeros, there will be
poles that are located symmetrically about the origin in the complex frequency
plane. If using the Routh-Hurwitz array as an go/no-go test of stability, the
row of zeros indicates a condition where poles exist symmetrically along either
20 © Richard Tymerski and Frank Rytkonen, 2017
the real axis or the imaginary axis. This is enough to indicate that the system
is unstable. However, when a parameterized characteristic polynomial occurs,
it is of interest to be able to determine all of the elements in the Routh-Hurwitz
array. Since division by zero is not allowed, the row of zeros must be replaced
with a nonzero row. This is accomplished by creating a divisor polynomial
p(s) from the row above the row containing the zeros and nding its derivative
with respect to s, then replacing the row of zeros with the coe cients in the
derivative. The divisor polynomial is created by multiplying the rst term in the
row by the power of s associated with the row, then multiplying each additional
term by decreasing the power of s by a factor of 2 each time, and adding all
2 1
of the terms. For example, assume the s row was [3 3] and the s row was [0
2
0]. The rst term in the divisor polynomial is created by multiplying 3 by s to
get 3s2 . The second term in the divisor polynomial is created by multiplying 3
0 2
by s to get 3. Therefore, the divisor polynomial is p(s) = 3s + 3. Taking the
1
derivative with respect to s gives 6s, therefore the new s row is [6 0].
2.3.3 Parameterized Routh-Hurwitz Analysis
As mentioned previously, the Routh-Hurwitz analysis technique can be used
with parameterized systems. One of the most popular parameterized systems
to analyze involves the DC gain of the controller. The Routh-Hurwitz analysis
can be used to determine the range of DC gain for which the system will be
stable.
Given a unity gain feedback system with proportional controller K, and a
system transfer function of:
10
s3 + 9s2 + 23s + 15
form the Routh-Hurwitz array, then determine the range of K for which the
system is stable. Verify the result with the MATLAB roots command.
The closed-loop transfer function is:
10K
T (s) =
s3 + 9s2 + 23s + (15 + 10K)
The Routh-Hurwitz array is formed from the characteristic equation:
s3 1 23
s2 9 15 + 10K
9·23−1·(15+10K)
s1 9
s0 15 + 10K
Evaluation of the rst column terms indicates that 15+10K < 207 and
15+10K > 0. These two inequalities lead to a range for stable operation that
is -1.5 < K < 19.2.
Check: The characteristic polynomial with K = -1.5 is s3 + 9s2 + 23s.
The roots command was used in MATLAB to determine the poles were at
© Richard Tymerski and Frank Rytkonen, 2017 21
[-4.5±j1.6583, 0], which shows a pole at the origin of the complex plane, and
therefore the system is unstable. The characteristic polynomial with K = 19.2
iss3 + 9s2 + 23s + 207. The roots command was used in MATLAB to determine
the poles were at [0±j4.7958, -9], which shows a complex pole pair on the jω
axis, and therefore the system is unstable. Thus, the range for stable operation
is veri ed to be -1.5 < K < 19.2.
Another use of the Routh-Hurwitz analysis is evaluating the range of a pa-
rameter in the characteristic equation that is uncertain. Given a unity gain
feedback system with uncertainty ∆ and a characteristic equation of:
s3 + 2s2 + 3(1 + ∆)s + 6
form the Routh-Hurwitz array, then determine the range of ∆ for which the
system is stable. Verify the result with the MATLAB roots command.
The Routh-Hurwitz array is formed from the characteristic equation:
s3 1 2
s2 3(1 + ∆) 6
s1 1 + 3∆
s0 6
Evaluation of the rst column terms indicates that 1 + 3∆ > 0. This in-
equality leads to a range for stable operation that is ∆ > −1 3 .
Check: The characteristic polynomial with ∆ = −1
3
3 2
is s + 2s + 2s + 4.
The roots command was used in MATLAB to determine the poles were at [-
√
2, 0±j 2]. Since there are a complex pole pair on the jω axis, the system is
unstable for this value of ∆. Thus, the range for stable operation is veri ed to
−1
be ∆> 3 .
22 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 3
Steady State Error
The output of a system, y(t) can be decomposed into two components: 1) steady
state response, yss (t), and 2) transient response,ytr (t), so that
y (t) = yss (t) + y tr (t)
For a stable system the transient component will eventually die out, leaving just
the steady state response.
In this chapter we will examine the steady state response of feedback systems.
The desired steady state response will dictate the type of frequency compen-
sation than can be used for a speci c system. Generally, the input(s) used in
assessing the steady state response is one or all of the following:
1
1. Step: r (t) = u(t), with R (s) = L {r (t)} = s
1
2. Ramp: r (t) = t, with R (s) = L {r (t)} = s2
3. Parabola: r (t) = 21 t2 , with R (s) = L {r (t)} = 1
s3
The motivation for using these inputs may be seen by observing a Taylor series
expansion of a general input signal, r(t) (around point t = a):
dr 1 d2 r 2
r (t) = r (a) + (t − a) + (t − a) + . . .
dt t=a 2! dt2 t=a
= A0 + A1 t + A2 t 2 + . . .
Thus the step, ramp and parabolic inputs can be seen as the rst three order
terms of a general input signal.
In discussing steady state response we are particularly interested in comparing
it with some desired or ideal value. The dierence will be de ned as the steady
state error. We will be careful to consider the cases for, with reference to Figure
3.1,
23
1. H(s) = 1, i.e. unity gain feedback
2. H(s) 6= 1, i.e. non-unity gain feedback
Figure 3.1: General feedback system.
As we have seen the closed loop gain of the system of Figure 3.1 is given by
Y (s) G (s)
=
R(s) 1 + G (s) H(s)
which can also be written as
Y (s) 1 G (s) H(s)
= ·
R(s) H(s) 1 + G (s) H(s)
For very large loop gains, i.e. |G (s) H (s)| 1, the second factor reduces to
unity:
G (s) H(s)
≈ 1, for |G (s) H (s)| 1
1 + G (s) H(s)
so that
Y (s) 1
≈ , for |G (s) H (s)| 1
R(s) H (s)
Of course, this is precisely the reason that feedback is used in the rst place.
Namely, for a large loop gain, the overall gain of the system can be controlled
by a highly stable gain H(s).
1
We consider the gain,
H(s) , as the ideal closed loop gain. Furthermore, the term
G(s)H(s)
1+G(s)H(s) , will be seen as a correction term, which deviates from unity at nite
values of loop gain.
24 © Richard Tymerski and Frank Rytkonen, 2017
3.1 Unity gain feedback
Consider the unity gain feedback system of Figure 3.2, where H(s) = 1.
Figure 3.2: Unity gain feedback system.
The ideal output for a unity gain system is the input, i.e. Y (s) = R(s), since
Y (s) 1
R(s) = H(s) = 1. Any deviations of the output from the input, due to the
correction term, can be seen as the error. So that we can de ne the error signal
as
E (s) = R (s) − Y (s)
In terms of the unity gain feedback structure, this is seen as the signal at the
input of the transfer function G (s).
In the time domain, the error is expressed as:
e (t) = r (t) − y(t)
and the steady state error, ess , is de ned as
ess , lim e (t)
t→∞
= lim {r (t) − y(t)}
t→∞
To determine ess , the full response of a system, y (t), may be determined and
use of the above expression may be made. To illustrate this, let us consider a
1
feedback system with G (s) = s(s+2) (and H (s) = 1). The closed loop system
gain is given by:
Y (s) G (s)
=
R(s) 1 + G(s)
1
s(s+2)
= 1
1 + s(s+2)
1
= 2
(s + 1)
1
With a unit step input, R(s) = s , the output, Y (s), is given by
1 1
Y (s) = 2 ·
(s + 1) s
© Richard Tymerski and Frank Rytkonen, 2017 25
A partial fraction expansion leads to:
1 1 1
Y (s) = − −
s s + 1 (s + 1)2
So that the time domain output is given by
y (t) = L−1 {Y (s)}
= 1 − e−t − te−t
We can identify the two components of the output response: yss (t) = 1, and
ytr (t) = −e−t − te−t .
The steady state error is given by
ess = lim {r (t) − y(t)}
t→∞
= lim 1 − [1 − e−t − te−t ]
t→∞
=0
Note however that it is more expeditious to use the Laplace Transform Final
Value Theorem to determine the steady state error, ess . The nal value theorem
states that for a signal e (t), for which, L {e (t)} = E(s), the nal value, ess , is
given by
ess = lim e(t) = lim sE(s)
t→∞ s→0
Given the error as de ned above, in the Laplace domain:
E (s) = R (s) − Y (s)
G(s)
= R (s) − R(s)
1 + G (s)
1
= R(s)
1 + G (s)
which gives
1
ess = lim s R(s)
s→0 1 + G (s)
Note that there is an important requirement for the use of the above formula
1
and that is that the transfer function
1+G(s) needs to be stable.
1
Continuing the above example (where G (s) =
s(s+2) ) this results in
" #
s(s + 2) 1
ess = lim s 2
s→0 (s + 1) s
=0
This agrees with the previous result obtained using the full time response and
taking the limit as time goes to in nity.
26 © Richard Tymerski and Frank Rytkonen, 2017
Let us now consider the other two inputs:
Unit Ramp input: r (t) = t, with L {r (t)} = R(s) = 1
s2
1
ess = lim s · R(s)
s→0 1 + G (s)
1 1
= lim s · 2
s→0 1 + G (s) s
" #
s(s + 2) 1
= lim s 2 ·
s→0 (s + 1) s2
=2
Unit Parabolic input: r (t) = 21 t2 , with L {r (t)} = R(s) = 1
s3
1
ess = lim s · R(s)
s→0 1 + G (s)
1 1
= lim s ·
s→0 1 + G (s) s3
" #
s(s + 2) 1
= lim s 2 ·
s→0 (s + 1) s3
=∞
To summarize, we see that the steady state error for the three inputs of unit step,
unit ramp and unit parabola exhibit values of 0, 2 (a nite value) and in nity,
respectively. In general, it can be stated that there are two main factors which
impinge on the value of steady state error.
1. type of input (i.e. step, ramp, parabola etc.), and,
2. a property of the system, which is termed the system type. This is de ned
next.
System Type:
The general form of the transfer function of a system is given as follows:
n(s)
G (s) =
d(s)
© Richard Tymerski and Frank Rytkonen, 2017 27
where n(s) and d(s) denote the numerator and denominator polynomials, re-
spectively. Let us now consider that a N -th order factor of s appears in d(s).
That is to say, there are N zeros at s=0 appearing in d(s), so that G (s) can
be expressed as
n(s)
G (s) = ¯
sN · d(s)
where ¯ .
d (s) = sN · d(s) If this factorization is possible then we say that the
system type number is N. In other words, the system type number is given by
the number of poles at s=0 appearing in the transfer function G (s). If there
are none then the system type number is zero.
In determining the steady state error we used
1
ess = lim s · R(s)
s→0 1 + G (s)
Substituting for G (s) from above we have
¯
sN · d(s)
ess = lim s
s→0 ¯ + n(s) · R(s)
sN · d(s)
1
Given inputs that are powers of
s , that is inputs of the form
1
R (s) =
si
where constant, i = 1, 2, 3 . . . , then the steady state error is given by
¯
d(s)
ess = lim N ¯ ·sN −i+1
s→0 s · d(s) + n(s)
Consequently, we have the three cases:
1. When, N −i+1>0 or i < N + 1, then ess = 0
¯
h i
d(s)
2. When, N −i+1=0 or i = N + 1, then ess = lims→0 ¯
sN ·d(s)+n(s)
3. When, N −i+1<0 or i > N + 1, then ess = ∞
Relating this back to our previous example with transfer function given by
1
G (s) =
s(s + 2)
We see that the system type number is 1, i.e. N = 1, as there is one pole at
s = 0. For a step input, i = 1, which corresponds to case (1) above leading to
ess = 0. For a ramp input, i = 2, this is case (2) (since N = 1) so that the
steady state error is given by
28 © Richard Tymerski and Frank Rytkonen, 2017
¯
d(s)
ess = lim ¯ + n(s)
s→0 s1 · d(s)
s+2
= lim 1
s→0 s · (s + 2) + 1
=2
For parabolic input, i = 3, we have case (3) (since N = 1) resulting in a steady
state error ess = ∞. These results agree with those previously obtained.
Error Constants:
It is customary to de ne steady state error in terms of system error constants.
These are the position error constant, Kp , the velocity error constant, Kv , and
the acceleration error constant, Ka . They are de ned for a system G (s) as
follows:
Position error constant:
Kp , lim G(s)
s→0
Velocity error constant:
Kv , lim sG(s)
s→0
Acceleration error constant:
Ka , lim s2 G(s)
s→0
The steady state error may be de ned in terms of these constants. As we have
seen, in general
1
ess = lim s · R(s)
s→0 1 + G (s)
For the dierent inputs we have:
Step input:
1 1
ess = lim s ·
s→0 1 + G (s) s
1
=
1 + lims→0 G(s)
1
=
1 + Kp
© Richard Tymerski and Frank Rytkonen, 2017 29
Ramp input:
1 1
ess = lim s · 2
s→0 1 + G (s) s
1
=
lims→0 sG(s)
1
=
Kv
Parabolic input:
1 1
ess = lim s ·
s→0 1 + G (s) s3
1
=
lims→0 s2 G(s)
1
=
Ka
These results are summarized in Table 3.1 where the inputs have been scaled
by a constant A.
Table 3.1: Steady State Error, ess , for systems of dierent type numbers, N,
and for dierent inputs.
System Type Parabolic
Step input: Ramp input: input:
Number, r(t) = Au(t) r(t) = At
N r(t) = A2 t2
A
0 ess = ess = ∞ ess = ∞
1 + Kp
A
1 ess = 0 ess = ess = ∞
Kv
A
2 ess = 0 ess = 0 ess =
Ka
≥3 ess = 0 ess = 0 ess = 0
We can now summarize the procedure to determine the steady state error of
unity gain feedback systems.
Procedure to determine steady state error for unity gain feedback
systems:
Given G (s) (and H (s) = 1) and the type of input:
30 © Richard Tymerski and Frank Rytkonen, 2017
1. Determine the system type. To do this determine the number of poles at
zero (i.e. at s = 0) of transfer function G (s). Alternatively determine the
number of zeros appearing at s=0 of the transfer function: 1 − M (s),
G(s)
where M (s) = 1+G(s) , is the closed loop gain.
2. With the system and input types, the steady state error, ess , can be read
from Table 3.1 for most combinations or determined using the appropriate
error constant.
3.1.1 Example 1:
40
Consider a unity gain feedback system with G (s) = s+4 (and H (s) = 1).
a) Determine the steady state error for a unit step, unit ramp and unit
parabolic inputs using the results of Table 3.1.
b) Con rm your results of (a) by deriving the time domain response and
taking the limit in time.
Solution:
a) System type is N = 0, as there are no poles at s = 0. We can see the
steady state errors for the three inputs from the rst row of Table 3.1.
For both the ramp and parabolic inputs, we have ess = ∞. For the step
1
input, the steady state error is nite and given by ess = 1+K p
, where the
error constant, Kp , needs to be determined for this system.
It is given by
Kp , lim G(s)
s→0
40
= lim
s→0 s+4
= 10
Accordingly,
1
ess =
1 + Kp
1
=
1 + 10
= 0.0909
b) We'll now con rm the above results by deriving the time domain responses
for the three input types.
© Richard Tymerski and Frank Rytkonen, 2017 31
The closed loop system gain is given by
Y (s) G(s)
=
R (s) 1 + G(s)
40
s+4
= 40
1 + s+4
So that
Y (s) 40
=
R (s) s + 44
Step input:
1
With a step input, r (t) = u (t), so that, R(s) = s , the output, Y (s), is
given by
40 1
Y (s) = ·
s + 44 s
0.909 0.909
= −
s s + 44
So that
y (t) = L−1 {Y (s)}
= 0.909 − 0.909e−44t
The steady state error is given by
ess = lim {r (t) − y(t)}
t→∞
= lim 1 − [0.909 + 0.909e−44t ]
t→∞
= 1 − 0.909
= 0.0909
Ramp input:
1
For a ramp input, r (t) = t, so that, R(s) = s2 , the output, Y (s), is given
by
40 1
Y (s) = ·
s + 44 s2
A partial fraction expansion leads to
5 1 10 1 5 1
Y (s) = − · + · + ·
242 s 11 s2 242 s + 44
The steady state error is given by
32 © Richard Tymerski and Frank Rytkonen, 2017
ess = lim {r (t) − y(t)}
t→∞
5 10 5 −44t
= lim t − − + t+ e
t→∞ 242 11 242
=∞
Parabolic input:
2
For a parabolic input, r (t) = 21 t , so that, R(s) = 1
s3 , the output, Y (s),
is given by
40 1
Y (s) = ·
s + 44 s3
By a partial fraction expansion we have
5 1 5 1 10 1 5 1
Y (s) = · − · 2+ · 3− ·
10648 s 242 s 11 s 10648 s + 44
The steady state error is given by
ess = lim {r (t) − y(t)}
t→∞
10 1 2
1 2 5 5 5 −44t
= lim t − − t+ · t − e
t→∞ 2 10648 242 11 2 10648
=∞
3.2 Non-Unity Feedback
We now consider the case of a non-unity feedback system, i.e. H (s) 6= 1. As
discussed earlier, the closed loop gain is given by
Y (s) 1 G (s) H(s)
= ·
R(s) H(s) 1 + G (s) H(s)
Under the condition of in nite loop gain the second factor becomes unity and
the output is a scaled version of the input
1
Y (s) = R(s)
H(s)
G(s)H(s)
This is considered the ideal output. The factor
1+G(s)H(s) is considered a cor-
rection term which causes the actual output to deviate from the ideal when the
loop gain, i.e. G (s) H(s), is nite.
However, as we are interested in the steady state response, the dc gain of H (s)
is used to de ne the scaling constant. To this end we de ne the term kH (with
the assumption that H (s) has no poles at zero):
© Richard Tymerski and Frank Rytkonen, 2017 33
kH , lim H (s) = H(0)
s→0
1
In steady state we will consider the ideal steady gain as,
kH , consequently the
steady state error is de ned by the steady state value of the dierence between
1
the ideal steady state output,
k r(t), and the actual output, y (t) . That is,
H
1
ess , lim r (t) − y(t)
t→∞ kH
Using the Laplace nal value theorem this is given by
1
ess = lim s R (s) − Y (s)
s→0 kH
Substituting the closed loop transfer function, M (s)
1
ess = lim s R (s) − M (s)R (s)
s→0 kH
1
= lim s {1 − kH M (s)}R (s)
kH s→0
where M (s) is given by
Y (s) G(s)
M (s) = =
R (s) 1 + G (s) H(s)
We now de ne the system type number for the non-unity gain feedback system
as the number of zeros of the transfer function 1 − kH M (s) appearing at s = 0.
This, together with the type of input, R(s), are the major determinants of
the steady state error. Representing the transfer function, 1 − kH M (s), in the
following form:
sN · n̄(s)
1 − kH M (s) =
d(s)
where N represents the system type and the numerator, n (s) = sN · n̄(s)
N
1 s · n̄(s)
ess = lim s ·R(s)
kH s→0 d (s)
For inputs of the form R (s) = sAi , (such as for a step (i = 1), ramp (i = 2), and
parabolic inputs (i = 2)), the steady state error is given by
A n̄ (s)
ess = lim ·sN −i+1
kH s→0 d (s)
As before for the unity feedback system, we consider the following three cases:
1. When, N −i+1>0 or i < N + 1, then ess = 0
34 © Richard Tymerski and Frank Rytkonen, 2017
h i
A n̄(s)
2. When, N −i+1=0 or i = N + 1, then ess = kH lims→0 d(s)
3. When, N −i+1<0 or i > N + 1, then ess = ∞
Looking more closely at case (2), and represent M (s) by a rational polynomial:
bm sm + bm−1 sm−1 + · · · + b1 s + b0
M (s) =
sn + an−1 sn−1 + · · · + a1 s + a0
We are now in a position to determine the steady state errors for the various
inputs. Substituting for M (s) in the following expression for ess
1
ess = lim s · [1 − kH M (s)] · R (s)
kH s→0
for each of the three inputs leads to the following results:
Step input:
For a step input, i = 1, case (2) corresponds to a type 0 system, since N =
i − 1 = 0. Substituting R(s) = As leads to
n
1 s + · · · + (a1 − b1 kH ) s + (a0 − b0 kH ) A
ess = · lim s · ·
kH s→0 sn + an−1 sn−1 + · · · + a1 s + a0 s
A (a0 − b0 kH )
=
kH a0
Ramp input:
For a ramp input, i = 2, case (2) corresponds to a type 1 system, since N =
i − 1 = 1. Substituting R(s) = sA2 leads to
( )
1 s sn−1 + · · · + (a2 − b2 kH ) s + (a1 − b1 kH ) A
ess = · lim s · · 2
kH s→0 sn + an−1 sn−1 + · · · + a1 s + a0 s
A (a1 − b1 kH )
=
kH a0
Parabolic input:
For a parabolic input, i = 3, case (2) corresponds to a type 2 system, since
N = i − 1 = 2. Substituting R(s) = sA3 leads to
( )
1 s2 sn−2 + · · · + (a3 − b3 kH ) s + (a2 − b2 kH ) A
ess = · lim s · n n−1
· 3
kH s→0 s + an−1 s + · · · + a1 s + a0 s
A (a2 − b2 kH )
=
kH a0
© Richard Tymerski and Frank Rytkonen, 2017 35
The above results are summarized in Table 3.2. Note also that the unity feed-
back case where kH = 1 is also covered in these results and provide an alter-
native set of formulas from those shown in Table 3.2 which does not involve
determination of error constants.
Table 3.2: Steady State Error, ess , for systems of dierent type numbers, N,
and for dierent inputs for non-unity gain systems. kH , lims→0 H (s) = H(0)
System Step input: Ramp input: Parabolic input:
Type: r(t) = Au(t) r(t) = At r(t) = A2 t2
N
(a0 − b0 kH )
A
0 ess =
kH a0 ess = ∞ ess = ∞
(a1 − b1 kH )
A
1 ess = 0 ess =
kH a0 ess = ∞
(a2 − b2 kH )
A
2 ess = 0 ess = 0 ess =
kH a0
≥3 ess = 0 ess = 0 ess = 0
We can now summarize the procedure to determine the steady state error of
non-unity gain, as well as unity gain, feedback systems. A unity gain feed-
back systems error analysis using this approach is demonstrated in one of the
examples below.
Procedure to determine steady state error:
Given G (s) and H (s) and the type of input:
1. Determine constant kH , the DC gain of H (s), i.e. kH , lims→0 H (s)
= H(0).
2. Determine the system type. To do this determine the number of zeros
appearing at s=0 of the transfer function: 1 − kH M (s), where M (s) =
G(s)
1+G(s)H(s) , is the closed loop gain.
3. With the system type number and input type, the steady state error, ess ,
can be read from Table 3.2 for most combinations or determined using
the appropriate coe cients of certain numerator and denominator terms
of M (s).
3.2.1 Example 2:
40
Given a feedback system with, G (s) = s+4 and H (s) = 0.5.
36 © Richard Tymerski and Frank Rytkonen, 2017
a) Find the steady state error, ess , for unit step, ramp and parabolic inputs.
b) Con rm your results by deriving the full output time response and taking
the limit as time goes to in nity. Recall that steady state error is de ned
1
as the dierence between the ideal steady state output, i.e.
kH r(t), and
the actual output, y(t), so that
1
ess = lim r (t) − y(t)
t→∞ kH
Solution:
a) Steps:
1) As H (s) = 0.5, which is frequency independent, the constant kH =
0.5.
G(s)
2) The closed loop gain M (s) = 1+G(s)H(s) is found to be
40
s+4
M (s) = 40
1 + 0.5 · s+4
40
=
s + 24
Furthermore
40
1 − kH M (s) = 1 − 0.5 ·
s + 24
s+4
=
s + 24
From which we see that there are no zeros at s = 0, so that the
system type = 0.
3) With a system type of 0, from the rst row of Table 3.2 we see that
ess = ∞ for both ramp and parabolic inputs and for a unit step (with
A = 1), the error is given by
1 (a0 − b0 kH )
ess =
kH a0
Noting coe cients of the numerator and denominator of M (s) we
have a0 = 24, b0 = 40 and with kH = 0.5, we nd ess = 0.33.
b) We will con rm this last result rst by deriving the full output time re-
sponse:
Y (s) 40
= M (s) =
R (s) s + 24
© Richard Tymerski and Frank Rytkonen, 2017 37
We have the output
y (t) = L−1 {M (s) R(s)}
1
For a unit step input, R (s) = s,
−1 40 1
y (t) = L ·
s + 24 s
Obtaining a partial fraction expansion
1.667 1.667
y(t) = L−1 −
s s + 24
= 1.667 − 1.667e−24t
This has the form
y (t) = yss (t) + ytr (t)
where yss (t) = 1.667 and ytr (t) = −1.667e−24t . The transient term ytr (t)
will decay to zero as time progresses. The steady state error is de ned by
1
ess = lim r (t) − y(t)
t→∞ kH
1
= lim r (t) − [y ss (t) + ytr (t)]
t→∞ kH
The transient response will die out to zero so ignoring the transient com-
ponent in the output, we have:
1
ess = lim r (t) − yss (t)
t→∞ kH
1
= − 1.667
0.5
= 0.33
This con rms our previous result.
1
kH r(t), and actual outputs are shown
A plot of the steady state ideal, i.e.
in Figure 3.3. The time evolution of the dierence, representing the error
is shown in Figure 3.4.
38 © Richard Tymerski and Frank Rytkonen, 2017
Figure 3.3: The ideal steady state output and actual output. In steady state
the dierence is seen to be 2 - 1.667 = 0.33.
Figure 3.4: The time evolution of the error. The error signal settles to 0.33 in
the steady state.
Ramp input:
1
For a unit ramp input, R (s) = s2 , the output is given by
© Richard Tymerski and Frank Rytkonen, 2017 39
−1 40 1
y (t) = L · 2
s + 24 s
Obtaining a partial fraction expansion
0.069 1.667 0.069
y(t) = L−1 − + 2 +
s s s + 24
= −0.069 + 1.667t − 0.069e−24t
This has the form
y (t) = yss (t) + ytr (t)
where yss (t) = −0.069 + 1.667t and ytr (t) = −0.069e−24t . The transient
term ytr (t) will decay to zero as time progresses, so ignoring the transient
component in the output, we have:
1
ess = lim r (t) − yss (t)
t→∞ kH
For a unit ramp input, r (t) = t, this leads to
1
ess = lim t − [−0.069 + 1.667t]
t→∞ 0.5
= lim {0.069 + 0.333t]}
t→∞
=∞
Parabolic input:
1
For unit parabolic input, R (s) = s3 ,
−1 40 1
y (t) = L ·
s + 24 s3
Obtaining a partial fraction expansion
−10.0029 0.069 1.667 0.0029
y(t) = L − 2 + 3 −
s s s s + 24
t2
= 0.0029 − 0.069t + 1.667 − 0.0029e−24t
2
This has the form
y (t) = yss (t) + ytr (t)
2
where yss (t) = 0.0029 − 0.069t + 1.667 t2 and ytr (t) = −0.0029e−24t . The
transient term ytr (t) will decay to zero as time progresses. The steady
state error is given by:
40 © Richard Tymerski and Frank Rytkonen, 2017
1
ess = lim r (t) − yss (t)
t→∞ kH
t2
For a unit parabolic input, r (t) = 2 , this leads to
1 t2 t2
ess = lim · − [0.0029 − 0.069t + 1.667 ]
t→∞ 0.5 2 2
t2
= lim −0.0029 + 0.069t + 0.333
t→∞ 2
=∞
3.2.2 Example 3:
40
Given a feedback system with, G (s) = s+4 and H (s) = 1.
a) Find the steady state error, ess , for unit step, ramp and parabolic inputs.
b) Con rm your result for the input that produces a nite (non-zero) steady
state error by deriving the full output time response and taking the limit
as time goes to in nity.
Solution:
a) Steps:
1) As H (s) = 1, the constant kH = 1.
G(s) G(s)
2) The closed loop gain M (s) = 1+G(s)H(s) = 1+G(s) so that
40
s+4
M (s) = 40
1 + s+4
40
=
s + 44
and
40
1 − kH M (s) = 1 − 1 ·
s + 44
s+4
=
s + 44
From which we can see that the system type = 0, as there are no
zeros at s = 0.
© Richard Tymerski and Frank Rytkonen, 2017 41
3) With a system type of 0, from the rst row of Table 3.2 we see that
ess = ∞ for both ramp and parabolic inputs and for a unit step (with
A = 1), the error is given by
1 (a0 − b0 kH )
ess =
kH a0
Noting coe cients of the numerator and denominator of M (s) we
have a0 = 44, b0 = 40 and with kH = 1, we nd ess = 0.091.
b) We will con rm this last result by obtaining the full time domain response.
Y (s) 40
M (s) = =
R (s) s + 44
1
For a unit step input, R (s) = s , and the output is
y (t) = L−1 {M (s) · R(s)}
−1 40 1
=L ·
s + 44 s
Obtaining a partial fraction expansion
−1 0.909 0.909
y(t) = L −
s s + 44
= 0.91 − 0.91e−44t
This has the form
y (t) = yss (t) + ytr (t)
where yss (t) = 0.91 and ytr (t)=−0.91e−44t . The steady state error is
given by:
1
ess = lim r (t) − yss (t)
t→∞ kH
For a unit step, r (t) = 1, t > 0, this leads to
ess = lim {1 − 0.909}
t→∞
= 0.091
This con rms our previous result.
42 © Richard Tymerski and Frank Rytkonen, 2017
3.2.3 Example 4:
1 2
Given a feedback system with, G (s) = s and H (s) = s+4 .
a) Find the steady state error, ess , for unit step, ramp and parabolic inputs.
b) Con rm your results for step and ramp inputs by deriving the full output
time response and taking the limit as time goes to in nity.
Solution:
a) Steps:
2
1) As H (s) = s+4 , the constant kH , lims→0 H (s) = H (0) = 24 = 0.5.
G(s)
2) The closed loop gain M (s) = 1+G(s)H(s) so that
1
s
M (s) = 1 2
1+ s · s+4
s+4
= 2
s + 4s + 2
and
s+4
1 − kH M (s) = 1 − 0.5 ·
s2 + 4s + 2
s(s + 3.5)
= 2
s + 4s + 2
From which we can see that the system type = 1, as there is one zero
at s = 0.
3) With a system type of 1, from the second row of Table 3.2 we see
that ess = 0 and ess = ∞ for step and parabolic inputs, respectively.
For a unit ramp (with A = 1), the error is given by
1 (a1 − b1 kH )
ess =
kH a0
Noting the numerator and denominator coe cients of M (s) we see
that a0 = 2, a1 = 4, b1 = 1 and with kH = 0.5, we nd that ess = 3.5.
b) We will con rm this last result from the full time domain response for a
ramp input (R (s) = s12 ).
Y (s) s+4
M (s) = = 2
R (s) s + 4s + 2
© Richard Tymerski and Frank Rytkonen, 2017 43
We have the output
y (t) = L−1 {M (s) · R(s)}
−1 s+4 1
=L ·
s2 + 4s + 2 s2
Obtaining a partial fraction expansion
−1 3.5 2 1.78 3.52
y(t) = L − + 2− +
s s s + 3.41 s + 0.586
= −3.5 + 2t − 1.78e−3.41t + 3.52e−0.586t
This has the form
y (t) = yss (t) + ytr (t)
Where the rst two terms represent the steady state response, i.e. yss (t) =
−3.5 + 2t and the last two terms represent the transient response, i.e.
ytr (t) = −1.78e−3.41t + 3.52e−0.586t .
For a unit ramp, r (t) = t, the steady state error is given by:
1
ess = lim r (t) − yss (t)
t→∞ kH
1
= t − (−3.5 + 2t)
0.5
= 3.5
This con rms our previous result.
Figure 3.5 shows the ideal and actual outputs as a function of time. The
dierence is the error. The error as a function of time is shown in Figure
3.6, where it is seen that it converges to its steady state value of 3.5 after
10 seconds.
44 © Richard Tymerski and Frank Rytkonen, 2017
Figure 3.5: The ideal and actual outputs. The dierence of 3.5 between the
outputs represents the steady state error.
Figure 3.6: The error is seen to reach its steady state value of 3.5 after 10
seconds.
Step input:
We will now con rm the steady state error result for a unit step input
© Richard Tymerski and Frank Rytkonen, 2017 45
(R (s) = 1s ) by deriving the full time domain response:
y (t) = L−1 {M (s) · R(s)}
s+4 1
= L−1 ·
s2 + 4s + 2 s
Obtaining a partial fraction expansion
2 0.061 2.06
y(t) = L−1 + −
s s + 3.41 s + 0.586
= 2 + 0.061e−3.41t + 2.06e−0.586t
This has the form
y (t) = yss (t) + ytr (t)
Where the rst term represents the steady state response, i.e. yss (t) = 2,
and the remaining two terms represent the transient response, i.e. ytr (t) =
0.061e−3.41t + 2.06e−0.586t .
For a unit step input, r (t) = 1, t > 0, the steady state error is given by:
1
ess = lim r (t) − yss (t)
t→∞ kH
1
= ·1−2
0.5
=0
This con rms our previous result.
3.2.4 Example 5:
1 4
Given a feedback system with, G (s) = s and H (s) = s+4 .
a) Find the steady state error, ess , for unit step, ramp and parabolic inputs.
b) Con rm your results for the step and ramp inputs by deriving the full
output time response and taking the limit as time goes to in nity.
Solution:
a) Steps:
4
1) As H (s) = s+4 , the constant kH , lims→0 H (s) = H (0) = 44 = 1.
46 © Richard Tymerski and Frank Rytkonen, 2017
G(s)
2) The closed loop gain M (s) = 1+G(s)H(s) so that
1
s
M (s) = 1 4
1+ s · s+4
s+4
= 2
(s + 2)
and
s+4
1 − kH M (s) = 1 − 1 · 2
(s + 2)
s(s + 3)
= 2
s + 4s + 4
s(s + 3)
= 2
(s + 2)
Since there is one zero at s = 0, the system type = 1.
3) With a system type of 1, from the second row of Table 3.2 we see
that ess = 0 and ess = ∞ for step and parabolic inputs, respectively.
For a unit ramp, (with A = 1), the error is given by
1 (a1 − b1 kH )
ess =
kH a0
Noting coe cients of the numerator and denominator of M (s) we
have, a0 = 4, a1 = 4, b1 = 1 and with kH = 1, we nd, ess = 0.75.
b) We will con rm this last result by deriving the full time domain response
for a ramp input (R (s) = s12 ).
Y (s) s+4
M (s) = = 2
R (s) (s + 2)
We have the output
y (t) = L−1 {M (s) · R(s)}
( )
−1 s+4 1
=L 2 ·
(s + 2) s2
Obtaining a partial fraction expansion
( )
−1 0.75 1 0.75 0.5
y(t) = L − + 2+ +
s s s + 2 (s + 2)2
= −0.75 + t + 0.75e−2t + 0.5te−2t
© Richard Tymerski and Frank Rytkonen, 2017 47
This has the form
y (t) = yss (t) + ytr (t)
Where the rst two terms represent the steady state response, i.e. yss (t) =
−0.75 + t, and the remaining two terms represent the transient response,
−2t
i.e . ytr (t) = 0.75e + 0.5te−2t .
For a unit step ramp, r (t) = t, the steady state error is given by:
1
ess = lim r (t) − yss (t)
t→∞ kH
= lim {t − (−0.75 + t)}
t→∞
= 0.75
Step input:
We will now con rm the steady state error result for a unit step input
(R (s) = 1s ) by deriving the full time domain response:
Y (s) s+4
M (s) = = 2
R (s) (s + 2)
We have the output
y (t) = L−1 {M (s) · R(s)}
( )
−1 s+4 1
=L 2 ·
(s + 2) s
Obtaining a partial fraction expansion
( )
−1 1 1 1
y(t) = L − −
s s + 2 (s + 2)2
= 1 − e−2t − te−2t
This has the form
y (t) = yss (t) + ytr (t)
where yss (t) = 1 and ytr (t) = −e−2t − te−2t .
This leads to
1
ess = lim r (t) − yss (t)
t→∞ kH
= lim {1 − 1}
t→∞
=0
This con rms the result previously obtained.
48 © Richard Tymerski and Frank Rytkonen, 2017
3.2.5 Example 6:
1 8(s+1)
Given a feedback system with, G (s) = s2 (s+10) and H (s) = s+4 .
a) Find the steady state error, ess , for unit step, ramp and parabolic inputs.
b) Con rm your results for a unit ramp input by deriving the full output
time response and taking the limit as time goes to in nity.
Solution:
a) Steps:
8(s+1)
1) As H (s) = s+4 , the constant kH = lims→0 H (s) = H (0) = 84 = 2.
G(s)
2) The closed loop gain, M (s) = 1+G(s)H(s) , so that
1
s2 (s+10)
M (s) = 8(s+1)
1
1+ s2 (s+10) · s+4
s+4
=
s4 + 14s3 + 40s2 + 8s + 8
and
s+4
1 − kH M (s) = 1 − 2 ·
s4 + 14s3 + 40s2 + 8s + 8
s(s3 + 14s2 + 40s + 6)
=
s4 + 14s3 + 40s2 + 8s + 8
Since there is one zero at s = 0, the system type = 1.
3) With a system type of 1, from the second row of Table 3.2 we see
that ess = 0 and ess = ∞ for step and parabolic inputs, respectively.
For a unit ramp (with A = 1), the error is given by
1 (a1 − b1 kH )
ess =
kH a0
Noting coe cients of the numerator and denominator of M (s) we
have, a0 = 8, a1 = 8, b1 = 1 and with kH = 2, we nd ess = 0.375
b) We will con rm this last result by deriving the full time domain response
for a ramp input (R (s) = s12 ). Since
Y (s) s+4
M (s) = = 4
R (s) s + 14s3 + 40s2 + 8s + 8
© Richard Tymerski and Frank Rytkonen, 2017 49
We have the output
y (t) = L−1 {M (s) · R(s)}
−1 s+4 1
=L ·
s4 + 14s3 + 40s2 + 8s + 8 s2
Obtaining a partial fraction expansion
0.375 0.5 9.3·10−5 2·10−4
y(t) = L−1 − + 2 + +
s s s + 10 s + 3.75
0.187 + j0.521 0.187 − j0.521
+ +
s + 0.067 − j0.454 s + 0.067 + j0.454
= −0.375 + 0.5t + 9.3·10−5 e−10t + 2·10−4 e−3.75t
+ 0.375e−0.067t cos (0.454t) − 1.04e−0.067t sin (0.454t)
A note at the end of this chapter is provided that illustrates how a complex
conjugate pole pair and their associated complex conjugate residues may
be converted to a cos/sin representation, as shown above.
The form of the output response is
y (t) = yss (t) + ytr (t)
where the rst two terms represent the steady state response, i.e. yss (t) =
−0.375 + 0.5t, and the remaining terms represent the transient response.
This leads to
1
ess = lim r (t) − yss (t)
t→∞ kH
1
= lim t − (−0.375 + 0.5t)
t→∞ 2
= 0.375
Figure 3.7 show the time evolution of the error, which attains a steady
state value of 0.375.
50 © Richard Tymerski and Frank Rytkonen, 2017
Figure 3.7: The error signal as a function of time.
3.2.6 Example 7:
1 4(s+1)
Given a feedback system with, G (s) = s2 (s+10) and H (s) = s+4 .
a) Find the steady state error, ess , for unit step, ramp and parabolic inputs.
b) Con rm your results for a unit ramp input by deriving the full output
time response and taking the limit as time goes to in nity.
Solution:
a) Steps:
4(s+1)
1) As H (s) = s+4 , the constant kH , lims→0 H (s) = H (0) = 44 = 1.
G(s)
2) The closed loop gain M (s) = 1+G(s)H(s) so that
1
s2 (s+10)
M (s) = 4(s+1)
1
1+ s2 (s+10) · s+4
s+4
=
s4 + 14s3 + 40s2 + 4s + 4
and
s+4
1 − kH M (s) = 1 − 1 ·
s4 + 14s3 + 40s2 + 4s + 4
s(s3 + 14s2 + 40s + 3)
=
s4 + 14s3 + 40s2 + 4s + 4
© Richard Tymerski and Frank Rytkonen, 2017 51
Since there is one zero at s = 0, the system type = 1.
3) With a system type of 1, from the second row of Table 3.2 we see that
ess = 0 and ess = ∞ for both step and parabolic inputs, respectively.
For a unit ramp (with A = 1), the error is given by
1 (a1 − b1 kH )
ess =
kH a0
Noting coe cients of the numerator and denominator of M (s) we
have, a0 = 4, a1 = 4, b1 = 1and with kH = 1, we nd ess = 0.75.
b) We will con rm this last result by deriving the full time domain response
1
for a unit ramp input (R (s) = s2 ).
Y (s) s+4
M (s) = = 4
R (s) s + 14s + 40s2 + 4s + 4
3
We have the output
y (t) = L−1 {M (s) · R(s)}
s+4 1
= L−1 ·
s4 + 14s3 + 40s2 + 4s + 4 s2
Obtaining a partial fraction expansion
9.62·10−5 9.1·10−5
0.75 1
y(t) = L−1 − + 2+ +
s s s + 10 s + 3.875
0.375 + j1.53 0.375 − j1.53
+ +
s + 0.033 − j0.32 s + 0.033 + j0.32
= −0.75 + t + 9.62·10−5 e−10t + 9.1·10−5 e−3.875t
+ 0.75e−0.033t cos (0.32t) − 3.06e−0.033t sin (0.32t)
This has the form
y (t) = yss (t) + ytr (t)
where the rst two terms represent the steady state response. i.e. yss (t)=
−0.75 + t, and the remaining terms represent the transient response which
will decay to zero as time progresses.
This leads to
1
ess = lim r (t) − y (t)
t→∞ kH
= lim {t − (−0.75 + t)}
t→∞
= 0.75
52 © Richard Tymerski and Frank Rytkonen, 2017
Figure 3.8 show the time evolution of the error, which attains a steady
state value of 0.75.
Figure 3.8: The error signal as a function of time.
3.2.7 Example 8:
This nal example will illustrate both the non-unity gain and unity gain feedback
methods in assessing steady state error.
4(s+1)
Given a feedback system with, G (s) = s2 (s+10)(s+4) and H (s) = 1.
a) Find the steady state error, ess , for unit step, ramp and parabolic inputs.
b) Con rm your results for a unit ramp input by deriving the full output
time response and taking the limit as time goes to in nity.
Solutions:
Non unity gain method:
a) Steps:
1) As H (s) = 1, the constant kH , lims→0 H (s) = H (0) =1.
G(s) G(s)
2) The closed loop gain M (s) = 1+G(s)H(s) = 1+G(s) so that
© Richard Tymerski and Frank Rytkonen, 2017 53
4(s+1)
s2 (s+10)(s+4)
M (s) = 4(s+1)
1 + s2 (s+10)(s+4)
4s + 4
=
s4 + 14s3 + 40s2 + 4s + 4
and
4s + 4
1 − kH M (s) = 1 − 1 ·
s4 + 14s3 + 40s2 + 4s + 4
s2 (s2 + 14s + 40)
=
s4 + 14s3 + 40s2 + 4s + 4
Since there are two zeros at s = 0, the system type = 2.
3) With a system type of 2, from the second row of Table 3.2 we see
that ess = 0 and ess = 0 for both step and ramp inputs, respectively.
For a unit parabola (with A = 1), the error is given by
1 (a2 − b2 kH )
ess =
kH a0
Noting coe cients of the numerator and denominator of M (s) we
have, a0 = 4, a2 = 40, b2 = 0 and with kH = 1, we nd ess = 10.
b) We will con rm this result by deriving the full time domain response for
1
a unit parabolic input (R (s) = s3 ).
Y (s) 4s + 4
M (s) = = 4
R (s) s + 14s3 + 40s2 + 4s + 4
We have the output
y (t) = L−1 {M (s) · R(s)}
4s + 4 1
= L−1 ·
s4 + 14s3 + 40s2 + 4s + 4 s3
54 © Richard Tymerski and Frank Rytkonen, 2017
Obtaining a partial fraction expansion
5.72·10−5 2.15·10−3
−1 10 1
y(t) = L − + 3− +
s s s + 10 s + 3.875
5 − j0.53 5 + j0.53
+ +
s + 0.033 − j0.32 s + 0.033 + j0.32
t2
= −10 + + 5.7·10−5 e−10t + 2.15·10−3 e−3.875t
2
+ 10e−0.033t cos (0.32t) + 1.06e−0.033t sin (0.32t)
This has the form
y (t) = yss (t) + ytr (t)
Where the rst two terms represent the steady state components (i.e.
t2
yss (t) = −10 + 2 ) and the remaining terms represent the transient re-
sponse which will decay to zero as time progresses.
This leads to
1
ess = lim r (t) − y (t)
t→∞ kH
2
t2
t
= lim − (−10 + )
t→∞ 2 2
= 10
1
Figure 3.9 shows the time evolution of output, both the ideal, i.e.
kH r (t),
and the actual outputs. However, due the axis scaling involved the outputs
appear as identical. By looking closely at a small portion of the output
responses the dierence between the ideal and actual outputs can be seen.
This is shown in Figure 3.10 where the dierence can be seen to have a
value of 10, which represents the steady state error. Figure 3.11 shows the
time evolution of the error.
© Richard Tymerski and Frank Rytkonen, 2017 55
Figure 3.9: The ideal output and actual output are indistinguishable, however
there is a dierence between these signals which attains a value of 10 in steady
state.
Figure 3.10: The dierence between the ideal and actual outputs can be seen
here when looking at a small portion of the time response. The dierence seen
above has a value of 10, the steady state error.
56 © Richard Tymerski and Frank Rytkonen, 2017
Figure 3.11: The error signal as a function of time settles to a steady state value
of 10.
Unity gain method:
4(s+1)
Given that
s2 (s+10)(s+4) and H (s) = 1, which represents unity gain
G (s) =
feedback, the previously described procedure to assess steady state error may
be followed.
Following the procedure given for unity gain feedback system, we rst determine
the system type by noting the number of poles appearing at s=0 of transfer
function G (s) . The type number = 2. Consulting Table 3.1 across the third
row of this table which corresponds to a system of type number 2, it can be
seen that ess = 0 for both the step and ramp inputs and that for a parabolic
input, ess = K1a , (for A = 1) where Ka is the acceleration error constant given
by Ka = lims→0 s2 · G(s)
For the present system
4(s + 1)
Ka = lim s2 ·
s→0 s2 (s + 10)(s + 4)
1
=
10
Therefore the steady state error is
1
ess =
Ka
= 10
This agrees with our previous result.
© Richard Tymerski and Frank Rytkonen, 2017 57
3.3 Note: partial fraction containing a complex
pole pair
Inverse Laplace transformation simpli cation of a partial fraction ex-
pansion containing a complex conjugate pole pair
Given a complex conjugate pole pair, p∗1 , where p1 = α + jβ and p∗1 =
p1 and
∗
α − jβ , with corresponding residues, k1 and k1 , where k1 = a + jb and k1∗ =
a − jb, the following simpli cation can be made when determining the inverse
Laplace transform.
k1∗
k1 a + jb a − jb
L−1 + = L−1
+
s − p1 s − p∗1 s − α − jβ s − α + jβ
−1 (a + jb) (s − α + jβ) + (a − jb) (s − α − jβ)
=L
(s − α − jβ)(s − α + jβ)
" #
2a (s − α) − 2bβ
= L−1 2
(s − α) + β 2
" # " #
−1 (s − α) −1 β
= 2aL 2 − 2bL 2
(s − α) + β 2 (s − α) + β 2
= 2aeαt cos (βt) − 2beαt sin (βt)
58 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 4
Bode Plots
Introduction
In the following we will present magnitude and phase asymptotic approxima-
tions to a number of basic transfer functions. The value of these asymptotic
approximations is that simpli ed mathematical expressions may be used to pre-
cisely describe the asymptote. In the case of the magnitude characteristic it
is generally displayed with magnitude in dB versus frequency presented on a
log scale. When plotted using these scales, it can be well approximated using
straight line asymptotic segments. It is these segments that exact formulas may
be presented. Note however that annotations on the magnitude plot use the
absolute value rather than the relative value which the dB value represents.
Magnitude in dB is obtained by:
|H (s)|dB = 20 log [H (s)]|s=jω (4.1)
The phase plot is represented by phase angle in degrees versus log frequency.
The phase plot of a transfer function is obtained by setting
√ s = jω where
j= −1, and where ω represents the angular radian frequency. In sections of
ω
this book, we will prefer to use f= 2π when dealing with actual frequencies.
∠H (s) = ∠H (s)|s=jω (4.2)
4.1 Simple Gain
The simplest transfer function is that of constant gain which we will denote
as A, so that the transfer function is given as:
H (s) = A (4.3)
59
In this case the asymptotic and exact magnitude and phase characteristics
are the same and are shown in gure 4.1. As just mentioned above, note that the
magnitude line is annotated with its absolute value, rather than its dB value.
|H(s)|
A
0◦
H(s)
Figure 4.1: Simple Gain
4.2 Pole at Zero
The next transfer function considered is that of a single pole at zero frequency,
as given by:
A
H (s) = (4.4)
s
This transfer function is that of an integrator. The case of a nite pole
frequency dierent than zero is tackled below. The asymptotic magnitude and
phase plots are shown in gure 4.2. With reference to this gure, we can in-
terpret the parameter A as the gain of the transfer function at the angular
frequency of ω = 1.
A
ω
A
|H(s)| −20dB/dec
ω=1
−90◦
H(s)
Figure 4.2: Pole at Zero
60 © Richard Tymerski and Frank Rytkonen, 2017
ωo
Alternatively, this same transfer function may be represented as H (s) = s
where ωo = A. With reference to gure 4.3, we see that ωo may be interpreted
as the value of frequency for which the transfer function has a gain of unity.
ωo
ω
1
|H(s)| −20dB/dec
ω = ωo
Figure 4.3: Pole at Zero
4.3 Zero at Zero
The next transfer function considered is that of a single zero at zero frequency,
as given by:
H (s) = As (4.5)
This transfer function is that of a dierentiator The case of a nite zero
frequency dierent than zero is tackled below. The asymptotic magnitude and
phase plots are shown in gure 4.4. With reference to this gure, we can in-
terpret the parameter A as the gain of the transfer function at the angular
frequency of ω = 1.
+20dB/dec
|H(s)| A
Aω
ω=1
+90◦
H(s)
Figure 4.4: Zero at Zero
© Richard Tymerski and Frank Rytkonen, 2017 61
H (s) = ωso
Alternatively, this same transfer function may be represented as
1
where ωo =
A . With reference to gure 4.5, we see that ωo may be interpreted
as the value of frequency for which the transfer function has a gain magnitude
of unity.
+20dB/dec
|H(s)| 1 ω
ωo
ω = ωo
Figure 4.5: Zero at Zero
4.4 Pole at ωo
The next transfer function considered is that of a single pole at a frequency
of ωo , as given by:
A
H (s) = (4.6)
1 + ωso
The asymptotic magnitude and phase plots are shown in gure 4.6.
A 3dB
Aωo
ω
|H(s)|
ωo
−20dB/dec
◦ 10
0
−45◦
H(s) −45◦ /dec
−90◦
ωo 10ωo
Figure 4.6: Pole at ωo
62 © Richard Tymerski and Frank Rytkonen, 2017
4.5 Zero at ωo
The next transfer function considered is that of a single zero at a frequency
of ωo , as given by:
s
H (s) = A 1 + (4.7)
ωo
The asymptotic magnitude and phase plots are shown in gure 4.7.
Aω
|H(s)| 3dB
ωo
A +20dB/dec
10ωo +90◦
H(s) +45◦
0◦ +45◦ /dec
ωo
10 ωo
Figure 4.7: Zero at ωo
4.6 Right Half Plane Zero at ωo
The next transfer function considered is that of a single right half plane zero
at a frequency of ωo , as given by:
s
H (s) = A 1 − (4.8)
ωo
The asymptotic magnitude and phase plots are shown in gure 4.8.
4.7 Complex Pole Pair with Resonant Frequency
at ωo
The next transfer function considered is that of a complex pole pair with
resonant frequency at ωo , as given by:
A
H (s) = 2 (4.9)
s s
1+ Qωo + ωo
The asymptotic magnitude and phase plots are shown in gure 4.9.
© Richard Tymerski and Frank Rytkonen, 2017 63
Aω
|H(s)| 3dB
ωo
A +20dB/dec
ωo
0◦ 10
−45◦
H(s) −45◦ /dec
−90◦
10ωo
ωo
Figure 4.8: Right Half Plane Zero at ωo
AQ
A
A( ωωo )2
|H(s)|
1
−40dB/dec
10− 2Q ωo
0◦
H(s)
−90◦
−Q × 180◦ /dec −180◦
1
10 2Q ωo
ωo
Figure 4.9: Second Order Complex Pole at ωo
4.8 Complex Zero Pair with Resonant Frequency
at ωo
The next transfer function considered is that of a complex zero pair with
resonant frequency of ωo , as given by:
64 © Richard Tymerski and Frank Rytkonen, 2017
2 !
s s
H (s) = A 1 + + (4.10)
Qωo ωo
The asymptotic magnitude and phase plots are shown in gure 4.10.
40dB/dec
|H(s)| A( ωωo )2
Q
A
A
Q
1
10 2Q ωo
180◦
Q × 180◦ /dec
H(s)
90◦
0◦
1
10− 2Q ωo
ωo
Figure 4.10: Second Order Complex Zero at ωo
4.9 Composite Transfer Functions
Having just presented the asymptotic Bode plots for some basic transfer func-
tion we will next demonstrate how these may be used in constructing asymptotic
Bode plots for more complicated transfer functions. This then will allow form-
ing simpli ed mathematical expressions for magnitude and phase which will be
used in compensator design.
As an example we present the following transfer function:
T
T (s) = o (4.11)
1 + ωs1 1 + ωs2 1+ s
ω3
where
To = 250, ω1 = 2π (10) , ω2 = 2π (100) , ω3 = 2π (300)
© Richard Tymerski and Frank Rytkonen, 2017 65
Somewhat arbitrarily we can identify three constituent basic transfer func-
tions which when multiplied together form the composite transfer function.
To 1 1
T (s) = (4.12)
s s
1+ ω1 1+ ω2 1 + ωs3
| {z } | {z } | {z }
Ta (s) Tb (s) Tc (s)
We will rst construct the magnitude plot. Figure 4.11a shows the asymptotic
response for each of the components. Note that the magnitude annotations are
given in absolute terms so that the composite magnitude is simply the product
of the constituent magnitudes in the relevant frequency interval. In contrast, the
slopes expressed in dB are simply added together. The result of the composite
magnitude is shown in gure 4.11b.
Similarly the constituent phase response is shown in gure 4.12a; and com-
posite phase plot is shown in gure 4.12b.
The nal form of the asymptotic Bode plot is given in its customary form
with magnitude response place above the phase response, shown in gure 4.13.
66 © Richard Tymerski and Frank Rytkonen, 2017
a) f1 f2 f3
To To f1
|Ta (s)| f
−20dB/dec
1 f2
|Tb (s)| f
−20dB/dec
1 f3
|Tc (s)| f
−20dB/dec
b) To To f1
f
To f1 f2
f2
|T (s)|
−20dB/dec
T o f1 f2 f3
f3
−40dB/dec
−60dB/dec
f1 f2 f3 10f1 f3 10f2 10f3
10 10 10
Figure 4.11: a) Asymptotic magnitude plots for the constituent transfer func-
tions, b) Asymptotic magnitude plot for the composite transfer function
© Richard Tymerski and Frank Rytkonen, 2017 67
f1 f2 f3
a) 0◦ −arctan( ff )
1
Ta (s)
−45◦ /dec
−90◦
◦
0
Tb (s) −arctan( ff2 )
−45◦ /dec
◦
−90◦
0
Tc (s) −arctan( ff3 )
−45◦ /dec
0◦
b)
−90◦
T (s) −45◦ /dec
−90◦ /dec
−135◦ /dec
−90◦ /dec
−270◦
◦
−45 /dec
f1 f2 f3 10f1 f3 10f2 10f3
10 10 10
Figure 4.12: a) Asymptotic phase plots for the constituent transfer functions,
b) Asymptotic plot plot for the composite transfer function
68 © Richard Tymerski and Frank Rytkonen, 2017
f1 = 10 f2 = 100 f3 = 300
a) To = 250 To f1
f
To f1 f2
f2
|T (s)|
−20dB/dec
To f1 f2 f3
f3
−40dB/dec
−60dB/dec
0◦
b)
T (s) −45◦ /dec
−90◦ /dec
−135◦ /dec
−90◦ /dec
−270◦
−45◦ /dec
f1 f2 f3
10 10
10f1 f3 10f2 10f3
10
Figure 4.13: Final constructed asymptotic Bode plot showing, a) asymptotic
magnitude response, b) asymptotic phase response
© Richard Tymerski and Frank Rytkonen, 2017 69
4.10 Summary of Bode Plots
70 © Richard Tymerski and Frank Rytkonen, 2017
© Richard Tymerski and Frank Rytkonen, 2017 71
72 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 5
Compensator Design
5.1 Design Procedure
5.1.1 Introduction
In this chapter we will demonstrate a procedure for designing frequency com-
pensators for the standard feedback con guration shown in Figure 5.1. G(s), as
before, represents the plant transfer function; H(s) represents the feedback gain
and is used to set the closed loop gain and Gc (s) represents the compensator.
Figure 5.1: Feedback System Block Diagram
To demonstrate the design procedure, in the sequel we will use a plant and
feedback gain with the following transfer functions:
Go
G (s) = (5.1)
s
1+ ω1 1 + ωs2 1+ s
ω3
H (s) = k (5.2)
where Go = 500, ω1 = 2π (10), ω2 = 2π (100), ω3 = 2π (300), and k = 0.5.
73
The compensators considered in the sequel are the following:
1) Proportional (P) compensator:
Gc (s) = kp (5.3)
2) Dominant pole (I, integrator) compensator:
ωI
Gc (s) = (5.4)
s
3) Dominant pole with zero (PI, proportional plus integrator) compensator:
ωI s
Gc (s) = 1+ (5.5)
s ωz
4) Lead compensator:
s
1+ ωz
Gc (s) = Gco s , ωz < ωp (5.6)
1+ ωp
5) Lead with integrator and zero compensator
s s
ωI 1 + ωz1 1+ ωz2
Gc (s) = (5.7)
s 1 + ωsp
The rst three compensators may be considered to be members of the three
term controller, PID (proportional, integral, derivative), family of compensators.
We will see that as the complexity of the compensator increases the performance
also increases. The performance measures used are the rise time, settling time
and percentage overshoot of the step response. For the simpler compensators,
i.e. proportional and dominant pole compensators, only one design parameter
is needed to be found. For the most involved compensator, the lead with inte-
grator and zero compensator, there are a total of four design parameters to be
determined.
5.1.2 Uncompensated System
We start our evaluation with the uncompensated loop gain T (s) = kGc (s) G (s),
where Gc (s) = 1. The loop gain is given as
T
T (s) = o (5.8)
s
1+ ω1 1 + ωs2 1+ s
ω3
where
To = Go k = 500 · 0.5 = 250
74 © Richard Tymerski and Frank Rytkonen, 2017
f1 f2 f3 fc
a) To To f1
f
T o f1 f2
f2
|T (s)|
−20dB/dec
To f1 f2 f3
f3
1 ⇒ 0dB −40dB/dec
−60dB/dec
0◦
b)
T (s) −45◦ /dec
−90◦ /dec
−135◦ /dec
−180◦
Negative
Phase
Margin
◦
−90 /dec
−270◦
◦
−45 /dec
f1 f2 f3 10f1 f3 10f2 10f3
10 10 10
Figure 5.2: Bode Plot: Uncompensated System
ω1 = 2π (10) , ω2 = 2π (100) , ω3 = 2π (300)
We construct the Bode plot of the loop gain, shown in Figure 5.2. Using this
constructed plot we can easily determine simpli ed (approximate) expressions
© Richard Tymerski and Frank Rytkonen, 2017 75
for the fc , the unity gain crossover frequency, and PM, the phase margin:
To f1 f2 f3 p
3
= 1 =⇒ fc = To f1 f2 f3 (5.9)
fc3
fc fc fc
P M = 180 − arctan − arctan − arctan (5.10)
f1 f2 f3
Equations (5.9) and (5.10) result in fc = 422 Hz and P M = −40◦ .
In a similar fashion we can also determine fGM , the frequency at which the
phase reaches −180◦ , and subsequently the gain margin:
fGM fGM fGM
−180 = − arctan − arctan − arctan (5.11)
f1 f2 f3
To f1 f2
GM = −20 log 2 (5.12)
fGM
Evaluating 5.11 and 5.12 results in fGM = 184 Hz and GM = −17.3 dB,
respectively.
Figure 5.3 is a Matlab Bode plot of the uncompensated loop gain produced
using the 'margin' command. Matlab uses the unapproximated transfer func-
tion models and so is able to accurately determine the margins and associated
frequencies: fc = 385 Hz, P M = −36.1◦ , fGM = 184 Hz and GM = −14.8 dB.
A side by side comparison of these results with those from the asymptotic line
analysis is shown in Table 5.1.
Table 5.1: Uncompensated System margins
PM (◦ ) fC (Hz) GM (dB) fGM (Hz)
Asymptotes -40 422 -17.3 184
Matlab -36.1 385 -14.8 184
The phase margin test indicates that the uncompensated closed loop system is
unstable. A Matlab time domain simulation of the step response of the uncom-
pensated system is shown in Figure 5.4. The output quickly becomes unbounded
for the unit step input indicative of an unstable system. So compensation is
needed to make the system stable and further to improve the performance.
76 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm = −14.8 dB (at 184 Hz) , Pm = −36.1 deg (at 385 Hz)
50
Magnitude (dB)
−50
−100
0
Phase (deg)
−90
−180
−270
−1 0 1 2 3 4
10 10 10 10 10 10
Frequency (Hz)
Figure 5.3: Matlab Analysis of Uncompensated System
79
x 10 Uncompensated System
6
0
Magnitude
−2
−4
−6
−8
−10
0.325 0.33 0.335 0.34 0.345
Time (sec)
Figure 5.4: Matlab Analysis of Uncompensated System
© Richard Tymerski and Frank Rytkonen, 2017 77
5.1.3 Proportional Compensated System
In our rst compensator design we will assess the e cacy of using a propor-
tional compensator:
Gc (s) = kp (5.13)
kp simply represents a constant gain. Note that the eect of varying the value
of kp is to raise and lower the magnitude Bode plot while keeping the phase
plot unaected. So the value of kp can be set to obtain a unity gain crossover
frequency (fc ) which results in an acceptable phase margin.
Generally the design procedure would require that asymptotic Bode plots
for the now compensated loop gain be constructed, however, in the case of a
proportional compensator, since the shape of the plots (magnitude and phase)
are unchanged we need simply to replace any occurrences of the To with kp T o
in Figure 5.2 and proceed accordingly.
As a general rule of thumb, to obtain an acceptable phase margin (generally
45◦ ≤ P M ≤ 60◦ ) one usually sets the unity gain crossover frequency (fc )
to occur in the segment of the asymptotic magnitude plot that has a slope of
−20dB/dec. From the constructed magnitude plot we nd
kp To f1
= 1 =⇒ fc = kp To f1 (5.14)
fc
We can substitute the above equation for fc into the phase margin equation
shown next to determine the required value of kp .
fc fc fc
P M = 180 − arctan − arctan − arctan
f1 f2 f3
kp To f1 kp To f1
= 180 − arctan (kp To ) − arctan − arctan (5.15)
f2 f3
With a desired value of phase margin of P M = 45◦ equation (5.15) evaluates
to kp = 0.0311 and fc = 77.65.
Using the obtained value of kp an evaluation of the compensated loop gain
with the unapproximated transfer functions was performed by Matlab and is
shown in Figure 5.5 where we see that the obtained phase margin is 55◦ . This
value, due to the approximate nature of our design equations, turns out to more
than required, but nonetheless acceptable. Had it not been so, one could simply
iterate.
A step response simulation of the proportional compensated closed-loop sys-
tem is shown in Figure 5.6. A summary of all the performance results (as
furnished by the Matlab stepinfo function) are given in the table 5.2. There
we see in particular that the overshoot, rise-time, settling-time and steady-state
error values are 20%, 2.9 ms, 15.4 ms and −11%, respectively.
78 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm = 15.4 dB (at 184 Hz) , Pm = 54.7 deg (at 63.4 Hz)
50
Magnitude (dB)
−50
−100
−150
0
Phase (deg)
−90
−180
−270
−1 0 1 2 3 4
10 10 10 10 10 10
Frequency (Hz)
Figure 5.5: Matlab Proportional Compensated Loop Gain Bode Plot
Proportional Compensation
2.5
1.5
Magnitude
0.5
0
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035
Time (sec)
Figure 5.6: Step Response of Proportional Compensated Closed-Loop System
© Richard Tymerski and Frank Rytkonen, 2017 79
Table 5.2: Proportionally Compensated System Performance Features
Proportional Compensation
Characteristics Value
Overshoot 20 %
Rise time 2.9 ms
Settling time 15.4 ms
Steady-state error −11 %
Bandwidth 63 Hz
Phase margin 55◦
Gain margin 15 dB
5.1.4 Dominant Pole Compensated System
The next form of frequency compensation to be discussed is the dominant
pole compensation. As the name suggests a pole is inserted in the loop gain
which dominates the dynamics of the loop. That is to say that the frequency
response of the loop gain up to the unity gain crossover frequency is mainly
determined by the dominant pole. To achieve this the pole needs to be placed
at a frequency much lower (usually a decade or so) than the lowest pole or zero
of the uncompensated loop gain. This requirement unfortunately reduces the
loop bandwidth and subsequently the speed of response. However, compensator
design is simpli ed and good stability margins may be easily obtained. If the
pole is placed at zero frequency then this represents an integrator which may
result in obtaining a zero steady state error characteristic.
In the design that follows, an integrator is employed so that the compensator
transfer function is given by:
ωI
Gc (s) =
s
where ωI = 2π · fI is an appropriately chosen design constant. It represents
the frequency (in Hz) at which the compensator gain is at unity. Figure 5.7
shows the Bode plot asymptotes for the magnitude and phase of this compen-
sator.
Design of the compensator now consists of selecting an appropriate compen-
sator parameter, fI .
Figure 5.8 shows the graphical construction of the phase asymptotes for the
loop gain with the compensator. Note that because the plant's transfer func-
tion is third order (with no zeros), it features a phase shift of −270◦ at high
frequencies. Also, since the next higher frequency f2 ≥ 10 · f1 the phase shift
at f1 is −45◦ . Furthermore, the compensator contributes its own −90◦ phase
shift and does so for all frequencies. Consequently, the total phase shift of the
80 © Richard Tymerski and Frank Rytkonen, 2017
fI
f
| ωsI |
−20dB/dec
1 ⇒ 0dB
fI
ωI
s −90◦
Figure 5.7: Bode Plot: Dominant Pole Compensator
compensated open loop transfer function at f1 is −135◦ . Consequently, in this
design the frequency f1 is chosen to be the unity gain crossover frequency of the
overall system, so that we get a +45◦ phase margin.
Figure 5.9 shows how the plant and compensator transfer functions combine
to produce the magnitude response of the compensated loop. To achieve a phase
margin that is +45◦ , we require the magnitude at f1 to equal 1 (0dB), therefore
fc = f1 .
fI To
=1
f1
f1 10
fI = = = 0.04
To 250
The dominant pole compensator in this case is:
ωI 2π · 0.04
Gc (s) = =
s s
Figure 5.10 shows resulting gain and phase asymptotic construction of the
Bode plot. We next run the full unapproximated compensated loop transfer
function through the Matlab 'margin' command to verify the design results.
Figure 5.11 shows the results obtained. In particular, a phase margin of PM =
45.9◦ with a unity gain crossover frequency fc = 7.84 Hz was obtained, which
◦
compares favorably with the design values of P M = 45 and fc = f1 = 10 Hz.
Figure 5.12 shows the unit step response of the dominant pole compensated
closed loop system. It is clearly seen that zero steady state response has been
attained but not without going through signi cant overshoot rst. The features
of the closed loop system are summarized in the Table 5.3.
© Richard Tymerski and Frank Rytkonen, 2017 81
Table 5.3: Dominant Pole Compensated System Features
Dominant Pole Compensation
Characteristics Value
Peak amplitude 22.2% overshoot
Rise time 24.7 ms
Settling time 134 ms
Steady-state error 0 %
Bandwidth 7.84 Hz
Phase margin 45.9◦
Gain margin 18.2 dB
5.1.5 Dominant Pole Compensated System with zero
The dominant pole compensator of the previous section, while stable and
featuring zero steady state error performance, exhibits several undesirable char-
acteristics which include a large overshoot and long settling time. In our eort
to achieve stability, we have sacri ced the bandwidth of the system. Unfortu-
nately, the lower the bandwidth, the slower the response. Thus, we need to
increase the bandwidth to speed up the response. This can be done by adding a
zero to the compensator that will cancel the lowest frequency pole of the plant.
By doing this, the canceled pole no longer aects the phase lag seen at the gain
crossover frequency. For our system a the 10 Hz pole is canceled so that the
remaining poles at 100 and 300 Hz are now the poles which limit the bandwidth.
Accordingly we will be able to extend the bandwidth by a decade.
The transfer function for the new compensator is given by
ωI s
Gc (s) = 1+
s ωz
where
ωz = ω1
The compensated loop gain T (s) = kGc (s)G(s) with this compensator now
becomes:
To ωI
T (s) =
s s
s 1+ ω2 1+ ω3
The construction of the compensated magnitude plot is shown in Figure 5.13
where the uncompensated plant and compensator magnitude asymptotes are
combined. The nal magnitude and phase plots using the asymptotic construc-
tion procedure is shown in Figure 5.14. Using the low frequency magnitude
asymptote we see that at the unity gain crossover frequency fc
82 © Richard Tymerski and Frank Rytkonen, 2017
To fI
=1
fc
=⇒ fc = To fI (5.16)
The general expression for φf , the phase response at an arbitrary frequency
f is given by:
f f
φf = −90 − arctan − arctan (5.17)
f2 f3
Consequently the phase margin is given by:
P M = 180 + φfc
fc fc
= 90 − arctan − arctan
f2 f3
To fI To fI
= 90 − arctan − arctan (5.18)
f2 f3
With a design value of P M = 45◦ the required value of fI is solved using
Equation (5.18) to yield fI = 0.258 so that ωI = 2πfI = 1.623. This results,
using (5.16), in a gain crossover frequency, fc = 64.58 Hz.
To verify the design procedure the unapproximated loop gain transfer function
is run through the Matlab 'margin' command which produces the plot shown
in Figure 5.15. The obtained phase margin and bandwidth are seen to be
P M = 51◦ and fc = 56 Hz. The bandwidth has been greatly improved.
The unit step response of the closed loop system is shown in Figure 5.16. A
summary of the performance using this compensator is shown in Table 5.4.
Table 5.4: Dominant Pole with Zero Compensated System Features
Dominant Pole with Zero Compensation
Characteristics Value
Overshoot 22.2%
Rise time 3.05 ms
Settling time 16.7 ms
Steady-state error 0 %
Bandwidth 62.3 Hz
Phase margin 46.3 degree
Gain margin 14.5 dB
© Richard Tymerski and Frank Rytkonen, 2017 83
5.1.6 Dominant Pole Compensated System with zero, im-
proved phase margin
The addition of the zero to dominant pole compensation has allowed us to
increase the speed of response by extending bandwidth. This is manifested in
the time domain response by a substantial decrease in the rise and settling times.
However, the overshoot, while slightly improved, may be seen as overly large.
Nevertheless, it too may be reduced by appreciating the fact that overshoot and
phase margin are inversely related. So we will increase the phase margin to
reduce the overshoot.
Using the same compensator as in the previous section, we will now redesign
it to achieve a phase margin of 60◦ . The zero frequency is left unchanged, so
that fz = f1 , but a new value of fI will be determined to achieve the desired 60◦
phase margin. Solving equation (5.18), now with P M = 60 we see the required
value of fI = 0.1636 so that ωI = 2πfI = 1.0276.
To verify the design the Bode plot of the loop gain was produced using the
'margin' command in Matlab. This plot is shown in gure 5.17. We see that
a phase margin of 62◦ was achieved with a bandwidth of 37.9 Hz. Of course
the extension in phase margin is necessarily accompanied by a reduction in
bandwidth.
The step response of the closed loop system is shown in Figure 5.18. The
resulting performance characteristics are tabulated in the Table 5.5. There we
see that the overshoot has been reduced to 4.46%. Recall that a phase margin of
45◦ had previously resulted in a 17% overshoot. This reduction in overshoot has
been attained at the expense of an increase in rise time. However, the settling
time has been slightly reduced.
Table 5.5: Dominant Pole with Zero (Improved PM) Compensated System Fea-
tures
Dominant Pole with Zero Compensation (Improved Margin)
Characteristics Value
Overshoot 4.46 %
Rise time 5.81 ms
Settling time 16.5 ms
Steady-state error 0
Bandwidth 35.1 Hz
Phase margin 64 degree
Gain margin 20.6 dB
84 © Richard Tymerski and Frank Rytkonen, 2017
5.1.7 Lead Compensated System
Next we consider the case of using a lead compensator, the transfer function
of which is given by:
s
1+ ωz
Gc (s) = Gco s , ωz < ωp (5.19)
1+ ωp
The design of this compensator requires the appropriate determination of the
three variables, Gco , fz and fp , the low frequency gain, zero frequency and pole
frequency, respectively. Note in particular that the zero frequency is required to
be at a lower value than the pole frequency. This constraint exists so that the
phase response, rst starting at zero at low frequencies, becomes positive, i.e.
leads, as the frequency increases before returning to zero at high frequencies. In
essence, the lead compensator provides a phase boost that is adjustable based
on the pole and zero frequencies. The maximum phase boost φmax possible is
φmax = 90◦ and occurs at a frequency fφmax which is the geometric mean of
the zero and pole frequencies of the compensator. The geometric mean of two
numbers represents the midpoint between these numbers when represented on
a logarithmic scale.
p
fφmax = fz fp (5.20)
The compensator also provides a gain boost at higher frequencies so that
with proper design it can both extend loop bandwidth while increasing the
phase margin. Proper design of the compensator requires that the frequency of
maximum boost aorded by this compensator is set to the unity gain crossover
frequency, fc . The asymptotic Bode plot of the lead compensator is shown in
Figure 5.19.
When the compensator is placed in the loop, the loop gain of the system now
becomes:
To Gco 1 + ωsz
T (s) =
1 + ωsp 1 + ωs1 1 + ωs2 1+ s
ω3
The construction of the asymptotic magnitude response from the constituent
parts is shown in Figure 5.20. Both the resulting magnitude and phase asymp-
totic responses of the loop gain are shown in Figure 5.21. As for previous
compensators, the annotations on these plots are used in the design procedure.
The exact expression for the phase φ is given by:
© Richard Tymerski and Frank Rytkonen, 2017 85
f f f
φf = arctan − arctan − arctan
fz fp f1
f f
− arctan − arctan (5.21)
f2 f3
Consequently the phase margin is given by:
P M = 180 + φfc
fc fc fc
= 180 + arctan − arctan − arctan
fz fp f1
fc fc
− arctan − arctan (5.22)
f2 f3
As mentioned previously, we will set the unity gain crossover frequency fc
to the maximum phase boost frequency fφmax so that using equation (5.20) we
have:
fc = fφmax
p
= fz fp (5.23)
In order to minimize the eect on the phase margin of the phase lag due
to the compensator pole we will set this pole frequency an order of magnitude
above the crossover frequency:
fp = 10fc (5.24)
Equation (5.24) together with equation (5.23) results in a relationship be-
tween the zero and pole frequencies of the compensator:
fp = 100fz (5.25)
We can use the zero frequency of the compensator to cancel the pole fre-
quency f2 of the plant, so that fz = f2 . This together with equations (5.25)
and (5.22) may be used to determine the unity gain crossover frequency, fc , for
a given desired phase margin. For a margin of 60◦ we nd fc = 187 Hz.
From the magnitude asymptote we see that
To Gco f1
=1 (5.26)
fc
so that for a given fc we can solve for the required compensator low frequency
gain Gco :
fc
Gco = (5.27)
To f1
For our design we obtain a value of Gco = 0.0749.
86 © Richard Tymerski and Frank Rytkonen, 2017
To verify our design we produce the plot using the Matlab 'margin' command
on the unapproximated transfer functions of the compensated loop. This is show
in gure 5.22. There we nd that the obtained phase margin is P M = 63.9◦
with fc = 164 Hz, which validates our design procedure.
The unit step response of the closed loop system with this compensation is
shown in gure 5.23. The features of the step response are presented in the
Table 5.7. We see, due to the extended bandwidth, that the speed of response,
represented by the rise and settling times is quite good. Percentage overshoot
is also relatively low due to the 60◦ phase margin employed. However, as there
is no longer an integrator in the forward path, the steady state error is now
non-zero. This will be remedied in the next and nal compensator design.
Table 5.6: Lead Compensation
Lead Compensation
Feature Value
Overshoot 4.23 %
Rise time 2.25 ms
Settling time 6.29 ms
Steady-state error 10%
Bandwidth 83.8 Hz
Phase margin 71.2◦
Gain margin 19.3 dB
5.1.8 Lead Compensated System with integrator and zero
In this nal compensator design, we will augment the lead compensator of
the previous section with an integrator and zero. The integrator is added to
provide the closed loop system with a zero steady state error performance. This
is contrasted with the approach previously discussed where the integrator was
primarily used to as the dominant pole. In the present case by canceling lower
frequency poles, we're able to extend the unity gain bandwidth of the loop
gain to obtain quick closed loop response. The zero is added to leave the high
frequency magnitude and phase response unchanged from the lead compensator
case.
The transfer function of the compensator considered here is given by:
s s
ωI 1 + ωz1 1+ ωz2
Gc (s) = (5.28)
s 1 + ωsp
The parameters ωz2 and ωp correspond to ωz and ωp of the lead compensator
design, which leaves ωI and ωz1 to be determined. ωz1 can be simply set to ω1 .
© Richard Tymerski and Frank Rytkonen, 2017 87
The low frequency gain of the lead compensator of the previous section was
denoted Gco . This was the value of the loop magnitude at f1 (in particular, and
below this frequency, in general). To maintain this value of gain at f1 we will
adjust ωI to achieve this. The low frequency magnitude asymptote is given by
fI
f so that at f1 we have
fI
= Gco =⇒ fI = Gco f1 (5.29)
f1
This completes the design of this compensator. To verify our design we
produce the plot using the Matlab 'margin' command on the unapproximated
transfer functions of the compensated loop. This is show in gure 5.24. There
we nd that the obtained phase margin is P M = 60◦ with fc = 164 Hz, which
very closely agrees with the results obtained for the lead compensator.
Next, we exam the step response of the closed loop system which is shown in
5.25. It is clear that now we have zero steady state error. Further performance
features are given in the table below.
Table 5.7: Lead Compensation with integrator and zero
Lead Compensation with integrator and zero
Feature Value
Overshoot 4.23 %
Rise time 2.25 ms
Settling time 6.29 ms
Steady-state error 10%
Bandwidth 83.8 Hz
Phase margin 71.2◦
Gain margin 19.3 dB
5.1.9 Summary
The following table shows the summary of all of the results.
88 © Richard Tymerski and Frank Rytkonen, 2017
f1 f2 f3
0◦
a)
−45◦ /dec
T (s)U N COM P
−90◦ /dec
−135◦ /dec
−180◦
b) −90◦ /dec
−270◦
ωI −45◦ /dec
s −90◦
−90◦
c)
T (s) −45◦ /dec
−90◦ /dec
−135◦ /dec
−270◦
−90◦ /dec
−360◦
◦
−45 /dec
f1 f2 f3 10f1 f3 10f2 10f3
10 10 10
Figure 5.8: Dominant Pole: Phase Construction
© Richard Tymerski and Frank Rytkonen, 2017 89
f1 = fc f2 f3
a) To To f1
f
T o f1 f2
f2
|T (s)U N COM P |
−20dB/dec
To f1 f2 f3
f3
1 ⇒ 0dB −40dB/dec
−60dB/dec
b) fI
f
1 ⇒ 0dB
| ωsI | fI
−20dB/dec
To fI
c) f
1 ⇒ 0dB
−20dB/dec To f1 fI
f2
|T (s)| T o f1 f2 fI
f3
−40dB/dec
−60dB/dec To f1 f2 f3 fI
f4
−80dB/dec
Figure 5.9: Dominant Pole: Magnitude Construction
90 © Richard Tymerski and Frank Rytkonen, 2017
f1 = fc f2 f3
T o fI
a) f
1 ⇒ 0dB
−20dB/dec To f1 fI
f2
|T (s)| T o f1 f2 fI
f3
−40dB/dec
To f1 f2 f3 fI
−60dB/dec f4
−80dB/dec
−90◦
c)
T (s) −45◦ /dec
Phase
Margin
−180◦
−90◦ /dec
−135◦ /dec
−270◦
−90◦ /dec
−360◦
◦
−45 /dec
f1 f2 f3 10f1 f3 10f2 10f3
10 10 10
Figure 5.10: Dominant Pole Compensated System
© Richard Tymerski and Frank Rytkonen, 2017 91
Bode Diagram
Gm = 18.2 dB (at 27.1 Hz) , Pm = 45.9 deg (at 7.84 Hz)
50
Magnitude (dB) −50
−100
−150
−200
−90
Phase (deg)
−180
−270
−360
−1 0 1 2 3 4
10 10 10 10 10 10
Frequency (Hz)
Figure 5.11: Matlab Analysis of Dominant Pole Compensated System
Dominant Pole Compensation
2.5
1.5
Magnitude
0.5
0
0 0.05 0.1 0.15 0.2 0.25 0.3
Time (sec)
Figure 5.12: Step Response of the Dominant Pole Compensated System
92 © Richard Tymerski and Frank Rytkonen, 2017
f1 = fz f2 f3
a)
To To f1
f
T o f1 f2
f2
|T (s)U N COM P |
−20dB/dec
To f1 f2 f3
f3
1 ⇒ 0dB −40dB/dec
−60dB/dec
b) fI
f
fI
|GC (s)| f1
−20dB/dec
c) To fI
f
−20dB/dec
T o fI f2
f2 1 ⇒ 0dB
|T (s)| T o fI f2 f3
f3
−40dB/dec
−60dB/dec
Figure 5.13: Dominant Pole with Zero Magnitude Construction
© Richard Tymerski and Frank Rytkonen, 2017 93
f1 fc f2 f3
a) To fI
f
−20dB/dec
To fI f2
f2 1 ⇒ 0dB
|T (s)| To fI f2 f3
f3
−40dB/dec
−60dB/dec
b) −90◦
−45◦ /dec
T (s)
Phase
Margin
◦
−180
−90◦ /dec
−270◦
◦
−45 /dec
Figure 5.14: Dominant Pole with Zero Compensated System
94 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm = 15.8 dB (at 173 Hz) , Pm = 50.5 deg (at 55.5 Hz)
100
50
Magnitude (dB)
−50
−100
−150
−90
Phase (deg)
−135
−180
−225
−270
−1 0 1 2 3 4
10 10 10 10 10 10
Frequency (Hz)
Figure 5.15: Loop Gain and Phase Response of the Dominant Pole Compensated
System with Zero
Dominant Pole With Zero Compensation
2.5
1.5
Magnitude
0.5
0
0 0.005 0.01 0.015 0.02 0.025 0.03
Time (sec)
Figure 5.16: Step Response of the Dominant Pole with Zero Compensated Sys-
tem
© Richard Tymerski and Frank Rytkonen, 2017 95
Bode Diagram
Gm = 19.8 dB (at 173 Hz) , Pm = 62 deg (at 37.9 Hz)
100
50
Magnitude (dB) 0
−50
−100
−150
−90
Phase (deg)
−135
−180
−225
−270
−1 0 1 2 3 4
10 10 10 10 10 10
Frequency (Hz)
Figure 5.17: Matlab Analysis of Dominant Pole Compensated System with Zero
(Improved Margin)
Dominant Pole With Zero Compensation (Improved PM)
2.5
1.5
Magnitude
0.5
0
0 0.005 0.01 0.015 0.02 0.025 0.03
Time (sec)
Figure 5.18: Step Response of the Dominant Pole with Zero Compensated Sys-
tem (Improved Margin)
96 © Richard Tymerski and Frank Rytkonen, 2017
Gco ffpz
a) Gco ffz
|Gc (s)|
Gco
20dB/dec
p
fz fp
b)
45◦ /dec −45◦ /dec
Gc (s)
0◦ 0◦
fz fp
fz fp fc 10fz 10fp
10 10
Figure 5.19: Bode Diagram: Lead Compensator
© Richard Tymerski and Frank Rytkonen, 2017 97
f1 = fz f2 f3 fp
a)
To To f1
f
T o f1 f2
f2
|T (s)U N COM P |
−20dB/dec
To f1 f2 f3
f3
1 ⇒ 0dB −40dB/dec
−60dB/dec
b) Gco ff2 Gco ffp2
|Gc (s)| Gco
20dB/dec
c)
To Gco To Gco f1
f
|T (s)| To Gco f1 f2
f2
−20dB/dec
−40dB/dec 1 ⇒ 0dB
To Gco f1 f3 fp
f3
−60dB/dec
Figure 5.20: Lead Compensation Magnitude Construction
98 © Richard Tymerski and Frank Rytkonen, 2017
f1 f2 fc f3 fp
a)
To Gco To Gco f1
f
|T (s)U N COM P | To Gco f1 f3
1 ⇒ 0dB f2
−20dB/dec
−40dB/dec
To Gco f1 f3 fp
f3
−60dB/dec
0◦
b)
T (s) −45◦ /dec
−90◦ /dec
−135◦ /dec
Phase
Margin −180◦
−90◦ /dec −270◦
−45◦ /dec
f1 f3 fp 10f1 10f3 10fp
10 10 10
Figure 5.21: Lead Compensated System
© Richard Tymerski and Frank Rytkonen, 2017 99
Bode Diagram
Gm = 35.1 dB (at 1.76e+03 Hz) , Pm = 63.9 deg (at 164 Hz)
40
20
Magnitude (dB)
0
−20
−40
−60
−80
0
−45
Phase (deg)
−90
−135
−180
−225
−1 0 1 2 3 4
10 10 10 10 10 10
Frequency (Hz)
Figure 5.22: Matlab Analysis of Lead Compensated System
Lead Compensation
2.5
1.5
Magnitude
0.5
0
0 1 2 3 4 5 6 7 8
Time (sec) −3
x 10
Figure 5.23: Step Response of the Lead Compensated System
100 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm = 34.8 dB (at 1.73e+03 Hz) , Pm = 60.4 deg (at 164 Hz)
100
Magnitude (dB)
50
−50
−100
−90
Phase (deg)
−135
−180
−225
−1 0 1 2 3 4
10 10 10 10 10 10
Frequency (Hz)
Figure 5.24: Matlab Analysis of Lead Compensated System with integrator and
zero
Combined Compensator
2.5
1.5
Magnitude
0.5
0
0 1 2 3 4 5 6 7 8
Time (sec) −3
x 10
Figure 5.25: Step Response of the Lead Compensated System with integrator
and zero
© Richard Tymerski and Frank Rytkonen, 2017 101
Table 5.8: Summary of Compensators
G (s) = Go
1+ ωs 1+ ωs 1+ ωs
1 2 3
H (s) = k
where Go = 500, ω1 = 2π (10), ω2 = 2π (100), ω3 = 2π (300), and k = 0.5.
Gc (s) Gc (s) fc φP M GM OS tr ts ERR
parameters (Hz) (deg) (dB) (%) (ms) (ms) (%)
1 (uncompensated) none 385 −36 −15 na na na ∞
kp kp = 0.03 63 55 15 20 2.9 15.4 −11
ωI
s ωI = 0.25 7.8 46 18 22 25 137 0
ωI s
s
1+ ωz
ωI = 1.62 56 51 16 17 34 18 0
ωz = 2π(10)
ωI s
s
1+ ωz
ωI = 1.03 38 62 20 6 5.3 16 0
ωz = 2π(10)
s
1+
Gco 1+ ωsz Gco = 0.075 164 64 35 8.1 1.3 3.9 -5
ωp
ωz = 2π(100)
ωp = 2π(10, 000)
ωI 1+ ωsz 1+ ωsz
1 2 ωI = 4.71 164 60 35 8.3 1.3 4 0
s
s 1+ ωp ωz1 = 2π(10)
ωz2 = 2π(100)
ωp = 2π(10, 000)
102 © Richard Tymerski and Frank Rytkonen, 2017
5.1.10 MATLAB Code
1 function compensators
2
3 clear all;
4 close all;
5
6 t = linspace(0, 0.35, 10000);
7 f = logspace(−1, 4, 1000);
8 w = 2*pi*f;
9 s = tf('s');
10
11 Go = 500;
12 f1 = 10;
13 f2 = 100;
14 f3 = 300;
15
16 w1 = 2*pi*f1;
17 w2 = 2*pi*f2;
18 w3 = 2*pi*f3;
19 k = 0.5;
20 To = Go*k;
21 yf = 2;
22
23 %====================================================================
24 %====================================================================
25 % UNCOMPENSATED
26 %====================================================================
27
28 G = Go/((1+s/w1)*(1+s/w2)*(1+s/w3));
29
30 titl = 'Uncompensated System';
31 Gc = 1;
32
33 xlmt = [0.325 0.35];
34 disp(titl)
35 analysis(Gc, G, k, w, titl, t, xlmt, yf)
36
37 % RiseTime: 0.0031
38 % SettlingTime: 0.3500
39 % SettlingMin: −9.9007e+79
40 % SettlingMax: −8.9587e+79
41 % Overshoot: 0
42 % Undershoot: 55.0478
43 % Peak: 9.9007e+79
44 % PeakTime: 0.3500
45
46 %====================================================================
47 %====================================================================
48 % Proportional Compensation
49 %====================================================================
50
51 fn = @(kp) 135 − atand(To*f1*kp/f1) − atand(To*f1*kp/f2) ...
52 − atand(To*f1*kp/f3);
53
54 kp = fzero(fn, 0) % kp = 0.0311
© Richard Tymerski and Frank Rytkonen, 2017 103
55 fc = To*f1*kp % fc = 77.6459
56
57 titl = 'Proportional Compensation';
58 Gc = kp;
59
60 xlmt = [0 0.035];
61 disp(titl)
62 analysis(Gc, G, k, w, titl, t, xlmt, yf)
63
64 % RiseTime: 0.0029
65 % SettlingTime: 0.0154
66 % SettlingMin: 1.6011
67 % SettlingMax: 2.1341
68 % Overshoot: 20.4502
69 % Undershoot: 0
70 % Peak: 2.1341
71 % PeakTime: 0.0068
72
73 %====================================================================
74 %====================================================================
75 % Dominant Pole Compensation
76 %====================================================================
77
78 titl = 'Dominant Pole Compensation';
79 wI = w1/To % 0.2513
80 Gc = wI/s;
81
82 xlmt = [0 0.3];
83 disp(titl)
84 analysis(Gc, G, k, w, titl, t, xlmt, yf)
85
86 % RiseTime: 0.0245
87 % SettlingTime: 0.1365
88 % SettlingMin: 1.8000
89 % SettlingMax: 2.4440
90 % Overshoot: 22.2103
91 % Undershoot: 0
92 % Peak: 2.4440
93 % PeakTime: 0.0580
94
95 %====================================================================
96 %====================================================================
97 % Dominant Pole With Zero Compensation
98 %====================================================================
99
100 titl = 'Dominant Pole With Zero Compensation';
101
102 fn = @(fI) 45 − atand(To*fI/f2) − atand(To*fI/f3);
103 fI = fzero(fn, 0)
104
105 fc = To*fI % 64.58
106 wI = 2*pi*fI % 1.623
107 Gc = wI/s*(1+s/w1);
108
109
110 xlmt = [0 0.030];
111 disp(titl)
104 © Richard Tymerski and Frank Rytkonen, 2017
112 analysis(Gc, G, k, w, titl, t, xlmt, yf)
113
114 % RiseTime: 0.0034
115 % SettlingTime: 0.0175
116 % SettlingMin: 1.8012
117 % SettlingMax: 2.3496
118 % Overshoot: 17.4798
119 % Undershoot: 0
120 % Peak: 2.3496
121 % PeakTime: 0.0079
122
123 %====================================================================
124 %====================================================================
125 % Dominant Pole With Zero Compensation (Improved Phase Margin)
126 %====================================================================
127
128 titl = 'Dominant Pole With Zero Compensation (Improved PM)';
129
130 fn = @(fI) 30 − atand(To*fI/f2) − atand(To*fI/f3);
131 fI = fzero(fn, 0)
132
133 fc = To*fI % 40.88
134 wI = 2*pi*fI % 1.0276
135 Gc = wI/s*(1+s/w1);
136
137 xlmt = [0 0.03];
138 disp(titl)
139 analysis(Gc, G, k, w, titl, t, xlmt, yf)
140
141 % RiseTime: 0.0053
142 % SettlingTime: 0.0159
143 % SettlingMin: 1.8014
144 % SettlingMax: 2.1219
145 % Overshoot: 6.0951
146 % Undershoot: 0
147 % Peak: 2.1219
148 % PeakTime: 0.0113
149
150 %====================================================================
151 %====================================================================
152 % Lead Compensation
153 %====================================================================
154
155 fz = 100 % = f2
156 fp = 100*fz
157 fn = @(fc) 120 + atand(fc/fz) − atand(fc/f1) ...
158 − atand(fc/f2) − atand(fc/f3) − atand(fc/fp);
159 fc = fzero(fn, 0) % 187
160 Gco = fz*fc/(To*f1*f2) % 0.0749
161 wz = 2*pi*fz;
162 wp = 2*pi*fp;
163
164 titl = 'Lead Compensation';
165 Gc = Gco*(1+s/wz)/(1+s/wp);
166
167 xlmt = [0 0.008];
168 disp(titl)
© Richard Tymerski and Frank Rytkonen, 2017 105
169 analysis(Gc, G, k, w, titl, t, xlmt, yf)
170
171 % RiseTime: 0.0013
172 % SettlingTime: 0.0039
173 % SettlingMin: 1.7192
174 % SettlingMax: 2.0517
175 % Overshoot: 8.0633
176 % Undershoot: 0
177 % Peak: 2.0517
178 % PeakTime: 0.0027
179
180 %====================================================================
181 %====================================================================
182 % Combined Compensation
183 %====================================================================
184
185 titl = 'Combined Compensator';
186 % fc, unity gain xover frequency: same value as for lead compensator
187 wI = 2*pi*fc/To % 4.7
188 wz1 = w1;
189 wz2 = w2;
190 % wp: use the same value as for lead compensator
191 Gc = wI*(1+s/wz1)*(1+s/wz2)/(s*(1+s/wp));
192
193 xlmt = [0 0.008];
194 disp(titl)
195 analysis(Gc, G, k, w, titl, t, xlmt, yf)
196
197 % RiseTime: 0.0013
198 % SettlingTime: 0.0040
199 % SettlingMin: 1.8121
200 % SettlingMax: 2.1662
201 % Overshoot: 8.3110
202 % Undershoot: 0
203 % Peak: 2.1662
204 % PeakTime: 0.0027
205 end
206
207
208 function s = analysis(Gc, G, k, w, titl, t, xlmt, yf)
209
210 % loop gain
211 L = Gc*G*k;
212
213 figure
214 [mag, phase] = bode(L,w);
215 margin(mag, phase, w);
216
217 h = gcr;
218 h.AxesGrid.Xunits = 'Hz';
219 h.AxesGrid.TitleStyle.FontSize = 12;
220 h.AxesGrid.XLabelStyle.FontSize = 12;
221 h.AxesGrid.YLabelStyle.FontSize = 12;
222
223 %======================================
224
225 % closed loop gain
106 © Richard Tymerski and Frank Rytkonen, 2017
226 Gs = 1/k * L/(1+L);
227
228 % Plot of Step response results
229 figure
230 yout = step(Gs, t);
231 plot(t, yout);
232 grid on;
233 title(titl,'FontSize',12);
234 xlabel('Time (sec)','FontSize',12);
235 ylabel('Magnitude','FontSize',12);
236 xlim(xlmt);
237
238 % Time Domain Analysis Parameters
239 s = stepinfo(yout,t);
240 ss_error = (yout(end)−yf)/yf * 100
241 end
© Richard Tymerski and Frank Rytkonen, 2017 107
108 © Richard Tymerski and Frank Rytkonen, 2017
Part II
Classical Control: Application
109
Chapter 6
Modelling - Introduction
6.1 Introduction
In the following chapters we will present a simple practical system to which we
will apply precise control. This system is a dc-to-dc power converter for which
we desire to have accurate control of the output voltage as it will function as a
voltage regulator subject to input voltage and output load variations.
thus we start with a plant which is given as a circuit con guration for which
we need to derive a model, which in the case of the classical control design
approach we will be applying, will need to be a transfer function model. Using
this model a compensator transfer function will be designed and subsequently
the closed loop performance will be simulated.
To fully verify the practical design a number of extra steps will need to be
undertaken. This involves actual realization of the compensator transfer func-
tion into an appropriate circuit which is then used in a circuit level simulation
to assess the performance achieved. If deemed not satisfactory then this process
may be iterated. This procedure is represented in the ow chart shown in Figure
6.1.
111
Figure 6.1: Design Flow Diagram
112 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 7
The System
7.1 Introduction
In this chapter, the parameters for an example control system will be de ned
and derived. From the parameters of this example system, subsequent chap-
ters will be devoted to applying control design techniques to optimize system
performance parameters.
A control system begins with a model for plant, that has at least one particular
parameter to be controlled. To control the plant, the parameter to be controlled
is compared to a stable reference value and the dierence is input to an error
ampli er. The error ampli er then commands the plant, controlling the desired
plant parameter. A basic diagram illustrating this architecture is shown in
Figure 7.1.
Compensator Plant
Figure 7.1: Feedback System Block Diagram
113
7.2 The Plant: Buck Converter
7.2.1 Introduction
The fundamental item in every control system is the plant, the item that is to
be controlled. In this section, the plant will be de ned as a buck converter, a
switched mode DC power supply.
Figure 7.2: Buck Converter Circuit System Diagram
The buck regulator, which is shown complete in Figure 7.2 including circuit
losses and feedback compensation, is a basic switched mode power supply. The
buck regulator acts to reduce the steady state output voltage based on an applied
duty cycle of applied input voltage. The duty cycle is switched at a frequency
higher than the resonant frequency LC tank on the output. The output lter
allows the circuit to convert the input voltage to a lower output voltage with
minimal circuit losses.
The complete system block diagram for the buck regulator is shown in Fig-
ure 7.4. The output voltage of the system is fed back to a reference (reduced by
H(s)), and the dierence (error signal) is fed to a compensator which drives a
pulse-width modulator to control the output voltage. Additionally, this model
includes disturbance inputs in terms of step loading and input voltage variation
for design characterization.
7.2.2 Transfer Function Derivations
To model the plant based on the diagram of Figure 7.4, three transfer functions
are required to be derived. The transfer function are the control to output
Gvd (s), input voltage to output Gvg (s), and the output current to output
114 © Richard Tymerski and Frank Rytkonen, 2017
Figure 7.3: Simpli ed System Diagram
Figure 7.4: Generalized Power System Model
voltage, or open loop output impedance Zout (s). Additional transfer functions
will be derived in the section, such as the control to inductor current Gid (s),
output current to inductor current Gii (s), and the input voltage to inductor
current Givg (s). These transfer functions will be utilized in following chapters.
Using the state space analysis approach, the complete set of transfer functions
will be derived for the buck converter shown in Figure 7.5.
Gvd (s) Analysis
To analyze the small signal control to output transfer function of the buck
converter, an output load change is modeled with a current source, as shown in
Figure 7.5. In terms of the state space analysis, this additional source will be
modeled as another input variable to the system.
© Richard Tymerski and Frank Rytkonen, 2017 115
Figure 7.5: Buck Converter Circuit with Non-Ideal Circuit Elements
Listed below are the fundamental equations for state space analysis. x de nes
the state variables of the system and the u variables de ne the inputs. The
number of states is de ned by the number of storage elements in the system.
For the buck converter, there are two states. The output voltage of the converter
is the voltage across the capacitor and the corresponding parasitic resistance.
i
x=
v
vg
u=
io
x˙ = Ax + Bu
y = Cx + Eu
Applying the principles of superposition to the buck converter, the capacitor
current and inductor voltage equations are found and summarized below for
both switch positions.
During DTs,
diL R
L = −(rl + rc || R)iL − Vc + Vg + Io (R || rc )
dt R + rc
dVc R 1 R
C = iL − Vc + 0Vg − Io
dt R + rc R + rl R + rc
R
Vout = (rc || R) iL + Vc + 0Vg − (R || rc ) Io
R + rc
116 © Richard Tymerski and Frank Rytkonen, 2017
Figure 7.6: Buck Converter Superposition Analysis: DTs
During D'Ts,
diL R
L = −(rl + rc || R)iL − Vc + 0Vg + Io (R || rc )
dt R + rc
dVc R 1 R
C = iL − Vc + 0Vg − Io
dt R + rc R + rl R + rc
R
Vout = (rc || R) iL + Vc + 0Vg − (R || rc ) Io
R + rc
With the circuit de ned over the two subintervals, the A, B, C, and E matrices
can be de ned as shown below:
© Richard Tymerski and Frank Rytkonen, 2017 117
Figure 7.7: Buck Converter Superposition Analysis: D'Ts
" #
− (rc kR+r
L
l)
− (R+rR
c )L
A1 = A2 = A = R 1
(rc +R)C − (rc +R)C
1
B1 = L
0
0
B2 =
0
D
B= L
0
118 © Richard Tymerski and Frank Rytkonen, 2017
R
C1 = C2 = C = (rc || R) R+rc
E1 = E2 = E = 0 − (rc || R)
With the state space matrices de ned, the control to output transfer function
Gvd (s) = C(sI − A)−1 Bd + Ed, where Bd = (A1 − A2 )X +
can be calculated as
(B1 − B2 )U and Ed = (C1 − C2 )X + (E1 − E2 )U . Applying basic matrix
manipulation techniques, Gvd (s) is calculated below.
DV g R2 Rrc
R+r − Io(R+rc )(R+rl ) − (R+rc )(R+r l)
X = −A−1 BU = l
R 2 rc R(Rrc +Rrl +rc rl )
DRVg
Io (R+rc )(R+rl ) + (R+rc )(R+rl ) + R+rl
Vg
Bd = (A1 − A2 )X + (B1 − B2 )U = L
0
Ed = (C1 − C2 )X + (E1 − E2 )U = 0
Vg (1 + sRC)
Gvd (s) = C(sI−A)−1 Bd+Ed = rc +R 2 rc rl (R+rl )
L
R s LC +s R + rl + rc + R C + R
Gii (s) Analysis
When calculating the output load to inductor current transfer function, it
can be noticed that the inductor voltage and capacitor current equations will
be identical to those used in calculating Gvd (s) above. Using this fact, only the
output equation is needed to be derived to nd the C and E matrices.
y=i
C1 = C2 = C = 1 0
E1 = E2 = E = 0 0
Using the values found above, the output load to inductor current function
is equal to Gii (s) = −(C(sI − A)−1 B + E), with the negative sign due to the
de ned current direction.
R−rc
R+rl + src C
Gii (s) = C(sI − A)−1 B + E = rc +R 2 rc rl (R+rl )
L
R s LC +s R + rl + rc + R C + R
© Richard Tymerski and Frank Rytkonen, 2017 119
Gid (s), Gvvg (s), and Givg (s) Analysis
To calculate Gid (s), the control to inductor current transfer function, Gvvg (s),
the input voltage to output voltage transfer function and Givg (s), the input
voltage to inductor current transfer function, the same parameters derived above
can be used to solve each equation.
Vg (1 + s (R + rc ) C)
Gid (s) = C(sI−A)−1 Bd+Ed = (R+rl )
R rc +R 2 L rc rl
R s LC +s R + rl + rc + R C + R
D (1 + src C)
Gvvg (s) = C(sI−A)−1 B+E = rc +R 2 rc rl (R+rl )
L
R s LC +s R + rl + rc + R C + R
D
(1 + s (R + rc ) C)
Givg (s) = C(sI−A)−1 B+E = rc +R 2
R
rc rl (R+rl )
L
R s LC +s R + rl + rc + R C + R
Zo (s) Analysis
To calculate the output impedance of the Buck converter, it is possible to use
state space analyses techniques. However, due to the input voltage connection
of the Buck converter we can take advantage of the fact that the impedance of
the buck on the output looks the same regardless of the switch location.
Figure 7.8: Ideal Buck Converter Circuit
1 sL
Zo (s) = SLk kR = L
sC 1 + s R + s2 LC
120 © Richard Tymerski and Frank Rytkonen, 2017
Figure 7.9: Buck Converter Circuit with Non-Ideal Circuit Elements
One way to incorporate losses into the impedance function is to replace the
energy storage element in the impedance equation with the sum of the element
and its non-ideal resistive component. Starting with the inductor, every instance
of sL is replaced with sL + rl in Zo (s).
sL + rl
Zo (s) = rl L
1+ R +s R + rl C + s2 LC
rl
Assuming
R << 1
sL + rl
Zo (s) = L
1+s R + rl C + s2 LC
Now, adding the ESR of the capacitor:
sC
sC ⇒
1 + SRc
(sL + rl ) (1 + src C)
Zo (s) = L
rc
1+s R + (rl + rc ) C + s2 1 + R LC
The complete output impedance of the Buck converter is found to be:
rl 1 + s rLl (1 + src C)
Zo (s) = L
1+s R + (rl + rc ) C + s2 LC
rc
Assuming (
R << 1).
To summarize the results of this section, Figure 7.10 shows the results of the
state space analysis for the buck converter presented in this chapter. The results
of the analysis will be leveraged throughout the text.
© Richard Tymerski and Frank Rytkonen, 2017 121
Buck Converter Transfer Functions
Ideal Case Losses Included
Figure 7.10: Summary of Plant Transfer Functions
7.3 Pulse-width Modulator
With a complete model in place for the Buck regulator, the next item in the
system diagram to derive is the pulse-width modulator.
From inspection of Figure 13.2, it can be approximated that the duty cycle
can be represented by the following relationship:
Vc (t)
d (t) = for 0 ≤ Vc (t) ≤ VM
VM
d(t) 1
Rearranging,
Vc (t) = VM . For a complete derivation con rming the PWM
conversion gain can be approximated to this equation, refer to the analysis
presented in [1].
122 © Richard Tymerski and Frank Rytkonen, 2017
Figure 7.11: PWM Conversion Diagram
7.4 Summary
Now that the basic system has been de ned, the nal block to be derived in
the Buck converter system model is the compensator, Gc (s). The compensator
will be the primary topic of the next several chapters, as it will be leveraged to
improve the closed-loop performance of the derived buck regulator system. The
equations in this chapter will be heavily leveraged in the remainder of the text.
© Richard Tymerski and Frank Rytkonen, 2017 123
124 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] R. Middlebrook, Predicting modulator phase lag in pwm converter feedback
loops, in Powercon, 1981.
125
126 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 8
Single Loop Voltage Mode
Control
This chapter develops a buck converter design example using dierent compen-
sation methods to ensure closed loop stability and to optimize system perfor-
mance. Various compensators are designed using asymptotic Bode plots based
primarily on loop bandwidth and stability margins. Computer simulation re-
sults are included to show time domain step response behavior and to verify
performance improvements.
8.1 Introduction
The buck converter is a switch mode, DC-DC, power supply. It accepts a
source voltage, Vg and produces a lower output voltage, V with high e ciency.
An important component of a practical buck converter is control feedback which
assures a constant output voltage and attenuates unwanted disturbances. The
feedback loop of a buck converter presents several challenges which are explored
in the compensation examples.
In this paper we present a series of example buck converter feedback compen-
sation approaches. The design of the buck converter circuit is kept constant to
allow comparison of the eects of dierent compensation schemes. The primary
tool that will be applied to evaluate the dierent compensation approaches are
asymptotic Bode plots which are drawn based on corner frequencies of each
block in the regulator system. This methodology provides a quick and e cient
assessment of circuit performance and an intuitive sense for the trade os for
each compensation approach. Bode plots also directly illuminate the two critical
loop stability characteristics, gain and phase margin (GM and PM respectively).
Additional analysis of each compensation approach is undertaken through
computer simulation. The PECS [1] circuit simulator is used to evaluate the
127
eects of Vg transients, a common problem in real power supply designs. A
Matlab [2] simulation is also performed to validate the manual Bode analysis
and to determine the exact gain and phase margin. Finally a closed loop Mat-
lab simulation is used to show the ability of the feedback system to attenuate
undesired eects as a function of frequency.
8.2 Buck Converter System Models
8.2.1 General Model
Figure 8.1 is a block diagram of the system components of a buck converter
with feedback. The converter power stage accepts Vg as its power source and the
control input d(s) to produce the output voltage V. The feedback sensor H(s),
monitors the converter output voltage which is then compared with a reference
voltage Vref . The dierence output of these two voltages is provided to the
feedback compensation circuit Gc (s) and then to the pulse width modulator
(PWM) which produces the control waveform for the switching converter d(s).
The resulting loop gain is thus given by
1
T (s) = Gc (s) Gvd (s)H(s) (8.1)
VM
Figure 8.1: Generalized Power System Model
8.2.2 Simpli ed System Model
The general buck converter block diagram provides a complete model for
analysis of converter. However, for our analysis we will use a simpli ed model
show in Fig. 8.2 which includes only the elements required for the analysis we
will provide. We do not evaluate any source of disturbance except Vg transients.
128 © Richard Tymerski and Frank Rytkonen, 2017
Figure 8.2: Simpli ed System Diagram
8.2.3 Design Targets
To facilitate easy comparison between the selected compensation schemes,
the design of the buck converter is xed with speci ed values. These values are
speci ed in Table 8.1.
Table 8.1: Speci ed values
Name Value Description
Vg 28V Input Voltage
V 15V Output Voltage
Iload 5A Load current
L 50uH Buck inductor value
C 500uF Buck capacitor value
Vm 4V PWM ramp amplitude
H(s) 1/3 Sensor gain
fs 100kHz PWM frequency
8.2.4 Buck Converter Model Analysis
Figure 8.3 shows a schematic model for the power converter block. The LCR
is a second order circuit with a transfer function described by equation (8.2). It
ωo
has a resonant frequency value, ωo = 6.28k rad/s or fo (=
2π ) = 1.0 kHz from
(8.3) and a Q of 9.5 from (8.4). The low frequency gain of the converter is equal
to Vg which is speci ed to be 28V.
1
Gvd (s) = Vg 2 (8.2)
s s
1+ +
Qω0 ω0
1
ωo = √ (8.3)
LC
© Richard Tymerski and Frank Rytkonen, 2017 129
Figure 8.3: Converter Power Stage
r
C
Q=R (8.4)
L
Consider the transfer function v(s)/vd (s) of the low pass lter formed by the
LCR network. The switching frequency fs = 100kHz is much higher than the
resonant frequency f0 = 1kHz of the LCR network. During circuit operation,
the switch toggles the LCR input between Vg and ground with a duty cycle D
determined by the feedback loop. A Fourier analysis of the LCR input waveform
includes an average DC component V = DVg and an fs fundamental component
and its harmonics as typi ed by a rectangular waveform. The LCR acts as a
low pass lter with a cut o frequency equal to fo . It passes the DC component
to the output but attenuates fs and its harmonics.
8.3 Uncompensated System
It is instructive to start our evaluation by examining the uncompensated loop
gain, that is with a Gc (s) = 1. The loop gain is then given from (8.1) as
To
T (s) = 2 (8.5)
s s
1+ +
Qω0 ωo
where
Vg H(0)
To = (8.6)
Vm
To construct a Bode plot we use the values from equations (8.2)-(8.4) to
establish the shape of the Bode magnitude plot. The low frequency gain given
by (8.6) has a value of 2.33. The magnitude around fo peaks due to the resonant
Q of 9.5. At frequencies above fo the gain declines at -40dB/decade.
130 © Richard Tymerski and Frank Rytkonen, 2017
The Bode phase plot is determined only by Gvd (s). It has a low frequency
1
phase shift of 0◦ . At fo 10− 2Q or 886Hz (≈ 900Hz), the phase turns negative
and at f0 the phase has reached −90◦ . The phase continues to become more
1
negative until it reaches −180◦ at 10 2Q or 1129Hz (≈ 1.1kHz). At frequencies
higher than 1.1kHz the phase remains at −180◦ .
fo = 1kHz
To Q = 22
To = 2.33 Q = 9.5
|T (s)|
To ( ffo )2
fc
1 ⇒ 0dB
1 −40dB/dec
10− 2Q fo =
900Hz
0◦
−Q × 180◦ /dec
T (s)
−90◦
f
−tan−1 Qfo
1−( ffo )2
, ∀f
1
10 2Q fo =
1.1kHz
−180◦
Figure 8.4: Uncompensated Gain and Phase Plot
From the Bode plot it can be determined that unity gain occurs at a frequency,
f = fc such that
2
fo
To =1 (8.7)
fc
which with To =2.33 and fo =1kHz, results in fc =1.5kHz. At this frequency
the phase is −180◦ providing zero phase margin. The phase asymptotes show
◦
that phase does not cross the −180 phase level (but is asymptotic to it) which
implies that the gain margin is in nite. Figure 8.5 is a Matlab margin plot
indicating the actual unity gain frequency to be 1.8 kHz with a phase margin
◦
of 4.7 . Also, the Matlab analysis indicates an in nite gain margin.
© Richard Tymerski and Frank Rytkonen, 2017 131
Bode Diagram
40
Gm = Inf dB (at Inf Hz) , Pm = 4.72 deg (at 1.82e+003 Hz)
30
20
Magnitude (dB)
10
-10
-20
-30
-40
0
-45
Phase (deg)
-90
-135
-180
2 3 4
10 10 10
Frequency (Hz)
Figure 8.5: Matlab Uncompensated Bode plot
Figure 8.6 shows a PECS implementation of the open loop buck converter
system. The input to the modulator is set to 2.1V which results in the target
V 15
steady state duty ratio of D=
Vg = 28 = 0.54 required to set the output voltage
at V = 15V for a nominal input voltage of Vg = 28V.
Figure 8.7 shows the output voltage response of the open loop system shown
in Figure 8.6 for voltage steps in Vg of 28V→30V→28V. The response is in-
dicative of the high resonance Q of 9.5 at the resonant frequency fo =1kHz.
Note also that at an input voltage of Vg =30V the output voltage settles at
V = DVg =0.54×30 = 16.2V, as shown in Fig. 8.7.
132 © Richard Tymerski and Frank Rytkonen, 2017
Del = 0.0
Per = 10 u
SW1 L1
V1 D1 50 u C1 R1 VP1
28 500 u 3.0
V2
2.1
k1 = 1.0
k2 = 0.0
k3 = 0.0
Vpk = 4.0
Period = 10 u
Figure 8.6: PECS Schematic of Open Loop System
x101 VP1
1.70
1.65
1.60
1.55
1.50
1.45
1.40
8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0
x10-2
Figure 8.7: PECS Simulation of Open Loop System
© Richard Tymerski and Frank Rytkonen, 2017 133
8.4 Dominant Pole Compensation
Dominant pole compensation is one of the simplest and most common forms
of feedback compensation. The motivating idea behind this type of feedback
control is to shape the loop gain of the system such that two objectives are
achieved:
1. High gain is achieved at DC and low frequencies. This condition ensures
low steady state error. In the case of an integrator where the pole appears
at zero frequency, i.e. DC, the error is zero.
2. The gain at the plant's lowest frequency pole is less than or equal to
0dB. This condition ensures a positive phase margin and, consequently,
stability.
For the case of dominant pole compensation, these objectives are achieved
using a compensator consisting of a single pole at a frequency well below those
of the plant's poles. For the purposes of this example, an integrator is employed
ωI
Gc (s) = (8.8)
s
where ωI (= 2πfi ) is an appropriately chosen design constant. Figure 8.8
shows the Bode plot asymptotes for the magnitude and phase of this compen-
sator.
fI
f
| ωsI |
−20dB/dec
1 ⇒ 0dB
fI
1
s −90◦
Figure 8.8: Bode Plot of Dominant Pole Compensator
Design of the compensator now consists of selecting an appropriate compen-
sator parameter, fI . Following the previously stated criteria, this is a matter
of choosing the largest compensator gain such that the total gain at the lowest
frequency plant pole(s) is less than 0dB. The loop gain of the system with this
compensator is given by
134 © Richard Tymerski and Frank Rytkonen, 2017
ωI To
T (s) = " 2 # (8.9)
s s
s 1+ +
Qω0 ω0
Figure 8.9 shows the graphical construction of the phase asymptotes for the
loop gain with the compensator. Note that because the plant's dominant pole
is second order, it contributes a phase shift of −180◦ at high frequencies and a
◦
shift of exactly −90 at fo . Furthermore, the compensator contributes its own
−90◦ phase shift and does so for all frequencies. Consequently, the total phase
shift of the compensated loop gain transfer function is −180◦ at the dominant
pole frequency, fo . For this reason it is prudent to design in some additional
gain margin. A value of 3dB is initially chosen for this analysis.
− 1 fo =
10 2Q fo =
900Hz 1kHz
0◦
−Q × 180◦ /dec
1
s
1+ Qω o
+( ωso )2
−90◦
f
−tan−1 Qfo
1−( ffo )2
, ∀f 1
10 2Q fo =
1.1kHz
−180◦
1 −90◦
s
− 1
10 2Q fo =
900Hz
−90◦
−Q × 180◦ /dec
T (s)
−180◦
f
−90 − tan−1 Qfo
1−( ffo )2
, ∀f 1
10 2Q fo =
1.1kHz
−270◦
Figure 8.9: Graphical Construction of Phase Asymptotes for Dominant Pole
Compensated Loop Gain
© Richard Tymerski and Frank Rytkonen, 2017 135
Figure 8.10 shows how the plant and compensator transfer functions combine
to produce the gain of the compensated open loop. To achieve a loop gain that
is -3dB at fo , we require the magnitude at fo to equal 0.7
fI To Q
= 0.7 (8.10)
fo
For To = 2.33 and fo = 1.0kHz, we nd fI = 32.
fo = 1kHz
To Q = 22
To = 2.33 Q = 9.5
To
s
+( ωso )2
1+ Qω o To ( ffo )2
1 ⇒ 0dB
−40dB/dec
1 ⇒ 0dB
| ωsI | −20dB/dec
fI
f
fI To fI To Q
fc f fo
1 ⇒ 0dB
3dB
−20dB/dec Q = 9.5 −3dB ⇒ 0.7
|T (s)|
fI To
fo
fI To fo 2
f ( f )
−60dB/dec
Figure 8.10: Graphical Construction of Gain Asymptotes for Dominant Pole
Compensated Loop Gain
Figure 8.11 shows the Bode plot of the resulting gain and phase asymptotes
and Figure 8.12 shows a Matlab margin analysis which con rms the design.
136 © Richard Tymerski and Frank Rytkonen, 2017
fc fo = 1kHz
fI To fI To Q
f fo
1 ⇒ 0dB
3dB
−20dB/dec Q = 9.5 −3dB ⇒ 0.7
|T (s)|
fI To
fo
2
fI To fo
f f
1
10− 2Q fo = −60dB/dec
−90◦ 900Hz
Phase
Margin
= 90◦ −Q × 180◦ /dec
T (s) −180◦
f
−90 − tan−1 Qfo
1−( ffo )2
, ∀f 1
10 2Q fo =
1.1kHz
−270◦
Figure 8.11: Dominant Pole Compensated Loop Gain Asymptotic Bode Plot
With a compensator designed and veri ed via Matlab, the next stage is to
design a circuit that implements the compensator. Figure 8.13 shows the general
form of an operational ampli er in a integrator con guration. The transfer
function for this circuit is given by:
−1
G(s) = (8.11)
(s/ωo )
where
1
ωo = (8.12)
RC
where ωo is the frequency at which the integrator gain is unity.
A capacitor value of 50nF is chosen for C. This value is within the range of
low-cost, commercially available ceramic capacitors and is small enough to avoid
© Richard Tymerski and Frank Rytkonen, 2017 137
Bode Diagram
50
Gm = 3.04 dB (at 1e+003 Hz) , Pm = 89.5 deg (at 74.6 Hz)
Magnitude (dB)
0
-50
-100
-90
-135
Phase (deg)
-180
-225
-270
1 2 3 4
10 10 10 10
Frequency (Hz)
Figure 8.12: Matlab Analysis of Dominant Pole Compensator
Figure 8.13: Op-Amp Integrator Circuit
any op-amp slew rate issues. Equating ωo with the compensator parameter, ωI
(= 2πfI ) and solving for R gives
1 1
R= = ≈ 100kΩ (8.13)
ωI C 2π(32)(50nF)
A PECS simulation is created to verify the time domain performance of the
implementation. Figure 8.14 shows the complete PECS circuit model for the
design.
Figure 8.15 shows the results of the PECS simulation for a 2V disturbance
on the supply voltage, Vg . The input voltage steps are 28V→30V→28V. The
simulation exhibits several undesirable characteristics:
138 © Richard Tymerski and Frank Rytkonen, 2017
Del = 0.0
Per = 10 u
SW1 L1
V1 D1 50 u C1 R1 VP1
28 500 u 3.0
C4 R6
50 n R5 2.0 k
100 k R7
V3
1.0 k
5.0
k1 = 1.0
k2 = 0.0
k3 = 0.0
Vpk = 4.0
Period = 10 u
Figure 8.14: PECS Schematic of Dominant Pole Compensated System
1. The regulator does a poor job of rejecting the input voltage disturbance.
Nearly all of the input voltage excursion shows up as a transient on the
output.
2. The regulator exhibits a substantial amount of ringing in response to the
input disturbance. Closer examination of the ringing, as shown in Figure
8.16, reveals that the frequency of the oscillations is the same as the res-
onant frequency of the plant, fo , and is not the result of defective control
loop design.
It is clear from the simulation results that, although the design is stable and
exhibits zero steady-state error, there is much room for improvement, particu-
larly with respect to its transient response.
One additional experiment is performed using the dominant pole compensa-
tion scheme. The Q of the plant's dominant pole is reduced by placing a large
capacitor in series with a small damping resistance. Figures 8.17 and 8.18 show
the PECS circuit schematic and simulation results, respectively.
One can see clearly that the ringing of the previous design has been eliminated.
Unfortunately, the poor rejection of input voltage transients remains.
© Richard Tymerski and Frank Rytkonen, 2017 139
x101 VP1
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0
x10-2
Figure 8.15: PECS Simulation of Dominant Pole Compensated System
Figure 8.16: Pole of Dominant Pole Simulation Showing Oscillation at Resonant
Frequency
Furthermore, this is probably not an ideal solution from a practical stand-
point. The large value capacitor will be relatively expensive in terms of com-
ponent price and physical space. Alternate compensation schemes still oer the
potential for better performance at lower cost.
140 © Richard Tymerski and Frank Rytkonen, 2017
Del = 0.0
Per = 10 u
SW1 L1
V1 D1 50 u C1 R8 R1 VP1
28 500 u 300 m 3.0
C3
5.0 m
C4 R6
50 n R5 2.0 k
100 k R7
V3
1.0 k
5.0
k1 = 1.0
k2 = 0.0
k3 = 0.0
Vpk = 4.0
Period = 10 u
Figure 8.17: PECS Schematic of Dominant Pole with Damping
x101 VP1
1.65
1.60
1.55
1.50
1.45
1.40
1.35
8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0
x10-2
Figure 8.18: PECS Simulation of Dominant Pole Compensated System with
Added Output Filter Damping
© Richard Tymerski and Frank Rytkonen, 2017 141
8.5 Dominant Pole Compensation with Zero
The dominant pole compensator of the previous section, while stable and hav-
ing zero steady state error, exhibits several undesirable characteristics including
poor rejection of input supply voltage excursions and pronounced ringing in
response to transients. One might assume that these issues are related to the
minimal, 3dB, gain margin for which the compensator was designed. This sec-
tion explores that line of reasoning by modifying the compensator of the previous
section in order to substantially increase the gain margin.
The dominant pole compensator is modi ed by adding a zero at the resonant
frequency of the plant and by reducing the gain to -10dB. Overall gain margin
is improved in two ways:
1. by directly increasing the gain margin at the resonant frequency, fo , from
3dB to 10dB.
2. by shifting the frequency at which the phase reaches −180◦ beyond the
resonant frequency and the gain peak due to the plant's Q.
The form of the modi ed compensator transfer function is:
1 + s/ωz
Gc (s) = ωI (8.14)
s
ωz
We will use ωz = ωo or fz = 2π = fo . Which results in a loop gain of
1 + s/ωo To
T (s) = ωI 2 (8.15)
s
s s
1+ Qωo + ωo
Figure 8.19 shows the resulting Bode plot asymptotes. We would like to set
√
the gain at fo to 1/ 10 (which corresponds to -10dB). From the magnitude plot
we see that we want
fI To Q 1
=√ (8.16)
fo 10
which given To = 2.33, Q = 9.5, fo = 1kHz , results in fI = 14.3. Figure
8.20 shows a Matlab con rmation of the Bode plot. Note that a gain margin
of 11dB is predicted at a phase cross-over frequency of 1.06kHz, slightly higher
than the plant's resonant frequency.
Figure 8.21 shows a standard op-amp implementation with the desired trans-
fer function. The transfer characteristics of the circuit are given by:
1 + s/ω1
G(s) = −A s (8.17)
ω1
where:
142 © Richard Tymerski and Frank Rytkonen, 2017
fc fo = 1kHz
fI To fI To Q
f fo
1 ⇒ 0dB
10dB
−20dB/dec Q = 9.5 −10dB ⇒ √1
10
|T (s)|
fI To
fo
2
fI To fo
f f
−40dB/dec
− 1
10 2Q fo =
900Hz
−47◦
f
−90◦ + tan−1 ( ff ) − tan−1 Qfo
, ∀f
fz o 1−( ff )2
◦ 10
45◦ /dec o
−90
Phase Margin =
T (s) 90◦ −135◦
10fz
−(Q × 180◦ − 45◦ )/dec −180◦
45◦ /dec
−222◦
1
10 2Q fo =
1.1kHz
Figure 8.19: Open Loop System Gain and Phase with pole-zero Compensation
(10dB GM)
R2 1
A= and ω1 = (8.18)
R1 R2 C1
ω1
Equating f1 (=
2π ) to the plant resonant frequency, fo and ωI to Aω1 provides
two equations with three unknowns. Choosing, somewhat arbitrarily, a value of
100k for R1, leads to the following values.
fI R1 (14.3)(100kΩ)
R2 = = = 1.4kΩ (8.19)
f1 (1kΩ)
1 1
C1 = = = 110nF (8.20)
ω1 R 2 2π(1kHz)(1.4kΩ)
© Richard Tymerski and Frank Rytkonen, 2017 143
Bode Diagram
50
Gm = 11 dB (at 1.06e+003 Hz) , Pm = 91.7 deg (at 33.3 Hz)
Magnitude (dB)
-50
-100
-150
-45
-90
Phase (deg)
-135
-180
-225
1 2 3 4 5
10 10 10 10 10
Frequency (Hz)
Figure 8.20: Matlab Analysis of Dominant Pole Compensator with Zero
Figure 8.21: op-amp Integrator with Zero
Figure 8.22 shows a PECS circuit implementation of the system with the new
compensator. Figure 8.23 shows the response of the system to a transient on
the input voltage.
The modi ed compensator shows little improvement over the original circuit.
It still fails to provide good rejection of input voltage transients and the previ-
ously observed ringing is still present.
144 © Richard Tymerski and Frank Rytkonen, 2017
Del = 0.0
Per = 10 u
SW1 L1
V1 D1 50 u C1 R1 VP1
28 500 u 3.0
C2 R4 R2
110 n 1.4 k R5 2.0 k
100 k R3
V3
1.0 k
5.0
k1 = 1.0
k2 = 0.0
k3 = 0.0
Vpk = 4.0
Period = 10 u
Figure 8.22: PECS Schematic of Dominant Pole with Zero Compensation (10
dB GM)
x101 VP1
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0
x10-2
Figure 8.23: PECS Simulation of Dominant Pole with Zero Compensation (10
dB GM)
© Richard Tymerski and Frank Rytkonen, 2017 145
8.6 Lead Compensation
A more sophisticated way to improve the performance of the buck converter
is with a lead compensator. The transfer function of this compensator is
s
1+ ωz
Gc (s) = Gco , (8.21)
s
1+ ωp
where ωz < ωp . As can be seen from the plot of the transfer function shown in
Figure 8.24, the lead compensator provides both a phase boost that is adjustable
based on the pole and zero frequencies, and a gain boost at higher frequencies
that can result in a higher crossover frequency for a lead-compensated buck
converter. Generally, a lead compensator is used to provide a phase boost, the
level of which is chosen to improve the phase margin to a desired value. The
new crossover frequency can be chosen arbitrarily. The design shown here will
be to obtain a 45◦ phase margin and a crossover frequency of 5 kHz for the loop
gain with a lead compensator.
f
Gco fpz
a) Gco ffz
|Gc (s)|
Gco
20dB/dec
fp
45◦ log
p
fz fp fz
b)
10f f
45◦ log fz −45◦ log 10fp
45◦ /dec −45◦ /dec
Gc (s)
0◦ 0◦
fz fp
fz fp fc 10fz 10fp
10 10
Figure 8.24: Bode Plot of Lead Compensator
146 © Richard Tymerski and Frank Rytkonen, 2017
fo fz fp
c = fp
fz fp
Q = 9.5
|T (s)| To Gco fc To Gco fo2
−40dB/dec f = fz f
1 ⇒ 0dB
2
−20dB/dec
fo
To Gco f 2
fc fp f fo
f2 = To Gco fpz f
10f
45◦ log fz
−40dB/dec
0◦ 45◦ /dec
T (s) − (Q × 180◦ − 45◦ ) /dec
fp
p 45◦ log − 180◦
fz
fz fp
f
−45◦ log 10f p
− 180◦
45◦ /dec Phase
◦ Margin
−180
−45◦ /dec
1 1
10
− 2Q
fo 10 2Q fo fc 10fz 10fz
fz fo fp
10 10
Figure 8.25: Bode Plot of Lead Compensated System
When the compensator is placed in the loop, the loop gain of the buck con-
verter system becomes
1 + ωsz
T (s) = T0 Gc0 2 (8.22)
1 + ωsp 1 + Qω s
0
+ s
ω0
© Richard Tymerski and Frank Rytkonen, 2017 147
The asymptotic Bode plot of this loop gain is shown in Fig. 8.25. The
expressions shown can be used to place the pole and zero frequencies of the
compensator to obtain the desired phase margin and unity-gain crossover fre-
quency. As can be seen, the phase margin of the lead compensated system is
given by
◦ fp
φM = 45 log
fz
For a desired phase margin of 45◦ we have
fp
45◦ = 45◦ log
fz
or
fp = 10fz
Also, the crossover frequency, fc will necessarily be the geometric mean of
the pole and the zero frequency. Since the phase margin condition gives a
relationship between the pole and zero frequencies, this can be used to solve for
both.
p
fc =
fz fp
p
5 kHz = 10fz2
5 kHz
fz = √
10
fz = 1.58 kHz and fp = 15.8 kHz
These relationships result in the pole and zero frequencies for the lead com-
pensator. To complete the design, the required low-frequency gain Gco of the
compensator to place the unity-gain point at the appropriate frequency must be
determined. This can be found by equating the values of the gain asymptotes
at fz .
2
f0 fc
T0 Gc0 =
fz fz
Substituting the values of fo and To for the example converter, and the values
of fz and fc as previously calculated, the gain Gco of the compensator is
2
1 fz fc
Gco =
T0 f0 fz
2
1 1.58 kHz 5 kHz
Gco =
2.33 1 kHz 1.58 kHz
Gco = 3.4
As seen in previous designs and now in the phase plot of Fig. 8.25, the
phase response is asymptotic to −180◦ at high frequencies and so does not cross
through this level which implies an in nite gain margin.
148 © Richard Tymerski and Frank Rytkonen, 2017
In summary, we have designed a lead compensator which, using asymptotic
Bode plot approximations, result in a 45c irc phase margin with a unity gain
frequency of 5kHz and an in nite gain margin. The Matlab simulation in Figure
8.26 veri es the results, above.
Bode Diagram
40
Gm = Inf dB (at Inf Hz) , Pm = 55.9 deg (at 5.35e+003 Hz)
20
Magnitude (dB)
-20
-40
-60
-80
45
0
Phase (deg)
-45
-90
-135
-180
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 8.26: Matlab Lead Compensator
With all of the parameters of the lead compensator determined, what remains
is to implement the compensator using an op-amp circuit and simulate the
closed-loop converter to evaluate its performance. A general circuit that can
be used to implement any lead or lag compensator is shown in Fig. 8.27. The
transfer function of this circuit is
s
1+ ωz
Gc (s) = Gco s (8.23)
1+ ωp
where
R2
Gco = − (8.24)
R1
ωz 1
fz = = (8.25)
2π 2πR1 C1
ωp 1
fp = = (8.26)
2π 2πR2 C2
© Richard Tymerski and Frank Rytkonen, 2017 149
The resistor ratio sets the low frequency gain, and the two resistor-capacitor
pairs set the pole and zero frequencies. Using standard resistor values of R1 =
100 kΩ and R2 = 330 kΩ results in the required low frequency gain of close to
Gco = 3.4. Using (8.23) we nd
1
C1 = ⇒ C1 = 1.0 nF
2π (1.58 kHz) (100 kΩ)
1
C2 = ⇒ C2 = 33 pF
2π (15.8 kHz) (330 kΩ)
It it also necessary to derive a value for the reference voltage on the non-
inverting input of the op-amp. The sensed voltage from the output will be 5 V
in steady-state as before, and the control voltage should be 2.14 V. Using these
in combination with the resistor values for the lead compensator, the reference
voltage can be found.
R2 R1
Vref = Vsense + Vcontrol
R1 + R2 R1 + R2
330 kΩ 100 kΩ
Vref = (5 V) + (2.14 V) = 4.33 V
100 kΩ + 330 kΩ 100 kΩ + 330 kΩ
Figure 8.27: op-amp circuit implementation of lead compensator
Using these values in the PECS simulator (see Figure 8.28 for PECS schematic),
the response of the lead-compensated buck converter to a step in the input volt-
age was simulated as before. The results of the simulation are shown in Fig-
ure 8.29. The lead compensator is quite eective in increasing the phase margin
of the system. The oscillatory behavior evident in the output voltage of the
uncompensated converter is not present, and the magnitude of the steady-state
error due to the step is reduced, though not eliminated. Thus, the system with
the lead compensator is very stable, but will still exhibit steady-state errors to
150 © Richard Tymerski and Frank Rytkonen, 2017
a step disturbance. To x this problem, the system type number must be in-
creased by adding a pole at s = 0, as was seen previously. This is the approach
taken in the design of the subsequent compensators.
Del = 0.0
Per = 10 u
SW1 L1
V1 D1 50 u C1 R1 VP1
28 500 u 3.0
C3 C2
R2
33 p 1.0 n
R5 R4 2.0 k
330 k 100 k R3
1.0 k
V3
k1 = 1.0
k2 = 0.0
k3 = 0.0 4.3
Vpk = 4.0
Period = 10 u
Figure 8.28: PECS Schematic of Lead System
8.7 Dominant Pole with Lead Compensation
So far we have seen that with a dominant pole integral compensation a zero
steady state error can be achieved at the expense of limited bandwidth with
resulting large overshoot in the step response. In contrast lead compensation is
able to extend bandwidth thus reducing step response overshoot. However, due
to severely curtailed low frequency loop gain, a non-zero steady state error is
seen.
In this section a compensator which is a composite of the two previous com-
pensators is examined. The exact form of the compensator is:
ωI 1 + ωs1 1+ s
ωz
Gc (s) = (8.27)
s 1 + ωsp
© Richard Tymerski and Frank Rytkonen, 2017 151
x101 VP1
1.512
1.510
1.508
1.506
1.504
1.502
1.500
1.498
8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0
x10-2
Figure 8.29: PECS Simulation of Lead System
Eectively, to the lead compensator design of the previous section we are
ω1
adding an integrator pole, i.e. a pole at zero frequency, and a zero at
2π ). f1 (=
In the following we will consider two dierent values for the zero frequency f1 .
In the rst case f1 will be chosen to be the largest frequency which, based
on the phase asymptote, contributes +90◦ to the crossover frequency fc , thus
◦
fully canceling the −90 contribution from the integrator pole. This eectively
leaves the phase margin unchanged from the lead compensator design of the
previous section. From the phase asymptotes plots of a zero, we see that the
fc
zero frequency f1 should be at
10 which is 500Hz.
In the second design considered here we will lower the zero frequency to
f1 = 150Hz and examine the eect on the closed loop performance.
In either case the expression for the loop gain is
ωI 1 + ωs1 1 + ωsz
T (s) = To 2 (8.28)
s 1 + ωsp 1 + Qω s
o
+ s
ωo
ωI
where f1 is either 500Hz or 150Hz, as discussed above and fI = 2π is the
only design variable to be determined.
152 © Richard Tymerski and Frank Rytkonen, 2017
8.7.1 Design 1: Zero f1 = 500Hz
As before, asymptotic plots for the loop gain are drawn. As the construction of
the phase plot is more involved than that of the magnitude plot, its construction
is shown separately in Fig. 8.30. In Fig. 8.30, the top plot is that of the previous
lead compensation design, as seen in Fig. 8.25. The plot of the phase of the
1 s
component
s 1+ ω1 is shown in the center plot where f1 = 500Hz. The nal
phase plot for the new loop gain is shown in the bottom plot. Both magnitude
and phase plots for the new loop gain are shown together in Fig. 8.31.
To determine, fI , the one unknown variable in the loop gain, we note that at
the frequency f1 the magnitude is set equal to the low frequency loop gain of
the lead compensation design of the last section.
fI
T0 = T0 Gco |lead (8.29)
f1
For f1 = 500 we nd fI = 1770. Thus the expression for the compensator is
as given in (8.27) with the following values
ωI = 2π(1770)
ω1 = 2π(800)
(8.30)
ωz = 2π(1580)
ωp = 2π(15800)
To con rm the accuracy of the design, the Bode plot of the exact loop gain
was evaluated using Matlab. This is shown in Fig. 8.32. Our asymptotic design
values of crossover frequency fc and phase margin of 5kHz and 45◦ , respec-
tively were determined by Matlab as given by the Matlab "margin" command
to be more precisely 5,370Hz and 50.5◦ , respectively, thus con rming the design
procedure.
A compensator which realizes the transfer function is shown in Fig. 8.33
where we nd
1
ωI =
R1 (C2 + C3 )
1
ω1 =
R2 C 2
(8.31)
1
ωz =
R1 C 1
1
ωp = C2 C3
R2 C2 +C3
© Richard Tymerski and Frank Rytkonen, 2017 153
fp
c =
10f
fo fz fz fp fp
45◦ log fz
0◦ 45◦ /dec
fp
T (s) − (Q × 180◦ − 45◦ ) /dec 45◦ log fz − 180◦
p
lead
fz fp
f
−45◦ log 10fp − 180◦
45◦ /dec Phase
◦
−180 Margin
−45◦ /dec
0◦
10f
1+ ωs
45◦ log f1
1
s
−90◦ +45◦ /dec
+90◦ /dec
10f
45◦ log f1
−90◦ +45◦ /dec p
fz fp
T (s) −(Q × 180◦ − 90◦ )/dec +45◦ /dec
Phase −45◦ /dec
Margin
+90◦ /dec
−180◦
1
− 2Q 1
f1 fz 10 fo f 10 2Q fo fp fc = 10fz 10fp
o
10 10 10
10f1
Figure 8.30: Bode Plot of Lead Compensator (500Hz)
154 © Richard Tymerski and Frank Rytkonen, 2017
fp
c = fp
f1 fo fz
fz fp
To ffI −20dB/dec fc To Gco |lead fo2
f
= fz f
|T (s)| To ffI1 = To Gco |lead −40dB/dec
2
fo
1 ⇒ 0dB To Gco |lead f −20dB/dec fc fp
= To Gco |lead fp
f
f2 z
−40dB/dec
◦
+90 /dec
◦ 10f
45 log f1
−90◦ +45◦ /dec p
fz fp
T (s) − (Q × 180◦ − 90◦ ) /dec +45◦ /dec
Phase
−45◦ /dec
◦ Margin
−180◦ +90 /dec
1
− 2Q 1
10 fo 10 2Q fo
f1 fz fp fc = 10fz 10fp
10 10 10
10f1
fo
Figure 8.31: Bode Plot of System with Lead plus Integral Compensation (500Hz)
Setting R1 = 100K and using the approximation C3 C2 we nd the com-
ponent values:
1
C1 = = 2.2nF
ωz R 1
1
C2 = = 1nF
ωI R1
(8.32)
1
R2 = = 330kΩ
ω1 C2
1
C3 = = 33pF
ωp R2
© Richard Tymerski and Frank Rytkonen, 2017 155
Bode Diagram
100
Gm = Inf dB (at Inf Hz) , Pm = 50.5 deg (at 5.37e+003 Hz)
80
60
Magnitude (dB)
40
20
-20
-40
-60
-80
-100
0
-45
Phase (deg)
-90
-135
-180
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 8.32: Matlab Lead Compensator with Integrator and Zero at 500Hz
Figure 8.33: Compensator Circuit for Dominant Pole with Lead Compensation
A PECS implementation of the closed loop system is shown in Fig. 8.34. The
simulated response of input voltage steps 26V → 30V → 28V is shown in Fig.
8.35. Clearly seen here is the zero steady state error and a maximum voltage
deviation of around 80 mV with a settling time of around 1 ms.
8.7.2 Design 2: Zero f1 = 150 Hz
The above design procedure will now be repeated for the case of the zero
f1 = 150 Hz. The resulting asymptotic phase plot construction is shown in Fig.
156 © Richard Tymerski and Frank Rytkonen, 2017
Del = 0.0
Per = 10 u
SW1 L1
V1 D1 50 u C1 R1 VP1
28 500 u 3.0
C3 C2
R2
33 p 2.2 n
C4 R5 R4 2.0 k
1.0 n 330 k 43 k R3
1.0 k
V3
k1 = 1.0
k2 = 0.0
k3 = 0.0 5.0
Vpk = 4.0
Period = 10 u
Figure 8.34: PECS Schematic of Lead Compensated System with Zero at 500Hz
x101 VP1
1.5040
1.5030
1.5020
1.5010
1.5000
1.4990
1.4980
1.4970
1.4960
9.80 9.90 10.00 10.10 10.20 10.30 10.40 10.50 10.60 10.70 10.80
x10-2
Figure 8.35: PECS Simulation of Lead Compensated System with Zero at 500Hz
8.36. The nal magnitude and phase asymptotic plots are given in Fig. 8.37.
© Richard Tymerski and Frank Rytkonen, 2017 157
The new fI is now found to be from (8.33)
fI = f1 To = 150 × 3.4 = 351 (8.33)
Using the new values of fI = 351 and f1 = 150, a more precise value of
crossover frequency and phase margin is found from Matlab to be 5,350Hz and
54.3◦ , respectively, as seen in Fig. 8.38. Recall that the asymptotic plots indi-
cate 5kHz and 45◦ , respectively.
The change of f1 = 150Hz to f1 = 150Hz results in only a change in one
capacitor value in the compensator. The resulting PECS implementation is
shown in Fig. 8.39 along with the response of input voltage steps of 28V →
30V → 28V , in Fig. 8.40. We now see that the peak voltage variation has
slightly increased to 90 mV but the settling time has tripled to around 3ms.
8.8 Extended Bandwidth Design
In the following we examine the performance of a compensator (closely related
to the previous two) which is designed to produce an extended loop bandwidth.
To this end a unity gain crossover frequency fc = 40kHz is, somewhat arbitrarily,
chosen. The compensator used is
s s
ωI 1 + ωz1 1+ ωz2
Gc (s) = (8.34)
s
z1 ω z2 ω
The zeros fz1 (= 2π and fz2 =
2π are simply chosen as follows. Zero fz2 is
set so fz2 = fo so as to counter the eects of the plant complex pole pair. The
fo
lower frequency zero fz1 is set so that fz1 =
10 to minimize the phase drop at
fo . The resulting loop gain expression is given by
(1 + ωsz )(1 + ωsz )
1 2
T (s) = ωI To 2 (8.35)
s
s 1 + Qω o
+ ωso
The asymptotic magnitude and phase responses of the resulting loop gain are
shown in Fig. 8.41, where the phase contributions of the dierent factors are
individually drawn and then summed at the bottom plot to produce the overall
asymptotic loop gain phase plot.
To determine the quantity ωI (= 2πfI ) in (8.34) the high frequency asymp-
totes of the magnitude plot is used. At the crossover frequency fc we have
To fI fo
=1 (8.36)
fz1 fc
158 © Richard Tymerski and Frank Rytkonen, 2017
fp
c =
f fo fz fz fp fp
1
10f
45◦ log fz
0◦ 45◦ /dec
T (s) −(Q × 180◦ − 45◦ )/dec
fp
p 45◦ log fz − 180◦
lead
fz fp
f
−45◦ log 10fp
− 180◦
+45◦ /dec Phase
◦
−180 Margin
−45◦ /dec
0◦
10f
1+ ωs
45◦ log f1
1
s
−90◦ +45◦ /dec
+90◦ /dec
10f
45◦ log f1
−90◦ +45◦ /dec p
fz fp
T (s) −(Q × 180◦ − 90◦ )/dec +45◦ /dec
Phase −45◦ /dec
Margin
+90◦ /dec
−180◦
1
− 2Q 1
f1 fz 10 fo f 10 2Q fo fp fc = 10fz 10fp
o
10 10 10
10f1
Figure 8.36: Bode Plot of Lead Compensator (150Hz)
© Richard Tymerski and Frank Rytkonen, 2017 159
fp
c = fp
f1 fo fz
fz fp
To ffI −20dB/dec fc To Gco |lead fo2
f
= fz f
|T (s)| To ffI1 = To Gco |lead −40dB/dec
1 ⇒ 0dB To Gco |lead ( ffo )2 −20dB/dec fc fp
f2
= To Gco |lead
−40dB/dec
+90◦ /dec
45◦ log( 10f
f1 )
−90◦ +45◦ /dec p
fz fp
T (s) −(Q × 180◦ − 90◦ )/dec +45◦ /dec
Phase
−45◦ /dec
◦ Margin
−180◦ +90 /dec
1
− 2Q 1
10 fo 10 2Q fo
f1 fz fp
10 10 10 = fc 10fz 10fp
fo 10f1
Figure 8.37: Bode Plot of System with Lead plus Integral Compensation (150Hz)
so that we have
fz1 fc
fI = (8.37)
To fo
with the values at hand we nd
fI = 172 (8.38)
From the phase asymptotic plot of Fig. 8.41 we can clearly see that the
expected phase margin is 90◦ . Using Matlab we more precisely nd with the
design values used fc = 40kHz and phase margin is 88.6◦ as shown in Fig. 8.42.
160 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
100
Gm = Inf dB (at Inf Hz) , Pm = 54.3 deg (at 5.35e+003 Hz)
80
60
Magnitude (dB)
40
20
-20
-40
-60
-80
-100
45
0
Phase (deg)
-45
-90
-135
-180
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Frequency (Hz)
Figure 8.38: Matlab Lead Compensator with Integrator and Zero at 150Hz
The resulting PECS implementation is shown in Fig. 8.43 along with the
response of input voltage steps of 28V → 30V → 28V , in Fig. 8.44. We now
see that the peak voltage variation has greatly reduced to just 30mV.
© Richard Tymerski and Frank Rytkonen, 2017 161
Del = 0.0
Per = 10 u
SW1 L1
V1 D1 50 u C1 R1 VP1
28 500 u 3.0
C3 C2
R2
33 p 2.2 n
C4 R5 R4 2.0 k
3.3 n 330 k 43 k R3
1.0 k
V3
k1 = 1.0
k2 = 0.0
k3 = 0.0 5.0
Vpk = 4.0
Period = 10 u
Figure 8.39: PECS Schematic of Lead Compensated System with Zero at 150Hz
x101 VP1
1.506
1.504
1.502
1.500
1.498
1.496
1.494
9.8 10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4
x10-2
Figure 8.40: PECS Simulation of Lead Compensated System with Zero at 150Hz
162 © Richard Tymerski and Frank Rytkonen, 2017
Figure 8.41: Extended Bandwidth Bode Plot and Phase Construction
© Richard Tymerski and Frank Rytkonen, 2017 163
Bode Diagram
100
Gm = Inf , Pm = 88.6 deg (at 4e+004 Hz)
80
Magnitude (dB)
60
40
20
-20
45
0
Phase (deg)
-45
-90
-135
0 1 2 3 4 5
10 10 10 10 10 10
Frequency (Hz)
Figure 8.42: Matlab Analysis of Extended Compensator
Del = 0.0
Per = 10 u
SW1 L1
V1 D1 50 u C1 R1 VP1
28 500 u 3.0
R7 C2
68 k 18 n C4 R6
10 n 16 k
R7
V2
8.0 k
k1 = 1.0
k2 = 0.0 5.0
k3 = 0.0
Vpk = 4.0
Period = 10 u
Figure 8.43: PECS Schematic of Extended System
164 © Richard Tymerski and Frank Rytkonen, 2017
x101 VP1
1.5015
1.5010
1.5005
1.5000
1.4995
1.4990
1.4985
1.4980
8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0
x10-2
Figure 8.44: PECS Simulation of Extended System
© Richard Tymerski and Frank Rytkonen, 2017 165
8.9 Conclusion
The following table shows the summary of all of the results.
166 © Richard Tymerski and Frank Rytkonen, 2017
Table 8.2: Summary of Compensators
To
Loop Gain T (s) = Gc (s) 2,
s
1+ Qω o
+( ωso )
where To = 2.33, Q = 9.5, and ωo = 2π(1kHz)
Compensator Compensator φM fc ∆v
Design Transfer Function Asymptote Asymptote (mV)
Gc (s) (Matlab) (Matlab)
(degrees) (kHz)
Uncompensated Gco 0 1.5 2,800
Open Loop Gco = 1 (5) (1.82)
ωI
Dominant Pole 90 0.0744 3,700
s
(3dB gain ωI = 2π(32) (90) (0.0746)
margin)
ωI (1+ ωs )
1
Dominant Pole 90 0.0333 3,700
s
+ Zero (10db ωI = 2π(14.3) (92) (0.033)
gain margin) ω1 = 2π(1, 000)
1+ ωsz
Lead G co 1+ s 45 5.0 120
ωp
(56) (5.35)
Gco = 3.4
ωz = 2π(1, 580)
ωp = 2π(15, 800)
ωI (1+ ωs )(1+ ωsz )
1
Lead + 45 5.0 80
s(1+ ωsp )
Integrator + (51) (5.37)
ωI = 2π(1, 770)
Zero at 500Hz
ω1 = 2π(500)
ωz = 2π(1, 580)
ωp = 2π(15, 800)
ωI (1+ ωs )(1+ ωsz )
1
Lead + 45 5.0 90
s(1+ ωsp )
Integrator + (54) (5.35)
ωI = 2π(351)
Zero at 150Hz
ω1 = 2π(150)
ωz = 2π(1, 580)
ωp = 2π(15, 800)
ωI (1+ ωsz )(1+ ωsz )
1 2
Extended 90 40 30
s
Bandwidth ωI = 2π(172) (89) (40)
ωz1 = 2π(100)
ωz2 = 2π(1000)
© Richard Tymerski and Frank Rytkonen, 2017 167
168 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] R. W. Erickson and D. Maksimovi¢, Fundamentals of Power Electronics,
2nd ed. New York, NY: Springer Science+Business Media, LLC, 2001.
[2] R. Tymerski, PECS Simulator ©1999-2009, Portland, OR.
[3] MATLAB, R2012b. Natick, MA: The Mathworks, Inc., 2012.
169
Appendix
8.9.1 Compensator Circuits
170 © Richard Tymerski and Frank Rytkonen, 2017
© Richard Tymerski and Frank Rytkonen, 2017 171
8.10 MATLAB Code
1 clear all
2 close all
3
4 f0 = 1000;
5 Q = 9.5;
6 T0 = 2.33;
7 w0 = 2*pi*f0;
8
9 s = tf('s');
10 Ts = T0/((s/w0)^2 + s/(Q*w0) + 1);
11
12 %%%%%%%%%%%%%%%%%
13 % Open loop
14
15 figure(1)
16 margin(Ts)
17 h = gcr;
18 h.AxesGrid.Xunits = 'Hz';
19 h.AxesGrid.TitleStyle.FontSize = 16;
20 h.AxesGrid.XLabelStyle.FontSize = 12;
21 h.AxesGrid.YLabelStyle.FontSize = 12;
22
23 %%%%%%%%%%%%%%%%%%
24 % Lead compensation
25
26 Gc0 = 3.4;
27 wz = 2*pi*1500;
28 wp = 2*pi*15000;
29
30 Gc1 = Gc0*(1+s/wz)/(1+s/wp);
31
32 Ts1 = Gc1*Ts;
33
34 figure(2)
35 margin(Ts1)
36 h = gcr;
37 h.AxesGrid.Xunits = 'Hz';
38 h.AxesGrid.TitleStyle.FontSize = 16;
39 h.AxesGrid.XLabelStyle.FontSize = 12;
40 h.AxesGrid.YLabelStyle.FontSize = 12;
41
42
43 %%%%%%%%%%%%%%%%%%
44 % 500
45
46 wi = Gc0*2*pi*500;
47 wz2 = 2*pi*500;
48 wz = 2*pi*1500;
49 wp = 2*pi*15000;
50
51 Gc2 = wi/s*(1+s/wz2)*(1+s/wz)/(1+s/wp);
52 Ts2 = Gc2*Ts;
53
172 © Richard Tymerski and Frank Rytkonen, 2017
54 figure(3)
55 margin(Ts2)
56 h = gcr;
57 h.AxesGrid.Xunits = 'Hz';
58 h.AxesGrid.TitleStyle.FontSize = 16;
59 h.AxesGrid.XLabelStyle.FontSize = 12;
60 h.AxesGrid.YLabelStyle.FontSize = 12;
61
62
63
64
65
66 %%%%%%%%%%%%%%%%%%
67 % 150
68
69 wi = Gc0*2*pi*150;
70 wz2 = 2*pi*150;
71 wz = 2*pi*1500;
72 wp = 2*pi*15000;
73
74 Gc3 =wi/s*(1+s/wz2)*(1+s/wz)/(1+s/wp);
75 Ts3 = Gc3*Ts;
76
77 figure(4)
78 margin(Ts3)
79 h = gcr;
80 h.AxesGrid.Xunits = 'Hz';
81 h.AxesGrid.TitleStyle.FontSize = 16;
82 h.AxesGrid.XLabelStyle.FontSize = 12;
83 h.AxesGrid.YLabelStyle.FontSize = 12;
84
85
86 %%%%%%%%%%%%%%%%%%
87 % Extended bandwidth
88
89 %wi = Gc0*2*pi*100;
90 wi = 2*pi*100*40000/(T0*1000); % fc = 40000
91 wz1 = 2*pi*100;
92 wz2 = 2*pi*1000;
93
94 Gc4 = wi/s*(1+s/wz2)*(1+s/wz1);
95 Ts4 = Gc4*Ts;
96
97 figure(5)
98 margin(Ts4)
99 h = gcr;
100 h.AxesGrid.Xunits = 'Hz';
101 h.AxesGrid.TitleStyle.FontSize = 16;
102 h.AxesGrid.XLabelStyle.FontSize = 12;
103 h.AxesGrid.YLabelStyle.FontSize = 12;
104
105 %%%%%%%%%%%%%%%%%%
106 % Dominant pole
107
108 Gcd0 = 200;
109
110 Gc5 = Gcd0/s;
© Richard Tymerski and Frank Rytkonen, 2017 173
111
112 Ts5 = Gc5*Ts;
113
114 figure(6)
115 margin(Ts5)
116 h = gcr;
117 h.AxesGrid.Xunits = 'Hz';
118 h.AxesGrid.TitleStyle.FontSize = 16;
119 h.AxesGrid.XLabelStyle.FontSize = 12;
120 h.AxesGrid.YLabelStyle.FontSize = 12;
121
122 %%%%%%%%%%%%%%%%%%
123 % Dominant pole with zero
124
125 Gcdz0 = 1/sqrt(10)*w0/(T0*Q); % 89.76
126 wz = 2*pi*1000;
127
128 Gc6 = Gcdz0*(1+s/wz)/s;
129
130 Ts6 = Gc6*Ts;
131
132 figure(7)
133 margin(Ts6)
134 h = gcr;
135 h.AxesGrid.Xunits = 'Hz';
136 h.AxesGrid.TitleStyle.FontSize = 16;
137 h.AxesGrid.XLabelStyle.FontSize = 12;
138 h.AxesGrid.YLabelStyle.FontSize = 12;
174 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 9
Droop and Multi-Loop
Control
175
()
Abstract
Constant output voltage is an important feature of a DC voltage regulator.
This paper describes three compensation techniques including voltage droop,
inductor current droop, and voltage compensation to minimize voltage devi-
ation to changes in the output load of the system. Through simulation it is
con rmed that droop compensation improves voltage deviation by a factor of
two in comparison to traditional voltage compensation.
9.1 Introduction
In DC-DC voltage regulators, it is important to supply a constant voltage,
regardless of the current load on the output. The goal of this paper is to describe
three feedback compensation techniques for the Buck converter to limit the
voltage deviation in response to a current step on the output. The designs to
be implemented include a voltage droop compensator [1], an inductor current
compensator [2], and a conventional voltage compensation circuit. For this
design, resistive losses will be included for the inductor and the capacitor to
provide a more complete and accurate analysis.
9.2 Design
9.2.1 Passive Droop Compensation
Concept of droop control
As discussed in [1], the basic concept behind droop control is to apply com-
pensation to the Buck converter in a way that creates a constant, closed-loop
output impedance. By creating a constant output impedance, any variation in
load current will result in a change in output voltage to maintain a constant
impedance. Knowing the maximum load current requirements, the maximum
droop of the system is simply ∆V = ∆IR.
Reviewing the output section of the buck converter including losses, it can
be seen that the open loop output impedance at high frequencies is equal to
the parasitic resistance of the output capacitor. For this design, the parasitic
resistance of the capacitor will be utilized as the value of the output impedance
for the compensated Buck converter.
Derivation of the closed-loop output impedance
As shown in Figure 9.4, the output voltage variation of a Buck converter is
determined based on the variation of the duty cycle, variations in the source
176 © Richard Tymerski and Frank Rytkonen, 2017
Figure 9.1: Transient Response of System with Droop Control
Figure 9.2: Active Droop Control System Block Diagram
voltage, and variations in the load current. For this example, input voltage
variations will be neglected.
By de nition,
Zo (s)
Zoc (s) = (9.1)
1 + T (s)
Following Figure 9.4, T (s) = Fm HGvd (s)Gcon (s), where Fm is the PWM
comparator eect, Gvd (s) is the control to output transfer function, H is the
feedback attentuation, and Gcon (s) is the compensation block to be designed.
To nd Zoc (s) it is necessary to rst calculate Zo (s) (the open loop output
© Richard Tymerski and Frank Rytkonen, 2017 177
Bode Diagram
20
Gm = Inf , Pm = 56.1 deg (at 1.69e+003 Hz)
10
Magnitude (dB)
-10
-20
-30
-40
-50
-60
-70
-80
0
-45
Phase (deg)
-90
-135
-180
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 9.3: MATLAB Uncompensated Bode plot
Figure 9.4: Buck converter control loop
impedance) and Gvd (s). Applying state space averaging methods to calculate
the small signal model of Zo (s) and Gvd (s), the functions are realized as shown
below.
178 © Richard Tymerski and Frank Rytkonen, 2017
s
(1 + ωc )(1 + ωsl )
Zo (s) = rl 2 (9.2)
s s
1+ Qω0 + ω0
s
1+ ωc
Gvd (s) = Vg 2 (9.3)
s s
1+ Qω0 + ω0
√
√1 , 1 rl 1 LC
Where ωo ≈ CL
ωc = rc C , ωl = L, ωR = RC , and Q≈ rl +rc .
Recalling that our aim is to derive a compensator circuit that will implement
a constant output impedance equal to the parasitic resistance of the capacitor,
Zoc is set equal to rc .
Zo (s) Zo (s)
Zoc (s) = = = rc
1 + T (s) 1 + Fm Gvd (s)Gcon (s)
Expanding Zo (s) and Gvd (s):
(1+ ωs )(1+ ωsc )
rl s
l
s 2
1+ Qω o
+ω 2
o
rc = Fm (1+ ωsc )Vg
1+ s s 2 Gcon (s)
1+ Qω o
+ω 2
o
Rearranging the equation,
s 1 1 rc rl rl
rc Fm Vg (1 + )Gcon (s) = rl − rc + [( + )rl − ]s + ( − 2 )s2
ωc ωl ωc Qωo ωl ωc ωo
Expanding the s2 term,
rl rc rl rc
− 2 = rl 1 − 1 = rc (LC − LC) = 0
ωl ωc ωo L rc C LC
Gcon (s) can then be simpli ed into the form:
s
1+ ωzv
Gcon (s) = Kv s (9.4)
1+ ωpv
rl −rc Rl −Rc
Where Kv = rc Vg Fm H ,ωpv = ωc , and ωzv = L−Rc2 C .
Using the circuit parameters de ned in the introduction, Kv = .1.71, ωzv =
4.1k rad
s , and ωpv = 40k rad
s . For a Matlab calculation of these values, please
refer to the MATLAB code provided at the end of the chapter.
Figure 9.5 show the frequency response of the loop gain of the system. Note
that in this compensation design, a small gain at low frequencies is implemented,
which is contrary to typical feedback designs where nearly in nite DC gain is
desired.
© Richard Tymerski and Frank Rytkonen, 2017 179
In Figures 9.6 and 9.7, the open and closed loop output impedance and the
system audio susceptibility are shown as a function of frequency. Note that as
expected, the closed loop output impedance is approximately a constant −26dB
or 50mΩ over the frequency range.
With the compensator circuit now completely de ned, it can be realized us-
ing an operational ampli er circuit. As seen in Figure 9.8, the circuit can be
implemented using a single op-amp.
Since the loop gain of this system is very low, it is not safe to assume that a
reference of 5 V (Vo H ) will work for this system. Looking at the block diagram,
D
if the duty ratio is known, the output voltage of the ampli er is
Fm . Using this
value, the value of Vref can found by applying nodal analysis at V− . Using the
V
DC value of D (
Vg = .53), Vref is found to be equal to approximately 3.9 V.
Through simulation of the droop circuit (Figure 9.8), it is found that the
system performs exactly as expected for a step in current of 0.1 A to 5.0 A.
With an output impedance of 50mΩ, the voltage change ideally would be equal
to 4V = (4.9A)(50mΩ) = .245V , which is approximately what is seen in Fig-
ure 9.8. In the next section, we will expand upon this design to incorporate
additional compensation using the inductor current.
Bode Diagram
20
Gm = Inf , Pm = 92.9 deg (at 6.33e+003 Hz)
10
0
Magnitude (dB)
-10
-20
-30
-40
-50
-60
45
Phase (deg)
-45
-90
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 9.5: MATLAB Bode Plot of Loop Gain with Passive Droop Compensa-
tion
180 © Richard Tymerski and Frank Rytkonen, 2017
-5
-10
Magnitude (dB)
-15
-20
-25
-30
45
Phase (deg)
-45
-90
2 3 4 5 6
10 10 10 10 10
Frequency (Hz)
Figure 9.6: MATLAB Bode Plot of Zo for Passive Droop Compensated System
-10
-20
Magnitude (dB)
-30
-40
-50
-60
-70
-80
0
-45
Phase (deg)
-90
-135
-180
1 2 3 4 5
10 10 10 10 10
Frequency (Hz)
Figure 9.7: MATLAB Bode Plot of Gvg for Passive Droop Compensated System
© Richard Tymerski and Frank Rytkonen, 2017 181
Del = 0.0
Per = 10 u
SW1 Rl L1
250 m 50 u C1
V1 I1 VP1
500 u
Rc
28 SW2 100 m
50 m
C2 C3
R5
146 p 2.4 n
R6 R2 2.0 k
171 k 100 k R7
1.0 k
V2
k1 = 1.0
k2 = 0.0
k3 = 0.0 4.0
Vpk = 4.0
Period = 10 u
Figure 9.8: PECS Schematic of System with Passive Droop Compensation
x101 VP1
1.505
1.500
1.495
1.490
1.485
1.480
1.475
1.470
9.5 10.0 10.5 11.0 11.5 12.0
x10-3
Figure 9.9: PECS Simulation of Passive Droop Compensation Response to a
Load Current Step
182 © Richard Tymerski and Frank Rytkonen, 2017
x101 VP1
1.500
1.495
1.490
1.485
1.480
1.475
1.470
9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
x10-3
Figure 9.10: PECS Simulation of Passive Droop Compensation Response to a
Supply Voltage Disturbance
9.2.2 Active Droop Compensation
Concept of Current Sensing Droop Control
This mode of control implements a constant output impedance equal to the
parasitic resistance of the capacitor, similar to that of the previous section.
However, this feedback system is composed of two loops. One loop is the volt-
age loop that was used in the Section 1 design. The second loop is a current
sensing loop, which measures the inductor current and provides a feedback volt-
age proportional to this current. The goal of this design as presented in [2] is to
combine these two loops into one compensator to control the deviation in the
output voltage. This can be seen in Figure 9.11.
Figure 9.12 shows the current and voltage loops in terms of transfer functions
via small-signal block diagram. Zo (s), Gvd (s), and Fm are the same transfer
functions used in the voltage droop mode. Ri is the inductor current sensing
gain. Av (s) is the transfer function of the feedback compensator, and is syno-
mynous to Gcon (s) in the voltage droop mode. Gii (s) is the transfer function
of inductor current to load current. Gid (s) is the transfer function of induc-
tor current to duty cycle. Applying state space averaging methods to calculate
the small signal model of Gii (s) and Gid (s)(see Appendix 1), the functions are
realized as shown below.
s
1+ ωc
Gii (s) = 2 (9.5)
s s
1+ Qω0 + ω0
© Richard Tymerski and Frank Rytkonen, 2017 183
Figure 9.11: Buck converter with the current sensing mode [2]
s
Vin 1+ ωR
Gid (s) = 2 (9.6)
Ro
s s
1+ Qω0 + ω0
√
√1 , 1 Rl 1 LC
where ωo ≈ CL
ωc = Rc C , ωl = L , ωR = RC , and Q≈ Rl +Rc .
Design of Current Sensing Droop Control
To create a feedback compensator Av (s) for the current sensing droop control,
the rst step is realizing the functions for the current loop Ti (s) and the voltage
loop Tv (s). This can be achieved by following each loop in Figure 9.12. For a
complete diagram including input voltage disturbances, refer to Figure 9.20.
Ti (s) = Av (s)Fm Gid (s)Ri (9.7)
Tv (s) = Av (s)Fm Gvd (s) (9.8)
In order to determine a single compensator Av (s) for both loops, Ti (s) and
Tv (s) need to be related. Because the compensator eects both loops, it is
important to design the loops with the same characteristics. This allows both
loops to be in unison and not work against each other. This can be achieved by
designing both loops to have the same crossover frequency. This happens when
the ratio of the two loops is set equal to 1.
Tv (s) Gvd (s) R(1 + ωsc )
= = (9.9)
Ti (s) Ri Gid (s) Ri (1 + ωsR )
184 © Richard Tymerski and Frank Rytkonen, 2017
Figure 9.12: Small-signal block diagram of the current sensing mode
It can be seen that this ratio equals 1 when Ri = Rc and when ω > ωc , since
the zero from the output capacitor is normally much larger than ωR .
The design should be similar to the voltage droop control in terms of having
a constant impedance gain equal to the parasitic losses of the output capacitor.
The closed-loop output impedance function, Zoc (s), is shown below.
Zo (s)(1 + Ti (s)) + Ti (s) GvdG(s)G ii (s)
id (s)
Zoc (s) = (9.10)
1 + Ti (s) + Tv (s)
Setting the above equation equal to the value of Rc the transfer function
of Av (s) can be derived. From [2], the current loop should be stable with a
phase margin of around 90◦ . In order to achieve this, a zero, ωz , is needed to
compensate for the power stage double pole. The high frequency switching noise
should also be ltered. This requires a pole, ωp , placed well before the switching
frequency. The current loop should have a crossover frequency that is higher
than the parasitic zero of the output capacitor. This can be done by making
the gain, ωi , of the compensator su ciently large. Since in nite DC gain is
1
required, an integrator is used by placing a pole at zero,
s . The compensator
transfer function can now be realized.
© Richard Tymerski and Frank Rytkonen, 2017 185
Figure 9.13: Small-signal block diagram of the current sensing mode -General
186 © Richard Tymerski and Frank Rytkonen, 2017
s
1+ ωz
Av (s) = ωi (9.11)
s(1 + ωsp )
where ωz = ωo , ωp = (2π)50, 000, and ωi = 100, 000
The compensator can now be implemented using an operational ampli er
circuit. As seen if Figure 9.17, this circuit can be implemented using a single
op-amp. The summing of the two loops is incorporated into the op-amp used
by the compensator. Please note the use of a voltage divider in the voltage
feedback loop is similar to that in the previous section, only it has been scaled
1
to a ratio of
2 for component value selection.
The loop gain of this system is a ratio of the current and voltage loops, and
once again it's not safe to assume a reference of 5 V will work for this system.
Vref is found to be approximately 3.8 V in this design.
Loop Gain Analysis
With the design stage complete, the system can be analyzed for stability and
crossover frequency veri cation. The outer loop, T2 , shown below, determines
the system stability.
Tv (s)
T2 (s) = (9.12)
1 + Ti (s)
It can be seen in Figure 9.14 that all three loops have the same crossover
frequency. Stability is veri ed with T2 having a phase margin of about 105◦ .
This is really close to the design of 90◦ , with other poles and zeros from Tv and
Ti accounting for the slight dierence.
It can be observed in Figure 9.15 that the impedance gain is nearly constant.
The impedance phase is also nearly constant as it changes only slightly over the
entire range of frequencies.
In Figure 9.18, the current sensing droop control was simulated with a step
in the load current, the same as was performed Section 1. The results are
nearly the same as with the voltage droop control. There are slight transient
spikes, but they are small and are on the order of the ripple. These spikes are
caused from the slight deviation in the constant output impedance. With the
output impedance at 50mΩ, the ideal voltage change would again be .245 V.
Aside from the slight transient spikes, this is what is approximately seen in
Figure 9.18. This two loop compensation control can achieve the same results
as the simple voltage droop control, yet have the versatility to compensate for
both voltage and current. In the next section, a voltage compensation scheme
will be presented and compared to the droop control methods.
© Richard Tymerski and Frank Rytkonen, 2017 187
Bode Diagram
Gm
100
= 87.9 dB (at 2.71e+006 Hz) , Pm = 84.1 deg (at 6.67e+003 Hz)
80
60
Magnitude (dB)
40
20
-20
-40
-60
-80
-100
0
-45
Phase (deg)
-90
-135
-180
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 9.14: MATLAB Bode Plot of Loop Gains with Active Droop Compen-
sation
9.2.3 Voltage Mode Compensation
Concept of voltage compensation
The nal design that will be discussed in this report is a traditional voltage
compensation design. Back in Figure 9.4, we found for the purposes of droop
control that we would design for changes in output current and neglect any
disturbances in the input voltage. For this design, the compensation circuit will
vb
be designed to reduce the audio susceptibility of the circuit (Gcl (s) =
vgb). This
design will then be tested by applying a step disturbance to the load current,
and determining the maximum deviation of the output voltage in response to
the disturbance.
By following the loop in Figure 9.4, it can be seen by inspection that Gcl (s) =
Gvg (s)
1+T (s) , where T (s) = Gvd (s)(F m)Gcon (s) and Gvd (s) is the same as in Section
1 and Section 2. Gvg (s) can be found to equal the following expression:
s
1+ ωc
Gvg (s) = D 2 (9.13)
s s
1+ Qω0 + ω0
188 © Richard Tymerski and Frank Rytkonen, 2017
-5
-10
Magnitude (dB)
-15
-20
-25
-30
45
Phase (deg)
-45
-90
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 9.15: MATLAB Bode Plot of Zo for Active Droop Compensated System
-10
-20
Magnitude (dB)
-30
-40
-50
-60
-70
-80
-90
-100
360
Phase (deg)
180
-180
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Frequency (Hz)
Figure 9.16: MATLAB Bode Plot of Gvg for Active Droop Compensated System
© Richard Tymerski and Frank Rytkonen, 2017 189
Del = 0.0
Per = 10 u
SW1 Rl L1
250 m 50 u C1
V1 R14 I1 VP1
500 u
R8 2.0 k R13 Rc
28 SW2 100 m
50 m 1.0 k 50 m
C2
33 p
R11 C3 R10 R7
96 k 1.6 n 5.5 k
R9 2.0 k
5.5 k R12
V2
k1 = 1.0
k2 = 0.0 1.0 k
k3 = 0.0 2.5
Vpk = 4.0
Period = 10 u
Figure 9.17: PECS Schematic of System with Active Droop Compensation
x101 VP1
1.505
1.500
1.495
1.490
1.485
1.480
1.475
1.470
9.5 10.0 10.5 11.0 11.5 12.0
x10-3
Figure 9.18: PECS Simulation of Active Droop Compensated Response to a
Load Current Step
190 © Richard Tymerski and Frank Rytkonen, 2017
x101 VP1
1.482
1.480
1.478
1.476
1.474
1.472
1.470
1.468
9.5 10.0 10.5 11.0 11.5 12.0
x10-3
Figure 9.19: PECS Simulation of Active Droop Compensated Response to a
Supply Voltage Disturbance
Figure 9.20: Complete Small-signal block diagram of the current sensing mode
© Richard Tymerski and Frank Rytkonen, 2017 191
Where all parameters of the equation are the same as described in the previous
sections.
Designing loop compensation
The goal of this design is to create a compensation block that will maxi-
mally reduce the eect of input voltage disturbances on the output. To improve
on the basic integrator compensator design, two zeros are added around the
crossover frequency to combat the extra −90◦ of phase shift introduced by the
integrator. Two poles are also introduced to ensure that the switching frequency
noise will be canceled with the introduction of the zero. The equation for this
compensation block is shown below:
s s
ωI (1 + ωz1 )(1 + ωz2 )
Gcon (s) = s s (9.14)
s (1 + ωp1 )(1 + ωp2 )
where ωI is the constant gain and ωz1 , ωz2 , ωp1 , and ωp2 are the new param-
eters to be designed.
To gain a better understanding of the system, the system transfer functions
are plotted for three dierent cases of zero placement:
192 © Richard Tymerski and Frank Rytkonen, 2017
Figure 9.21: Bode Plot Asymptotes for Case 1
© Richard Tymerski and Frank Rytkonen, 2017 193
Figure 9.22: Bode Plot Asymptotes for Case 2
194 © Richard Tymerski and Frank Rytkonen, 2017
Figure 9.23: Bode Plot Asymptotes for Case 3
© Richard Tymerski and Frank Rytkonen, 2017 195
To determine a proper location for the introduced components, it is important
to rst start by improving the phase margin. This is accomplished by having
at least one zero below the natural frequency of the system. By introducing
one zero rather than both at this point, it will work to exactly cancel the phase
shift introduced by the integrator without dropping the loop gain more than
necessary. Introducing the second zero after the natural frequency will help
extend the loop gain bandwidth, pushing the crossover frequency further toward
higher frequency.
Through careful adjustment of parameter location and system response sim-
ulation, the system parameters were calculated as shown below. An optimum
crossover frequency is found in terms of improving the phase margin, yet also
maximizing loop gain bandwidth at fc = 6.31kHz . This will be shown in the
system response later in this section.
krad
ωz1 = (2π)5.06
s
krad
ωz2 = (2π)8.22
s
krad
ωp1 = ω( z) = (2π)6.37
s
krad
ωp2 = (2π)63.6
s
rad
ωI = 17k
s
Figure 9.24 describe the loop gain of the system as a function of frequency.
Note that with the previously discussed changes, high DC gain, switching fre-
quency attenuation, and system stability are all accomplished.
Figure 9.27 is the circuit realization of the compensation scheme designed
above. Figure 9.28 shows the simulation results of the circuit in response to
the change in output current described in the introduction. Note that the
maximum deviation from peak to peak using this voltage compensation scheme
is 300 mV. The system shows a spike in voltage when the current is changed, and
then quickly reduces to the expected voltage. This clearly shows the dierence
between this method of design and the constant impedance method, where a
constant impedance will have half of the peak to peak voltage deviation; yet,
there is a dierence in the average output voltage level depending on the load
applied. However, since power supply requirements are typically quanti ed in
terms of an output voltage tolerance range, the voltage droop compensation and
current droop compensation allow for tighter restrictions on levels, thus making
them a better design compared to traditional voltage compensation.
196 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm
100
= 85.6 dB (at 2.71e+006 Hz) , Pm = 74.2 deg (at 6.31e+003 Hz)
80
60
Magnitude (dB)
40
20
-20
-40
-60
-80
-100
-45
Phase (deg)
-90
-135
-180
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 9.24: MATLAB Bode Plot of Loop Gains with Voltage Mode Compen-
sation
-10
-20
Magnitude (dB)
-30
-40
-50
-60
-70
-80
90
45
Phase (deg)
-45
-90
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 9.25: MATLAB Bode Plot of Zo for Voltage Mode Compensated System
© Richard Tymerski and Frank Rytkonen, 2017 197
0
-10
-20
Magnitude (dB)
-30
-40
-50
-60
-70
-80
-90
-100
90
45
Phase (deg)
-45
-90
-135
-180
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 9.26: MATLAB Bode Plot of Gvg for Voltage Mode Compensated System
Del = 0.0
Per = 10 u
SW1 Rl L1
250 m 50 u C1
V1 I1 VP1
500 u
Rc
28 SW2 100 m
50 m
C2 R8 C3
R5
33 p 4.5 k 5.5 n
R2 C2 R2 2.0 k
76 k 7.0 n 24 k R7
1.0 k
V2
k1 = 1.0
k2 = 0.0
k3 = 0.0 5.0
Vpk = 4.0
Period = 10 u
Figure 9.27: PECS Schematic of System with Voltage Mode Compensation
198 © Richard Tymerski and Frank Rytkonen, 2017
x101 VP1
1.530
1.520
1.510
1.500
1.490
1.480
1.470
9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
x10-3
Figure 9.28: PECS Simulation of Voltage Mode Compensated Response to a
Load Current Step
x101 VP1
1.515
1.510
1.505
1.500
1.495
1.490
1.485
9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0
x10-3
Figure 9.29: PECS Simulation of Voltage Mode Compensated Response to a
Supply Voltage Disturbance
© Richard Tymerski and Frank Rytkonen, 2017 199
9.3 Summary
Through implementation of a voltage droop, inductor current droop, and a
voltage compensation circuit, it was found that the voltage and current droop
compensation techniques were able to have an output voltage deviation of half
the size of the voltage compensation method. This reduction in output voltage
deviation is an eect of creating a constant closed loop output impedance on
the output of the converter. The only downside to the droop compensation
methods is that the output voltage changes to the deviation value, rather than
introducing a small transient and returning, as is the case with the voltage
compensation.
Overall, due to the fact that regulated voltages are de ned over an acceptable
output range, the droop control methods both allow the smallest deviation that
can t in a given tolerance window. Ideally the current sensing droop control is
the most complete method of compensation due to the two loop compensation.
Practically, however, the voltage droop method accurately reduces the output
voltage deviation and is the simplest to implement in terms of components.
9.4 MATLAB Code
1 clear
2 close all
3 format compact
4
5 s = tf('s');
6
7 Vg = 28;
8 R = 3;
9 L = 50e−6;
10 C = 500e−6;
11 rl = 0.25;
12 rc = 0.05;
13 Vm = 4;
14 Vo = 15;
15 D = Vo/Vg;
16
17
18 H = 1/3;
19 w0 = 1/sqrt(L*C);
20 f0 = w0/(2*pi);
21 wc = 1/(rc*C);
22 wr = 1/(R*C);
23 wl = rl/L;
24 Q = sqrt(L/C)/(rl+rc);
25 PWM = 1/Vm;
26 T0 = Vg*H*PWM;
27
28
200 © Richard Tymerski and Frank Rytkonen, 2017
29 f = logspace(1,6,1000);
30 w = 2*pi*f;
31
32 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
33 %%% Plant Open−loop
34
35 Gvg = D*(1+s/wc)/(1+s/(Q*w0)+(s/w0)^2);
36 Gvd = Vg*(1+s/wc)/(1+s/(Q*w0)+(s/w0)^2);
37 Zo = rl*(1+s/wc)*(1+s/wl)/(1+s/(Q*w0)+s^2/w0^2);
38
39 %%% Loop gain
40 T = tf(T0*[1/wc 1], [1/w0^2 1/(Q*w0) 1]);
41
42 figure(1)
43 [mag, phase] = bode(T,w);
44 margin(mag, phase, w)
45
46 h = gcr;
47 h.AxesGrid.Xunits = 'Hz';
48 h.AxesGrid.TitleStyle.FontSize = 16;
49 h.AxesGrid.XLabelStyle.FontSize = 12;
50 h.AxesGrid.YLabelStyle.FontSize = 12;
51
52 % Zoc = Zo/(1+T);
53 % Gvgc = Gvg/(1+T);
54 %
55 % figure(2)
56 % bode(Zo);
57 % hold
58 % bode(Zoc)
59 % title('');
60 % h = gcr;
61 % h.AxesGrid.Xunits = 'Hz';
62 % h.AxesGrid.TitleStyle.FontSize = 16;
63 % h.AxesGrid.XLabelStyle.FontSize = 12;
64 % h.AxesGrid.YLabelStyle.FontSize = 12;
65 %
66 %
67 % figure(3)
68 % bode(Gvg);
69 % hold
70 % bode(Gvgc)
71 % title('');
72 % h = gcr;
73 % h.AxesGrid.Xunits = 'Hz';
74 % h.AxesGrid.TitleStyle.FontSize = 16;
75 % h.AxesGrid.XLabelStyle.FontSize = 12;
76 % h.AxesGrid.YLabelStyle.FontSize = 12;
77
78
79
80
81 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
82 %%% Droop passive
83
84 Kv = (rl−rc)/(rc*Vg*(1/Vm)*H);
85 wzc = (rl−rc)/(L−rc*rc*C);
© Richard Tymerski and Frank Rytkonen, 2017 201
86 wpv = wc;
87
88 Gcdroop_p = tf(Kv*[1/wzc 1], [1/wpv 1]);
89
90 Tdroop_p = Gcdroop_p * T;
91
92 figure(4)
93 [mag, phase] = bode(Tdroop_p,w);
94 margin(mag, phase, w)
95 h = gcr;
96 h.AxesGrid.Xunits = 'Hz';
97 h.AxesGrid.TitleStyle.FontSize = 16;
98 h.AxesGrid.XLabelStyle.FontSize = 12;
99 h.AxesGrid.YLabelStyle.FontSize = 12;
100
101
102 Zoc = Zo/(1+Tdroop_p);
103 Gvgc = Gvg/(1+Tdroop_p);
104
105 figure(2)
106 bode(Zo);
107 hold
108 bode(Zoc)
109 title('');
110 h = gcr;
111 h.AxesGrid.Xunits = 'Hz';
112 h.AxesGrid.TitleStyle.FontSize = 16;
113 h.AxesGrid.XLabelStyle.FontSize = 12;
114 h.AxesGrid.YLabelStyle.FontSize = 12;
115
116
117 figure(3)
118 bode(Gvg);
119 hold
120 bode(Gvgc)
121 title('');
122 h = gcr;
123 h.AxesGrid.Xunits = 'Hz';
124 h.AxesGrid.TitleStyle.FontSize = 16;
125 h.AxesGrid.XLabelStyle.FontSize = 12;
126 h.AxesGrid.YLabelStyle.FontSize = 12;
127
128
129 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
130 %%% Droop active
131
132 wi_da = 100000;
133 wz_da = w0;
134 wp_da = 2*pi*50000;
135
136 % wi_da = 7.3529e+004;
137 % wz_da = w0;
138 % wp_da = 2*pi*5.4683e+004;
139
140 Gcvdroop_a = tf(wi_da*[1/wz_da 1], conv([1 0], [1/wp_da 1]));
141
142 Tvdroop_a = Gcvdroop_a * T;
202 © Richard Tymerski and Frank Rytkonen, 2017
143
144 figure(5)
145 [mag, phase] = bode(Tvdroop_a,w);
146 margin(mag, phase, w)
147
148 hold
149
150 Ti = tf(Vg/R*[1/wr 1], [1/w0^2 1/(Q*w0) 1]);
151 Tidroop_a = PWM * H *Gcvdroop_a * Ti * rc;
152
153 [mag, phase] = bode(Tidroop_a,w);
154 margin(mag, phase, w)
155
156 T2 = Tvdroop_a/(1+Tidroop_a);
157 [mag, phase] = bode(T2,w);
158 margin(mag, phase, w)
159
160 h = gcr;
161 h.AxesGrid.Xunits = 'Hz';
162 h.AxesGrid.TitleStyle.FontSize = 16;
163 h.AxesGrid.XLabelStyle.FontSize = 12;
164 h.AxesGrid.YLabelStyle.FontSize = 12;
165
166 hold off
167
168
169
170
171 Gii=(1+s/wc)/(1+s/(Q*w0)+s^2/w0^2);
172 Gid=(Vg/R)*(1+s/wr)/(1+s/(Q*w0)+s^2/w0^2);
173 Gig=s*C/(1+s/(Q*w0)+s^2/w0^2);
174
175 % Av=wi*(1+s/w1)/(s*(1+s/w2));
176 % Ti= Av*Fm*Gid*H*Ri1;
177 % Tv=Av*Fm*H*Gvd;
178 % T2=Tv/(1+Ti);
179 %Gvgc=Gvg/(1+T2);
180
181 Ti = Tidroop_a;
182 Tv = Tvdroop_a;
183
184 Zoc = (Zo*(1+Ti)+Ti*(Gvd*Gii)/Gid)/(1+Ti+Tv);
185 Gvgc = (Gvg*(1+Ti)−Ti*(Gvd*Gig)/Gid)/(1+Ti+Tv);
186
187 figure(9)
188 bode(Zo);
189 hold
190 bode(Zoc)
191 title('');
192 h = gcr;
193 h.AxesGrid.Xunits = 'Hz';
194 h.AxesGrid.TitleStyle.FontSize = 16;
195 h.AxesGrid.XLabelStyle.FontSize = 12;
196 h.AxesGrid.YLabelStyle.FontSize = 12;
197
198
199 figure(10)
© Richard Tymerski and Frank Rytkonen, 2017 203
200 bode(Gvg);
201 hold
202 bode(Gvgc)
203 title('');
204 h = gcr;
205 h.AxesGrid.Xunits = 'Hz';
206 h.AxesGrid.TitleStyle.FontSize = 16;
207 h.AxesGrid.XLabelStyle.FontSize = 12;
208 h.AxesGrid.YLabelStyle.FontSize = 12;
209
210
211
212
213 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
214 %%% Voltage mode
215
216 wi = 17000;
217 wz1 = 0.8*w0;
218 wz2 = 1.3*w0;
219 wp1 = wc;
220 wp2 = 10*wp1;
221
222 Gcvmode = tf(wi*conv([1/wz1 1], [1/wz2 1]), conv([1 0], ...
conv([1/wp1 1], [1/wp2 1])));
223
224 Tvmode = Gcvmode * T;
225
226 figure(6)
227 [mag, phase] = bode(Tvmode,w);
228 margin(mag, phase, w)
229 h = gcr;
230 h.AxesGrid.Xunits = 'Hz';
231 h.AxesGrid.TitleStyle.FontSize = 16;
232 h.AxesGrid.XLabelStyle.FontSize = 12;
233 h.AxesGrid.YLabelStyle.FontSize = 12;
234
235 Zoc = Zo/(1+Tvmode);
236 Gvgc = Gvg/(1+Tvmode);
237
238 figure(7)
239 bode(Zo);
240 hold
241 bode(Zoc)
242 title('');
243 h = gcr;
244 h.AxesGrid.Xunits = 'Hz';
245 h.AxesGrid.TitleStyle.FontSize = 16;
246 h.AxesGrid.XLabelStyle.FontSize = 12;
247 h.AxesGrid.YLabelStyle.FontSize = 12;
248
249
250 figure(8)
251 bode(Gvg);
252 hold
253 bode(Gvgc)
254 title('');
255 h = gcr;
204 © Richard Tymerski and Frank Rytkonen, 2017
256 h.AxesGrid.Xunits = 'Hz';
257 h.AxesGrid.TitleStyle.FontSize = 16;
258 h.AxesGrid.XLabelStyle.FontSize = 12;
259 h.AxesGrid.YLabelStyle.FontSize = 12;
260
261
262
263 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
264 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
265 %%% Components
266
267 %%% Droop passive
268 display(' Droop passive ')
269 R1 = 100000;
270 C1 = 1/(R1*wzc);
271 R2 = Kv*R1;
272 C2 = 1/(R2*wpv);
273
274 R1
275 R2
276 C1
277 C2
278 display(' ')
279
280 %%% Droop active
281
282 display('Droop active ')
283 C1 = 33e−12;
284 R2 = 1/(wp_da*C1);
285 C2 = 1/(R2*wz_da);
286 R1 = 1/(C2*wi_da);
287
288
289 R1
290 R2
291 C1
292 C2
293 display(' ')
294
295 %%% Voltage mode, R1 >> R3, C1 >> C3
296
297 display('Voltage mode ')
298 C3 = 33e−12;
299 R2 = 1/(C3*wp2);
300 C1 = 1/(R2*wz1);
301 R1 = 1/(C1*wi);
302 C2 = 1/(R1*wz2);
303 R3 = 1/(C2*wp1);
304
305 C1
306 C2
307 C3
308 R1
309 R2
310 R3
311
312 %%% Droop passive
© Richard Tymerski and Frank Rytkonen, 2017 205
313 % R1 =
314 % 100000
315 % R2 =
316 % 1.7143e+005
317 % C1 =
318 % 2.4375e−009
319 % C2 =
320 % 1.4583e−010
321
322
323 % Droop active
324 % wi_da = 70000;
325 % wz_da = w0;
326 % wp_da = 70000;
327 %
328 % R1 =
329 % 3.9113e+004
330 % R2 =
331 % 4.3290e+005
332 % C1 =
333 % 3.3000e−011
334 % C2 =
335 % 3.6524e−010
336
337
338 % %%% Droop active
339 % wi_da = 150000;
340 % wz_da = w0;
341 % wp_da = 50000;
342 % R1 =
343 % 2.5554e+004
344 % R2 =
345 % 6.0606e+005
346 % C1 =
347 % 3.3000e−011
348 % C2 =
349 % 2.6089e−010
350
351
352 %%% Voltage mode
353 % wi = 7000;
354 % wz1 = 0.3*w0;
355 % wz2 = 1.4*w0;
356 % wp1 = wc;
357 % wp2 = 10*wp1;
358 %
359 % C1 =
360 % 6.9570e−009
361 % C2 =
362 % 5.5000e−009
363 % C3 =
364 % 3.3000e−011
365 % R1 =
366 % 2.3957e+004
367 % R2 =
368 % 7.5758e+004
369 % R3 =
206 © Richard Tymerski and Frank Rytkonen, 2017
370 % 4.5455e+003
371
372
373 % %%% Voltage mode
374 % wi = 17000;
375 % wz1 = 0.8*w0;
376 % wz2 = 1.3*w0;
377 % wp1 = wc;
378 % wp2 = 10*wp1;
379 %
380 % C1 =
381 % 2.6089e−009
382 % C2 =
383 % 5.3942e−009
384 % C3 =
385 % 3.3000e−011
386 % R1 =
387 % 2.2547e+004
388 % R2 =
389 % 7.5758e+004
390 % R3 =
391 % 4.6346e+003
392
393
394 %%%% Droop active
395 R1 = 50e3;
396 R2 = 593e3;
397 C1 = 5e−12;
398 C2 = 267e−12;
399 wi = 1/(R1*(C1+C2));
400 fz = 1/(2*pi*R2*C2);
401 fp = 1/(2*pi*R2*C1*C2/(C1+C2));
402 display('Droop active − good')
403 wi
404 fz
405 fp
© Richard Tymerski and Frank Rytkonen, 2017 207
208 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] K. Yao, M. Xu and F. Lee, Design Considerations for VRM Transient
Response Based on the Output Impedance, IEEE Trans. Power Electron.,
vol. 18, no. 6, pp. 12701277, November 2003.
[2] K. Yao, K. Lee, M. Xu and F. Lee, Optimal Design of the Active Droop
Control Method for the Transient Response, in IEEE Applied Power Elec.
Conf. and Expo., vol. 2, 2003, pp. 718723.
209
210 © Richard Tymerski and Frank Rytkonen, 2017
Part III
Classical Control: Laboratory
211
Chapter 10
Introduction to the Labs
Classical control design is generally undertaken in the frequency domain as op-
posed to the time domain. Examination of a system in the frequency domain
allows for simpler determination of stability, through the use of phase and gain
margin metrics.
The classical control design methodology requires that a system model in the
form a transfer function be available. This is complicated by the fact that often
a suitable model may not be apparent. The following set of labs starts with a
simple system consisting of a single-pole, double-throw switch followed by an
LC lter, proceeds through the modelling of the system and subsequently to the
design of an eective controller. The purpose of this system is to convert a dc
voltage at a higher level to a lower level while achieving a high power e ciency,
typically in the 90% range. The system examined is known a Buck dc-to-dc
power converter and is widely used in industry. The endgame is to enclose this
system with negative feedback to produce an eective voltage regulation, in the
face of input voltage and output load variations, and so an eective controller
needs to be designed.
The apparent simplicity of the buck converter belies the modeling challenges
that can be brought to light. The function of the switch in the system is to
produce pulses whose width can be varied. The control of the pulse width is
undertaken by a pulse width modulator (PWM). This is inherently a nonlinear
device since a sinusoidal input produces a sinusoidally modulated pulse train
which contains spectral components not present in the input. In this case, a
so-called describing function analysis is used in modelling the system. This ap-
proach determines the magnitude and phase of the spectral component in the
output which is at the same frequency as the sinusoidal input.
Furthermore the buck converter itself is a time varying system but from basic
considerations we are able to de ne an average model which features a number
of dierent transfer functions of interest. In essence the system considered has
213
three inputs and one output (the output voltage). There is one control input
and two disturbance inputs, leading to a total of three transfer functions that
need to be modelled.
Two sets of software tools are used to help with the design and veri cation
in these labs:
1. Matlab: As compensator design is undertaken in the frequency domain,
Bode plots are used to examine magnitude and phase responses of various
transfer functions, in particular the loop gain which is important in as-
sessing phase and gain margins. Additionally, Matlab is used to examine
time-domain simulations using the derived small-signal transfer function
models
2. PECS: This simulator permits circuit level simulation of the physical cir-
cuit, rather than just its small-signal model, and so more faithfully repre-
sents the operation of the actual system, showing large-signal eects such
as ripple voltage.
The software tools will be used to verify the derived transfer functions and,
in the process, help to obtain a better understanding of the system. The circuit
simulator allows one to see waveforms that closely resemble those that would be
observed in a hardware implementation as large signal eects can also be seen in
the simulation. Having arrived at transfer function models for a system, these
transfer functions are used in the classical control design process and can also
be used to produce time domain simulations. Thus it becomes instructive to see
how well these time domain simulations conform to the simulations obtained
from Matlab resulting from small-signal transfer function models. Becoming
further instructive when observing waveforms of the hardware implementation.
It is the aim of these series of labs to start with a simple system, that is widely
used, and to go through the whole process from understanding system operation
to the end point of reaching a design that incorporates feedback control. A big
picture set of aims for this series of labs is the following:
1. Obtain a clear understanding of the buck converter system operation
2. Obtain a suitable model of the system
3. Test the (open loop) system and verify the model.
4. Examine the eectiveness of a simple compensator used in (closed loop)
feedback control.
5. Design a more eective and albeit more complicated controller.
6. Test the improved system design and understand how and why the im-
provement has been achieved.
214 © Richard Tymerski and Frank Rytkonen, 2017
In terms of the labs themselves, the titles are listed next:
Lab 1: Introduction to a basic dc-to-dc power conversion system and the
PECS circuit simulator
Lab 2: System Identi cation of a 2nd Order System through Step Response
Lab 3: System Identi cation of the dc-to-dc Buck converter
Lab 4: Open loop system construction and testing: the Buck dc-to-dc
voltage converter
Lab 5: Closed Loop Feedback System - Analysis: Analysis and perfor-
mance of a closed loop dc-to-dc Buck converter system
Lab 6: Closed Loop Feedback System - Design: Design of an eective
feedback compensator for a closed loop dc-to-dc converter system
Labs 1 to 3 involve the software tools in helping to understand the system
and in the process of system identi cation i.e. discovering and verifying trans-
fer functions. Labs 4 to 6 involve hardware construction. In particular, Lab. 6
involves controller design using the asymptotic Bode plot construction method-
ology discussed in class. The design is fully veri ed using the software tools
before implementation.
The labs have been written to be stand-alone. Consequently, su cient back-
ground material has been included in each lab with the aim to provide su cient
understanding required for the lab and hopefully, for the most part, obviating
the need to search elsewhere for this information.
© Richard Tymerski and Frank Rytkonen, 2017 215
216 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 11
Lab 1
Introduction to a basic dc-to-dc power con-
version system and the PECS circuit sim-
ulator
11.1 Objectives
1. To introduce a basic dc-to-dc power conversion system.
2. To introduce the PECS simulator which simulates these systems at the
circuit level. Speci cally to gain experience with the use of the switch
(SW), pulse width modulator (MOD) and clock (CLK) elements used in
PECS and which appear in later labs.
Before using the PECS simulator, read the documentation which provides an
overview of PECS su cient for this and subsequent labs.
11.2 Circuit #1
The circuit in Figure 11.1 switches a voltage source (V1) ON and OFF to pro-
duce a rectangular wave (appearing across voltage port VP1) which is then
ltered through an LC network which produces a lower dc voltage across a load
(R1). This voltage, monitored by port VP2, will be examined.
This example circuit also illustrates how clock elements can be used to control
switches.
217
Figure 11.1: A pulse generator followed by a second order (LC) lter, (L =
560 µH, C = 100 µF and R = 25 Ω) constitutes a dc-to-dc voltage converter.
(buck_clocks.ckt)
11.2.1 Tasks
1. Construct the circuit in Figure 11.1 in PECS. Leave the initial conditions
for L and C at zero and set the initial state of the switches to ON and
OFF for the top and bottom switches, respectively. (However, the initial
switch state is not important here but must be set to some state prior to
trying to run a simulation). Also, be aware when building the circuit that
connections to components are only made at the nodes of the components
2. Use the following simulation parameters: Final Time = 6e-2, Step Size =
2e-7, Start time = 0, End time = 6e-2. These simulation parameters will
provide a simulation of the circuit for 60 ms (as speci ed by Final Time )
where recording of the waveform points occur every 200 ns (as speci ed by
Step Size ) as well as points occurring at switching discontinuities. At the
end of the simulation time points occurring between the Start Time and
End Time will be saved to the hard drive, which will subsequently be read
by the plotting program (PECSPLOT). For the times chosen here, points
from the whole simulation run will be saved. The relatively short Step
Size value chosen results in many points being saved which will produce
smooth output plots.
3. Run the simulation. This can be initiated from the menu items by selecting
Simulation → Run, or more conveniently from the top icon bar by clicking
the (left) script R (which appears in red).
4. Obtain a plot of the waveform across VP2, the output voltage. Looking
at your plot determine the steady state value, that is, the value of the
output voltage at the end of the simulation.
5. We would like to now look more closely at 4 or 5 cycles at the end of the
simulation. Use the Zoom feature in PECSPLOT to isolate these. Access
218 © Richard Tymerski and Frank Rytkonen, 2017
this through menu items View → Zoom and then use the mouse to isolate
the time period of interest. Left click the mouse anywhere in the plotting
area at the desired starting time and drag to the desired ending time.
This can be repeated any number of times to hone into your desired time
interval.
6. Under the plot obtained in the previous task add the VP1 waveform. Do
this by accessing from the menu items: Plots → Add Plot then select the
desired out from the list of outputs shown.
7. Use the measuring feature (accessed through menu item Plots → Measure )
to nd the peak-to-peak voltage ripple of the output voltage (VP2). Use
the right (→ ) and left (← ) arrows on the keyboard to precisely pinpoint
the maximum and minimum values of the waveform after initially placing
the measurement markers by clicking the left and right mouse buttons.
8. For the waveform of VP1, note the peak amplitude, period and pulse width
of this waveform. Determine the duty ratio of the pulse train. The duty
ratio is de ned as the length of the high portion of the pulse, i.e. the pulse
width, divided by the period.
9. Taking the above plots into consideration, explain why you would expect
to get the steady state value you found in task (4).
11.3 Circuit #2
The circuit in Figure 11.2 produces a sawtooth voltage waveform which ap-
pears across the capacitor (C1). This is achieved by using a constant current
source (I1) to charge the capacitor and having the capacitor rapidly discharged
through the resistor (R1) when the voltage has reached a preset level. The ca-
pacitor voltage and current are monitored by VP1 and IP1, respectively.
This circuit illustrates the use of the pulse width modulator element. However,
in this circuit not all features of the modulator are used. The modulator is
basically a comparator with four inputs, two of which connect externally, one
connects to a user set constant value and the last connects to an internal saw-
tooth signal. We will just use one of the external connections and the internal
constant input. (The internal sawtooth signal is not used).
© Richard Tymerski and Frank Rytkonen, 2017 219
Figure 11.2: Sawtooth generator. A 1 A current source charges a 100 µF capac-
itor which is periodically quickly discharged through a 10 mΩ resistor. (saw-
tooth_3.ckt)
11.3.1 Tasks
1. Construct the circuit in Figure 11.2 in PECS. Note that for the modulator
we are setting K1 = −1 and K3 = 2, with the other modulator parameters
left untouched. The clock element has a Delay = 0 and Period = 210e-6.
2. Use the following simulation parameters: Final Time = 1e-3, Step Size =
1e-6, Start time = 0, End time = 1e-3. Run the simulation.
3. Obtain a plot of the voltage waveform across the capacitor (VP1) and
under this have a plot of the capacitor current (IP1).
4. For the waveform of VP1, note the peak amplitude and period. Given
that K1 = −1, what other factors in the circuit determines the peak
amplitude and why?
11.4 Circuit #3
We will modify the circuit in Figure 11.1 by replacing one of the clocks with a
modulator and a DC voltage source. The modulator output is connected to the
switch control terminal where the deleted clock had been. The added voltage
source's positive terminal is connected to the top input of the modulator. The
negative terminal is connected to ground. The con guration we are seeking is
for the modulator to turn OFF the upper switch (and turn ON the lower switch).
The modulator parameter K1 associated with the top modulator input is set to
K1 = 1. (Also be sure to have K2 = 0 and K3 = 0). We will also specify the
modulator internal sawtooth to have a peak voltage of 5 V, i.e. Vpk = 5.
220 © Richard Tymerski and Frank Rytkonen, 2017
Furthermore, we will change the frequency of operation of this circuit to 40 kHz .
So the period parameters of the modulator and the remaining clock should be
changed to 25 µs, i.e. set P eriod = 25 µs, for both these components.
Also, we will operate the circuit at 50% duty ratio. Determine the value of the
voltage source needed to achieve this, given the parameters stated above.
11.4.1 Tasks
1. Obtain a copy of your schematic. (buck_mod.ckt)
2. Repeat the tasks of Circuit #1.
3. Complete the following table.
Switching Duty Peak-to-peak Steady State Peak-to-peak
Frequency Ratio Input Voltage Average
to Filter Output Voltage
Output Voltage
Ripple
Circuit
#1
Circuit
#3
4. Explain the dierences seen in the peak-to-peak ripple voltage values be-
tween Circuit #3 and Circuit #1. Are they in line with your expectations?
Why?
© Richard Tymerski and Frank Rytkonen, 2017 221
222 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 12
Lab 2
System Identi cation of a 2nd Order System
through Step Response
12.1 Objectives
To observe the step response of a second order system exempli ed by an LCR
circuit. By taking note of certain features of the response the parameters of its
transfer function will be deduced thus performing a system identi cation.
12.2 Background
In classical control a transfer function is used to mathematically describe the
system to be controlled. The LCR network examined in this lab is an important
component of the system we will be using in subsequent labs for which we will
be designing controllers.
System identi cation is the term used to describe the process by which a
system's transfer function is determined by suitable probing of inputs and ex-
amining the resulting output response. In this lab we will examine the step
response of a second order system to determine the parameters of its transfer
function. We will use a small-signal approach. Small signal refers to the fact
that the response will be examined for a small variation around the DC operat-
ing point which is not necessarily zero. Since the LCR circuit is linear, all small
signal models will be identical. That is, a change of operating point does not
alter the transfer function in this case. Nevertheless we will demonstrate the
small signal approach here.
Note that for an LCR network the transfer function can be easily determined
through fundamental circuit analysis, so the student will use the results obtained
through this procedure to con rm their identi ed model.
The LCR network examined in this lab is shown in Figure 12.1.
223
Figure 12.1: PECS schematic of the LCR network used in this lab. The
values of the components are L = 560 µH , C = 100 µF and R = 25 Ω.
(LCR_step_0.ckt)
The input is V1, the 5 V voltage source, and the output is the voltage which
appears across R1 which in PECS is monitored by the voltage port VP1. (In
PECS the presence of a voltage port dictates to the simulator the requirement
to store the voltage appearing across this port in the output variables to be
subsequently plotted).
To obtain the small-signal response, a 10% step input will be applied (V1
changes from 5V to 5.5V) and the consequential voltage changes around the
steady state value of the output voltage will be examined.
We will consider a second order transfer function, G (s) , expressed as follows:
1
G(s) = K
a2 s2 + a1 s + 1
We see that there are three parameters a1 , a2 and K that need to be de-
termined by the identi cation procedure to fully characterize this system. In
the case of a second order underdamped system, that is, a system that features
complex poles. The transfer function can also be written as
1
G(s) = K 2
s
ωn + 2ζ ωsn + 1
where ωn is the undamped natural frequency and ζ is the damping factor
where ζ < 1.
Consequently the output step response, c (t) , can be found to be [1]
q
1 −ζω n t 2
c (t) = 1 − p 2
e cos ω n 1 − ζ t − φ
1−ζ
where φ = tan−1 √ζ .
1−ζ 2
A typical step response for an underdamped second order system is shown
in Figure 12.2.
224 © Richard Tymerski and Frank Rytkonen, 2017
c(t)
cmax
1.02cf inal
cf inal
0.98cf inal
0.9cf inal
0.1cf inal
t
Tr Tp Ts
Figure 12.2: Second-order underdamped step response
Of particular note in this response is the percentage overshoot, %OS , and
settling time, Ts .
The percentage overshoot is the maximum amount the output waveform
overshoots the steady state, or nal value, expressed as a percentage of the nal
value. Therefore, it is given by:
cmax − cf inal
%OS = × 100
cf inal
The variables cmax and cf inal are shown in Figure 12.2.
On the other hand, the settling time, Ts , is the time taken from the initiation
of the step for the output waveform oscillations to remain within a band of ±2%
of the nal value.
We will determine these two measures from a simulation and use them to
subsequently determine ωn and ζ as seen next.
Using the expression for the output step response, the percentage overshoot
can be found to be given by
− √ ζπ
1−ζ 2
%OS = e × 100
Making ζ the subject of the equation leads to:
© Richard Tymerski and Frank Rytkonen, 2017 225
−ln (%OS/100)
ζ= q
π 2 + ln2 (%OS/100)
To determine the settling time, Ts , we again use the expression for the output
step response c (t) given above to nd [1]
4
Ts =
ζω n
or
4
ωn =
ζTs
Thus from the simulation plot one can determine the variables cmax , cf inal
and Ts and then utilize the above formulas to nd ωn and ζ.
The nal parameter to be determined is K, which represents the DC (i.e.
zero frequency) gain of the transfer function and is given by
∆c cf inal − c0
K= =
∆v vf inal − v0
where cf inal and c0 represent the nal (steady state) output level after the
step has been applied and the (steady state) value of the output before the
application of the step input, respectively. Similarly for vf inal and v0 which now
refers to the input. We will apply a 10% step input ∆v = 0.5 with vf inal = 5.5
and v0 = 5.
12.3 Tasks
12.3.1 PECS simulation
1. Enter the LCR schematic shown in Fig. 1 into PECS. Note the values of
the components: L = 560 µH , C = 100 µF and R = 25 Ω. Leave the
initial conditions for the inductor and capacitor at zero.
2. Setup the input source to achieve a 10% step of the input voltage. As
mentioned above we will change the input voltage from V1 = 5 V to
V 1 = 5.5 V . To set this up in PECS we need to bring up the V1 element
dialog window by double clicking on the V1 symbol. Enter the initial
value of V1=5 V in the Value parameter space. Next click on the Steps
button and then enter t1 = 0.11 and v1 = 5.5. This is the time at which
and value to which the input voltage V1 will change.
3. To set up the simulation parameters for the simulation click on the menu
item Simulation → Parameters . . . This will bring up a dialog window.
Enter the following parameters: Final time = 0.2, Step Size = 1e-6, Start
Time = 0.101 and End time = 0.2.
226 © Richard Tymerski and Frank Rytkonen, 2017
4. Run the simulation. From the resulting plot obtained from the simulation
determine the peak overshoot value and the nal steady state value. We
0 0
will refer to these values as cmax and cf inal .
5. To determine the small signal model we will subtract the initial output
0
voltage level c0 from the two voltage levels found in Task (4) and also
oset the step time to zero. So that in terms of the small signal model we
have:
0 0
cmax = cmax − c0
0 0
cf inal = cf inal − c0
6. Using the values from Task (5) determine the percentage overshoot, %OS ,
and subsequently determine the damping factor, ζ, using the formulas
given above.
7. We will now determine the settling time. From your step response plot
0
determine the time value Ts at which further oscillations remain with
±2 % of the small signal nal value. The small signal settling time Ts is
obtained by osetting the time of the step:
0
T s = T s − step time
8. The nal parameter of our model K can next be determined using the
appropriate formula from above. The model is now fully speci ed.
12.3.2 Matlab simulation results check
We will next check the results obtained above.
9. Derive the transfer function of the LCR circuit. This is perhaps most
easily achieved using the impedance divider rule. Obtain your transfer
function in symbolic form. Identify the transfer function coe cients K, a1
and a2 which are functions of the component values L, C and R. Complete
the following table and include it in your report:
Transfer PECS simulation From transfer From transfer
Function derived values function derivation: function derivation:
Parameters (from Tasks 6,7&8) symbolic form evaluated
ζ
K
ωn
10. We will now use a simulation function available in Matlab (lsim ) to obtain
the step response in an analogous fashion to that obtained using PECS.
Use the following Matlab code to do this. Be sure to understand each line
of code.
© Richard Tymerski and Frank Rytkonen, 2017 227
Before you can run this code, enter K, a1 and a2 as functions of L, C and
R (found in the previous task) on the appropriate lines.
L = 560e-6;
C = 100e-6;
R = 25;
% enter transfer function parameters K, a1 & a2 as functions of L, C and R
K = ?; % transfer function DC gain
a1 = ?; % coefficient of s^1 in denominator polynomial
a2 = ?; % coefficient of s^2 in denominator polynomial
tf_LCR = tf(K, [a2, a1, 1]); % transfer function of the RLC network
% t is a vector of 1000 time values linearly spaced between 0 and 0.2
t = linspace(0, 0.2, 1000);
u = 5*ones(length(t), 1);
step_time = 0.11; % step the input at step_time
n = find(t >= step_time);
u(n) = u(n) + 0.5; % input containing the 10% step at step_time
y = lsim(tf_LCR,u,t); % simulate the LCR network with the desired input
figure(1)
plot(t,y)
title('Output response including the large-signal start-up transient')
% isolate the small-signal step response
c_prime_0 = y(n(1)-1); % initial output before the step
ys = y(n) - c_prime_0; % small signal output response
ts = t(n) - step_time; % small signal response times
figure(2)
plot(ts, ys)
title('Step response')
stepinfo(ys,ts) % obtain the step response metrics
11. Compare the plots obtained from the Matlab code to that obtained using
PECS.
228 © Richard Tymerski and Frank Rytkonen, 2017
12. Compare the values of percentage overshoot and settling time determined
by the Matlab function stepinfo in the above Matlab code to the values
you determined form the PECS simulation. Complete the following table:
From From
Response
PECS Matlab function
Feature
Simulation stepinfo
% overshoot
%OS
Settling
Time, Ts
13. In the subsequent labs we will use the LCR network as a low pass lter
but we will include the losses of the inductor which are modelled as an
equivalent series resistance (ESR ). In this task we'll qualitatively assess
the eect of this ESR on the transfer function.
Rederive the transfer function of the network where the inductor L is now
replaced with a series combination of the inductor L and a resistor rL .
Note: in deriving the new transfer function a short cut can be taken by
using the previously obtained transfer function and replacing any term of
sL with sL + rL .
To more easily determine the qualitative eect of loss inclusion in the
transfer function, the newly obtained transfer function is simpli ed with
the approximation:
R + rL ≈ R
which is true when rL R.
With the above approximation the qualitative change in the response can
be determined by inspection. State your observation on this matter. Hint:
Does it (substantially) change any of the following of the transfer func-
tion:
(a) DC gain?
(b) Undamped natural frequency?
(c) Damping factor?
Reference:
th
[1] Norman S. Nise, Control Systems Engineering, 7 edition. Pages 173
176.
© Richard Tymerski and Frank Rytkonen, 2017 229
230 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 13
Lab 3
System Identi cation of the dc-to-dc Buck
converter
13.1 Objectives
The circuit simulator PECS will used to examine and characterize the steady
state operating conditions of the dc-to-dc buck converter and will aid in the
con rmation of the system transfer functions. The open loop response to step
changes in the input voltage as well as step load changes are also examined us-
ing both PECS and Matlab. Matlab will also be used in examining the system
transfer functions. Through these simulations the student will gain a better
understanding of the operation of the buck converter circuit. The transfer func-
tions veri ed here will be used later to design eective closed loop feedback
control.
13.2 Background
The LCR network examined in the previous lab is used together with a single
pole, double throw switch to derive a power processing circuit known as the
dc-to-dc Buck converter. This circuit takes a dc voltage source at the input and
transforms it to a lower value dc level at the output, whilst achieving a high
power e ciency, typically in the 90% range. This is possible through the use of
a high frequency switch.
The schematic of the buck converter is shown below in Figure 13.1. The con-
verter schematic has been divided into 3 sections: 1) the input voltage source,
Vg , 2) the single-pole double-throw switch, and 3) the LCR network which com-
231
prises the low-pass lter. To more accurately model the losses in the inductor a
series resistor, rL , is included. The output load to which the power is delivered
in represented by resistance R.
The switch is operated in cyclical manner with period, Ts . At the start of
each period the switch is in its upper position which connects the input source
to the output lter. The switch stays in this position for length of time, DT s ,
where D is known as the duty ratio which takes a value 0 < D < 1. At the
end of the DT s subinterval the switch changes position to disconnect the input
source.
Figure 13.1: Dc-to-dc Buck converter.
0
The length of time remaining until the end of cycle is D0 T s where D ≡ 1−D.
So we see that through the switching action the voltage vs appearing at the
input of the low pass lter is a rectangular wave. The output of the lter is
predominately a constant dc level, which corresponds to the average of the input
waveform, together with a small ripple which represents the un ltered residuals
of the input waveform. Neglecting losses (which generally will be very small by
design) the dc output voltage is given by V = DVg . Given the range of D we
see that the output can be adjusted from 0 to Vg . Control of the output voltage
is achieved by variation of the duty ratio. To denote a time varying quantity a
lower case symbol will be used and thus a varying duty ratio is denoted by d.
Also, to further highlight a signal that represents a deviation around a steady
state average, we will use a caret `^', so that dˆ is the small signal deviation
around the average duty ratio D. Therefore, the time varying duty ratio d (t )
is comprised of an average (DC) value together with a deviation dˆ around this
average so that d = D + dˆ or alternatively, dˆ = d − D.
To achieve a varying duty ratio given a control voltage, vc , a pulse width
232 © Richard Tymerski and Frank Rytkonen, 2017
modulator (PWM) circuit is used, see Figure 13.2. This is comprised of an op-
amp comparator to which one of the inputs is connected to a sawtooth waveform,
vsaw , which has a peak-to-peak amplitude of VM and period Ts . As shown in
Figure (2b) a comparison of the control voltage, vc , results in a rectangular
output waveform of period, Ts , and duty ratio, d. Combining the PWM with
the buck converter results in an open loop controlled buck converter shown in
Figure 13.3. Through the use of the PECS simulator we will examine the steady
state operation of this system.
(a)
(b)
Figure 13.2: (a) PWM comparator, (b) comparison of the control signal, vc ,
with the sawtooth waveform vsaw , results in a variable pulse width rectangular
waveform used to drive the switch in the buck converter.
© Richard Tymerski and Frank Rytkonen, 2017 233
Figure 13.3: Open loop controlled buck converter. The duty ratio d of the
converter is set by the control voltage, vc , via the PWM comparator.
13.3 System Transfer Functions
In a later lab we will design a closed loop controller for this system. To be
able to do this using a classical control design methodology we will rst need
to determine important transfer functions of the system. We will consider three
transfer functions. The rst is the control-to-output voltage transfer function.
This transfer function has two components: the duty ratio to output voltage
transfer function of the buck converter power stage, Gvd , and the pulse width
modulator transfer function, GP W M .
Control-to-output transfer function:
v̂ v̂ dˆ
= Gvd · GP W M = ·
v̂c dˆ v̂c
where the caret (^) has been used to denote a small signal signal quantity.
Note that since the modulator is nonlinear, a so-called describing function anal-
ysis method is used to determine the transfer function which ends up being a
(frequency independent) constant gain given by:
dˆ 1
GP W M = =
v̂c VM
The control-to-output transfer function plays a very important role in con-
trol design as it forms part of the loop gain which is important to stability and
achieving good stability margins (both phase and gain).
234 © Richard Tymerski and Frank Rytkonen, 2017
The other two transfer functions of the buck converter we will consider are 1)
the input voltage to output voltage transfer function and, 2) output load current
to output voltage transfer function:
v̂
1. input voltage to output voltage transfer function: Gvg = v̂g
v̂
2. output load current to output voltage transfer function:
îo
= −Zout
These transfer functions quantify how variations in the input quantity at
various frequencies propagate to the output. That is, how much of an aect
does input voltage variations or load current variations have on the output volt-
age. Ideally, in a voltage regulator system as we are considering here, we would
like this to be zero. In this lab we will examine the Bode magnitude response to
see what level of transmission is achieved in open loop operation. With a prop-
erly designed control system incorporating feedback, these input disturbance
propagations through the system will be greatly diminished.
A block diagram model of the buck converter transfer functions which will
be used in a later lab for controller design is shown in Figure 13.4. In this lab
we'll do a partial veri cation of these transfer functions comparing them with
previously derived results.
Figure 13.4: Block diagram model of the Buck converter along with the pulse
width modulator.
For transfer functions Gvg and Gvd considering the signal ow from the input
through to the output of the converter, one can readily assume a form as follows
v̂s v̂
Gvg (s) = · = Kvg ·GLP F (s)
v̂g v̂s
© Richard Tymerski and Frank Rytkonen, 2017 235
and
v̂s v̂
Gvd (s) = · = Kvd ·GLP F (s)
dˆ v̂s
where v̂s represents the small signal voltage variations at the input of the
output lter and where Kvg and Kvd are constant gains and GLP F (s) represents
the transfer function of the second order low pass LCR lter which, as seen in
the previous lab, is given by
1
GLP F (s) = 2
s
ωn + 2ξ ωsn + 1
Note that the damping ratio, ξ, now includes the eect of inductor losses, as
considered at the end of Lab. 2, by including rL , the inductor ESR (equivalent
series resistance). Constants Kvg and Kvd represent the eect of the switching
elements in propagating variations of the input voltage level (for Gvg ) or vari-
ations of the duty ratio (for Gvd ) to the input of the low pass lter. Kvg and
Kvd represent the DC gain of the relevant transfer functions and will be found
through simulation below.
Output load current to output voltage transfer function: v̂
îo
=
−Zout :
The nal transfer function that we'll consider is related to the output impedance
of the buck converter. Despite the presence of switching which aected the two
other transfer functions considered (i.e. Gvd and Gvg ), the output impedance
is more straightforwardly determined as switching has no eect. The circuit
con guration of the buck converter during the rst (DT s ) subinterval is seen
in Figure 13.5a, and during the remainder of the period (the D0 T s interval) is
seen in the Figure 13.5b. As independent sources are nulled for determination
of impedances we can see that the output impedance, Zout , are the same during
the two subintervals and can be simply seen as a parallel connection of three
impedances such that:
1
Zout = (sL + rL ) k k R
sC
You will be asked to evaluate this in a latter task.
(a) (b)
Figure 13.5: Buck converter con guration during (a) the rst subinterval, DT s ,
and (b) the second subinterval, D0 T s .
236 © Richard Tymerski and Frank Rytkonen, 2017
The actual transfer function of interest for us is that related to how output
current variations, îo , lead to output voltage variations, v̂ . With reference to
Figure 13.6 we see that the output current io is given by
io = Io + îo
where the capitalized symbol refers to the DC steady state value and the
term with a caret (^) indicates a small-signal variation. A similar expression
can be written for the output voltage: v = V + v̂
Figure 13.6: The eect of output current variations,îo , causing output voltage
variations, v̂ , is quanti ed by transfer function −Zout .
Consequently the small signal transfer function for the output impedance
Zout is given by
v̂
Zout =
−îo
v̂
and consequently the transfer function of interest which we would like to
îo
determine is given by
v̂
(s) = −Zout
îo
Note however that in the simulation (and later in the lab with the hardware
implementation), in order to achieve output current variations we will be step-
ping the load, that is, changing the load resistance between two dierent values.
This however causes the system transfer functions to be modi ed somewhat.
However, as seen in Lab. 2 the major change that occurs is that of varying
the damping factor of the circuit. Nevertheless considering the convenience of
performing a step load change in the lab, the approximation considered here
will be accepted.
© Richard Tymerski and Frank Rytkonen, 2017 237
13.4 Tasks
1. Start-up transient: In this rst task we will examine the start-up tran-
sient and steady state operation of the buck converter. Build in PECS
the buck converter circuit shown in Figure 13.7 below. Use simulation
parameters: nal time = 0.06, step size = 1e-6, start time = 0 and end
time = 0.06. Run the simulation and obtain the output voltage plot. Note
that the large start-up transient is not of much interest to us here as it is a
large signal phenomenon and may be easily avoided with a slight redesign.
However, note the steady state value of the output voltage.
Figure 13.7: PECS schematic of the Buck converter with pulse width modulator.
(Lab3_1.ckt)
2. Steady-state characteristics: We will now rerun the simulation ex-
cept we will only display the last few cycles of the response. This can be
achieved by setting the start time = 5.9881e-2 in the simulation param-
eters dialog window and rerunning the simulation. Obtain a plot of the
output voltage, the diode voltage and switch current, in three separate
plots one above the other so that relative timing relationships can be ob-
served. You can do this by rst producing a plot of the output voltage
238 © Richard Tymerski and Frank Rytkonen, 2017
(VP1), then using PECSPLOT to add a plot containing the diode voltage
(VP2), this will be added under the current plot, followed subsequently
by adding the switch current (IP1) plot. (Lab3_1a.ckt)
Determine the following from the plots:
(a) The average output voltage (a visual estimate is su cient)
(b) The peak-to-peak output voltage (this is the output voltage `ripple')
(c) The peak-to-peak diode voltage
(d) The peak inductor current,
(e) The frequency of the waveforms
(f ) The duty ratio
Explain how the duty ratio is set in the circuit, given the current param-
eters of the sawtooth waveform.
3. Kvg and Step input voltage change: We will now determine constant
Kvg using a step change of the input voltage and monitoring the resulting
output voltage change, as was previously done in Lab 2. Recall from Lab
2 that
∆c cf inal − c0
Kvg = =
∆v vf inal − v0
where cf inal and c0 represent the nal (steady state) output level after the
step has been applied and the value of the output before the application of
the step input, respectively. Similarly for vf inal and v0 which now refers
to the input. We will apply a unit step input ∆v = 1 with vf inal = 11 and
v0 = 10.
To set this up in PECS we will introduce two step changes in the input
source. Bring up the input source (V1) parameter dialog window click on
the Steps . . . button and set t1 = 0.025 with v1 = 11 and t2 = 0.04 with
v2 = 10. We'll also change the simulation parameter Start Time = 2.001e-
002. Obtain the simulation plot and subsequently determine K vg using
the above equation. Also determine the maximum peak-to-peak output
voltage deviation ∆v and steady state error, SSE. The SSE is simply the
absolute dierence between the steady state values before and after the
input change, so this is represented by |cf inal − c0 |. For an example of how
these are determined see the note below. The SSE is somewhat misnamed
in the open loop context we have here but this metric will be used later
in comparison with closed loop contexts where the steady state output
voltage is desired to remain unchanged in the presence of a disturbance
input. (Lab3_1b.ckt)
© Richard Tymerski and Frank Rytkonen, 2017 239
4. Kvd : To determine constant Kvd we'll use a dierent input to that of
task (3). A sinusoidal input at a low frequency, much lower than the low
pass lter corner frequency, will drive the input of the modulator and the
resulting sinusoidal output voltage of the converter will be monitored. To
be clear about this, determine the lter corner frequency expressed inHz.
The sinusoidal source is attached as shown in Figure 13.8. We will use si-
nusoidal source parameters: Peak Amplitude = 0.2, Frequency = 100 and
Phase (degs) = 0. Use the same simulation parameters as in the previous
task. However, be sure to void the step changes that were introduced in
the previous task.
Run the simulation and obtain a plot of the driving sinusoid (VP3). Con-
rm that the amplitude and frequency are as desired. Now use the add
plot feature in PECSPLOT to add the plot of the output voltage (VP1)
below the current plot. Obtain peak-to-peak measurements of the two
waveforms and determine the voltage gain. Take note of the phase rela-
tionship between the two waveforms. Are they in-phase or out-of-phase?
Considering the in uence of the PWM gain, determine Kvd . Hint: From
previous discussions (and also from Figure 13.4) we see that the gain found
is given by
v̂
(s) = GP W M · Gvd = GP W M · Kvd GLP F (s)
v̂c
1
With GP W M = VM (with VM known) and for the frequency used at
well below the low pass lter corner frequency such that GLP F ≈ 1, the
parameter Kvd may be easily determined.
240 © Richard Tymerski and Frank Rytkonen, 2017
Figure 13.8: Buck converter with pulse width modulator driven by a sinusoidal
voltage source. The added sinusoidal source has parameters: Peak Amplitude
= 0.2 volts, Frequency = 100 Hz. and Phase (degs) = 0. (Lab3_2.ckt)
5. Step load change: We next examine the output voltage change to a step
in load. This test can be easily performed for an actual circuit and so will
be undertaken subsequently on the hardware in the lab and will form the
basis for examining how well the application of feedback improves on the
open loop performance.
Alter the buck converter circuit by adding a switch which is controlled by
two clock elements as shown in Figure 13.9. Be sure to set the initial switch
state of the added switch to be in the OFF state, otherwise the simulation
will be incorrect. Also make sure no other step changes are initiated in
your circuit. Run the simulation using the simulation parameters used
before and obtain a plot of the output voltage (VP1). From this plot
determine the maximum peak-to-peak output voltage deviation, ∆v , and
steady state error, SSE.
© Richard Tymerski and Frank Rytkonen, 2017 241
Figure 13.9: Buck converter with step load changes (Lab3_3.ckt)
6. Matlab
In the following tasks we will analyze the open-loop system using Matlab.
We'll examine both disturbance input transfer functions and also use Mat-
lab to perform time-domain simulations based on these transfer functions.
In the model for the PWM modulator use a peak-to-peak ramp amplitude
value of VM = 5.
Transfer functions
(a) Loop gain: Under the condition that there is no compensator, i.e.
Gc = 1 and the desired output voltage and reference voltages are,
V
V = 5 and Vref = 2.5, respectively so that H(s) = ref
V = 2.5
5 = 0.5,
determine the loop gain transfer function and use the Matlab margin
command to obtain the Bode plot of this (uncompensated) loop gain.
Have the plot display frequency in Hz. The command will also obtain
the unity gain and −180◦ phase crossover frequencies and the phase
and gain margins of the system. Make note of these in your report.
Matlab code to do this:
s = tf('s');
G_loop = ?; % input your loop gain expression as a function
of s
figure(1)
margin(G_loop)
h = gcr;
242 © Richard Tymerski and Frank Rytkonen, 2017
h.AxesGrid.Xunits = 'Hz'; % display the frequency in Hz
h.AxesGrid.TitleStyle.FontSize=12; % increase font size
h.AxesGrid.XLabelStyle.FontSize=12; % for readability
h.AxesGrid.YLabelStyle.FontSize=12;
(b) Input voltage to output voltage: Using the model for the (open-
loop) input source voltage to output voltage transfer function, Gvg ,
use the Matlab bodemag command to obtain the magnitude frequency
response of this transfer function (with frequency in Hz).
(c) Output current to output voltage: Using the model for the
(open-loop) output current to output voltage transfer function, −Zout ,
use the Matlab bodemag command to obtain the magnitude frequency
response of this transfer function (with frequency in Hz).
Be sure to include your Matlab code for (b) and (c) in your report.
These magnitude responses show the gain at various frequencies of in-
put disturbance in propagating to the output. With the subsequent
incorporation of feedback these responses will be greatly reduced.
Ideally we would like the response to be zero across all frequencies.
Needless to say that this cannot be achieved perfectly in practice.
Open-loop simulations:
Note that the following simulations obtained using Matlab are based
on the small-signal model only. Thus DC conditions and large sig-
nal eects are not modelled and consequently do not show up in the
simulations. In order to more easily compare the Matlab simulations
with those obtained from PECS we will simply add the average con-
verter output voltage to the response obtained from Matlab.
(d) Input voltage step response: Use the transfer function obtained
above for Gvg to obtain the response to 10% step input voltage
change. Since the nominal input voltage level is 10 V, we there-
fore will use a unit step input. Use the Matlab lsim command to
perform this simulation. Determine the maximum peak-to-peak out-
put voltage deviation, ∆v , and steady state error, SSE. Matlab code
to do this:
Vg = 10;
D = 0.5;
V = D*Vg;
s = tf('s');
Gvg = ? ; % input your expression for Gvg as a function of s
t = linspace(0.02, 0.06, 1000);
© Richard Tymerski and Frank Rytkonen, 2017 243
u = zeros(size(t));
ind = find(t>=0.025 & t<=0.04);% step is between 0.025<t<0.04
Vg_diff = 1;
u(ind) = u(ind) + Vg_diff;% form input vector containing the step
figure(2)
y = lsim(Gvg, u, t); % simulate the step response
plot(t,y+V) % add steady state voltage to the output and plot it
del_v = max(y) - min(y) % peak-to-peak voltage deviation
SSE = y(ind(end)) % steady state error
(e) Output current step response: Based on discussion in a prior
section of this lab, determine the converter output impedance, Zout .
We will use the transfer function −Z out to obtain the response for a
step load change. In order for this to mimic the practical circuit as
closely as possible you will rst determine the value of the current
step involved. Taking note of the load switching circuit shown in
Fig. 3, we see that the load switches between 25 ohm and 5 ohms.
V
This results in the output current switching between Io_1 = 25 and
V
Io_2 = 5 , where we have assumed that the output voltage does not
change appreciably. Thus the current step is Io_dif f = Io_2 − Io_1 .
Use the Matlab lsim command to perform a step response simula-
tion to this load step. Determine the maximum peak-to-peak output
voltage deviation, ∆v , and steady state error, SSE. Matlab code to
do this:
s = tf('s');
Zout = ? ; % input your expression for Zout as a function of s
Vg = 10;
D = 0.5;
V = D*Vg;
Io_1 = V/25; % load current before step. (25 ohm load)
Io_2 = V/5; % load current after step. (5 ohm load)
Io_diff = Io_2 - Io_1; % current step
t = linspace(0.02, 0.06, 1000);
u = zeros(size(t));
ind = find(t>=0.025 & t<=0.04);% step is between 0.025<t<0.04
u(ind) = u(ind) + Io_diff;
figure(3)
244 © Richard Tymerski and Frank Rytkonen, 2017
y = lsim(-Zout, u, t);
plot(t,y+V)
del_v = max(y) - min(y)
SSE = y(ind(end))
13.5 Note
Computing maximum peak-to-peak output voltage deviation, ∆v , and
steady state error, SSE :
With reference to Figure 13.10 we see that the output voltage before the
input step is at 5 V (see value at time = 0.2646). The input step occurs at time
0.30 causing the output to oscillate between max and min values of 5.996 and
3.199 before settling to new steady state output value of 4.816. Subsequently
the input step reverts to its initial value at time 0.34 resulting in oscillations
occurring between max and min values of 6.617 and 3.82. The quantity ∆v is
determined as the dierence between the maximum and minimum deviations in
the step response, so that ∆v = 6.617 − 3.199 = 3.418 V. The SSE (steady state
error) is determined as the dierence in the two steady state values, so that SSE
= 5.0 − 4.816 = 0.1840 V.
Figure 13.10: The plot shows the output voltage response to an input step
change. This response is used to determine the maximum peak-to-peak output
voltage deviation, ∆v , and steady state error, SSE.
© Richard Tymerski and Frank Rytkonen, 2017 245
13.6 Results
Be sure to include a summary of your results by completing the following tables
and including them in your report.
Transfer function DC gains:
From PECS: From model: From model:
Tasks (3) and (4) Symbolic Model Symbolic formula evaluated
Kvg
Kvd
Uncompensated stability margins and associated frequencies, from Task 6a:
Phase Crossover Gain Crossover
Gain Margin Phase Margin
Frequency Frequency
Step response characteristics:
PECS Matlab
Tasks (3) and (5) Tasks (6d) and (6e)
vg step: ∆v
vg step: SSE
iout step: ∆v
iout step: SSE
Provide answers to the following questions regarding the step response re-
sults:
1. Comparison of the results for ∆v for iout step changes obtained from
PECS and Matlab dier more than one might expect. Provide a reason
why. (Hint: look closely to how this is modelled).
2. From basic circuit considerations provide a simple symbolic expression for
the SSE quantity found for a step in input voltage, vg .
13.7 Postscript
In this lab we have developed a linear model for the buck converter system which
resulted in deriving three transfer functions: 1) Gvd , 2) Gvg and 3) −Zout . These
transfer functions quantify how the duty ratio control input, dˆ, and other (dis-
turbance) inputs, v̂g and îo , cause output voltage variations, v̂ . The pulse width
modulator `describing function' is much more involved to determine despite the
simplicity of the nal result being a constant, which was given here without
246 © Richard Tymerski and Frank Rytkonen, 2017
further discussion. Together with transfer function, Gvd , the control voltage,
v̂c , to output, v̂ , transfer function can be determined.
Through simulations, both at a circuit level (using PECS) and at a transfer
function level (using Matlab), the model has been con rmed.
In subsequent labs a hardware implementation of these circuits will be ex-
amined with the nal goal of designing an eective compensator for closed loop
feedback control.
© Richard Tymerski and Frank Rytkonen, 2017 247
248 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 14
Lab 4
Open loop system construction and test-
ing: the Buck dc-to-dc converter
14.1 Objectives
To build and examine the operation of an open loop dc-to-dc buck converter.
This system converts a dc voltage level to a lower dc voltage level at high power
e ciency. We will examine the performance of this circuit to step load changes.
This will establish a baseline level of performance by which the closed loop
designs of later labs will be judged.
14.2 Background
The open loop dc-to-dc buck converter circuit to be constructed is shown in
Figure 14.1 where the individual function blocks are identi ed. There are several
function blocks that are discussed below:
1. Buck converter power stage: This contains the LC lter and load re-
sistance as well as the switches. The single-pole, double-throw switch of
the buck converter is implemented using a mosfet and diode combination.
To minimize losses and damping in the buck converter, the components
used there should all be high quality. This translates for each component
to mean the following:
(a) Buck converter mosfet: high power mosfet with low RDS(on) value.
(b) Diode: this needs to be fast reverse recovery power diode. The diode
that has been speci ed is a Schottky diode which features a very
249
Figure 14.1: Schematic of the open-loop dc-to-dc buck converter.
250 © Richard Tymerski and Frank Rytkonen, 2017
fast recovery time as well as a lower voltage conduction drop than a
silicon diode.
(c) Inductor: this needs to be a power inductor which can handle an
appreciable DC current ow. It should also have a low equivalent
series resistance (ESR).
(d) Capacitor: this should be a high quality capacitor with a low ESR.
Note also that the load resistances need to handle the power that they
will dissipate, so the speci ed power rating needs to be observed.
Further discussion concerning components appears at the end of this lab.
Bearing the above in mind, arbitrary substitution of components is to be
avoided.
2. Load switching mosfet: The load will be switched between two dierent
values in order to examine the stepped-load performance of the converter.
Switching of the load is done by turning ON and OFF a mosfet which
is in parallel with a portion of the load. This mosfet is controlled by an
external square wave generator.
3. Mosfet driver: this is required in order to drive the mosfet with sharp
step transitions at a high frequency. It interfaces between the comparator
and the buck converter power mosfet.
4. DC + superimposed AC block: this is simply a variable resistive volt-
age divider which provides an adjustable DC voltage level. This is fed to
the comparator (discussed next).
The adjustable DC allows for the duty ratio, which controls the buck
converter, to be set. An external AC signal may be fed into the circuit
which superimposes the AC on top of the DC level. The resulting AC
modulated duty ratio will be see in the buck converter output voltage.
5. Comparator: The comparator and the sawtooth generator (discussed
next) together form the pulse width modulator (PWM). As discussed
above, in the present circuit a DC voltage is applied to the inverting
input of the comparator and a sawtooth waveform is applied to the non-
inverting input. As the sawtooth transitions past the DC voltage level, the
comparator will change state producing a rectangular output waveform.
The duty ratio of this waveform can be changed by adjusting the DC level
using the potentiometer voltage divider.
6. Sawtooth generator: A constant current source (comprising transistor
Q5, zener diode D2 and resistors R5, R6 and VR2 in Figure 14.1 is used to
charge a capacitor (C4 in Figure 14.1) resulting in a voltage ramp appear-
ing across the capacitor. At a predetermined voltage across the capacitor
© Richard Tymerski and Frank Rytkonen, 2017 251
the LM555 circuit discharges it. This process is ongoing producing a saw-
tooth waveform. The level of the constant current can be adjusted (by
varying VR2 in Figure 14.1) which adjusts the rate at which the threshold
discharge voltage is reached thus varying the frequency of the resulting
sawtooth.
14.3 Tasks
We will construct the circuit in a step-by-step fashion and test each function
block as it is constructed. Note that we will be using two dierent power supply
sources. A 10 V high current source is needed for the buck converter and a 15
V low current source will power the rest of the circuit. A number of tasks below
ask that you take a screenshot (or a photo) of the waveform(s) appearing on the
oscilloscope. If this is not possible you'll need to neatly sketch the waveform
providing voltage level and time period annotations.
1. Construct the sawtooth generator:
(a) After you assemble the circuit, use an oscilloscope to monitor the
sawtooth voltage waveform across the charging capacitor, C4. Adjust
the potentiometer (VR2) to obtain a frequency of 40 kHz.
(b) Take a screenshot of the sawtooth waveform. What are the mini-
mum and maximum voltage levels of the sawtooth? The peak-to-
peak voltage dierence represents VM in our modelling of the PWM
modulator.
2. Construct the comparator and DC + superimposed AC circuits:
(a) Assemble the circuit. At this time we will open jumper J1 and
close jumper J2. Also the just-constructed sawtooth generator signal
should be connected to the non-inverting input of the comparator.
(b) Based on the sawtooth waveform you've just observed, what range of
duty ratios are you able to achieve by varying the Duty Ratio Adjust-
ment potentiometer (VR1) from one extreme to the other? Show how
you can calculate this. Con rm your results in the lab. Note that
the duty ratio is de ned by the length of the high time of the pulse
that appears at the input of the output lter as a ratio of the period.
Due to use of a p-channel mosfet in the buck converter power stage a
low comparator output corresponds to the mosfet turning ON, which
produces the high portion of the pulse, the time interval of which
determines the duty ratio, as was just mentioned. Therefore, use
this time interval of the low voltage level at the comparator output
divided by the square wave period as the duty ratio value.
(c) Use an oscilloscope to monitor the output of the LM311 (pin 7). Vary
the duty-ratio adjustment potentiometer (VR1) to set a 50% duty
252 © Richard Tymerski and Frank Rytkonen, 2017
ratio. Check that you have 15 V peak-to-peak square wave. (If so
your comparator circuit is functioning properly). Take a screenshot
of this waveform.
3. Construct the mosfet driver:
(a) Connect the two transistors and resistor of the mosfet driver to the
10 V power supply. We will connect the just-constructed comparator
circuit by closing jumper J1 and opening jumper J2.
(b) Use an oscilloscope to monitor the voltage at the common emitter
connection of the two transistors. Check that you are seeing a 10 V
peak-to-peak square wave. (If so, your driver circuit is functioning
properly). Take a screenshot of this waveform.
4. Construct the Buck converter:
(a) Assemble the Buck converter. (Do not add the load switching mos-
fet at this time). At this point the whole circuit should be fully
functional (without load switching).
(b) Use an oscilloscope to observe the waveform across the switching
diode. Check that you are seeing a 10 V peak-to-peak square wave.
Also, you should see sharp rising and falling transitions. (If so, your
power mosfet is likely switching properly). Take a screenshot of this
voltage waveform.
(c) To further verify proper functioning of your power stage, use the
oscilloscope to monitor the voltage across the output load, the series
combination of the 5 Ω and 20 Ω resistors. Determine its DC value. Is
this in accordance with the duty ratio value that you had previously
set up?
(d) For even further veri cation of the proper operation of the circuit we
will inject a small sinusoidal waveform that will modulate the duty
ratio, the eect of which will be seen in output voltage. Recall that
this was done previously via PECS simulation in Lab 3. You'll be
now able to con rm the results obtained there.
To proceed, connect a small-amplitude, low-frequency sinusoidal volt-
age (100 Hz or lower) to the Vi terminal which feeds into the DC +
superimposed AC block. This will superimpose an AC variation on
top of the DC voltage appearing at the inverting terminal of the com-
parator. The frequency is chosen to be much below the LC resonant
1
frequency of the output lter, fo = √
2π LC
= 673Hz . The ampli-
tude should be chosen to be large enough to facilitate measurement
of the resulting signal across the output, and no larger so as to not
violate the small-signal assumption. Display the input and output
signals (as de ned next) on the oscilloscope and take a screenshot.
© Richard Tymerski and Frank Rytkonen, 2017 253
Using the oscilloscope measure the peak-to-peak amplitude of the si-
nusoidal variation appearing across the converter load. This is the
output signal. Now with the oscilloscope, measure the peak-to-peak
amplitude of the sinusoid at the inverting input of the comparator
(pin 3 of the LM311). This is the input signal. Determine the ratio of
the amplitudes of the sinusoids: output amplitude/input amplitude.
Can you say what this number represents with respect to the control
to output transfer function and what its components are?
Also take note of the phase dierence between the output and the
input. Is the output in-phase or out-of-phase with the input at the
chosen frequency? In this task we simply want to verify whether the
signal is being inverted in this signal path. In the next lab we will be
closing the loop with negative feedback via a compensator so we will
need to determine whether the compensator will need to provide the
◦
180 phase inversion. What is your assessment of this?
5. Switched load performance:
At the present point you should have a fully functional dc-to-dc converter
which is converting the 10 V DC input to a 5 V DC output across the
series resistor combination of 5Ω and 20 Ω (for a total of 25 Ω) load.
(a) We will now attach the load switching mosfet circuit and further
connect it to a square wave generator which provides a 5 V amplitude
signal at a low frequency. The square wave lower voltage level should
be 0 V and the higher voltage level should be 5 V. The frequency
should be adjusted so as to see the full settled output response of the
converter. (A square wave frequency in the range of 50 Hz to 100 Hz
should be ne). The mosfet will be turning ON and OFF shorting
out the 20 Ω resistor in the load. Thus the output current will be
5 V 5 V
pulsing between
25 Ω = 0.2 A and 5 Ω = 1 A (ignoring output
voltage changes).
(b) The varying load current will cause the output voltage to vary. Take
a screenshot of the output voltage response. Determine the maximum
peak-to-peak output voltage deviation, ∆v , and the steady state er-
ror, SSE. If necessary, please see the note in Lab. 3 concerning how
to determine these quantities.
14.4 Results
(a) Complete the following tables to summarize your waveform observa-
tions in the previous tasks.
Tabulate your results from Task 1b:
254 © Richard Tymerski and Frank Rytkonen, 2017
Minimum Maximum VM
Value Value = pk-pk voltage
Sawtooth
(Task 1b)
Tabulate your results from Task 2b:
Task 2b Duty Ratio (D)
Min. D: formula to
determine min. D
Min. D: formula
evaluated
Min. D: measured
in lab
Max. D: formula to
determine max. D
Max. D: formula
evaluated
Max. D: measured
in lab
Tabulate your results from Task 4d:
Input Sine Voltage
pk-to-pk =
(Task 4d)
Output Sine Voltage
pk-to-pk =
(Task 4d)
Output/Input Ratio
(Task 4d)
(b) To see how well our prior simulations conform to practice complete
the following table:
From Hardware Using PECS Using Matlab
from from from
Lab 4 (this lab), Task 5b Lab 3, Task 5 Lab 3, Task 6e
∆v
SSE
(c) Write your observations concerning the io step response results and
provide explanations for any discrepancies you see.
© Richard Tymerski and Frank Rytkonen, 2017 255
14.5 Notes - Buck converter components:
As mentioned earlier, in order to produce a high level of performance, and also
to be able to use a system model that is not overly complicated by the need
to include many parasitic elements, the components of the buck converter need
to be of high quality. We'll take a look at the speci c components used in our
circuit and take note of some important characteristics seen in their datasheets.
Capacitor: The 100 µF lter capacitor is manufactured by Kemet and has
part number A758EK107M1AAAE016. It is polymer aluminum and features
a very low ESR (equivalent series resistance) of just 16 mΩ. Generally, the
ESR together with the capacitor forms a zero in the transfer functions; how-
ever, given these characteristics for the capacitor the zero is positioned at a
1
frequency of approximately
2πRESR C ≈ 100 kHz . This is well beyond the
loop bandwidth of our system and consequently may be neglected, as we have
done in these labs. The low ESR also minimizes the voltage ripple appearing in
the output.
Inductor: The 560 µH inductor is manufactured by Bourns Inc. and has part
number 2200HT-561-V-RC. It has a maximum DC resistance of 230 mΩ. We
have used this value in our modeling. This is the only parasitic element that
is included in our system model. This was done as it has appreciable eect on
load regulation, i.e. output voltage variation due to load changes.
Diode: The diode used is manufactured by Sanken and has part number RA
13V1. It is a Schottky diode with a fast switching recovery time of less than
500 ns, and has a forward conduction drop of just 360 mV @ 2 A. This compares
very favorably compared to the 0.6 V to 0.7 V conduction drop of the average
silicon diode. Thus further minimizing parasitic eects.
Mosfet: The IRF9530 mosfet is available from a number of dierent manufac-
tures. It has a maximum RDS(on) of 0.30 Ω. Its n-channel complement, the
IRF530 mosfet, used to switch the load, has a maximum RDS(on) of 0.16 Ω.
Load resistors: The values and power ratings of the load resistances are
5 Ω, 5 W and 20 Ω, 2 W .
256 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 15
Lab 5
Closed-Loop Feedback System - Analysis:
Analysis and performance of a closed loop
dc-to-dc Buck converter system
15.1 Objectives
To build and examine the performance of a closed-loop dc-to-dc buck voltage
regulator. A simple compensator is provided. (In the next lab this will be
replaced by a better performing, albeit more complicated, compensator designed
by the student). First an analysis of the system using the closed loop transfer
functions is examined. Subsequently a simulation of the closed loop system is
performed both at the transfer function level, using Matlab, and at the circuit
level, using PECS. Having rst gained an appreciation of the operation of the
circuit and the performance of the system through simulation, next a hardware
implementation is built and performance is examined in the laboratory and
results are compared with those previously obtained by simulation.
15.2 Background
The dc-to-dc converter together with the PWM modulator, introduced in Lab.
3, is now operated in closed loop as depicted in Figure 15.1. As seen in this
gure, the output voltage (the controlled variable) is scaled (via the resistive
divider comprising Ra and Rb ), fed back and compared with a reference voltage
producing an error signal. This signal is next processed through the feedback
compensator (also known as a frequency compensator) which produces the con-
trol signal to the converter via the PWM modulator.
The output voltage of the system, v , is a function of its three inputs: 1) duty
ratio, d, 2) input source voltage, vg , and, 3) load current, io . So that
257
Figure 15.1: Closed loop dc-to-dc buck converter voltage regulator
Figure 15.2: Closed loop dc-to-dc buck converter voltage regulator block dia-
gram
258 © Richard Tymerski and Frank Rytkonen, 2017
v = f (d, vg , io )
As this function is nonlinear, a linearized model is developed through a Taylor
series expansion around a steady state operating point given by V = f (D, Vg , Io ),
where capitalized variables refer to steady state values. This results in the
following small signal model:
v̂ = Gvd (s) dˆ + Gvg (s) v̂g − Zout (s) îo
where the caret `^' indicates a small variation around the relevant steady state
variable. This represents the power stage small-signal model, and is shown
in block diagram form in Figure 15.2. Also shown in this gure are the blocks
representing the modulator, compensator and feedback gain. This forms a closed
loop feedback system. With the feedback loop closed we have
Gc (s)
dˆ = (v̂ref − H (s) v̂)
VM
where v̂ref is the reference voltage (which in a regulator system is constant, so
later we will set v̂ref = 0). When substituted and rearranged, the above results
in:
v̂ = Gvref _CL (s)v̂ref + Gvg_CL (s)v̂g − Zout_CL (s)îo
where
1 T (s)
Gvref _CL (s) =
H(s) 1 + T (s)
Gvg (s)
Gvg_CL (s) =
1 + T (s)
Zout (s)
Zout_CL (s) =
1 + T (s)
Where T (s) is the loop gain given by:
1
T (s) = · Gc (s) · Gvd (s) · H(s)
VM
Alternatively, these closed loop transfer functions could also have been straight-
forwardly derived by a block diagram reduction of Figure 15.2.
The open loop transfer functions for the converter and modulator are summa-
rized in Table 15.1.
© Richard Tymerski and Frank Rytkonen, 2017 259
Table 15.1: Transfer Functions of the buck converter and modulator
2 √
s s LC √1
∆ (s) = 1 + ω0 Q + ω0 , Q= L ,
rL C+ R
ω0 = LC
v̂ Vg
Gvd ,
dˆ ∆(s)
v̂ D
Gvg ,
v̂g ∆(s)
v̂ sL
rL 1 + rL
−Z out , −
îo ∆(s)
dˆ 1
GP W M ,
v̂c VM
Rb
H(s)− feedback gain
Ra + Rb
The system to be analyzed and built in this lab is shown in Figure 15.4. This
is a modi cation of the open loop circuit examined in Lab. 4. A number of
elements have been added to the open-loop circuit:
1. Compensator: this is added to shape the loop gain to assure stability
and to obtain adequate phase and gain margins.
2. Divider: this is a resistive divider which takes the output converter volt-
age and divides it to produce a lower level voltage which will be compared
to a suitable reference voltage. From a control theoretic point of view, this
is denoted as the feedback gain in the standard non-unity gain feedback
block diagram.
3. Voltage reference: this is the input of a feedback system. Since the
system here is a voltage regulator, the input is a constant voltage. This is
achieved using a Zener diode.
The compensator used in this lab is the integral compensator, which is shown
in its usual form in Figure 15.3. The transfer function for this compensator is
given by:
1
Gc (s) = −
RCs
260 © Richard Tymerski and Frank Rytkonen, 2017
We will add this transfer function and that of the resistive divider, (which
corresponds to the H (s ) block in Figure 15.2), in closing the loop around the
system. The resulting compensated loop gain transfer function of the system
will be examined.
Figure 15.3: Integral compensator implementation, Gc (s) = − Ksi , where Ki =
1
RC
15.3 Tasks
15.3.1 Pre-Lab
In the following tasks we will analyze the closed-loop system. For the PWM
modulator model use the peak-to-peak ramp amplitude value VM that you mea-
sured as part of Lab. 4.
1. Loop gain Analysis:
(a) Asymptotic Bode plots: Sketch and annotate the asymptotic
Bode plot (magnitude and phase) for each of the following. The
annotations should comprise labeling of break frequencies, slopes of
sloping lines, gains of sloping lines and gain and phase levels of zero
slope lines.
i. Uncompensated loop gain, i.e. product of all the transfer func-
tions in the loop, except set Gc (s) = 1. Be sure to use a Q value
that takes account of the ESR of the inductor. Don't forget to
annotate the sketch.
ii. Compensator transfer function. Here the integral controller has
transfer function, Gc (s) = − Ksi , where
1
Ki =
RC . (Ignore the
negative sign in Bode plot construction.) Don't forget to anno-
tate the sketch.
iii. Construct the (composite) asymptotic Bode plot for the com-
pensated loop gain. Do this by graphically combining the plots
of (i) and (ii). Don't forget to annotate the sketch. Using this
© Richard Tymerski and Frank Rytkonen, 2017 261
Figure 15.4: Schematic of the closed-loop voltage regulator system.
262 © Richard Tymerski and Frank Rytkonen, 2017
plot determine the phase margin and unity gain crossover fre-
quency, and the gain margin (in dB) and the associated −180◦
phase crossover frequency.
(b) Routh-Hurwitz: Derive the compensated loop gain, T, with an
integral controller with transfer function, Gc (s) = − Ksi . Use the
Routh-Hurwitz test to nd the range of values of Ki for which the
loop is stable. To determine the closed loop stability using Routh-
Hurwitz you'll need to examine the coe cients of the denominator
1 T
polynomial of transfer function
1+T or 1+T . These transfer func-
tions appear as part of the closed loop transfer functions previously
derived. State the value of Ki used in the schematic of Fig. 3.
2. Closed-loop transfer functions - Matlab:
(a) Loop gain: Use the Matlab margin command to obtain the Bode
plot of the compensated loop gain. Have the plot display frequency
in Hz. This command will also determine the phase and gain mar-
gins of the system, and the associated frequencies, i.e. unity gain
crossover frequency and the −180◦ phase crossover frequency, re-
spectively. These should con rm the numbers that you determined
in Task (1.a.iii). Make note of these in your report.
(b) Input voltage to output voltage: Determine the closed-loop in-
put source voltage to output voltage transfer function which we'll
denote as: Gvg_CL . Use the Matlab bodemag command to obtain the
magnitude frequency response of this transfer function. On the same
plot show the open loop transfer function, Gvg . Show the response in
Hz over a frequency range of 1 Hz to 10 kHz.
(c) Output current to output voltage: Determine the closed-loop
output current to output voltage transfer function. Since this is the
negative of the output impedance, we will denote it as −Z out_CL . Use
the Matlab bodemag command to obtain the magnitude frequency re-
sponse of this transfer function. On the same plot show the open loop
transfer function, −Z out . Show the response in Hz over a frequency
range of 1 Hz to 10 kHz.
3. Closed-loop simulations Matlab:
Note that the following simulations obtained using Matlab are based on
the small-signal model only. Thus DC conditions and large signal eects
are not modelled and so consequently do not show up in the simulations.
However it is recommended that the steady state output voltage be added
to the responses below (as was done in Lab. 3), so that an easy comparison
can be done with the PECS simulations in Task 4.
(a) Input voltage step response: Use the transfer function previously
obtained for Gvg_CL to obtain the output step response for a 10%
© Richard Tymerski and Frank Rytkonen, 2017 263
input voltage step, which for a nominal input voltage of 10 V cor-
responds to a unit step. If required, refer to Lab. 3 to see how to
use the Matlab lsim command to perform a unit step response sim-
ulation. Obtain the step response plot and determine the maximum
peak-to-peak output voltage deviation, ∆v , and steady state error,
SSE.
(b) Output current step response: Use the transfer function previ-
ously obtained for −Z out_CL to determine the step response for a
step load change. If required, refer to Lab. 3 to see how to determine
the current load step value and to see how it can be used with the
Matlab lsim command to perform step response simulation. Obtain
the step response plot and determine the maximum peak-to-peak
output voltage deviation, ∆v , and steady state error, SSE.
4. Closed-loop simulations PECS: We will now use the circuit simu-
lator to obtain the same two closed loop responses discussed in Task (3)
above. The PECS simulations will show DC conditions and large signal
eects, such as ripple, not available using the Matlab small-signal models.
(a) Input voltage step response: Con gure a PECS schematic to
obtain the output voltage step response for the input voltage stepping
from 10 V (the nominal input voltage level) to 11 V. Obtain the
step response plot and determine the maximum peak-to-peak output
voltage deviation, ∆v , and steady state error, SSE.
(b) Output current step response: Con gure a PECS schematic to
obtain the output step response to a switched load, as was previously
undertaken in Lab. 3. Obtain the step response plot and determine
the maximum peak-to-peak output voltage deviation, ∆v , and steady
state error, SSE.
15.3.2 In the Lab
5. Build the circuit:
(a) Check circuit operation: Now that the simulations of the previous
tasks have been performed, hopefully you've obtained some greater
appreciation for the functioning and the performance of the closed
loop regulator system. We will now build the system as shown in Fig-
ure 15.4. Before performing the load switching test (to be discussed
next) make sure your system is functioning properly by checking vari-
ous voltage waveforms in the circuit. These may include the sawtooth
waveform, the voltage waveform across the switching diode (i.e. at
the input of the LC lter) as well as the output voltage. The output
voltage level should be at a nominal value of 5 V.
264 © Richard Tymerski and Frank Rytkonen, 2017
(b) Output current step response: For simplicity in the following
we will restrict ourselves in the lab to only obtaining the step load
response.
Connect a square wave generator which produces a 5 V amplitude
signal to the load switching mosfet as shown in the schematic. While
monitoring the output voltage response adjust the frequency of the
applied signal to a maximum required to fully see the evolving re-
sponse before the next switching event occurs. A frequency in the
range of 50 Hz to 100 Hz should be adequate. Take a screen shot of
this response. Determine the maximum peak-to-peak output voltage
deviation, ∆v , and steady state error, SSE.
15.3.3 Post-Lab
6. In your report include the following tables to succinctly summarize your
results.
(a) In the following table, summarize results of your loop analysis ob-
tained by
i. the asymptotic Bode plot method, and,
ii. Matlab con rmation.
Phase Margin Unity Gain Gain Margin Phase
Crossover, f Crossover, f
(degrees) (kHz) (dB) (kHz)
φ PM G c GM GM
Asymptotes
Matlab
(b) To compare the step response results obtained by the three ap-
proaches summarize them in the following table:
Matlab PECS
Lab
Simulation Simulation
vg : step ∆v Unavailable
vg : step SSE Unavailable
iout : step ∆v
iout : step SSE
(c) Write your observations concerning these results.
7. The next two tasks (i.e. Tasks (8) and (9)) are optional. Consider doing
either one or both. They examine the performance of the system using
alternative compensators. In Task (8), the performance of a proportional
compensator i.e. Gc (s) = −Kp , where Kp is a constant, is examined. In
s
1+
Task (9), a lead compensator, where Gc (s) = −K 1+ ωsz where ωz and ωp
ωp
© Richard Tymerski and Frank Rytkonen, 2017 265
are zero and pole frequencies, respectively, such that ω z < ω p , is examined.
The performance with these controllers feature one striking qualitative
dierence with that of the integral controller for the stepped input tests
undertaken here. Can you state what that is? (Hint: do a quick simula-
tion using PECS, using the compensator circuits below along with the R
and C values suggested there, and see what that is.)
15.4 Optional Tasks - Alternative compensators
Having already tackled tasks (1) to (6) for the case of integral control, it
is straightforward to examine the case of proportional and lead control.
15.4.1 Proportional Control
8. The proportional controller is shown in Figure 15.5. In PECS and in
the hardware, one needs only to swap out the capacitor of the integral
controller with an appropriately sized resistor. To achieve a gain of ten,
we will set R2 = 1M Ω, (given that R1 = 100kΩ).
Repeat tasks (1) to (6), to examine the performance of a proportional
controller.
Figure 15.5: Proportional compensator implementation, Gc (s) = −Kp , where
R2
Kp = R1
15.4.2 Lead Control
9. The lead controller is shown in Figure 15.6.
266 © Richard Tymerski and Frank Rytkonen, 2017
s
1+
Figure 15.6: Lead compensation implementation, Gc (s) = −K 1+ ωsz , for ωz <
ωp
ωp .
The zero and pole frequencies are given by ω z = R11C1 and ω p = R21C2 and
K= R 2
R1 . Use R1 = 22 kΩ, R2 = 820 kΩ, C1 = 4.7 nF and C2 = 12 pF.
Repeat tasks (1) to (6), to examine the performance of the lead controller.
15.5 Note
The op-amp used in the compensator, i.e. the CA3140, was chosen since, as
stated in the datasheet, it has a common mode input voltage capability down
to 0.5 V below the negative supply terminal which is more than adequate for
our use of a 2.5 V reference voltage at one of its input terminals. Other op-amps
do not fair so well so one needs to bear this in mind in seeking a substitute for
this device.
© Richard Tymerski and Frank Rytkonen, 2017 267
268 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 16
Lab 6
Closed Loop Feedback System - Design:
Design of an eective feedback compen-
sator for a closed loop dc-to-dc converter
system
16.1 Objectives
This is the nal in this series of six labs culminating in the design of an eective
frequency compensator for a practical feedback system. There are four main
objectives:
1. Design of a feedback compensator using the asymptotic Bode plot method-
ology.
2. Veri cation of the design before implementation in the lab. This is done
both at the transfer function level using Matlab, and at the circuit level
using PECS.
3. Building the complete feedback system in the lab and subsequently testing
it.
4. To appreciate the eectiveness of the design, a comparison with previous
implementations is made. Three implementations are compared:
(a) Open loop (Lab 4)
(b) Closed loop with integral compensation (Lab. 5)
(c) Closed loop with `dominant pole plus lead' compensation (Lab. 6
(this lab))
269
16.2 Background
For this lab we start with the circuit implementation of Lab. 5. The integral
compensator in the Lab 5 circuit will be replaced with a `dominant pole plus
lead' compensator that will be designed in this lab. The compensator has a
transfer function given by:
ω0 1 + ωs1 1+ s
ω2
Gc (s) = −
s 1 + ωs3
A circuit implementation of this transfer function is shown in Figure 16.1. This
compensator enables the loop gain to exhibit a very high gain at low frequencies
as well as an extended bandwidth while achieving desired phase and gain mar-
gins. The design of the compensator is to be undertaken using the asymptotic
Bode plot method which straightforwardly approaches the problem of eective
loop shaping.
Figure 16.1: `Dominant pole plus lead' compensator to be designed in this lab.
The poles and zeros of the compensator in terms of component values are given
by:
1
ω0 =
R1 (C2 + C3 )
1
ω1 =
R 2 C2
1
ω2 =
R 1 C1
1
ω3 =
R2 C2 C3
C2 +C3
In Lab. 5 we implemented the integral controller where the compensator transfer
Ki
function is given by (ignoring sign) Gc (s) =
s . Also, (as an optional task),
an opportunity was given to examine proportional control where Gc (s) = Kp .
270 © Richard Tymerski and Frank Rytkonen, 2017
These compensators may be seen as speci c components of the three term PID
(Proportional Integral Derivative) compensators. If we consider the general
PID compensator we have
Ki
Gc (s) = Kp + + Kd s
s
where the third (derivative) term has now been added. Note however that this
third term, on its own, is non-causal and therefore not realizable. To remedy
this, it is customary to associate a high frequency pole with this term. This
results in the following for the total PID compensator
Ki Kd s
Gc (s) = Kp + +
s 1 + as
where a represents the added high frequency pole. The above may be arranged
in quotient form
(K p +aK d )s2 + (aKp + Ki ) s + aK i
Gc (s) =
s(s + a)
Thus the general PID compensator is comprised of two real poles (with one at
zero frequency, the integral term) and two zeros, which are not necessarily
real. Comparing this with the `dominant pole plus lead' compensator transfer
function, we see the same pole/zero features except that the `dominant pole
plus lead' compensator has real valued zeros.
16.3 Tasks
16.3.1 Pre-Lab
1. Design of feedback compensator: Design a `dominant pole plus lead'
compensator for the system. The compensator should achieve a phase
margin ≥ 45◦ and gain margin ≥ 10 dB. The loop gain bandwidth (i.e.
1
the unity gain crossover frequency) should be set at
8 of the switching
40 kHz
frequency, i.e.
8 = 5 kHz. Note that use of this compensator, which
features a pole at zero, assures a performance characteristic of zero steady
state error to step inputs. Fully document your design procedure.
Use the asymptotic Bode plot method to design your compensator. This
methodology involves using asymptotic Bode plot construction of the
desired loop gain from which simpli ed equations may be derived for use
in the design process. It does not inherently rely on trial and error
iteration and so you are requested not to use such an approach. In the
text by Tymerski & Rytkonen the methodology is discussed for the
suggested compensator for the buck regulator in a section entitled
Dominant Pole with Lead Compensation. There are two design
© Richard Tymerski and Frank Rytkonen, 2017 271
variations discussed there; one being better than the other. (So choose
wisely).
Determine the compensator parameters from simpli ed equations derived
from your asymptotic plots. As a nal step in the design, implement the
compensator as a circuit. The needed equations for this are given above.
For the model of the PWM modulator use a peak-to-peak ramp
amplitude value that you measured in Lab. 4. Clearly note this value in
your report.
2. Compensator design veri cation: With the compensator design com-
pleted in Task (1) we will now verify the design before implementing it in
the lab. This veri cation is similar to that previously done in Lab. 5 for
a dierent compensator. The Matlab code developed there can be reused
here.
In the following tasks we will analyze the closed-loop system using Matlab
and PECS.
Closed-loop transfer functions - Matlab:
(a) Loop gain: Determine the loop gain transfer function and use the
Matlab margin command to obtain the Bode plot of this loop gain.
Have the plot display frequency in Hz. The command will also obtain
the unity gain crossover and −180◦ phase crossover frequencies and
the phase and gain margins of the system. Make note of these in
your report.
(b) Input voltage to output voltage: Determine the closed-loop in-
put source voltage to output voltage transfer function which we'll
denote as: Gvg_CL .Use the Matlab bodemag command to obtain the
magnitude frequency response of this transfer function. On the same
plot show the open loop transfer function, Gvg . Display frequency in
Hz over a range of 1 Hz to 10 kHz.
(c) Output current to output voltage: Determine the closed-loop
output current to output voltage transfer function. Since this is the
negative of the output impedance, we will denote it as −Z out_CL . Use
the Matlab bodemag command to obtain the magnitude frequency
response of this transfer function. On the same plot show the open
loop transfer function, −Z out . Display frequency in Hz over a range
of 1 Hz to 10 kHz.
3. Closed-loop simulations Matlab:
Note that the following simulations obtained using Matlab are based on
the small-signal model. The DC conditions and large signal eects are not
modelled and consequently do not show up in the simulations.
272 © Richard Tymerski and Frank Rytkonen, 2017
(a) Input voltage step response: Use the transfer function obtained
above for Gvg_CL to obtain the step response for the 10% input
voltage step. As the nominal input voltage 10 V, this implies a unit
step change. If required, refer to Lab 3 to see how to use the Matlab
lsim command to perform step response simulation. As shown in
Lab 3 add the steady state average voltage to this simulation so as to
ease the comparison with the PECS simulation to follow. Obtain the
step response plot and determine the maximum peak-to-peak output
voltage deviation, ∆v , and steady state error, SSE.
(b) Output current step response: Use the transfer function ob-
tained above for −Z out_CL to obtain the step response for a step
load change. If required, refer to Lab. 3 to see how to determine
the current load step value and to see how it can be used with the
Matlab lsim command to perform step response simulation. As with
the input voltage step simulation add the average output voltage to
the simulation to simplify the comparison with the PECS simulation
which follows. Obtain the step response plot and determine the max-
imum peak-to-peak output voltage deviation, ∆v , and steady state
error, SSE.
4. Closed-loop simulations PECS:
We will now use the circuit simulator to obtain the same two closed loop
responses discussed in task 3 above. The PECS simulations will show DC
conditions and large signal eects, such as ripple, not available using the
Matlab small-signal models.
(a) Input voltage step response: Con gure a PECS schematic to
obtain the input voltage step response to steps from 10 V to 11 V
back to 10 V, as done in previous labs. Obtain the step response plot
and determine the maximum peak-to-peak output voltage deviation,
∆v , and steady state error, SSE.
(b) Output current step response: Con gure a PECS schematic to
obtain the output voltage response for step load changes from 25 Ω
to 5 Ω back to 25 Ω. Obtain the step response plot and determine
the maximum peak-to-peak output voltage deviation, ∆v , and steady
state error, SSE.
16.3.2 In the Lab
Now that you've con rmed your design with both Matlab and PECS, we
can con dently build the circuit.
5. Build and test the new compensator:
© Richard Tymerski and Frank Rytkonen, 2017 273
(a) Add new compensator: Replace the integral compensator of Lab
5 with your newly designed compensator and con rm that the circuit
is functioning properly with this compensator. Check that the output
is at a constant 5 V level. Do not operate load switching at this time.
(b) Output current step response: Apply the load switching signal
and observe the output voltage response. Adjust the frequency of
load switching, if necessary. Take a screen shot of the output volt-
age response. Determine the maximum peak-to-peak output voltage
deviation, ∆v , and steady state error, SSE.
16.3.3 Post-Lab
Results:
6. In your report include the following tables to succinctly summarize your
results.
(a) In the following table, summarize results of your loop design obtained
by
i. the asymptotic Bode plot method, and,
ii. Matlab con rmation
Phase Margin Unity Gain Gain Margin Phase
Crossover, f Crossover, f
(degrees) (kHz) (dB) (kHz)
φ PM G c GM GM
i) Asymptotes
ii) Matlab
(b) Summarize the performance of your design. We will also take the
opportunity to compare the results with those obtained from previous
labs.
Three implementations will be compared:
i. Open loop (Lab 4)
ii. Closed loop with integral compensation (Lab. 5)
iii. Closed loop with `dominant pole plus lead' compensation (Lab.
6, this lab)
The results will be summarized by completing the following table:
φP M : phase margin obtained from Matlab margin command
fc : unity gain crossover frequency obtained from Matlab margin
command
∆v : maximum peak-to-peak output voltage variation, result may
be obtained from the LAB, PECS or MATLAB.
SSE : steady state error voltage result obtained from the LAB,
PECS or MATLAB.
274 © Richard Tymerski and Frank Rytkonen, 2017
Open loop* Integral Integral + lead
(Uncompenstated) Compensator, Compensator,
(from Lab. 4) (from Lab. 5) (from Lab. 6, this lab)
Compensator
Transfer
No compensator
Function
Gc (s)
φP M (degrees)
MATLAB
fc (kHz)
MATLAB
iout step: ∆v (mV)
LAB
iout step: ∆v (mV)
PECS
iout step: ∆v (mV)
MATLAB
iout step: SSE (mV)
LAB
iout step: SSE (mV)
PECS
iout step: SSE (mV)
MATLAB
vg step: ∆v (mV)
PECS
vg step: ∆v (mV)
MATLAB
vg step: SSE (mV)
PECS
vg step: SSE (mV)
MATLAB
*This is the open loop (uncompensated) system. That is, unlike the
other two systems feedback is not applied. It is included here to see
how well feedback control is able to improve on open loop control.
(c) Write your observations concerning these results.
© Richard Tymerski and Frank Rytkonen, 2017 275
276 © Richard Tymerski and Frank Rytkonen, 2017
Appendix A
List of Parts
277
No. Item
C1 100 µF capacitor
electrolytic
C2 100 µF capacitor
Kemet A758EK107M1AAAE016
C3 10 nF capacitor
C4 3.3nF capacitor
C5 1 µF capacitor
C6 1 µF capacitor
C7 1 µF capacitor
C8 1 µF capacitor
C9 22 nF capacitor
D1 Power Schottky Diode
Sanken RA 13V1
D2 1N5222 2.5 V Zener Diode
D3 1N5222 2.5 V Zener Diode
L1 560 µH inductor
Bourns Inc. 2200HT-561-V-RC
1
R1 1 kΩ 16 W Resistor
R2 5 Ω 5 W Power Resistor
R3 20 Ω 2 W Power Resistor
1
R4 Ω 16
47 W Resistor
1
R5 2.7 kΩ
16 W Resistor
1
R6 560 Ω
16 W Resistor
1
R7 4.7 kΩ
16 W Resistor
1
R8 3.3 kΩ
16 W Resistor
1
R9 220 kΩ
16 W Resistor
1
R10 12 kΩ
16 W Resistor
1
R11 100 kΩ
16 W Resistor
1
R15 1 kΩ
16 W Resistor
1
R16 1 kΩ
16 W Resistor
Q1 Q2N2222 NPN Transistor
Q2 Q2N2907 PNP Transistor
Q3 IRF 9530 P-Channel MOSFET
Q4 IRF 530 N-Channel MOSFET
Q5 Q2N2907 PNP Transistor
U1 LM555 Timer
VR1 10kΩ Variable Resistor
VR2 1kΩ Variable Resistor
X1 LM311 Voltage Comparator
X2 CA3140 Op Amp
278 © Richard Tymerski and Frank Rytkonen, 2017
Appendix B
Lab Grading Sheets
279
Lab 1 Grading Sheet
Circuit #1:
1. Your PECS schematic /1
2. Task 4:
(i) VP2 plot /1
(ii) Steady state output voltage value /1
3. Tasks 6 and 7:
(i) Zoomed plot with VP2 and VP1 /1
(ii) Peak-to-peak ripple of VP2 /1
4. Task 8: VP1:
(i) peak amplitude /1
(ii) period /1
(iii) pulse width /1
(iv) duty ratio /1
5. Task 9: Explanation of steady state value /1
Circuit #2:
1. Task 1: Your PECS schematic /1
2. Task 3: Plot of VP1 and IP1 /1
3. Task 4: VP1 (voltage across the capacitor):
(i) peak amplitude /1
(ii) period /1
(iii) Factors determining amplitude and /1
(iv) why? /1
Circuit #3:
1. Task 1: Your PECS schematic /3
2. Task 2
(i) VP2 plot /1
(ii) Steady state output voltage value /1
(iii) Zoomed plot with VP2 and VP1 /1
(iv) Peak-to-peak ripple of VP2 /1
(v) VP1:
(a) peak amplitude /1
(b) period /1
(c) pulse width /1
(d) duty ratio /1
(vi) Explanation of steady state value /1
280 © Richard Tymerski and Frank Rytkonen, 2017
3. Task 3: Completed table /5
4. Task 4:
(i) The dierence in ripple values between Circuit #3 and Circuit #1 /1
(ii) Why would you expect this? /1
Report: /5
Total: /40
© Richard Tymerski and Frank Rytkonen, 2017 281
Lab 2 Grading Sheet
1. Task 1: Your PECS schematic /1
2. Task 4:
(i) Plot /1
0
(ii) cmax /1
0
(iii) cf inal /1
3. Task 5:
(i) cmax /1
(ii) cf inal /1
4. Task 6:
(i) %OS /2
(ii) ζ /2
5. Task 7:
0
(i) Ts /1
(ii) T s /1
6. Task 8: K /2
7. Task 9:
(i) LCR transfer function derivation /2
(ii) K as a function of elements /1
(iii) a1 as a function of elements /1
(iv) a2 as a function of elements /1
(v) completed table /6
8. Task 10: Your complete Matlab code /2
9. Task 11:
(i) Matlab plot 1 /1
(ii) Matlab plot 2 /1
10. Task 12:
(i) Output of Matlab stepinfo function /1
(ii) Completed table /2
11. Task 13:
(i) Derivation of transfer function with rL included /2
(ii) Transfer function with simpli cation applied /1
(iii) Appreciable change in DC gain? /1
(iv) Appreciable change in undamped natural frequency? /1
(v) Appreciable change in damping factor? /1
Report: /7
Total: /45
282 © Richard Tymerski and Frank Rytkonen, 2017
Lab 3 Grading Sheet
1. Task 1:
(i) Your PECS schematic /1
(ii) Start-up transient plot /1
(iii) Steady state output voltage value /1
2. Task 2:
(i) Plot of output voltage, diode voltage and switch current in proper format
/3
(ii) Average output voltage value /1
(iii) Peak-to-peak output voltage ripple value /1
(iv) Peak-to-peak diode voltage value /1
(v) Peak inductor current /1
(vi) Switching frequency /1
(vii) Duty ratio /1
(viii) Explanation of how duty ratio is set /2
3. Task 3:
(i) Simulation plot /1
(ii) Kvg /2
(iii) ∆v /1
(iv) SSE /1
4. Task 4:
(i) Your PECS schematic /1
(ii) Filter corner frequency in Hz. /1
(iii) Plot of VP3 and VP1 in proper format /1
(iv) Peak-to-peak of VP3 and of VP1 /2
(v) In-phase or out of phase? /1
(vi) Kvd /2
5. Task 5
(i) Your PECS schematic /1
(ii) Simulation plot of VP1 /1
(iii) ∆v /1
(iv) SSE /1
6. Task 6a:
(i) Loop gain transfer function /2
(ii) Your complete MATLAB code /1
(iii) Matlab plot /1
© Richard Tymerski and Frank Rytkonen, 2017 283
(iv) Unity gain and phase crossover frequencies, phase and gain margins values
/2
7. Task 6b:
(i) Gvd transfer function /2
(ii) Your Matlab code /1
(iii) Your Matlab plot /1
8. Task 6c:
(i) −Zout transfer function /2
(ii) Your Matlab code /1
(iii) Your Matlab plot /1
9. Task 6d:
(i) Your complete Matlab code /1
(ii) Matlab plot /1
(iii) ∆v /1
(iv) SSE /1
10. Task 6e:
(i) Zout transfer function /1
(ii) Your Matlab code /1
(iii) Your Matlab plot /1
(iv) ∆v /1
(v) SSE /1
11. Results (summary):
(i) Transfer function DC gains' table /3
(ii) Margins and associated frequencies table /2
(iii) Step response characteristics table /2
(iv) Comparison of results for ∆v and iout changes /2
(v) Simple symbolic expression for SSE for a step in ∆v /2
Report: /5
Total: /70
284 © Richard Tymerski and Frank Rytkonen, 2017
Lab 4 Grading Sheet
1. One photo of constructed circuit (power stage on perf board and the rest on
solderless board?) /7
2. Task 1b:
(i) Screenshot of sawtooth (40 kHz?) /1
(ii) Minimum values of sawtooth /1
(iii) Maximum values of sawtooth /1
3. Task 2b:
(i) Minimum achievable duty ratio calculation /2
(ii) Maximum achievable duty ratio /2
(iii) Minimum achieved duty ratio value obtained in the lab /1
(iv) Maximum achieved duty ratio value obtained in the lab /1
4. Task 2c:
(i) Screenshot of output of LM311 (15 V pk-pk? and 50% duty ratio?) /1
5. Task 3b:
(i) Screenshot of output of mosfet driver (10 V pk-pk?) /1
6. Task 4b:
(i) Screenshot of diode voltage (10 V pk-pk? Sharp transitions?) /1
7. Task 4c:
(i) Measured value of average output voltage /1
(ii) Expected value of average output voltage (why?) /1
8. Task 4d:
(i) Screenshot of input and output sinusoidal /1
(ii) Measured pk-pk value of output sinusoid /1
(iii) Measured pk-pk value of input /1
(iv) Gain = ratio of output/input calculated /1
(v) What does this gain represent? /1
(vi) What are the components of this gain? /2
(vii) In-phase or out-of-phase? /1
(viii) Will the compensator need to provide phase inversion so as to provide
negative feedback? /1
9. Task 5b:
(i) Screenshot of output voltage response to stepped load change /1
(ii) ∆v, maximum pk-pk output voltage deviation /1
(iii) SSE, steady state error /1
© Richard Tymerski and Frank Rytkonen, 2017 285
10. Results (summary):
(i) Sawtooth table /1
(ii) Duty ratio table /1
(iii) Sinusoid table /1
(iv) ∆v and SSE table /5
(v) Observations concerning step response /4
Report: /5
Total: /50
286 © Richard Tymerski and Frank Rytkonen, 2017
Lab 5 Grading Sheet
1. Task 1:
(i) Sketch of magnitude and phase response of uncompensated loop gain /1
(ii) Sketch properly annotated /1
2. Task 1a.ii:
(i) Sketch of magnitude and phase response of compensator /1
(ii) Sketch properly annotated /1
3. Task 1a.iii:
(i) Sketch of magnitude and phase response of compensated loop gain (i.e.
above two combined) /1
(ii) Sketch properly annotated /2
(iii) From sketch determine, unity gain crossover frequency /1
(iv) From sketch determine, phase margin /1
(v) From sketch determine, crossover frequency /1
(vi) From sketch determine, gain margin /1
4. Task 1b:
(i) Expression for compensated loop gain, T /1
(ii) Expression for denominator polynomial of 1/(1+T ) or T /(1+T ) /1
(iii) Stable range of Ki /1
(iv) Actual value of Ki used /1
5. Task 2a:
(i) Matlab margin plot /1
(ii) unity gain crossover frequency, phase margin, -180 crossover frequency,
gain margin /1
6. Task 2b:
(i) Expression for Gvg_CL /1
(ii) Matlab code to produce bodemag plots of Gvg_CL and (open loop)Gvg /1
(iii) Matlab bodemag plots of Gvg_CL and (open loop) Gvg /1
(iv) (iii) with requested frequency range /1
7. Task 2c:
(i) Expression for −Zout_CL /1
(ii) Matlab code to produce bodemag plots of −Zout_CL and(open loop)−Zout
/1
(iii) Matlab bodemag plots of −Zout_CL and (open loop) −Zout /1
(iv) (iii) with requested frequency range /1
8. Task 3a:
© Richard Tymerski and Frank Rytkonen, 2017 287
(i) Full Matlab code for simulation of step response of Gvg_CL /1
(ii) Step response obtained from the Matlab code /1
(iii) ∆v /1
(iv) SSE /1
9. Task 3b:
(i) Full Matlab code for simulation of step response of−Zout_CL /1
(ii) Step response obtained from the Matlab code /1
(iii) ∆v /1
(iv) SSE /1
10. Task 4a:
(i) PECS schematic for simulation of step response of Gvg_CL /1
(ii) Step response obtained from PECS /1
(iii) ∆v /1
(iv) SSE /1
11. Task 4b:
(i) PECS schematic for simulation of step response of −Zout_CL /1
(ii) Step response obtained from PECS /1
(iii) ∆v /1
(iv) SSE /1
12. Task 5b:
(i) Lab screen shot of step response of −Zout_CL /1
(ii) ∆v /1
(iii) SSE /1
13. Task 6a:
(i) Loop stability margins and frequencies table /1
14. Task 6b:
(i) ∆v and SSE summary table /1
(ii) Observations on results /2
15. Task 7:
(i) Step response dierence with proportional and lead compensator with the
integral compensator /2
16. Task 8: Optional compensator proportional compensator: if submitted grade
with identical grading sheet /2
17. Task 9: Optional compensator lead compensator: if submitted grade with
identical grading sheet /2
Report: /5
Total: /55
288 © Richard Tymerski and Frank Rytkonen, 2017
Lab 6 Grading Sheet
1. In Lab demonstration of switched load feedback voltage regulator /10
2. Task 1:
(i) Full documentation of your design procedure (do not copy plots from any-
where) /20
(ii) Compensator parameters from simpli ed equations derived from your asymp-
totic plots /5
(iii) model of the PWM modulator use a pk-pk ramp amplitude value measured
in Lab.4 /1
3. Task 2a:
(i) Determine the loop gain transfer function /1
(ii) Matlab margin plot in Hz /1
(iii) margins and associated frequencies /1
4. Task 2b:
(i) Expression for Gvg_CL /1
(ii) Matlab code to produce bodemag plots of Gvg_CL and (open loop) Gvg /1
(iii) Matlab bodemag plots of Gvg_CL and (open loop) Gvg /1
(iv) (iii) in frequency range 1 Hz to 10 kHz /1
5. Task 2c:
(i) Expression for −Zout_CL /1
(ii) Matlab code to produce bodemag plots of −Zout_CL and (open loop) −Zout
/1
(iii) Matlab bodemag plots of −Zout_CL and (open loop) −Zout /1
(iv) (iii) in frequency range 1 Hz to 10 kHz /1
6. Task 3a:
(i) Full Matlab code for simulation of step response of Gvg_CL /1
(ii) Step response obtained from the Matlab code /1
(iii) ∆v /1
(iv) SSE /1
7. Task 3b:
(i) Full Matlab code for simulation of step response of −Zout_CL /1
(ii) Step response obtained from the Matlab code /1
(iii) ∆v /1
(iv) SSE /1
8. Task 4a:
(i) PECS schematic for simulation of step response of Gvg_CL /1
© Richard Tymerski and Frank Rytkonen, 2017 289
(ii) Step response obtained from PECS /1
(iii) ∆v /1
(iv) SSE /1
9. Task 4b:
(i) PECS schematic for simulation of step response of −Zout_CL /1
(ii) Step response obtained from PECS /1
(iii) ∆v /1
(iv) SSE /1
10. Task 5b:
(i) Lab screen shot of step response of −Zout_CL /2
(ii) ∆v /1
(iii) SSE /1
11. Task 6a:
(i) Loop stability margins and frequencies table /4
12. Task 6b:
(i) Large results summary table /15
13. Task 6c:
(i) Observations on results /5
Report: /9
Total: /100
290 © Richard Tymerski and Frank Rytkonen, 2017
Part IV
Modern Control
291
Chapter 17
Introduction
There are three main problems that can be examined in the study of systems
in the controls context: system dynamics, system identi cation or modeling,
and system control. They develop from the three aspects that are present in
the block diagram of a basic system: input, system, and output [1]. Typically,
two of the three aspects are known, and the third must be determined from the
other two.
In system control, the system is known, and the input to the system that pro-
duces a desired output must be determined. Part II focuses on the fundamental
control problem of regulation for disturbance rejection as it pertains to DC-DC
converters, and uses the uk DC-DC converter as the platform for applying
the various design steps, leading up to a mimimal-order compensator design,
demonstrated in Chapter 23. It is assumed that the reader of this part of the
book is familiar with the classical control system design techniques presented
earlier as the modern control design methods build on a classical foundation.
Note that for the regulation problem, the desired output value is xed, whereas
in the servo problem, the desired output is to track a changing setpoint.
The uk DC-DC converter was chosen as an example system for two main
purposes. This nonlinear switching circuit can act to raise (boost) or lower
(buck) the voltage from input to output, making it a generic DC-DC converter
(compared to converters that can only boost or buck the input voltage, but not
do both). Also, the circuit contains four energy storage devices leading to a
fourth-order system, which creates su cient complexity in an output feedback
compensator to require compensator order reduction. This allows an original
idea regarding order reduction to be presented. Boost or buck converters are
typically implemented with only two energy storage components, and the result-
ing simplicity in compensators designed using modern control techniques either
does not require model reduction or renders one of the techniques presented in
this part of the text practically useless.
Analysis of the uk converter circuit begins in Chapter 18. The control
system analysis and design procedures use MATLAB from The Mathworks,
Inc., and code is presented at the end of each chapter for the relevant chap-
293
ter material. The nonlinear uk switching circuit is modeled as a small-signal
continuous linear time invariant (LTI) system using state space averaging. The
LTI model to be used during the design process is validated by transient com-
parison with a nonlinear circuit simulation to justify the assumption that the
small-signal model would be adequate. The open-loop performance character-
istics are tested, and a set of performance criteria for the closed-loop controlled
system are speci ed.
Chapter 19 covers pole placement using state feedback. This chapter uses
desired poles given by a lter prototype that is optimal with respect to an
integral performance index and discusses how to select a weighting parameter
that determines the closed-loop pole locations.
Integral augmentation of the state feedback architecture is described in
Chapter 20. This allows the closed-loop system to completely eliminate steady
state error, which could not be accomplished by state feedback alone.
Chapter 21 discusses state estimation using full- and reduced-order observers
to allow for the use of output feedback, as state information is not always
available to the designer.
Chapter 22 shows the application of optimal control and estimation using
linear quadratic methods. These techniques allow the designer to determine
optimal controller and optimal estimator gains. Loop transfer recovery is dis-
cussed as a means to recover desirable frequency-domain stability margins that
are lost when designing an optimal output feedback compensator.
In order to design compensators that can be constructed from a minimum
number of components, Chapter 23 covers order reduction methods. First, a
reduced-order optimal compensator with recovered loop gain is designed. This
step is followed by applying balanced realization and truncation techniques to
eliminate states with little eect on performance, resulting in additional com-
pensator order reduction.
Chapter 24 describes how to implement two of the nal compensator designs
that were created and shows the dierence in analog controller circuit complexity
that can arise from only one additional order in the compensator.
Chapter 25 presents the minimal compensator circuit test results from a
power electronics simulator that prove the performance of the nal controller
design exceeded the original design speci cations.
Finally, Chapter 26 wraps up Part II of the text with a recap of the methods
presented and their results.
294 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] B. A. Ogunnaike and W. H. Ray, Process Dynamics, Modeling, and Control.
New York, NY: Oxford University Press, 1994.
295
296 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 18
System Analysis
Prior to designing a controller for a system, the control system designer must
understand the system's characteristics. For example, is the system open-loop
stable? Are there dominant poles? Are there poles that may be neglected during
design? Is the system controllable using the selected inputs? Can an estimator
be constructed based on the measured outputs? These types of questions should
be answered both intuitively and mathematically prior to embarking on an
attempt to design a controller for the system.
As stated in Chapter 17, the uk DC-DC converter is used here as the
example system for demonstrating the compensator design processes described
in Part II. The starting point is the construction of a mathematical model of
the system in MATLAB. The model is a mathematical description of some or
all of the behavior of the real-world system that is adequate for performing
controller design. State space averaging yields a linear small-signal model for
the nonlinear switching system [1]. Additionally, a nonlinear circuit model was
created in the Power Electronics Circuit Simulator (PECS) software package in
order to validate the performance of the assumed linear model. PECS uses a
schematic-based circuit editor and features its own plotting tool, PECSPLOT.
A note on notation: the zeros, poles, and gains of systems discussed in Part
IV are in the Evans form, i.e., the coe cient of the highest power of s in each
factored term is unity and the stated gain is not the DC gain of the system. This
is in contrast to Bode form, where the constant in each factored term is unity
and the DC gain is explicitly stated. Evans form was chosen for convenience,
as it is the form used by zpk systems in MATLAB.
18.1 The uk Converter
The uk converter is a step-down/step-up converter based on a switching boost-
buck topology. Essentially, the converter is composed of two sections, an input
stage and an output stage. The schematic of the uk converter is presented in
Figure 18.1, with component values given in Subsection 18.2.3. (The lowercase
297
Figure 18.1: uk converter with inductor equivalent series resistances.
variables indicate small-signal deviations from nominal operating point variables
as obtained by linearization.) The input voltage vg is fed into the circuit via
inductor L1 . When transistor Q1 is on, current i1 builds the magnetic eld of
the inductor in the input stage. The diode CR1 is reverse biased, and energy
dissipates from the storage elements in the output stage. When Q1 turns o,
inductor L1 tries to maintain the current owing through it by reversing polarity
and sourcing current as its magnetic eld collapses. It thus provides energy to
the output stage of the circuit via capacitor C1 . Both currents i1 and i2 must
sum to zero in the steady state, since the assumption is that voltage v1 is
essentially constant (given that the voltage across a capacitor cannot change
instantaneously and the switching speed of the circuit is high). This provides
for the following charge conservation relation:
i1 ton + i2 tof f = 0 (18.1)
The inductor currents are the input and output currents, therefore, if the prin-
ciple of conservation of energy is applied:
vo Ds
= (18.2)
vg 1 − Ds
∆ ton
where Ds is the duty cycle of the switch, Ds = ton +tof f . Equation 18.2 shows
that by controlling the duty cycle of the switch (by small-signal deviation d),
the output voltage vo can be controlled and can be higher or lower than the
input voltage vg . By using a controller to vary the duty cycle during operation,
the circuit can also be made to reject disturbances, as will be shown.
298 © Richard Tymerski and Frank Rytkonen, 2017
18.2 The uk Converter Model
The uk converter selected was designed with just enough mutual inductance to
avoid a nonminimum phase converter structure, a requirement for a controller
design method used later in the text.
18.2.1 Analysis of Inductors with Mutual Coupling
and Equivalent Series Resistances
The equations for the voltage across two inductors L1 and L2 joined by mutual
coupling are:
di1 di2
vL1 = L1 +M
dt dt
di1 di2
vL2 = M + L2
dt dt
The solutions of the two simultaneous equations are:
di1 L2 −M
= vL + vL
dt L1 L2 − M 2 1 L1 L2 − M 2 2
di2 −M L1
= vL + vL
dt L1 L2 − M 2 1 L1 L2 − M 2 2
For the circuit with equivalent series resistances included in the inductor models
when Q1 conducts:
vL1 = vg − i1 R1
vL2 = v1 − v2 − i2 R2
therefore:
di1 M −M M R2 −L2 R1 L2
= 2
v2 + 2 v1 + 2
i2 + 2
i1 + 2 vg
dt σ σ σ σ σ
di2 −L1 L1 −L1 R2 M R1 −M
= 2
v2 + 2 v1 + 2
i2 + 2
i1 + 2 vg
dt σ σ σ σ σ
with σ2 = L1 L2 − M 2 .
© Richard Tymerski and Frank Rytkonen, 2017 299
When Q1 does not conduct:
vL1 = vg − i1 R1 − v1
vL2 = −v2 − i2 R2
therefore:
di1 M −L2 M R2 −L2 R1 L2
= v2 + 2 v1 + i2 + i1 + 2 v g
dt σ2 σ σ2 σ2 σ
di2 −L1 M −L1 R2 M R1 −M
= v2 + 2 v1 + i2 + i1 + 2 v g
dt σ2 σ σ2 σ2 σ
with σ2 = L1 L2 − M 2 .
18.2.2 The State Space Averaged Model
State space averaging is a well-known method used in modeling switching con-
verters. For a system with a single switching component with a nominal duty
cycle, a model may be developed by determining the state and measurement
equations for each of the two switch states, then calculating a weighted average
of the two sets of equations using the nominal values of the time spent in each
state as the weights. To develop the state space averaged model, the equations
for the rate of inductor current change derived in Subsection 18.2.1 are used
along with the equations for the rate of capacitor voltage change that may be
derived from the uk converter circuit. For the purposes of modeling, the state
vector is given by:
0
x = v2 v1 i2 i1
When Q1 conducts, the following state space matrices result:
1 1
− RC
2
0 C2 0
−1
0 0 C1 0
A1 =
− L12 L1
− L1σR 2 M R1
σ σ2 2 σ2
M R2
M
σ2 − σM2 σ2 − L2σR
2
1
0
0
B1 =
M
− 2
σ
L2
σ2
C1 = 1 0 0 0
D1 = [0]
300 © Richard Tymerski and Frank Rytkonen, 2017
When Q1 is not conducting, the circuit model is represented by the following
state space matrices:
1 1
− RC
2
0 C2 0
−1
0 0 0 C1
A2 =
− L12 M
− L1σR 2 M R1
σ σ2 2 σ2
M
σ2 − Lσ22 M R2
σ2 − L2σR
2
1
0
0
B2 =
− M2
σ
L2
σ2
C2 = 1 0 0 0
D2 = [0]
By representing the duty cycle of the switch as Ds , the following results may
be obtained for a state space averaged model of the uk converter:
∆
Ds0 = 1 − Ds
Vo Ds Ds
= = 0
Vg 1 − Ds Ds
A = Ds A1 + Ds0 A2
B = Ds B1 + Ds0 B2
C = Ds C1 + Ds0 C2
D = Ds D1 + Ds0 D2
X = −A−1 BVg
Bd = (A1 − A2 ) X + (B1 − B2 ) Vg
Dd = (C1 − C2 ) X + (D1 − D2 ) Vg
x̃˙ = Ax̃ + Bṽg + Bd d˜
v˜o = C x̃ + Dṽg + Dd d˜
where the tilde ( ˜ ) indicates a small signal deviation from nominal, and:
x = X + x̃
vg = Vg + ṽg
d = Ds + d˜
vo = Vo + v˜o
© Richard Tymerski and Frank Rytkonen, 2017 301
1 1
− RC 0 0
2 C2
−D 1−Ds
0 0 s
C1 C1
A =
Ds L1 +M −Ds M
L1
− 0 0
L1 L2 −M 2 L1 L2 −M 2
M −Ds M −L2 +L2 Ds
L1 L2 −M 2 L1 L2 −M 2 0 0
0
0
B =
− L LM−M 2
1 2
L2
L1 L2 −M 2
C = 1 0 0 0
D = [0]
0
s D Vg
− R(1−D 2
s ) C1
Bd =
Vg (L1 −M )
(1−Ds )(L1 L2 −M 2 )
Vg (−M +L2 )
(1−Ds )(L1 L2 −M 2 )
Dd = [0]
The equilibrium state vector is:
Ds Vg
V2
1−Ds
Vg
V1 1−Ds
X= =
I2 Ds Vg
R(1−Ds )
I1 Ds 2 Vg
R(1−Ds )2
302 © Richard Tymerski and Frank Rytkonen, 2017
18.2.3 Component Values
Here are the uk converter circuit component values used in the remainder of
Part IV:
L1 = 0.5 mH
R1 = 0.01 Ω
L2 = 7.5 mH
R2 = 0.01 Ω
M = −1.5 mH
C1 = 2.0 µF
C2 = 20 µF
R = 30 Ω
Vg = 12 V
d = 0.667
f = 100 kHz
18.3 uk Converter Open Loop Performance
Before a controller was designed, the performance of the open-loop uk model
was examined. A state space block diagram for the open-loop model is shown
in Figure 18.2. The state space equations were determined to be:
ẋ = Ax + Bvg + Bd d (18.3)
vo = Cx
0
x = v2 v1 i2 i1
© Richard Tymerski and Frank Rytkonen, 2017 303
Figure 18.2: State space model of the uk converter.
The state space matrices for the open-loop model from the disturbance input
vg vo are the state space averaged matrices {A, B, C, D}. The state
to the output
space matrices for the open-loop system from the control input d to the output
vo are the state space averaged matrices {A, Bd , C, D}. Thus, the model of the
uk converter has two inputs (a control input d and a disturbance input vg )
and one output (vo ).
The MATLAB model open-loop response to a unit step disturbance in vg is
shown in Figure 18.3. By inspection of the plotted response, it was determined
that the system reached lightly damped oscillations around a steady state DC
value in approximately 20 ms. The steady state value was 26 V, a value predicted
from the gain equation for the uk converter:
Ds
vo = vg (18.4)
1 − Ds
With nominal duty cycle Ds = 0.667, a 1 V step input in vg produces a 2 V
step in the output voltage vo . This shows that the open-loop system does not
reject disturbances on the input voltage vg . Also, note that the output of the
circuit is a lightly damped sinusoid, with an approximate frequency of 1.83 kHz
(11.5 krad/s).
The PECS circuit is shown in Figure 18.4. The simulator was set up to check
the performance of the nonlinear converter in response to a unit step up in vg .
304 © Richard Tymerski and Frank Rytkonen, 2017
27.5
27
26.5
Amplitude (V)
26
25.5
25
24.5
24
0 0.005 0.01 0.015 0.02 0.025 0.03
Time (s)
Figure 18.3: uk converter output voltage response to a unit step disturbance
in vg .
Figure 18.4: The uk converter simulated in PECS.
The PECS plot of these transients is shown in Figure 18.5. Comparison of
the MATLAB and PECS plots reveals that the linear model used in MATLAB
is an acceptable model of the plant to use for control system design.
© Richard Tymerski and Frank Rytkonen, 2017 305
Figure 18.5: Unit step response of the uk converter in PECS.
The pole-zero plot of Tvo d is shown in Figure 18.6. All poles and zeros are in
the LHP, therefore the uk converter is a stable minimum-phase system. The
locations for the zeros and poles are:
z = −1490 ± j9000
p = −879 ± j3641, −40 ± j11500
where the zeroes and poles have units of rad/s. The 1.83 kHz ringing in the
output transient caused by the unit step disturbance is due to the frequency
associated with the dominant pole pair at −40 ± j11500 rad/s.
306 © Richard Tymerski and Frank Rytkonen, 2017
4
x 10 Pole−Zero Map
1.5
0.5
Imaginary Axis
−0.5
−1
−1.5
−1500 −1000 −500 0
Real Axis
Figure 18.6: Map of the pole and zero locations of Tvo vg .
18.4 Controllability and Stabilizability
The idea of controllability refers to the ability of the input control u to aect
the system dynamics. Controllability is de ned as the ability to move the state
of a system from an initial value x0 to any arbitrary state xf within a nite
time period t using the input signal u. (Note that controllability says nothing
about the magnitude of the input signal u, i.e., the control eort, nor the time
t required to accomplish this transition.) Essentially, it is a test to determine if
the closed-loop system poles may be arbitrarily placed in the complex plane.
The controllability matrix Mc is constructed from (A, B) in the following
manner:
A2 B An−1 B
Mc = B AB ... (18.5)
where n is the order of the system. IfMc is a full rank matrix, the system is fully
controllable. The rank de ciency of Mc tells the designer how many modes are
uncontrollable. There is no rank de ciency in Mc for the uk converter model,
therefore the system is fully controllable.
18.5 Observability and Detectability
Observability refers to the ability to determine any initial state x0 using only
a nite record of the output y between an initial time and a nal time. The
© Richard Tymerski and Frank Rytkonen, 2017 307
observability matrix Mo is constructed from (A, C) in the following manner:
C
CA
Mo =
CA2
(18.6)
.
.
.
CAn−1
where n is the order of the system. If Mo is a full rank matrix, the system is
fully observable. The rank de ciency of Mo tells the designer how many modes
are unobservable. The uk converter model is fully observable.
18.6 Controlling the uk Converter
The model used in controller design is a small-signal model, since, like many
other methods of linearization, the state-space averaging method only holds for
small deviations from the nominal operating point. Most of the equations and
gures that follow refer to deviations from the nominal operating point of the
system unless otherwise stated or identi able from context.
The control system designer must always begin with a set of design speci-
cations when starting a project. The speci cations are a set of goals for the
behavior of the controlled system, and may need to change during the design
process if not achievable or as new information becomes available. Speci ca-
tions generally consider both transient behavior (e.g., rise time, settling time,
percent overshoot) and stability margins (e.g., relative stability, gain margin,
phase margin).
18.6.1 Time Domain Speci cations
Time domain constraints are given by the system performance speci cations.
The transient response of a regulated system is typically limited in terms of
both maximum amplitude deviation from the nominal output and settling time
in response to a transient. The goal for the uk converter controller design
example is to control the output voltage to within 1% of nominal (i.e., 23.76
to 24.24 V) in response to unit step voltage disturbances in the input. This
matches the 1% regulation of standard industrial power supplies sold by a major
control system equipment manufacturer. Also, the controller should be able to
maintain the nominal output voltage within tolerances as the input varies over a
range of 9 to 14 V, though this shall be considered a steady-state, not transient,
operating requirement. As a nal speci cation, steady-state error in the output
voltage shall be eliminated within 20 milliseconds of the start of a transient.
18.6.2 Frequency Domain Speci cations
The frequency response of the transfer function Tvo d should be high at low
frequencies for proper regulation and low at high frequencies for adequate noise
308 © Richard Tymerski and Frank Rytkonen, 2017
rejection. The example system base switching frequency is 100 kHz (6.28 × 105
rad/s). As the small signal model breaks down above half of the switching
frequency, the loop gain at any frequency above 50 kHz (3.14 × 105 rad/s)
should be less than 0 dB. Indeed, there should be a design margin left between
this frequency and the gain crossover frequency. A gain margin of at least 20
dB and a phase margin of at least 50◦ will be sought to ensure stability.
18.6.3 Control Eort Constraints
The uk converter nominal duty cycle is related to the steady-state gain of the
converter G by Equation 18.4. Neglecting circuit losses, Equation 18.4 may be
rearranged to calculate the duty cycle as a function of the output operating
point and input voltages, vo and vg :
vo
Ds = (18.7)
vo + vg
Therefore, the nominal duty cycle at the operating point of 24 V for an input
of 12 V is determined to be 0.667. However, the purpose of controller design is
to ensure the output voltage remains within 1% of 24 V despite disturbances in
the input voltage. Since a deviation model is used, the dierence between the
nominal operating duty cycle and the duty cycle required to keep the output at
exactly 24 V may be approximated, and this is shown in Figure 18.7.
0.08
0.06
0.04
∆ Duty Cycle
0.02
−0.02
−0.04
9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14
Input Voltage (V)
Figure 18.7: The small-signal duty cycle required over the full input voltage
range to maintain nominal output voltage.
It is this change in duty cycle that the controller must provide, as the devi-
ation in duty cycle is the small-signal control input of the uk converter. Thus,
© Richard Tymerski and Frank Rytkonen, 2017 309
it can be predicted from Equation 18.7 or Figure 18.7 that the the controller
must change the duty cycle by -0.018 to maintain the output at 24 V for a step
disturbance input on vg from the nominal 12 V to 13 V. This value of -0.018
will be used to verify the correct steady-state control eort in controller design.
(Note that Equation 18.7 does not account for any voltage losses within the cir-
cuit, so the duty cycle will actually be slightly higher from the calculated value
when any resistances are included in the circuit.) The duty cycle is limited
to 0 ≤ Ds ≤ 1, therefore if the control eort plus the nominal value of 0.667
exceeds these limiting values, the compensator design is not acceptable. This
leads to hard limits on the small-signal control eort of [−0.667, 0.333], though
the inclusion of a design margin to these limits may be desirable. It is up to
the individual designer to choose constraints on the control eort, however it is
generally best to allow the use of as much of the control eort range as possible.
310 © Richard Tymerski and Frank Rytkonen, 2017
18.7 MATLAB Code
1 % SSA Model of Minimum−Phase Cuk Converter
2
3 % Define physical inputs
4 clear
5 close all
6
7 Vg = 12;
8 Vo = 24;
9 r = 28;
10 c1 = 2*10^−6;
11 c2 = 2*10^−5;
12 d = Vo/(Vg+Vo);
13 l1 = 5*10^−4;
14 r1 = 0.01;
15 l2 = 7.5*10^−3;
16 r2 = 0.01;
17 m = −1.5*10^−3;
18
19 % Calculate state variables for each switch position
20 s2 = l1*l2−m^2;
21 A1 = [−1/(r*c2) 0 1/c2 0;
22 0 0 −1/c1 0;
23 −l1/s2 l1/s2 −l1*r2/s2 m*r1/s2;
24 m/s2 −m/s2 m*r2/s2 −l2*r1/s2];
25 B1= [0; 0; −m/s2; l2/s2];
26 B2 = B1;
27 A2 = [−1/(r*c2) 0 1/c2 0;
28 0 0 0 1/c1;
29 −l1/s2 m/s2 −l1*r2/s2 m*r1/s2;
30 m/s2 −l2/s2 m*r2/s2 −l2*r1/s2];
31 C1 = [1 0 0 0];
32 C2 = C1;
33 D = 0;
34
35 % Calculate combined state variables given duty cycle d
36 d1 = 1−d;
37 A = d*A1+d1*A2;
38 B = d*B1+d1*B2;
39 C = d*C1+d1*C2;
40
41 % Calculate B matrix for control input − Bd
42 X = −A^−1*B*Vg;
43 Bd = (A1−A2)*X;
44
45 % Define the state space model from vg to vo
46 SYS = ss(A,B,C,D);
47
48 % Define the state space model from d to vo
49 SYSd = ss(A,Bd,C,D);
50
51 % Unit step response from disturbance input vg to vo
52 figure;
53 [y t] = step(SYS,0.03);
© Richard Tymerski and Frank Rytkonen, 2017 311
54 plot(t, Vo+y);
55 xlabel('Time (s)');
56 ylabel('Amplitude (V)');
57 grid on
58
59 % Pole−zero map from d to vo
60 figure;
61 pzmap(SYSd);
62 h = gcr;
63 h.AxesGrid.TitleStyle.FontSize = 10;
64 h.AxesGrid.XLabelStyle.FontSize = 10;
65 h.AxesGrid.YLabelStyle.FontSize = 10;
66 grid on
67
68 % Open−loop Bode Plot from d to vo
69 figure;
70 margin(SYSd);
71 h = gcr;
72 h.AxesGrid.Xunits = 'Hz';
73 h.AxesGrid.TitleStyle.FontSize = 10;
74 h.AxesGrid.XLabelStyle.FontSize = 10;
75 h.AxesGrid.YLabelStyle.FontSize = 10;
76
77 clear A1 A2 B1 B2 C1 C2% X s2 r c1 c2 l1 l2 m d1
1 % Duty Cycle vs. Vg for Cuk Converter
2
3 % Define the plant using an external file
4 cuk_parameters;
5
6 % Define the range of input voltage to sweep
7 vg = 9:0.01:14;
8
9 d_new = Vo./(vg + Vo);
10 ∆_d = d_new−d;
11
12 % Plot change in duty cycle as vg is swept to keep Vo at 24 V
13 figure;
14 plot(vg, ∆_d);
15 xlabel('Input Voltage (V)');
16 ylabel('\Delta Duty Cycle');
17 axis([9 14 −0.04 0.08]);
18 grid on
19
20 % Plot duty cycle as vg is swept to keep Vo at 24 V
21 figure;
22 plot(vg, d_new);
23 xlabel('Input Voltage (V)');
24 ylabel('Duty Cycle');
25 axis([9 14 0.62 0.74]);
26 grid on
312 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] G. C. Verghese, Dynamic modeling and control in power electronics, in
The Control Handbook, W. S. Levine, Ed. Boca Raton, FL: CRC Press
LLC, 1996, ch. 78.1, pp. 14131424.
313
314 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 19
Pole Placement
For a system that is completely controllable and where all the states are acces-
sible, feedback of all of the states through a gain matrix can be used to place
the poles at any desired location in the complex plane. The control law used
for state feedback is:
u = −Kx (19.1)
which uses the matrix K to place the poles of the system at desired locations [1].
This type of compensator is said to employ full state feedback (FSFB). A FSFB
regulator is shown in Figure 19.1.
Figure 19.1: State feedback regulation.
315
19.1 Pole Placement via Ackermann's Formula
Ackermann's formula may be used with single-input, single-output (SISO) sys-
tems like the uk converter. Ackermann's formula is:
Mc−1 (An + α1 An−1 + . . . + αn−1 A + αn I)
K= 0 0 ... 1 (19.2)
This method of determining K may be used with the system in any representa-
tion. It is this method of pole placement that is used in the designs of the state
feedback controllers that follow.
19.2 uk Converter with State Feedback Com-
pensator
One problem with pole placement is how to go about selecting desirable pole
locations. Two main methods of design are commonly followed [2]:
Select pole locations such that a dominant complex pole pair exists. This
technique is generally used when designing tracking systems, for which
the transient time domain requirements (e.g., rise time, overshoot, settling
time, etc.) are able to be recast into desired dominant pole locations.
Select pole locations that have been determined to give a prototype time-
domain response, e.g., lter pole locations.
The latter method is used in this chapter for pole placement with full state
feedback control.
Graham and Lathrop [3] discuss assigning the system poles of higher-order
systems to prototype locations that minimizes a performance index (or cost
function) known as the integral of the time-weighted absolute error (ITAE) to
an input signal:
Z ∞
JIT AE = t |e(t)| dt (19.3)
0
By placing poles in an ITAE lter pattern to minimize JIT AE , the designer
achieves a response that is optimized with respect to deviation from setpoint
(provided by the absolute error) and settling time (errors that occur later in the
time history contribute more to the JIT AE cost). Since the goal of the control
system designer is to regulate the uk converter output voltage with respect
to input voltage disturbances, JIT AE provides a scalar gure of merit by which
to judge controller performance. For regulator problems, the desired output is
rejection of disturbance deviations from the nominal operating point. The error
between the desired output and the plant output is de ned as e(t) = r(t) − y(t).
Since r(t) = 0 for all time t in a regulator problem, the error e(t) is simply −y(t).
The frequency-normalized pole locations for minimum ITAE response are
given in Table 19.1 up through order ve (so that a full-order state feedback
316 © Richard Tymerski and Frank Rytkonen, 2017
controller with an integrator may be applied to the uk converter), where ω
is a multiplier that multiplies each pole location in the array of poles listed
to convert from frequency-normalized pole locations to desired pole locations .
1
The frequency multiplier ω moves the poles outward along radii extending from
the origin of the complex plane since it multiplies each real and complex value
in a given pole by the same amount, increasing the natural frequency of each
pole. The control system designer must determine the value of ω that places
the poles in such a way as to achieve the desired time domain response. A com-
puter program (e.g., MATLAB from The Mathworks with the Control Systems
Toolbox) can be used to iteratively design and test state feedback controllers
over a range of values for the scalar multiplier frequency ω using a simple search
algorithm. where all pole values are in rad/s. By using the steady state error
Table 19.1: Frequency-Normalized Pole Locations for ITAE Response
Order Factored Pole Locations with Multiplier
1 ω[−1]
2 ω[−0.7071 ± j0.7071]
3 ω[−0.7081, −0.521 ± j1.068]
4 ω[−0.424 ± j1.263, −0.626 ± j0.4141]
5 ω[−0.8955, −0.3764 ± j1.292, −0.5758 ± j0.5339]
as a measurement metric for each iteration during the design, m can be cho-
sen that produces a steady state error within the performance speci cation of
1%. Figure 19.2 shows a plot of steady-state error vs. ω, and this gure was
used to select a value of ω that corresponded to 0.24 V (1% voltage regulation).
Initially, a wide range of frequencies was selected with a large increment, then
the range and the increment were made smaller in order to narrow in on the
rst frequency with less than 0.24 V of steady state error, which occurs at ω
= 10115. This prevents moving the poles farther into the left half of the com-
plex plane than necessary to achieve the desired performance. Moving poles
too far results in increases in control eort that may see the control eort hit
a saturation limit in actual systems, e.g., if the duty cycle were to try to go
below 0 or above 1, it could not. The unit step disturbance response of the
system with a full state feedback controller designed in this manner is shown in
Figure 19.3. Note that there is no more than 0.24 V of maximum error to the 1
V step disturbance in input voltage, indicating that the disturbance is rejected
to within the performance speci cations. The amplitude and settling time of
the transient meet design speci cations, so this controller has very desirable
time-domain response characteristics. The loop gain of the regulated system is
shown in Figure 19.4, where the loop is broken at the large X shown on the
control input d in Figure 19.5.
1 Frequency-normalization in this case refers to the fact that the minimum natural frequency
given by the pole locations for any of the nth-order set of poles listed (without the frequency
multiplier ω ) is equal to 1 rad/s
© Richard Tymerski and Frank Rytkonen, 2017 317
0.28
0.27
Maximum Absolute Error (V)
0.26
0.25
0.24
0.23
0.22
1 1.002 1.004 1.006 1.008 1.01 1.012 1.014 1.016 1.018 1.02
Frequency Multiplier ω 4
x 10
Figure 19.2: Maximum absolute error of unit step disturbance as frequency
multiplier is swept.
24.25
24.2
Amplitude (V)
24.15
24.1
24.05
24
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s) x 10
−3
Figure 19.3: Response to unit step disturbance of input voltage.
318 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm = Inf , Pm = 66.7 deg (at 3.63e+003 Hz)
60
40
Magnitude (dB)
20
−20
−40
45
0
Phase (deg)
−45
−90
−135
−180
1 2 3 4 5
10 10 10 10 10
Frequency (Hz)
Figure 19.4: Loop gain with the full state feedback controller.
Figure 19.5: The full state feedback controller applied to the uk converter.
MATLAB calculations give the gain margin as ∞ and a phase margin of
66.7◦ , which are very desirable frequency-domain response characteristics.
Finally, the control eort of the design should be examined. Once again, the
control input to the uk converter is the change in duty cycle d used to turn
© Richard Tymerski and Frank Rytkonen, 2017 319
on and o Q1. The control eort is plotted in Figure 19.6, and it can be seen
that the eort is not approaching the limits assigned to d.
0.675
0.67
0.665
Duty Cycle
0.66
0.655
0.65
0.645
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s) −3
x 10
Figure 19.6: Control eort with the full state feedback controller.
It can also be seen that the steady-state deviation control eort is approxi-
mately -0.0163, which corresponds roughly to calculations using Equation 18.7.
320 © Richard Tymerski and Frank Rytkonen, 2017
19.3 MATLAB Code
1 % Full State Feedback Compensator
2
3 % Define the plant using an external file
4 cuk_parameters;
5
6 % Define ITAE normalized pole positions
7 ITAE_4 = [−0.4240+1.2360i, −0.4240−1.2360i, ...
8 −0.6260+0.4141i, −0.6260−0.4141i];
9
10 % Sweep scaling multiplier and find first multiplier that gives ...
max abs error
11 % ≤ 0.24 V
12 w0 = [10000:1:10200];
13 w0_length = length(w0);
14 maxerr = zeros(size(w0));
15
16 wb = waitbar(0,'Sweeping ITAE Filter Scaling Multiplier...');
17
18 for index = 1:length(w0);
19 P = w0(index) * ITAE_4;
20 k = place(A,Bd,P);
21 Abar = [A−Bd*k];
22 SYS1 = ss(Abar,B,C,D);
23 [y t] = step(SYS1,0.003);
24 maxerr(index) = max(abs(y));
25 waitbar(index/w0_length, wb)
26 end
27 close(wb);
28
29 % Plot the maximum absolute error as a function of the frequency ...
multiplier
30 figure;
31 h = plot(w0,maxerr);
32 xlabel('Frequency Multiplier \omega');
33 ylabel('Maximum Absolute Error (V)');
34 grid on
35
36 % Determine vector of scaling values that results in max abs ...
error ≤ 0.24 V
37 z = find(maxerr≤0.24);
38 % Select first element in that vector to use as scaling function
39 w = w0(z(1,1));
40 sprintf('ITAE pole scaling multiplier selected, FSFB: %4.0f',w)
41
42 % Use first scaling frequency with steady state error ≤ 0.24 to ...
scale the
43 % ITAE filter pole positions
44 P = w * ITAE_4;
45 k = place(A,Bd,P);
46 Abar = [A−Bd*k];
47 SYS_FSFB = ss(Abar,B,C,D);
48
49 % Plot closed−loop system response to a unit step disturbance input
© Richard Tymerski and Frank Rytkonen, 2017 321
50 [y t x] = step(SYS_FSFB,0.002);
51 figure;
52 plot(t, Vo+y);
53 xlabel('Time (s)');
54 ylabel('Amplitude (V)');
55 grid on
56
57 % System Loop Gain Plot
58 figure;
59 margin(A, Bd, k, 0);
60 h = gcr;
61 h.AxesGrid.TitleStyle.FontSize = 10;
62 h.AxesGrid.XLabelStyle.FontSize = 10;
63 h.AxesGrid.YLabelStyle.FontSize = 10;
64
65 % Control Effort Plot
66 figure;
67 plot(t, −k*x'+d);
68 xlabel('Time (s)');
69 ylabel('Duty Cycle');
70 grid on
322 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] R. T. Stefani, B. Shahian, C. J. Savant, Jr., and G. H. Hostetter, Design
of Feedback Control Systems, 4th ed. New York, NY: Oxford University
Press, 2002.
[2] G. F. Franklin, J. D. Powell, and A. Emami-Naeini, Feedback Control of
Dynamic Systems, 3rd ed. Boston, MA: Addison-Wesley, 1993.
[3] D. Graham and R. C. Lathrop, The synthesis of optimum transient re-
sponse: Criteria and standard forms, Trans. AIEE, vol. 72, pp. 273288,
Nov. 1953.
323
324 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 20
Integral Action
The previous state feedback design for the uk converter resulted in a maximum
error of 0.24 V of due to the 1 V disturbance in input voltage, which is just within
design speci cations. The steady state error was 0.22 V. Additional gain could
reduce this error, though it could never be eliminated, as the uk converter is
a type 0 system, which means that there will always be some nite steady-state
error to a unit step disturbance or setpoint change, even in a controlled system,
no matter how high the gain. However, it is desirable to eliminate steady-state
error to the unit step entirely if possible. The only way to do this is to have
1
the controller raise the type number . Full state feedback does not introduce
an integrator into the closed loop, therefore does not change the type number.
20.1 Adding Integrators
In order to eliminate any steady-state oset that may occur, an integrating
controller may be added to the controlled system. Integral control is a method
of output feedback, as shown in Figure 20.1.
1 The concept of type number goes hand-in-hand with the internal model principle, which
states that a loop must contain a transfer function that has a model of the signal it is trying
to reject. For example, if trying to reject a unit step 1
s
, at least one transfer function in the
loop must contain 1
s
.
325
Figure 20.1: Generic system controlled with a FSFB regulator and output inte-
gral feedback.
The integrating controller integrates the error between any reference signal
and the output e(t) = r(t) − y(t) and adds it to the state feedback control
R eort
to eliminate steady-state error. The equation for the integrator is xi = edt, or
ẋi = e. Since each row in the state space representation is a rst-order linear
dierential equation, and the integrator adds one new dierential equation to
the system ẋi = −y = −Cx, one new state xi must be added to the state vector
to raise the uk system from type 0 to type 1. The augmented state vector is
[x xi ]0 and the new state space quadruple is:
" #
A 0
A = (20.1)
−C 0
0
B = B 0
C = C 0
D = 0
The control law for this augmented system is u = −kx − ki xi . From the
above modi cations, the desired poles (with an added desired closed-loop pole
location to account for the pole associated with the integrator) can be used to
determine the state feedback gain, which has the structure K = [k ki ].
326 © Richard Tymerski and Frank Rytkonen, 2017
20.2 uk Converter with State Feedback and In-
tegral Compensator
The augmented controlled system of the uk converter is shown in Figure 20.2.
This control method is described as full state feedback with an integrator
(FSFBI).
Figure 20.2: System controlled with a FSFBI regulator.
The state quadruple for the system augmented with the new state and con-
trolled with the new control law may be derived from the block diagram.
ẋ = (A − Bd k)x − Bd ki xi + Bvg (20.2)
vo = Cx
along with the augmented closed-loop state space matrices
A − Bd k −Bd ki
Ā = (20.3)
−C 0
0
B̄ = B 0
C̄ = C 0
D̄ = [D]
The controlled system then becomes:
ẋ = Āx + B̄vg (20.4)
vo = C̄x
© Richard Tymerski and Frank Rytkonen, 2017 327
A frequency-sweep search technique similar to that used for the FSFB con-
troller was used to determine the pole placement for the system augmented
with an integrator, and the results are shown in Figure 20.3. The frequency
multiplier was swept and the rst frequency multiplier value with a maximum
absolute error determined to occur at ω = 7536.
0.248
0.246
0.244
Maximum Absolute Error (V)
0.242
0.24
0.238
0.236
0.234
0.232
0.23
0.228
7500 7510 7520 7530 7540 7550 7560 7570 7580 7590 7600
Frequency Multiplier ω
Figure 20.3: ITAE pole frequency multiplier determination.
The step disturbance transient is shown in Figure 20.4.
24.3
24.25
24.2
Amplitude (V)
24.15
24.1
24.05
24
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s) −3
x 10
Figure 20.4: Unit step disturbance response of system with FSFBI controller.
328 © Richard Tymerski and Frank Rytkonen, 2017
The loop gain of the controlled system may be seen in Figure 20.5, where
the loop is broken at the large X shown on the control input d in Figure 20.2.
MATLAB calculations give the gain margin as ∞ and a phase margin of 77.5◦ .
Bode Diagram
Gm = Inf , Pm = 75.5 deg (at 3.56e+003 Hz)
60
40
Magnitude (dB)
20
−20
−40
45
0
Phase (deg)
−45
−90
−135
1 2 3 4 5
10 10 10 10 10
Frequency (Hz)
Figure 20.5: Loop gain of uk converter controlled by FSFBI.
Figure 20.6 shows the change in duty cycle eected by the FSFBI controller
to control the uk converter. Note that the nal value of the control eort
is -0.018. This is the approximate change in duty cycle that is necessary to
completely reject the unit step disturbance in vg as shown in Figure 18.7.
© Richard Tymerski and Frank Rytkonen, 2017 329
0.675
0.67
0.665
Duty Cycle
0.66
0.655
0.65
0.645
0.64
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s) −3
x 10
Figure 20.6: Control eort of FSFBI compensator.
From this point forward in this paper, all of the example compensator de-
signs will include an integrator term to completely reject the eects of the step
disturbance in vg , and though sometimes not explicitly stated in the compen-
sator name, terms related to the integrator will appear in the state equations
as well as the block diagrams relating to control of the uk converter.
330 © Richard Tymerski and Frank Rytkonen, 2017
20.3 MATLAB Code
1 % Full State Feedback Compensator with Integration
2
3 % Define the plant using an external file
4 cuk_parameters;
5
6 % Define ITAE normalized pole positions
7 ITAE_5 = [−0.8955, −0.3764+1.2920i, −0.3764−1.2920i,...
8 −0.5758+0.5339i, −0.5758−0.5339i];
9
10 % Sweep scaling multiplier and find first multiplier that gives ...
max error
11 % ≤ 0.24 V
12 w0 = [7500:1:7600];
13 w0_length = length(w0);
14 maxerr = zeros(size(w0));
15
16 wb = waitbar(0,'Sweeping ITAE Filter Scaling Multiplier...');
17
18 for index = 1:length(w0);
19 P = w0(index) * ITAE_5;
20 A_prime = [A zeros(size(B));C zeros(size(D))];
21 Bd_prime = [Bd; 0];
22 K = place(A_prime,Bd_prime,P);
23 k = K(1:4);
24 ki = K(end);
25 Abar = [A−Bd*k, −Bd*ki; C, 0];
26 Bbar = [B; 0];
27 Cbar = [C 0];
28 SYS1 = ss(Abar,Bbar,Cbar,D);
29 [y t] = step(SYS1,0.005);
30 maxerr(index) = max(abs(y));
31 waitbar(index/w0_length, wb)
32 end
33
34 close(wb);
35
36 % Plot the maximum absolute error as a function of the frequency ...
multiplier
37 figure;
38 h = plot(w0,maxerr);
39 xlabel('Frequency Multiplier \omega');
40 ylabel('Maximum Absolute Error (V)');
41 grid on
42
43 % Determine vector of scaling values that results in max error ≤ ...
0.24 V
44 z = find(maxerr≤0.24);
45 % Select first element in that vector to use as scaling multiplier
46 w = w0(z(1,1));
47 sprintf('ITAE pole scaling multiplier selected, FSFBI: %4.0f',w)
48
49 % Scale the ITAE filter pole positions
50 P = w * ITAE_5;
© Richard Tymerski and Frank Rytkonen, 2017 331
51 A_prime = [A zeros(size(B));−C zeros(size(D))];
52 Bd_prime = [Bd; 0];
53 K = place(A_prime,Bd_prime,P);
54 k = K(1:4);
55 ki = K(end);
56
57 Abar = [A−Bd*k, −Bd*ki; −C, 0];
58 Bbar = [B; 0];
59 Cbar = [C 0];
60 SYS_FSFBI = ss(Abar,Bbar,Cbar,D);
61
62 % Plot closed−loop system response to a unit step disturbance input
63 [y t x] = step(SYS_FSFBI,0.002);
64 figure;
65 plot(t, Vo+y);
66 xlabel('Time (s)');
67 ylabel('Amplitude (V)');
68 grid on
69
70 % System Loop Gain Plot
71 figure;
72 margin(A_prime, Bd_prime, K, 0);
73 h = gcr;
74 h.AxesGrid.TitleStyle.FontSize = 10;
75 h.AxesGrid.XLabelStyle.FontSize = 10;
76 h.AxesGrid.YLabelStyle.FontSize = 10;
77
78 % Control Effort Plot
79 figure;
80 plot(t, −K*x'+d);
81 xlabel('Time (s)');
82 ylabel('Duty Cycle');
83 grid on
332 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 21
State Estimation
Since an n -th order system requires n states be fed back to the gain matrix K
to allow pole placement anywhere in the complex plane, this requires at least
n measurements of the state variables. This can be prohibitively expensive or
complex. In some cases, the internal system states may not even be measurable.
In general, only the input and output of a system are available to the control
system designer. However, if the system is fully observable, a state estimator
(also known as an observer) may be used to provide estimated state values for
use in feedback control. The use of an observer requires that the state estimates
converge to the actual state values (if starting from dierent initial states) more
rapidly than the system itself responds. The control law used is then:
u = −K x̂ (21.1)
where x̂ indicates that the states fed back into the system are estimates.
In order to quickly force the state estimate to converge to the actual values
of the state from arbitrary initial conditions, a correction term must be applied
to the estimator dynamics such that the error dynamics approach zero rapidly.
21.1 Full-Order State Estimators
A state estimator may be constructed from the same system state space model
used for control law gain determination as long as the system is fully observable.
The output of the estimator C x̂ can be compared to the output of the system,
and any dierence between them may be multiplied by a gain vector and fed
back to the state estimator dynamics. Therefore:
e = y − C x̂ (21.2)
= C(x − x̂)
333
Multiplying this error by a gain vector L, the desired state error correction term
is formed, which can then be added to the dynamics of the estimator to form:
x̂˙ = Ax̂ + Bu − LC(x − x̂) (21.3)
= (A − LC)x̂ + Bu + LCx
When L is chosen such that the eigenvalues of A − LC lie in the left half of the
complex plane, the estimator error e→0 as t → ∞. Since the state estimate
must converge to the controlled state faster than the state itself can change, the
eigenvalues of A − LC should be placed farther to the left than the eigenvalues
of A − BK . A good rule of thumb is to make the estimator dynamics at least
twice as fast as the controlled system dynamics.
To form an output feedback compensator based on an estimator, the sepa-
ration principle of controller design holds, which states that the controller gain
K and the observer gain L can be found independently. The proof of this is in
many other references (e.g., [1]), so it shall not be repeated here, but application
shall be made of the principle in the design examples to follow.
When paired with the linear state feedback control law, the estimator-based
compensator is formed. For the case of state feedback without an integral state
added, the compensator is given by:
x̂˙ = (A − BK − LC)x̂ + Ly (21.4)
u = −K x̂
Where the state of the system has been augmented by an integrator state, the
compensator is given by:
x̂˙
A − Bk − LC −Bki x̂ L
= + y (21.5)
ẋi 0 0 xi −1
x̂
u = −k −ki
xi
21.2 Full-Order Estimator-Based Compensator
The block diagram for the uk converter controlled with a full-order state esti-
mator with linear control law and integral action is shown in Figure 21.1, and
was used to derive the following closed-loop state equations:
ẋ = Ax − Bd kx̂ − Bd ki xi + Bvg (21.6)
ẋi = −Cx
x̂˙ = LCx − Bd ki xi + (A − Bd k − LC) x̂
vo = Cx
334 © Richard Tymerski and Frank Rytkonen, 2017
and the associated state space matrices:
A −Bd ki −Bd k
Ā = −C 0 0 (21.7)
LC −Bd ki A − Bd k − LC
0
B̄ = B 0 0
C̄ = C 0 0
D̄ = [D]
Figure 21.1: An estimated state feedback compensator with integral action.
The step disturbance transient is shown in Figure 21.2. There is more os-
cillatory behavior in the initial part of the transient response compared to the
response under FSFBI control. This is likely caused by the initial estimation of
states and their convergence to the actual state values. Comparison of the set-
tling times shows that they are approximately the same, and the only transient
dierences occur early in the transient.
© Richard Tymerski and Frank Rytkonen, 2017 335
24.15
24.1
24.05
24
Amplitude (V)
23.95
23.9
23.85
23.8
23.75
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s) −3
x 10
Figure 21.2: Unit step disturbance response of uk converter with ESFBI com-
pensator.
The loop gain of the controlled system may be seen in Figure 21.3, where
the loop is broken at the large X shown on the control input d in Figure 21.1.
MATLAB calculations give the gain margin as 5.97 dB and a phase margin
of 26.3◦ . These are signi cantly lower than the stability margins of previous
controllers designed, and these clearly do not meet the design speci cations.
336 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm = 5.97 dB (at 7.81e+003 Hz) , Pm = 26.3 deg (at 4.6e+003 Hz)
50
Magnitude (dB)
−50
−100
−150
0
Phase (deg)
−90
−180
−270
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (Hz)
Figure 21.3: Loop gain of uk converter controlled by ESFBI compensator.
Figure 21.4 shows the control eort of the ESFBI controller.
0.675
0.67
0.665
0.66
Duty Cycle
0.655
0.65
0.645
0.64
0.635
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s) −3
x 10
Figure 21.4: Control eort of ESFBI compensator.
Since the uk converter has four states, the observer itself will be a fourth-
order system. Along with the integral state, the compensator becomes a fth-
order system. When evaluating desired observer pole locations, keep in mind
© Richard Tymerski and Frank Rytkonen, 2017 337
that the poles of the observer must be placed to the left of the poles of the com-
pensated plant by a large margin to ensure that the state estimator dynamics
are faster than those of the plant. Similarly to the use of fth-order ITAE pole
locations for the plant under state feedback, fourth-order ITAE pole locations
may be used to place the poles of the observer. However, examination of the
frequency-normalized fth-order and fourth-order ITAE pole locations from Ta-
ble 19.1 shows that the fth-order poles have a minimum pole frequency greater
than the maximum pole frequency of the fourth-order poles. Thus, if the de-
signer intends to place the all of the fourth-order ITAE observer poles to the
left of the fth-order ITAE pole locations selected using ω by at least a factor
of n, the designer must scale the fourth-order pole locations such that the low-
est pole frequency of the fourth-order system must be rst moved out to the
largest pole frequency of the fth-order system. This can be done by multiply-
ing the fourth-order frequency-normalized poles by the ratio of the maximum
pole frequency of the fth-order poles to the minimum pole frequency of the
fourth-order poles. The resulting fourth-order pole locations can then each be
multiplied by n to move them radially by a factor of n farther into the left half
of the complex plane than the fth-order normalized pole locations, then they
can be multiplied by the value of ω used to select the desired fth-order pole
locations. Thus, the desired fourth-order pole locations have been deteremined.
21.3 Reduced-Order State Estimators
If some of the states appear directly in the output as a function of the measure-
ment equation (i.e., are not a linear combination of other states), those states do
not need to be estimated. Hence, a reduced-order estimator may be constructed
that only estimates the unmeasured states.
If C is a full rank matrix, a nonsingular linear transformation matrix can be
formed by choosing a matrix T of dimension (n − r) x n and forming:
C
P = (21.8)
T
The matrix T may be any arbitrary matrix that produces a nonsingular P
matrix, as P must be invertible.
Applying the standard linear transformation x = P x with Equation (21.8)
puts the system into an equivalent representation where C is of the form:
Ir 0 (21.9)
(I is a square identity matrix with dimension r x r, r < n). It can be assumed
that this representation exists without loss of generality since it is the result of
a linear transformation.
The system and feedback gain matrix can now be partitioned into measured
338 © Richard Tymerski and Frank Rytkonen, 2017
and unmeasured portions:
ẋm A11 A12 xm B1
= + u (21.10)
ẋu A21 A22 xu B2
y = xm
K = [km ku ]
Since xm corresponds to the states that appear in the output of the measurement
equation, xu represents the remaining unmeasured states. As xm is present in
the output, these states do not require estimation. This means that a reduced-
order state estimator can be constructed that allows the estimation of xu in
such a manner that all states (either measured or estimated) are available for
feedback via a linear control law:
u = −km xm − ku x̂u (21.11)
In order to ensure that the reduced-order observer dynamics converge to the
true state values of x, the error dynamics must converge to zero. A full-order
observer uses a correction term to perform this, which is a gain matrix that
multiplies the error between plant output and observer output. Unfortunately,
since only the xm states appear in the plant output, using the plant output
contributes no information about the unmeasured states to the estimator and
therefore has no dynamic eect on the estimate x̂u . However, a variable change
can be performed:
x̂u = Ly + z (21.12)
where z is the output of a system of order r < n:
ż = Ez + F y + Gu (21.13)
with E, F , and G and the observer gain L yet to be determined.
Since observer design is concerned with elimination of the error between the
actual state and its estimate, the estimation error can be de ned as eu = xu − x̂u
and the error dynamics will converge to zero if x̂u → xu .
Using the partitioned format of xu from Equation 21.10 along with x̂u de-
termined from the block diagram in Figure 21.5, it can be shown that:
x̂˙ u = L(A11 xm + A12 xu + B1 u) + E(x̂u − Lxm ) + F xm + Gu (21.14)
ẋu = A21 xm + A22 xu + B2 u
© Richard Tymerski and Frank Rytkonen, 2017 339
Figure 21.5: Reduced-order estimator construction.
Adding zero to the right side of x̂˙ u in the form of Exu − Exu :
x̂˙ u = (LA11 − EL + F )xm + (LA12 + E)xu . . . (21.15)
+(LB1 + G)u + E(xu − x̂u )
This gives the following equation for the estimator error dynamics when substi-
tuted into the time derivative of the unmeasured error ėu = ẋu − x̂˙ u :
ėu = (A21 − LA11 + EL − F )xm + (A22 − LA12 − E)xu . . . (21.16)
+(B2 − LB1 − G)u + Eeu
In order for the estimator error dynamics to be independent of the state x,
plant output y, and the input u, the rst three terms on the right side of
Equation 21.16 must be zero. This is accomplished by selecting:
E = A22 − LA12 (21.17)
F = A21 − LA11 + EL
G = B2 − LB1
This leaves ėu = Eeu , which converges to zero when E is an asymptotically
stable matrix. Thus, the error dynamics die out, leaving an estimate that equals
the state. This means that L must be selected such that A22 − LA12 → 0 as
t → ∞, i.e., the poles of E must lie in the left half of the complex plant. As
with the full-order observer, the reduced-order observer poles should be placed
such that the estimator dynamics are much more rapid than the controlled plant
dynamics.
340 © Richard Tymerski and Frank Rytkonen, 2017
When paired with the properly-partitioned linear state feedback control law,
the reduced-order estimator-based compensator is formed. For the case of state
feedback without an integral state added, the reduced-order compensator is
given by:
ż = (E − Gku )z + (F − Gku L − Gkm )y (21.18)
u = −ku z + (−ku L − km )y
Where the state of the system has been augmented by an integrator state, the
reduced-order compensator is given by:
ż E − Gku −Gki z F − Gku L − Gkm
= + y (21.19)
ẋi 0 0 xi −1
z
u = −ku −ki + (−ku L − km )y
xi
21.4 Reduced-Order Estimator-Based Compen-
sator
For the uk converter model, matrix C is of the form C = I 0 therefore v2
is a measured state, and the unmeasured states are v1 , i2 , and i1 . This means
that a reduced order observer may be designed that estimates only the three
unmeasured states. The block model for a system controlled by a compensator
made of a reduced-order estimator and a linear state feedback law is shown in
Figure 21.6, and was used to derive the following state equations:
ẋ = (A − Bd ku LC − Bd km C) x − Bd ki xi − Bd ku z + Bvg (21.20)
ẋi = −Cx
ż = (F C − Gkm C − Gku LC) x − Gki xi + (D − Gku ) z
vo = Cx
from which were determined the matrices:
A − Bd km C − Bd ku LC −Bd ki −Bd ku
Ā = −C 0 0 (21.21)
F C − Gkm C − Gku LC −Gki E − Gku
0
B̄ = B 0 0
C̄ = C 0 0
D̄ = [D]
where
E = A22 − LA12 (21.22)
F = EL + A21 − LA11
G = Bd2 − LBd1
© Richard Tymerski and Frank Rytkonen, 2017 341
Figure 21.6: A state feedback regulator with integral action based on a reduced-
order estimator.
To determine estimator pole placement, the same type of iterative algorithm
used for the full-order observer was implemented. The reduced-order observer
poles were placed to have faster dynamics than the poles of the controlled sys-
tem.
The step disturbance transient is shown in Figure 21.7.
342 © Richard Tymerski and Frank Rytkonen, 2017
24.2
24.15
24.1
24.05
Amplitude (V)
24
23.95
23.9
23.85
23.8
0 0.5 1 1.5 2 2.5 3
Time (s) x 10
−3
Figure 21.7: Unit step disturbance response of uk converter with ROESFBI
compensator.
The loop gain of the controlled system may be seen in Figure 21.8, where
the loop is broken at the large X shown on the control input d in Figure 21.6.
MATLAB calculations give the gain margin as −24.9 dB and a phase margin of
36.5◦ . These clearly do not meet the design speci cations, and uncertainty in
the system model may make the controlled system unstable.
© Richard Tymerski and Frank Rytkonen, 2017 343
Bode Diagram
Gm = −24.9 dB (at 311 Hz) , Pm = 33.3 deg (at 4.14e+003 Hz)
60
40
Magnitude (dB) 20
−20
−40
−60
0
Phase (deg)
−90
−180
−270
1 2 3 4 5
10 10 10 10 10
Frequency (Hz)
Figure 21.8: Loop gain of uk converter controlled by ROESFBI compensator.
344 © Richard Tymerski and Frank Rytkonen, 2017
21.5 MATLAB Code
1 % Estimated State Feedback Compensator with Integration
2
3 % Define the plant using an external file
4 cuk_parameters;
5
6 % Define ITAE normalized pole positions
7 ITAE_5 = [−0.8955, −0.3764+1.2920i, −0.3764−1.2920i,...
8 −0.5758+0.5339i, −0.5758−0.5339i];
9 ITAE_4 = [−0.4240+1.2360i, −0.4240−1.2360i, ...
10 −0.6260+0.4141i, −0.6260−0.4141i];
11
12 % Find the ratio of the maximum natural frequency of a normalized
13 % fifth−order ITAE filter to the minimum natural frequency of a
14 % normalized fourth−order ITAE filter.
15
16 ra54 = max(abs(ITAE_5))/min(abs(ITAE_4));
17
18 % Define the desired ratio of the minimum natural frequency of the
19 % estimator poles to the maximum natural frequency of the ...
controller poles
20 rra = 3;
21
22 % Sweep scaling multiplier and find first multiplier that gives ...
max error
23 % ≤ 0.24 V
24 w0 = [5400:1:5600];
25 w0_length = length(w0);
26 err_ITAE = zeros(size(w0));
27
28 wb = waitbar(0,'Sweeping ITAE Filter Scaling Multiplier...');
29 for index = 1:length(w0);
30 % Sweep frequency to scale the ITAE filter pole positions for
31 % the controller
32 Pk = w0(index) * ITAE_5;
33
34 % Set the minimum natural frequency of the ITAE filter pole ...
positions
35 % for the estimator to a multiple of the maximum natural ...
frequency of
36 % the controller poles to make the estimator converge faster ...
than the
37 % controller responds
38
39 Pl = rra * ra54 * w0(index) * ITAE_4;
40 A_prime = [A zeros(size(B));−C zeros(size(D))];
41 Bd_prime = [Bd; 0];
42 C_prime = [C 0];
43 K = place(A_prime,Bd_prime,Pk);
44 k = K(1:4);
45 ki = K(end);
46 L = place(A', C', Pl)';
47 Abar = [A, −Bd*ki, −Bd*k;
48 −C, 0, zeros(1,length(A));
© Richard Tymerski and Frank Rytkonen, 2017 345
49 L*C, −Bd*ki, A−Bd*k−L*C];
50 Bbar = [B; 0; zeros(4,1)];
51 Cbar = [C 0 zeros(size(C))];
52 SYS_ESFBI = ss(Abar,Bbar,Cbar,D);
53 [y t] = step(SYS_ESFBI,0.003);
54 maxerr(index) = max(abs(y));
55 waitbar(index/w0_length, wb)
56 end
57 close(wb);
58
59 % Plot the maximum absolute error as a function of the frequency ...
multiplier
60 figure;
61 plot(w0,maxerr);
62 axis tight
63 xlabel('Scalar Multiplier \omega');
64 ylabel('Maximum Error (V)');
65 grid on
66
67 % Determine vector of scaling values that results in max error ≤ ...
0.24 V
68 z = find(maxerr≤0.24);
69 % Select first element in that vector to use as scaling multiplier
70 w = w0(z(1,1));
71 sprintf('ITAE pole scaling multiplier selected, ESFBI: %4.0f',w)
72
73 % Use frequency of minimum ITAE to scale the ITAE filter pole ...
positions for
74 % the controller
75 Pk = w * ITAE_5;
76
77 % Set the minimum natural frequency of the ITAE filter pole ...
positions for
78 % the estimator to a multiplier of the maximum natural frequency ...
of the
79 % controller poles to make the estimator converge faster than the
80 % controller responds
81
82 Pl = rra * ra54 * w * ITAE_4;
83 A_prime = [A zeros(size(B));−C zeros(size(D))];
84 Bd_prime = [Bd; 0];
85 C_prime = [C 0];
86 K = place(A_prime,Bd_prime,Pk);
87 k = K(1:4);
88 ki = K(end);
89 L = place(A', C', Pl)';
90 Abar = [A, −Bd*ki, −Bd*k;
91 −C, 0, zeros(1,length(A));
92 L*C, −Bd*ki, A−Bd*k−L*C];
93 Bbar = [B; 0; zeros(4,1)];
94 Cbar = [C 0 zeros(size(C))];
95 SYS_ESFBI = ss(Abar,Bbar,Cbar,D);
96
97 % Plot controller poles and observer poles
98 figure;
99 plot(Pk,'bx')
100 hold on
346 © Richard Tymerski and Frank Rytkonen, 2017
101 plot(Pl,'r+')
102 hold off
103 legend('Controller poles','Observer poles')
104 xlabel('Real')
105 ylabel('Imaginary')
106 grid on
107
108 % Plot closed−loop system response to a unit step disturbance input
109 [y t x] = step(SYS_ESFBI,0.002);
110 figure;
111 h = plot(t, Vo+y);
112 xlabel('Time (s)');
113 ylabel('Amplitude (V)');
114 grid on
115
116 figure;
117 plot(t, x);
118 xlabel('Time (s)');
119 ylabel('States');
120 grid on
121 legend('v_2','v_1','i_2','i_1','x_i','v_{2e}','v_{1e}', ...
122 'i_{2e}','i_{1e}','Location','SouthEast');
123
124 % System Loop Gain Plot
125 A1 = [A, zeros(4,1), zeros(4,4);
126 −C, 0, zeros(1,4);
127 L*C, −Bd*ki, A−Bd*k−L*C];
128 Bd1 = [Bd;0;zeros(4,1)];
129 C1 = [zeros(1,4), ki, k];
130 D1 = 0;
131 sys1 = ss(A1,Bd1,C1,D1);
132 figure(5);
133 margin(sys1)
134 h = gcr;
135 h.AxesGrid.Xunits = 'Hz';
136 h.AxesGrid.TitleStyle.FontSize = 10;
137 h.AxesGrid.XLabelStyle.FontSize = 10;
138 h.AxesGrid.YLabelStyle.FontSize = 10;
139
140 % Control Effort Plot
141 figure;
142 h = plot(t, −[zeros(1,4), ki, k]*x'+d);
143 xlabel('Time (s)');
144 ylabel('Duty Cycle');
145 grid on
1 % Reduced−Order Estimated State Feedback Compensator with ...
Integration
2
3 % Define the system using an external file
4 cuk_parameters;
5
6 % Partition the matrices for reduced−order estimator design
7 A11 = A(1,1);
8 A12 = A(1,2:4);
9 A21 = A(2:4,1);
© Richard Tymerski and Frank Rytkonen, 2017 347
10 A22 = A(2:4,2:4);
11
12 B1 = B(1);
13 B2 = B(2:4);
14
15 Bd1 = Bd(1);
16 Bd2 = Bd(2:4);
17
18 % Define ITAE normalized pole positions
19 ITAE_5 = [−0.8955, −0.3764+1.2920i, −0.3764−1.2920i,...
20 −0.5758+0.5339i, −0.5758−0.5339i];
21 ITAE_3 = [−0.7081, −0.5210+1.068i, −0.5210−1.068i];
22
23 % Find the ratio of the maximum natural frequency of a normalized
24 % fifth−order ITAE filter to the minimum natural frequency of a
25 % normalized third−order ITAE filter.
26
27 ra53 = max(abs(ITAE_5))/min(abs(ITAE_3));
28
29 % Define the desired ratio of the minimum natural frequency of the
30 % estimator poles to the maximum natural frequency of the ...
controller poles
31 rra = 2;
32
33 % Sweep scaling multiplier and find first multiplier that gives ...
max error
34 % ≤ 0.24 V
35 w0 = [5700:1:5900];
36 w0_length = length(w0);
37 maxerr = zeros(size(w0));
38
39 wb = waitbar(0,'Sweeping ITAE Filter Scaling Multiplier...');
40
41 for index = 1:length(w0);
42 % Scale the controller pole positions using a search
43 Pk = w0(index) * ITAE_5;
44
45 % Set the minimum natural frequency of the ITAE filter pole ...
positions
46 % for the estimator to a multiple of the maximum natural ...
frequency of
47 % the controller poles to make the estimator converge faster ...
than the
48 % controller responds
49
50 Pl = rra * ra53 * w0(index) * ITAE_3;
51 A_prime = [A zeros(size(B));−C zeros(size(D))];
52 Bd_prime = [Bd; 0];
53 C_prime = [C 0];
54 K = place(A_prime,Bd_prime,Pk);
55 km = K(1);
56 ku = K(2:4);
57 ki = K(end);
58 L = place(A22', A12', Pl)';
59
60 E = A22 − L*A12;
61 F = E*L + A21 − L*A11;
348 © Richard Tymerski and Frank Rytkonen, 2017
62 G = Bd2 − L*Bd1;
63
64 Abar = [A−Bd*km*C−Bd*ku*L*C, −Bd*ki, −Bd*ku;
65 −C, zeros(1,4) ;
66 F*C−G*km*C−G*ku*L*C, −G*ki, E−G*ku];
67 Bbar = [B; 0; zeros(3,1)];
68 Cbar = [C 0 zeros(1,3)];
69 SYS1 = ss(Abar,Bbar,Cbar,D);
70 [y t] = step(SYS1,0.003);
71 maxerr(index) = max(abs(y));
72 waitbar(index/w0_length, wb)
73 end
74 close(wb);
75
76 % Plot the maximum absolute error as a function of the frequency ...
multiplier
77 figure;
78 plot(w0,maxerr);
79 axis tight
80 xlabel('Scalar Multiplier \omega');
81 ylabel('Maximum Error (V)');
82 grid on
83
84 % Determine vector of scaling values that results in max error ≤ ...
0.24 V
85 z = find(maxerr≤0.24);
86 % Select first element in that vector to use as scaling multiplier
87 w = w0(z(1,1));
88 sprintf('ITAE pole scaling multiplier selected, ESFBI: %4.0f',w)
89
90 % Determine controller and observer gains
91 Pk = w * ITAE_5;
92
93 % Set the minimum natural frequency of the ITAE filter pole ...
positions for
94 % the estimator to a multiplier of the maximum natural frequency ...
of the
95 % controller poles to make the estimator converge faster than the
96 % controller responds
97
98 Pl = rra * ra53 * w * ITAE_3;
99 A_prime = [A zeros(size(B));−C zeros(size(D))];
100 Bd_prime = [Bd; 0];
101 C_prime = [C 0];
102 K = place(A_prime,Bd_prime,Pk);
103 km = K(1);
104 ku = K(2:4);
105 ki = K(end);
106 L = place(A22', A12', Pl)';
107
108 E = A22 − L*A12;
109 F = E*L + A21 − L*A11;
110 G = Bd2 − L*Bd1;
111
112 Abar = [A−Bd*km*C−Bd*ku*L*C, −Bd*ki, −Bd*ku;
113 −C, zeros(1,4) ;
114 F*C−G*km*C−G*ku*L*C, −G*ki, E−G*ku];
© Richard Tymerski and Frank Rytkonen, 2017 349
115 Bbar = [B; 0; zeros(3,1)];
116 Cbar = [C 0 zeros(1,3)];
117 SYS_ROESFBI = ss(Abar,Bbar,Cbar,D);
118
119 % Plot controller and observer pole locations
120 figure;
121 plot(Pk,'bx')
122 hold on
123 plot(Pl,'r+')
124 hold off
125 legend('Controller poles','Observer poles')
126 xlabel('Real')
127 ylabel('Imaginary')
128
129 % Plot closed−loop system response to a unit step input
130 [y t x] = step(SYS_ROESFBI,0.003);
131 figure;
132 plot(t, Vo+y);
133 xlabel('Time (s)');
134 ylabel('Amplitude (V)');
135 grid on
136
137 % System Loop Gain Plot
138 A1 = [A, zeros(4,1), zeros(4,3);
139 −C, 0, zeros(1,3);
140 F*C−G*ku*L*C−G*km*C, −G*ki, E−G*ku];
141 Bd1 = [Bd; 0; zeros(3,1)];
142 C1 = [km*C+ku*L*C, ki, ku];
143 D = 0;
144 sys1 = ss(A1, Bd1, C1, D);
145 figure;
146 margin(sys1);
147 h = gcr;
148 h.AxesGrid.TitleStyle.FontSize = 10;
149 h.AxesGrid.XLabelStyle.FontSize = 10;
150 h.AxesGrid.YLabelStyle.FontSize = 10;
151
152 % Control Effort Plot
153 figure;
154 h = plot(t, −[km, zeros(1,3), ki, ku]*x'+d);
155 xlabel('Time (s)');
156 ylabel('Duty Cycle');
157 grid on
350 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] R. T. Stefani, B. Shahian, C. J. Savant, Jr., and G. H. Hostetter, Design
of Feedback Control Systems, 4th ed. New York, NY: Oxford University
Press, 2002.
351
352 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 22
Linear Quadratic Optimal
Control
Linear quadratic optimal control uses penalties on state transients x and control
eort u to optimize system performance with respect to a gure of merit deter-
mined by a cost function. There is typically a classical trade-o designed into
the cost function: one cannot have tight control over state transients with small
control eort. In other words, small output transients require large controller
gains (and therefore control eort). Additionally, quadratic forms are used to
ensure that only the magnitude and not the sign of the transient contributes to
the cost determined by the penalty function.
22.1 Linear Quadratic Regulators
To optimally control state transients and control eort within performance spec-
i cations, a compensator is sought that seeks to provide a control eort u that
minimizes a Lagrangian cost function:
Z ∞
J= (xT Qx + uT Ru)dt (22.1)
0
subject to the constraint of the state equation:
ẋ = Ax + Bu (22.2)
This is known as the linear quadratic regulator (LQR) problem. The weight
matrix Q is an n×n positive semide nite matrix (for a system with n states) that
penalizes variation of the state from the desired state. The weight matrix R is
an m × m positive de nite matrix that penalizes control eort. Solutions for the
constrained optimal system can be found in [1], [2], and [3]. The well-published
time invariant solution to this problem is:
K = R−1 B T P (22.3)
353
where P is the unique, symmetric, positive de nite solution to the steady-state
algebraic Riccati equation (ARE):
P A + AT P − P BR−1 B T P + Q = 0 (22.4)
The minimum value of the cost function is based on the initial state x0 , and is
given by:
Jmin = xT0 P x0 (22.5)
The LQR designed for a SISO system can be shown to possess very desirable
stability properties: it always has a gain margin between {-6 dB, ∞} and a phase
◦
margin of at least 60 . However, it has a high frequency roll-o rate of only 20
dB per decade so the open loop frequency response shows susceptibility to high
frequency noise.
Since the weight matrices Q and R are both included in the summation term
within the cost function, it is really the relative size of the weights within each
quadratic form which are important. Simple inspection of the cost function
shows that multiplying both weight matrices by the same real constant (e.g., κ)
will not aect their ratio. The multiplier κ may be factored out of the integral,
thus returning the cost function to its original form. Thus, the problem of
minimizing κJ becomes the same as minimizing J. Therefore, holding one
weight matrix constant while varying either the individual elements or a scalar
multiplier of the other is an acceptable technique for iterative design. It is good
for the designer to maintain an understanding of the eects of manipulating
individual weights, however. In general, raising the eective penalty a single
state or control input by manipulating its individual weight will tighten the
control over the variation in that parameter, however it may do so at the expense
of larger variation in the other states or inputs.
22.2 uk Converter with LQR Compensator
The fth-order system formed by augmenting the uk converter with an integral
state requires that Q be a ve-by- ve matrix. To review, the state vector is
[v2 v1 i2 i1 xi ]0 , where xi corresponds to the integral of the reference error e.
Since the states have physical signi cance in this model, it is easy to see that
each voltage, current, or error transient may be individually penalized using
the diagonal elements of the Q matrix. As the objective of controlling the uk
converter is to regulate the output vo = v2 in the face of disturbances to vg ,
penalizing transients that occur on state v2 is a logical choice, as is penalizing the
state xi associated with the reference error integral as the integral of that error
should be minimized to provide for good regulation. Hence, the Q matrix chosen
for design of the LQR has two positive entries corresponding to the rst (Q11 )
and last (Q55 ) entries along the diagonal to ensure it is positive semide nite.
The uk converter has only a single control input, and for initial design R was
set equal to 1 arbitrarily. If the control eort exceeds the limitations put on it
354 © Richard Tymerski and Frank Rytkonen, 2017
(refer to Section 18.6), the value of R may need to be increase to penalize the
control eort.
After proceeding through an iterative process where Q11 and Q55 were varied
with R xed, a nalized design was determined. The step disturbance response
of the controlled uk converter is shown in Figure 22.1
24.025
24.02
Amplitude (V)
24.015
24.01
24.005
24
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Figure 22.1: Unit step disturbance response of the uk converter controlled by
LQR.
The loop gain of the controlled system is shown in Figure 22.2, where the
loop is broken at the large X shown on the control input d.
© Richard Tymerski and Frank Rytkonen, 2017 355
Bode Diagram
Gm = Inf , Pm = 65.4 deg (at 1.22e+004 Hz)
80
60
Magnitude (dB)
40
20
−20
0
−45
Phase (deg)
−90
−135
−180
0 1 2 3 4 5
10 10 10 10 10 10
Frequency (Hz)
Figure 22.2: Loop gain of uk converter controlled by LQR compensator.
Figure 22.3 shows the control eort produced by the optimal controller.
−0.005
∆ Duty Cycle
−0.01
−0.015
−0.02
−0.025
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Figure 22.3: LQR control eort.
Note that the time of the unit step disturbance transient with the LQR
compensator was signi cantly longer than the settling times of the previously
designed compensators. However, the amplitude deviation was signi cantly
356 © Richard Tymerski and Frank Rytkonen, 2017
smaller. This is an acceptable design tradeo since the performance speci ca-
tions were still met.
22.3 Linear Quadratic Gaussian Regulators
The LQR problem requires that full state feedback be used. This is not always
possible, as was discussed in Section 21. The Kalman-Bucy lter is the dual
to the LQR problem; it forms an optimal state estimator in the presence of
process and measurement noise for a system that is observable. The presence
of noise introduces stochastic eects on the state trajectory, therefore, the op-
timal state estimator must deal with these stochastic eects appropriately by
removing them. Since the process of removing noise from a signal is commonly
known as ltering, the optimal observer became known as the Kalman lter, or
Kalman-Bucy lter, after its creator(s). The Kalman lter is based on essen-
tially the same mathematics as the LQR and, as such, has come to be known
as a linear quadratic estimator (LQE). The cost function J0 that is minimized
is the error variance between the state vector and its estimate. LQE calculates
the solution to an ARE (which happens to be the error covariance) and uses it
to determine L, the estimator gain vector, along the lines of the same equations
given for the LQR gain K . Q0 , the covariance matrix of the process noise, and
R0 , the covariance matrix of the sensor noise, have to be selected for optimal
determination of the observer gain vector L.
When combined, the linear quadratic controller and estimator form a struc-
ture known as a linear quadratic Gaussian (LQG) compensator. Once the state
variables have been estimated, they are fed back through the controller gain K
to close the loop. The separation principle previously mentioned still holds true
for LQG design: the LQR and LQE problems can be solved independently via
two algebraic Riccati equations.
Adding process disturbances and measurement noise to the state space sys-
tem description results in:
ẋ = Ax + Bu + ω (22.6)
y = Cx + ν
where ω is the disturbance signal (typically modeled by Gaussian white noise
of spectral density Q0 ) and ν is additive measurement noise (Gaussian white
noise, with spectral density R0 ). Note that the fact that neither ω or ν has a
coe cient implies a coe cient of I, meaning each state and output has its own
distinct noise [4]. The time invariant solution to the optimal estimator problem
is then:
L = P0 C T R0−1 (22.7)
where P (known as the estimation error variance) is the unique, symmetric,
positive de nite solution to the steady-state algebraic Riccati equation:
AP0 + P0 AT − P0 C T R0−1 CP0 + Q0 = 0 (22.8)
© Richard Tymerski and Frank Rytkonen, 2017 357
Since the spectral density of the process and measurement noise in a sys-
tem is typically unknown, designers frequently treat Q0 and R0 as additional
design parameters that can be manipulated. The bandwidth of the open-loop
system frequency response can be controlled using these matrices. This can
allow reduction of the susceptibility of the controlled system to noise at higher
frequencies.
22.4 uk Converter with LQG Compensator
The unit step response of the uk converter controlled by a LQG compensator
is shown in Figure 22.4.
24.025
24.02
Amplitude (V)
24.015
24.01
24.005
24
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Figure 22.4: Unit step disturbance response of uk converter controlled by LQG
compensator.
A comparison of the loop gains of the LQR and LQG controlled systems is
shown in Figure 22.5, where the loop is broken at the control input d. Loss
of gain and phase margins has clearly occurred, and the negative gain margin
indicates that the system will no longer be closed-loop stable.
358 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
Gm = −5.7 dB (at 2.08e+003 Hz) , Pm = 36.4 deg (at 3.87e+003 Hz)
100
50
Magnitude (dB)
−50
−100
−150
0
LQRI
LQGI
Phase (deg)
−90
−180
−270
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Frequency (Hz)
Figure 22.5: Loop gain of uk converter controlled by LQR vs. LQG.
Figure 22.6 shows the control eort produced by the LQG controller.
−0.005
∆ Duty Cycle
−0.01
−0.015
−0.02
−0.025
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Figure 22.6: LQG control eort.
Minimal discussion is given to this design as it requires the improvements
described in the next section.
© Richard Tymerski and Frank Rytkonen, 2017 359
22.5 Control with LQG/LTR Compensators
Newcomers to the world of optimal control might think that the pairing of the
optimal controller formed by the solution of the LQR problem and the optimal
estimator formed by the construction of a Kalman lter would have optimal
properties. This is not necessarily the case. Doyle [5] provided an example to
show that the LQG design loses the guaranteed stability margins of the LQR
design when feeding back estimated states. Doyle and Stein [6] then showed how
this problem could be addressed. In order to recover the good stability margins
and sensitivity properties of an LQR design, an iterative procedure known as
loop transfer recovery (LTR) may be performed during the LQG design . The
1
Doyle-Stein method of LTR is performed by iteratively increasing the intensity
of the noise covariance matrices used in Kalman lter design. LTR causes the
open loop frequency domain characteristics associated with the LQR design to
be either exactly or asymptotically recovered as an input noise matrix weighting
parameter q is increased. As q → ∞, the properties of the LQR are recovered.
Essentially, LTR produces a state estimator whose estimates x̂ are independent
of the control input u (or only weakly depended on u) and dependent only on
the input provided by the plant output y.
Performing the Doyle-Stein method of asymptotic loop transfer recovery on
a full-order compensator requires:
The system must be minimum-phase and strictly proper.
Ro = 1 and Qo = q 2 BB 0
The fact that the plant must be minimum-phase (all poles and zeros in the
left half of the complex plane and no pure delays) prevents the compensator
designed from being unstable, since the LTR technique moves some of the com-
pensator poles toward the plant zeros where pole-zero cancellation makes them
unobservable. (Other LTR methods may be used with nonminimum-phase sys-
tems by using subspace [8] or loop-shaping techniques [9].) The remainder of the
poles (an excess of poles exists because the plant is strictly proper) move toward
in nity in the left-half of the complex plane in a Butterworth lter pattern [10].
The eect of loop transfer recovery is to essentially decouple the observer
from the control input u by raising the observer gain L so that the state estimate
x̂ depends only on the plant output y . This is illustrated in Figure 22.7. The
decoupling is accomplished by the increasing noise intensity on u, which causes
L to increase such that y has a larger contribution to the state estimate.
1 A variety of other methods for LTR have been presented in the controls literature, includ-
ing several which require employment of subspace methods or special coordinate bases [7], [8],
but these techniques are beyond the scope of this work.
360 © Richard Tymerski and Frank Rytkonen, 2017
Figure 22.7: Input decoupling eect of loop transfer recovery.
In order to accomplish LTR, the loop is broken at the large X on the control
input shown in Figure 21.1. The loop is explicitly shown in Figure 22.8. The
frequency response of the loop from d to d0 is driven to asymptotically approach
the frequency response of the system with LQR control.
Figure 22.8: The loop to be recovered during loop transfer recovery with a
full-order observer.
Figure 22.9 shows the LQGI/LTR iterative design process applied to the uk
© Richard Tymerski and Frank Rytkonen, 2017 361
converter. Initial LQGI design resulted in a gain margin reduction from in nity
◦ ◦
to -5.7 dB and a loss of phase margin from 65.4 to 36.4 . The iterative loop
transfer recovery process resulted in a controlled system gain margin of 30.2
◦
dB and phase margin of 61.7 . Iteration was stopped at that point since these
margins are adequate. Further iterations would result in larger observer gains
that may be undesirable during implementation, and recovery of the undesirable
high frequency characteristics of the LQR compensator has already begun.
Bode Diagram
Gm = 30.2 dB (at 2.5e+005 Hz) , Pm = 61.7 deg (at 1.19e+004 Hz)
100
50
Magnitude (dB)
−50 LQRI
q=100
−100
q=102
−150 q=104
q=106
−200
0
Phase (deg)
−90
−180
−270
0 1 2 3 4 5 6 7
10 10 10 10 10 10 10 10
Frequency (Hz)
Figure 22.9: Loop transfer recovery of an LQGI compensator.
362 © Richard Tymerski and Frank Rytkonen, 2017
22.6 MATLAB Code
1 % Linear Quadratic Regulator Compensator with Integration
2
3 % Define the plant using an external file
4 cuk_parameters;
5
6 % Define the weighting matrices for the integral performance ...
index, with
7 % weights on the capacitor voltage and the output error
8 Cq = [C 0];
9 Q = Cq'*Cq;
10 Q(1,1) = 1;
11 Q(2,2) = 0;
12 Q(3,3) = 0;
13 Q(4,4) = 0;
14 Q(5,5) = 100000;
15 R = 1;
16
17 A_prime = [A zeros(size(B));−C zeros(size(D))];
18 Bd_prime = [Bd; 0];
19 B_prime = [B;0];
20 C_prime = [C 0];
21
22 % LQR System design
23 K = lqr(A_prime,Bd_prime,Q,R);
24 k = K(1:4);
25 ki = K(end);
26
27 Abar = [A−Bd*k, −Bd*ki; −C, 0];
28 Bbar = [B; 0];
29 Cbar = [C 0];
30
31 SYS_LQR = ss(Abar,Bbar,Cbar,D);
32
33 % LQR Step Response
34 [y t x] = step(SYS_LQR,0.02);
35 figure;
36 plot(t, Vo+y, 'b');
37 xlabel('Time (s)');
38 ylabel('Amplitude (V)');
39 grid on
40
41 % LQR Loop Gain Plot
42 figure;
43 margin(A_prime, Bd_prime, K, 0);
44 h = gcr;
45 h.AxesGrid.TitleStyle.FontSize = 10;
46 h.AxesGrid.XLabelStyle.FontSize = 10;
47 h.AxesGrid.YLabelStyle.FontSize = 10;
48
49 % Control Effort Plot
50 figure;
51 plot(t, −K*x'+d);
52 xlabel('Time (s)');
© Richard Tymerski and Frank Rytkonen, 2017 363
53 ylabel('Duty Cycle');
54 grid on
1 % Linear Quadratic Gaussian Compensator with Integration
2
3 % Design the LQR compensator
4 lqri;
5
6 % LQG Design
7 Q0 = 1e8*eye(size(A));
8 R0 = 1;
9
10 [L,P,E] = lqe(A,eye(size(A)),C,Q0,R0);
11
12 % Construct the closed−loop system for time−domain response testing
13 Abar = [A, −Bd*ki, −Bd*k;
14 −C, 0, zeros(1,4);
15 L*C, −Bd*ki, A−Bd*k−L*C];
16 Bbar = [B; 0; B];
17 Cbar = [C 0 zeros(size(C))];
18 SYS_LQG = ss(Abar,Bbar,Cbar,D);
19
20 % LQG Step Response
21 [y t x] = step(SYS_LQG, 0.02);
22 figure;
23 plot(t, Vo+y, 'b');
24 xlabel('Time (s)');
25 ylabel('Amplitude (V)');
26 grid on
27
28 % LQR vs. LQG System Loop Gain Plot
29 A1 = [A, zeros(4,1), zeros(4,4);
30 −C, 0, zeros(1,4);
31 L*C, −Bd*ki, A−Bd*k−L*C];
32 B1 = [Bd;0;zeros(4,1)];
33 C1 = [zeros(1,4), ki, k];
34 D1 = 0;
35 figure;
36 sys_lqr = ss(A_prime, Bd_prime, K, 0);
37 sys_lqg = ss(A1, B1, C1, D1);
38 margin(sys_lqr)
39 hold on
40 margin(sys_lqg)
41 h = gcr;
42 h.AxesGrid.TitleStyle.FontSize = 10;
43 h.AxesGrid.XLabelStyle.FontSize = 10;
44 h.AxesGrid.YLabelStyle.FontSize = 10;
45 hold off
46 legend('LQRI','LQGI')
47
48 % Control Effort Plot
49 figure;
50 h = plot(t, −[zeros(1,4), ki, k]*x'+d);
51 xlabel('Time (s)');
52 ylabel('Duty Cycle');
53 grid on
364 © Richard Tymerski and Frank Rytkonen, 2017
© Richard Tymerski and Frank Rytkonen, 2017 365
366 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] B. N. Datta, Numerical Methods for Linear Control Systems. San Diego,
CA: Elsevier Academic Press, 2004.
[2] R. C. Dorf and R. H. Bishop, Modern Control Systems, 10th ed. Upper
Saddle River, NJ: Pearson Prentice Hall, 2005.
[3] B. D. O. Anderson and J. B. Moore, Optimal Control: Linear Quadratic
Methods. Englewood Clis, NJ: Prentice Hall, Inc., 1990.
[4] G. M. Siouris, An Engineering Approach to Optimal Control and Estima-
tion Theory. New York, NY: Wiley, 1996.
[5] J. C. Doyle, Guaranteed margins for LQG regulators, IEEE Trans. Au-
tomat. Contr., vol. 23, pp. 756757, Aug. 1978.
[6] J. C. Doyle and G. Stein, Robustness with observers, IEEE Trans. Au-
tomat. Contr., vol. 24, pp. 607611, Aug. 1979.
[7] B. M. Chen, Theory of loop transfer recovery for multivariable linear sys-
tems, Ph.D. dissertation, Washington State Univ., Pullman, WA, Dec.
1991.
[8] A. Saberi and P. Sannuti, Observer design for loop transfer recovery and
for uncertain dynamical systems, IEEE Trans. Automat. Contr., vol. 35,
pp. 878897, Aug. 1990.
[9] G. Stein and M. Athans, The LQG/LTR procedure for multivariable feed-
back control design, IEEE Trans. Automat. Contr., vol. 32, pp. 105114,
Feb. 1987.
[10] B. Friedland, Control System Design: An Introduction to State-Space Meth-
ods. New York, NY: McGraw-Hill, 1986.
367
368 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 23
Compensator Order
Reduction
With the advent of computer control of systems, high-order system models can
be created that allow model-based control methods (such as observer-based com-
pensators) to be easily implemented. These digital controller implementations
have many advantages over analog controllers, which may be considered to be
outdated. However, analog control can often still be performed at the circuit
level with a few discrete components and may be more cost-eective to imple-
ment when compared to a microprocessor and its associated support circuitry
and programming. Thus, this section examines the idea of controller order re-
duction for use with analog circuitry. It focuses rst on reducing the order of
an LQGI/LTR compensator using model reduction techniques, then design of
an LQGI/LTR compensator using a reduced-order Kalman lter (ROKF), and
nally, application of model reduction techniques to the ROKF-based compen-
sator. This nal two-step order reduction technique has not been previously
seen in the literature.
23.1 Model Reduction of the LQGI/LTR Com-
pensator
Model reduction (MR) may be accomplished by creating a balanced realization
(i.e., equal and diagonal controllability and observability Gramian matrices) of
the system to be reduced using a linear transformation such as the balreal com-
mand in MATLAB [1]. Examination of the eigenvalues of the Gramian matrix
of the balanced realization allows the designer to identify states that are weakly
coupled to both the input and output of the compensator. These states, which
are at once both weakly controllable and weakly observable, have small Hankel
singular values associated with them. Hankel singular values are determined by
taking the square root of the product of the eigenvalues of the controllability
369
and observability Gramian matrices. In a balanced realization, the Hankel sin-
gular values are the diagonal entries of the common controllability/observability
Gramian matrix, and the states are ordered from highest to lowest Hankel sin-
gular value [2]. Compensator states with small Hankel singular values may be
eliminated with little impact to the performance of the compensator using the
modred command in MATLAB.
In this case, the system to be reduced is the compensator. The balreal com-
mand identi es only two states that may be eliminated from the LQGI/LTR
compensator designed previously without signi cant loss of accuracy, as may be
predicted by the information provided from the pole-zero plot in Figure 23.1.
Model reduction resulted in the addition of a high-frequency zero for this par-
ticular compensator. This zero was a simulation artifact created by the modred
command, therefore it was removed by truncation.
Examination of the LQGI/LTR compensator poles, zeros, and gain of the
transfer function yields:
p = −1490 ± j9000 −1129500 ± j1129500 0 (23.1)
z = −32410 −319 −1440 ± j9090
k = 7.195 × 107
6
x 10
1.5
0.5
Imaginary Axis
−0.5
−1
−1.5
−12 −10 −8 −6 −4 −2 0
Real Axis 5
x 10
Figure 23.1: Pole-zero plot of the LQGI/LTR compensator.
By comparing the frequencies at which the poles and zeros occur and their
complex plane locations, it can be seen that a complex pair of zeros at −1490 ±
j9000 essentially cancels out a complex pair of poles at −1440 ± j9090. This is
more readily viewed in the close-up view of the pole-zero plot in Figure 23.2.
Examination of the compensator after model reduction methods yields:
370 © Richard Tymerski and Frank Rytkonen, 2017
4
x 10
1.5
0.5
Imaginary Axis
−0.5
−1
−1.5
−4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0 0.5
Real Axis 4
x 10
Figure 23.2: Compensator pole-zero plot showing likely pole-zero pair cancella-
tion.
pr = −1126800 ± j1132300
0 (23.2)
zr = −319.5 −33035
kr = 7.18 × 107
where all poles and zeros are in rad/s.
Once model reduction has been accomplished, validation must occur to verify
that signi cant dierences do not exist between the full-order and model-reduced
compensators. Comparison of the full-order and model-reduced compensator
frequency responses is shown in Figure 23.3. Based on this diagram, it is readily
apparent that the model-reduced compensator may be used to replace the full-
order compensator without signi cant dierence, thus reducing the controller
order. The MRLQGI/LTR compensator can then be achieved with less analog
circuitry than the LQGI/LTR yet still perform adequately, and therefore may
be selected for implementation.
Care must be taken when performing model reduction to ensure desirable
stability margins are not lost. Comparable frequency responses between the
full-order and model-reduced compensators tell the designer that margins will
probably not change appreciably during model reduction. Veri cation of mar-
gins was performed for system with the MRLQGI/LTR compensator; no change
◦ ◦
in gain margin resulted but phase margin was reduced to 61.2 , a loss of 0.5 ,
which is not a signi cant dierence.
The step disturbance response for the model-reduced compensator is shown
in Figure 23.4. The step disturbance input is attenuated well, with a maximum
© Richard Tymerski and Frank Rytkonen, 2017 371
Bode Diagram
40
30
Magnitude (dB)
20
10
−10
90
LQGI/LTR
MRLQGI/LTR
45
Phase (deg)
−45
−90
0 1 2 3 4 5 6 7
10 10 10 10 10 10 10 10
Frequency (Hz)
Figure 23.3: Compensator frequency response comparison following model re-
duction.
deviation of just over 20 mV. This would be a perfectly acceptable controller
for the uk converter, however, additional order reduction (though impossible
to achieve in this controller incarnation without signi cantly impacting perfor-
mance) would be desirable and is explored in the next section.
24.025
24.02
24.015
24.01
24.005
24
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Figure 23.4: Unit step disturbance response of uk converter - MRLQGI/LTR
compensator.
372 © Richard Tymerski and Frank Rytkonen, 2017
23.2 A Reduced-Order LQGI/LTR Compensator
The model-reduced compensator designed in Section 23.1 is based on pole-zero
cancellation in a balanced state-space realization of the Kalman lter and trun-
cation to remove a high-frequency zero. However, a compensator based on a
LQRI paired with a reduced-order Kalman lter (ROKF) can be designed and
the LTR technique applied during the design process in order to develop a
ROLQGI/LTR compensator. Madiwale and Williams [3] described the mathe-
matics necessary for performing loop transfer recovery with reduced-order linear
quadratic compensators and provided proofs that the equations used in this sec-
tion achieve LTR.
The design of the ROLQGI/LTR compensator begins with construction of
a linear quadratic regulator. Once the regulator gain K has been determined,
the system matrices and K are partitioned to form a reduced-order observer as
in Equation 21.10.
Consider a minimum phase system with process noise ω (with positive de -
nite Gaussian spectral density matrix V) that is distributed into the state dy-
namics by W and let the system be free from measurement noise in the measured
state vector xm :
ẋ = Ax + Bu + W ω (23.3)
y = xm
Process noise characteristics are usually di cult to determine or unknown.
Thus, both W and the corresponding noise spectral density V are manipulated
as design parameters for determining the optimal reduced-order estimator gain
L in a manner similar to the manipulation of Q0 and R0 in full-order estimator
design methods. Both W and V are also partitioned as in Equation 21.10 in
order to form the reduced-order Kalman lter. Let:
V11 = W1 V1 W10 + q 2 B1 V2 B10 (23.4)
V12 = W1 V1 W20 + q 2 B1 V2 B20 (23.5)
V22 = W2 V1 W20 +q 2
B2 V2 B20 (23.6)
Then with:
0 −1
Ā = A22 − V12 V11 A12 (23.7)
0 −1
V̄ = V22 − V12 V11 V12
where V11 is nonsingular, the following ARE is solved for for Qo :
−1
ĀQo + Qo Ā0 − Qo A012 V11 A12 Qo + V̄ = 0 (23.8)
The Kalman lter gain L can then be determined from:
−1
L = (Qo A012 + V12
0
)V11 (23.9)
© Richard Tymerski and Frank Rytkonen, 2017 373
Now, as q is increased in Equations 23.4-23.6, the target feedback loop of the
LQR controller is recovered.
Once again, the loop is broken at the large X on the control input as shown
in Figure 21.6. The open loop is shown explicitly in Figure 23.5. The frequency
response of the loop from d to d0 is again driven to asymptotically approach the
frequency response of the system with LQR control as shown in Figure 23.6,
which is a plot of the iterative LTR process for this reduced-order compensator
and the uk converter.
Figure 23.5: Loop transfer recovery with a reduced-order observer.
374 © Richard Tymerski and Frank Rytkonen, 2017
100
50
Magnitude (dB)
−50
−100
100
LQR
−10
50 q=10
q=10−9
−8
0 q=10
−7
Phase (deg)
q=10
−50
−100
−150
−200
2 3 4 5 6
10 10 10 10 10
Frequency (rad/s)
Figure 23.6: Loop transfer recovery of a ROKF-based LQGI compensator.
During simulation, it was found that the original matrices selected to repre-
sent the process noise had values that were too large. The initial results showed
loop transfer recovery had already occurred, therefore the noise values had to
be made smaller to verify that LTR was taking place. For the model of the uk
converter to be controlled, the following partitions of the W and V matrices
were used to simulate the ctitious noise:
1 × 10−5
0 0
1 × 10−4
1 × 10−5
W1 = 0 0 , W2 =
0 0
0 0 1 × 10−5
1 × 10−5
0 0
, V2 = 1 × 10−5
1 × 10−5
V1 =
0 0
0 0 1 × 10−5
The scalar q was allowed to vary from 1 × 10−10 to 1 × 10−7 during the recovery
process.
Examination of the ROLQGI/LTR compensator transfer function yields:
pr = −1490.0 ± j9000.0 −2466000.0 0.0 (23.10)
zr = −32990.0 −319.2 −1442.0 ± j9087.0
kr = 70.74
© Richard Tymerski and Frank Rytkonen, 2017 375
where the poles and zeros are given in rad/s. This transfer function shows a
pole-zero pair that could possibly be canceled via model reduction methods.
The balanced realization approach to model reduction discussed in Section 23.1
was applied. Comparison of the Hankel singular values produced by the balreal
command revealed that only two states could be eliminated without signi cant
loss of accuracy in the controller model. Elimination of these states resulted in a
second-order compensator that had the following characteristics for its transfer
function:
pr = 0.0 −2469000.0 (23.11)
zr = −319.4 −33570.0
kr = 70.76
where the poles and zeros are given in rad/s. This model-reduced compensator
has a pole at the origin and two zeros on the negative real axis left of the pole,
which is a classical PID controller. It also has another pole on the negative real
axis beyond the zeros, which corresponds to high frequency low-pass ltering. It
may therefore be thought of as a feedback PID compensator with the derivative
term acted upon by a rst-order low-pass lter. This type of ltered derivative
action is typically included in PID controllers to reduce the bandwidth of the
controller and associated undesirable ampli cation of high-frequency noise, as
well as to make them implementable (the ideal PID equation is non-causal due
to the fact that there is an excess of zeros). This PID controller is very simple to
implement with a single inverting operational ampli er con guration. A second
inverter buer stage is needed to eliminate the undesired inversion caused by
the rst stage.
A frequency response comparison of the two compensators designed in this
section is shown in Figure 23.7. There is excellent correlation between the Bode
plots, showing that the MRROLQGI/LTR compensator performance will be
almost exactly the same as the ROLQGI/LTR compensator.
376 © Richard Tymerski and Frank Rytkonen, 2017
Bode Diagram
40
30
Magnitude (dB)
20
10
−10
90
45
Phase (deg)
−45
−90
0 1 2 3 4 5 6 7
10 10 10 10 10 10 10 10
Frequency (Hz)
Figure 23.7: Comparison of compensator frequency response - ROLQGI/LTR
and MRROLQGI/LTR.
Initial ROLQGI design resulted in no gain margin reduction from in nity
◦ ◦
but had a loss of phase margin from 65.4 to 56.3 . The iterative loop transfer
◦
recovery process resulted in a controlled system phase margin of 63.7 . Further
iterations would result in larger observer gains that may be undesirable during
implementation. Veri cation of margins was performed for system with the
MRROLQGI/LTR compensator; no change in gain margin resulted but phase
◦ ◦
margin was reduced to 63.3 , a loss of 0.4 . Again, this is not a signi cant
dierence.
The step disturbance response for the model-reduced compensator is shown
in Figure 23.8. The step disturbance input is attenuated well, with a maximum
deviation of less than 20 mV. This is a perfectly acceptable controller for the
uk converter.
© Richard Tymerski and Frank Rytkonen, 2017 377
24.02
24.018
24.016
24.014
Amplitude (V)
24.012
24.01
24.008
24.006
24.004
24.002
24
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
Figure 23.8: Unit step vg response of uk converter - MRROLQGI/LTR com-
pensator
378 © Richard Tymerski and Frank Rytkonen, 2017
23.3 MATLAB Code
1 % LQGI/LTR and MRLQGI/LTR Compensators
2 clc
3
4 % Design the LQR compensator
5 lqri;
6
7 % Define one of the Kalman filter weight matrices
8 R0 = 1;
9
10 % Plot the magnitude of the open loop LQR
11 h=figure;
12 bode(A_prime, Bd_prime, K, 0);
13 hold on
14
15 % Loop transfer recovery
16 q = [1,1e2,1e4,1e6];
17 for n = 1:length(q)
18 Q0 = q(n)*Bd*Bd';
19 [L,P,E] = lqe(A,eye(size(A)),C,Q0,R0);
20 Aol = [ A, zeros(4,1), zeros(4,4);
21 −C, 0, zeros(1,4);
22 L*C, −Bd*ki, A−Bd*k−L*C];
23 Bol = [Bd; 0; zeros(4,1)];
24 Col = [zeros(1,4), ki, k];
25 sysol = ss(Aol,Bol,Col,D);
26
27 % Plot the frequency response of the open loop LQGI/LTR
28 margin(Aol, Bol, Col, D);
29 end
30 hold off
31 childrenHnd =get(h, 'Children')
32 axes(childrenHnd(3))
33 legend('LQRI','q=10^{0}','q=10^{2}','q=10^{4}','q=10^{6}', ...
34 'Location','SouthWest')
35 h = gcr;
36 h.AxesGrid.TitleStyle.FontSize = 10;
37 h.AxesGrid.XLabelStyle.FontSize = 10;
38 h.AxesGrid.YLabelStyle.FontSize = 10;
39
40 % Compensator
41 Ao = [A−Bd*k−L*C, −Bd*ki;
42 zeros(1,4), 0];
43 Lo = [L; −1 ];
44 focomp = ss(Ao,Lo,K,0);
45 [zc,pc,kc]=ss2zp(Ao,Lo,K,0);
46 focomp = zpk(zc,pc,kc)
47
48 % Pole−zero plot of full−order compensator
49 [P,Z] = pzmap(focomp);
50 figure;
51 h = plot(real(P),imag(P),'x',real(Z),imag(Z),'bo');
52 ylabel('Imaginary Axis');
53 xlabel('Real Axis');
© Richard Tymerski and Frank Rytkonen, 2017 379
54 grid on
55
56 % Close−up of pole−zero plot
57 figure;
58 h = plot(real(P),imag(P),'x',real(Z),imag(Z),'bo');
59 ylabel('Imaginary Axis');
60 xlabel('Real Axis');
61 axis([−4e4,0.5e4,−1.5e4,1.5e4]);
62 grid on
63
64 % Reduce the order of the compensator
65 [focomp,g] = balreal(focomp);
66 g;
67 elim = (g<5e−2);
68 mrcomp = modred(focomp,elim);
69 [zrc prc krc] = ss2zp(mrcomp.a,mrcomp.b,mrcomp.c,mrcomp.d);
70 % An added high−frequency zero results from model reduction.
71 % Restore the system gain prior to removing the high frequency zero
72 % using truncation.
73 krc = krc*abs(zrc(1,1));
74 zrc = zrc(2:3,1);
75 mrcompzp = zpk(zrc,prc,krc)
76 [mrcomp.a,mrcomp.b,mrcomp.c,mrcomp.d] = zp2ss(zrc,prc,krc);
77
78 % Compensator Comparison Bode Plot
79 figure;
80 bode(focomp,mrcomp);
81 h = gcr;
82 h.AxesGrid.TitleStyle.FontSize = 10;
83 h.AxesGrid.XLabelStyle.FontSize = 10;
84 h.AxesGrid.YLabelStyle.FontSize = 10;
85 legend('LQGI/LTR','MRLQGI/LTR','Location','NorthWest');
86
87 % Plot step disturbance response with MRLQGI/LTR compensator
88 figure;
89 sys = ss(A,[B,Bd],C,D);
90 syscl = feedback(sys,mrcomp,[2],[1]);
91 [y,t,x] = step(syscl,0.02);
92 plot(t, Vo+y(:,1,1));
93 grid on
1 % ROLQGI/LTR and MRROLQGI/LTR Compensators
2
3 % Design the LQR compensator
4 lqri;
5
6 % Partition the system in terms of measured and unmeasured states
7 A11 = A(1,1);
8 A12 = A(1,2:4);
9 A21 = A(2:4,1);
10 A22 = A(2:4,2:4);
11
12 Bd1 = Bd(1);
13 Bd2 = Bd(2:4);
14
15 % Partition the gain vector determined by linquadreg.m
380 © Richard Tymerski and Frank Rytkonen, 2017
16 k = K(1:4);
17 km = K(1);
18 ku = K(2:4);
19 ki = K(end);
20
21 % Form the open−loop LQR system and plot the frequency response
22 olsys = ss(A_prime,Bd_prime,K,0);
23 [gm1 pm1 wgc1 wpc1] = margin(A_prime,Bd_prime,K,0);
24 gm1 = 20*log10(gm1);
25 h=figure;
26 bode(olsys,{1e1,1e7});
27 hold on
28
29 % Noise distribution matrices
30 F1 = 1e−4*eye(1,3);
31 F2 = 1e−5*diag([1,1,1]);
32
33 % White noise vector intensity
34 V1 = 1e−5*diag([1,1,1]);
35 V2 = 1e−5*1;
36
37 % Loop transfer recovery
38 q = [1e−10,1e−9,1e−8,1e−7];
39 for n = 1:length(q);
40 V11 = F1*V1*F1'+q(n)^2*Bd1*V2*Bd1';
41 V12 = F1*V1*F2'+q(n)^2*Bd1*V2*Bd2';
42 V22 = F2*V1*F2'+q(n)^2*Bd2*V2*Bd2';
43
44 Abar = A22−V12'*inv(V11)*A12;
45 Vbar = V22−V12'*inv(V11)*V12;
46
47 [Q,M,X] = care(Abar',A12',Vbar,V11);
48
49 L = (Q*A12'+V12')*inv(V11);
50
51 E = A22−L*A12;
52 F = E*L+A21−L*A11;
53 G = Bd2−L*Bd1;
54
55 % Build open loop system with plant, observer, and feedback law
56 Aol = [A, zeros(4,1), zeros(4,3);
57 −C, 0, zeros(1,3);
58 F*C−G*km*C−G*ku*L*C, −G*ki, E−G*ku];
59 Bol = [Bd; 0; zeros(3,1)];
60 Col = [km*C+ku*L*C, ki, ku];
61 sysol = ss(Aol,Bol,Col,D);
62
63 % Plot the frequency response of the open loop system
64 margin(sysol);
65 end
66 hold off
67 childrenHnd =get(h, 'Children');
68 axes(childrenHnd(3))
69 legend('LQRI','q=10^{−10}','q=10^{−9}','q=10^{−8}',...
70 'q=10^{−7}','Location','SouthWest')
71 h = gcr;
72 h.AxesGrid.TitleStyle.FontSize = 10;
© Richard Tymerski and Frank Rytkonen, 2017 381
73 h.AxesGrid.XLabelStyle.FontSize = 10;
74 h.AxesGrid.YLabelStyle.FontSize = 10;
75
76 % Define the reduced order compensator design
77 Ar = [E−G*ku, −G*ki;
78 zeros(1,3), 0];
79 Br = [F−G*ku*L−G*km; −1];
80 Cr = [ku ki];
81 Dr = ku*L+km;
82 [zr pr kr] = ss2zp(Ar,Br,Cr,Dr);
83 rocomp = zpk(zr,pr,kr);
84
85 % Apply model reduction techniques
86 [rocomp,g] = balreal(rocomp);
87 g
88 elim = (g<5e−2)
89 mrrocomp = modred(rocomp,elim);
90 [zrr prr krr] = ss2zp(mrrocomp.a,mrrocomp.b,mrrocomp.c,mrrocomp.d);
91 mrrocompzp = zpk(zrr,prr,krr)
92
93 % Compensator Comparison Bode Plot
94 figure;
95 bode(rocomp,mrrocomp);
96 h = gcr;
97 h.AxesGrid.TitleStyle.FontSize = 10;
98 h.AxesGrid.XLabelStyle.FontSize = 10;
99 h.AxesGrid.YLabelStyle.FontSize = 10;
100
101 % Plot step disturbance response
102 figure;
103 sys = ss(A,[B,Bd],C,D);
104 syscl = feedback(sys,mrrocomp,[2],[1]);
105 [y,t,x] = step(syscl,0.02);
106 plot(t, 24+y(:,1,1));
107 xlabel('Time (s)');
108 ylabel('Amplitude (V)');
109 grid on
110
111 % Calculate component values for the MRROLQGI/LTR compensator
112 % There are five free parameters to find and four equations.
113 % Arbitrarily assign R3, calculate the remaining component values.
114 R3 = 100000
115 R2 = R3/krr
116 C2 = 1/(R3*abs(zrr(1,1)))
117 R1 = R2*abs(prr(2,1))/abs(zrr(2,1))−R2
118 C1 = 1/(R1*abs(zrr(2,1)))
382 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] MATLAB Control Systems Toolbox 6.0 User's Guide, The Mathworks, 2004.
[2] R. S. Sánchez-Peña and M. Sznaier, Robust Systems: Theory and Applica-
tions. New York, NY: Wiley, 1998.
[3] A. N. Madiwale and D. E. Williams, Some extensions of loop transfer recov-
ery, in Proc. of the American Control Conference (ACC'85), Boston, MA,
Jun. 1985, pp. 790795.
383
384 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 24
Compensator Implementation
At this point, four optimal compensator designs that rely on output feedback
and state estimation have been developed. The initial design of the optimal
compensator began with a fth-order controller, with estimated states for each
of the four states in the plant and an augmented integral state (LQGI/LTR).
Model reduction techniques applied directly resulted in a third-order controller
(MRLQGI/LTR), which was a signi cant improvement in terms of minimizing
the circuitry for implementation. The nal design began with a fourth-order
compensator based on three states from a reduced-order observer augmented by
an integral state (ROLQGI/LTR), to which model reduction techniques were
applied to form a second-order transfer function (MRROLQGI/LTR). This nal
regulator had the form of a classical PID controller. The nal design had a
signi cant reduction in circuitry yet maintained excellent performance in both
the time and frequency domains.
The reduced-order compensators developed in Chapter 23 using model re-
duction techniques can be implemented with analog circuits using operational
ampli ers. The goal is to use the minimum amount of components and circuitry
for control (to minimize manufacturing costs) while maintaining adequate con-
troller performance.
24.1 MRLQGI/LTR Compensator Construction
The model-reduced compensator designed in Section 23.1 has two zeros on the
negative real axis, a LHP pair of complex poles, and a pole at the origin. This
compensator can be implemented by a PI compensator cascaded with a Tow-
Thomas biquadratic lter as seen in Figure 24.1. The Tow-Thomas lter is a
general second-order lter able to implement low-pass, high-pass, band-pass,
notch, and all-pass lters with appropriate choices of coe cients of the lter
transfer function [1]:
a2 s2 + a1 s + a0
Tb (s) = (24.1)
b2 s2 + b1 s + b0
385
The biquad lter section is used to implement the second-order denominator
term with a simple zero by setting a2 = 0. The PI section is used to implement
the other real zero and the pole at the origin. For both sections, it is desirable
to keep the poles and zeros within a certain frequency tolerance of each other
to keep the component values reasonable in size.
Figure 24.1: The MRLQGI/LTR compensator implemented using operational
ampli ers.
The transfer function of the PI section is given by:
C1 1
(s + C1 R1 )
Tp (s) = − C2 (24.2)
s
The transfer function of the biquad lter section is given by:
1 1
C3 R2 s + C32 R4 R5
Tb (s) = − 2 (24.3)
s + C31R3 s + C 21R2
3 4
24.2 MRROLQGI/LTR Compensator Construc-
tion
A practical example of the MRROLQGI/LTR compensator requires fewer com-
ponents to implement than the MRLQGI/LTR circuit. It is simply an analog
PID controller with a ltered derivative term [2]. Consider the circuit in Fig-
ure 24.2. With the inverting opamp con guration and some algebraic manipu-
386 © Richard Tymerski and Frank Rytkonen, 2017
Figure 24.2: The analog MRROLQGI/LTR compensator implementation.
lation, the transfer function is shown to be:
R3 1 1
R2 (s + C2 R3 )(s + R1 C1 )
T (s) = R2 +R1
(24.4)
s(s + R1 R2 C1 )
which shows the following zeros, poles, and gain:
h i
−(R2 +R1 )
poles = 0 R1 R2 C1
(24.5)
−1 −1
zeros = C2 R3 R1 C1
R3
gain =
R2
Component values may be determined by equating the expressions in Equation
24.5 with the compensator values given in Equation 23.11. Since there are
fewer equations than unknowns, one of the component values must be xed
before the other component values may be determined. The nal design used
the component values given in Table 24.1.
© Richard Tymerski and Frank Rytkonen, 2017 387
Table 24.1: Component values for MRROLQGI/LTR compensator implemen-
tation.
Component Value
R1 100 kΩ
R2 1.4 kΩ
R3 100 kΩ
C1 0.29 nF
C2 31.3 nF
388 © Richard Tymerski and Frank Rytkonen, 2017
References
[1] R. C. Jaeger, Microelectronic Circuit Design. Boston, MA: McGraw-Hill,
1997.
[2] W. J. Palm, Control Systems Engineering. New York, NY: Wiley, 1986.
389
390 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 25
Power Electronic Circuit
Simulation
The MRROLQGI/LTR compensator required the least amount of circuitry and
was therefore selected for implementation and testing in PECS. The PECS
environment provides for relatively short run times compared to SPICE-based
circuit simulation environments since power electronics circuits can typically be
simulated with simpler component models than other types of analog circuits.
25.1 Simulating the Controlled uk Converter in
PECS
The PECS implementation of the MRROLQGI/LTR compensator design from
Section 24.2 connected to the uk converter can be seen in Figure 25.1.
391
Figure 25.1: PECS simulation of uk converter - MRROLQGI/LTR compen-
sator.
First, the small-signal operation was tested using a step disturbance in vg as
was used during controller design. A simulation was set up to provide for input
voltage steps up and down from the nominal 12 V using a unit step to 13 V on
the uk input. The simulation used a time step of 1 µs and a run time of 0.1 s.
The results of this simulation are shown in Figure 25.2.
Figure 25.2: Unit step vg disturbances and vo response - MRROLQGI/LTR
compensator.
392 © Richard Tymerski and Frank Rytkonen, 2017
The maximum deviation in the output voltage is only 0.022 V in response to
a step input of 1 V. (Note that ripple voltage exists in the simulation which is not
present in the state space averaged model simulations in MATLAB. Neglecting
the ripple did not pose a problem, however, during the control system design
process.)
Next, a large-signal simulation was set up to provide for input voltage steps
up and down from the nominal 12 V through a speci ed operating range of 9-14
V on the uk input. The results of the large-signal simulation are shown in
Figure 25.3.
Figure 25.3: Large signal vg disturbances and vo response - MRROLQGI/LTR
compensator.
The maximum deviation of 0.11 V in the output voltage occurred when the
input voltage drops sharply from 14 V to 9 V but is rapidly brought back under
control. This value is well within the 0.24 V tolerance that was speci ed for
controller performance.
Finally, a simulation was set up to provide for 25% load current steps (0.214
A) around the nominal load current of 0.857 A. The results of this simulation
are shown in Figure 25.4.
© Richard Tymerski and Frank Rytkonen, 2017 393
Figure 25.4: Load current disturbance and vo response - MRROLQGI/LTR
compensator.
The maximum deviation of 0.175 V in the output voltage occurred when the
load current dropped sharply from 1.071 A to 0.643 A, but this is within the
transient design speci cation of regulation to within 1% of the nominal output
voltage.
The ability to reject large scale input voltage and load disturbances shows
that the compensator design is excellent. The MRROLQGI/LTR controller
allowed the system to not only meet the performance speci cations, but to
exceed them, and achieved these results after two separate reduction of order
techniques (reduced-order observer and model reduction) were applied during
the design process.
394 © Richard Tymerski and Frank Rytkonen, 2017
Chapter 26
Conclusion
Part II demonstrated the process of applying modern control design methods
to regulator design for DC-DC converters, and prototypically, to a uk DC-DC
converter. Full state feedback control for pole placement was applied - rst
without integral eort, then with an integrator added. Output compensation
using state estimation techniques with full- and reduced-order observers was
discussed and simulated. LQRI and LQGI/LTR techniques were then used to
design compensators that were optimized with respect to quadratic performance
indices based on state and control eort transients. Balanced realization of the
LQGI/LTR compensator identi ed weakly controllable/observable states, which
were then removed using truncation to create a third-order compensator (MR-
LQGI/LTR) that could be implemented with a combination PI/Tow-Thomas
biquad circuit.
The steps up to this point were typical application of modern state space
control methods found in most textbooks. The method that followed (in Sec-
tion 23.2) resulted in a minimal-order compensator. Namely, when the reduced-
order Kalman lter-based compensator design (ROLQGI/LTR) was combined
with model reduction using a balanced realization, the result was a second-order
compensator (MRROLQGI/LTR) that could be implemented by an analog PID
circuit. This MRROLQGI/LTR controller was applied to the uk converter in
a power electronics modeling environment and showed excellent input voltage
and load current disturbance rejection abilities. The two-step order reduction
combination of reduced-order observer design and truncated balanced realiza-
tion is a novel design method that, while applied to one of the more complex
DC-DC converters, appears to be applicable to compensator design in general.
395
396 © Richard Tymerski and Frank Rytkonen, 2017
Appendix C
PECS
Power Electronics Circuit Simulator
C.1 PECS Overall Description
PECS is a circuit simulator which features high simulation accuracy as well as
fast simulation times. It is particularly well suited to circuits which contain
ideal switches, as is the case with power electronic circuits. It was developed at
Portland State University [1], [2], [3].
The PECS software actually consists of two distinct programs:
1. PECS, provides graphical schematic capture and simulation functions. At
the end of a successful simulation run an output le is written to the hard
drive.
2. PECSPLOT, provides plotting and graphical post processing of selected
outputs designated in the PECS schematic. A le previously written to the
hard drive is read by this program. Note that PECSPLOT is automatically
called by the PECS program at the end of a simulation and, as such, the
user need not call this program directly. However, a user may use this
program directly if so desired on a previously stored PECS output le.
Figure C.1 shows the PECS user interface with a displayed circuit schematic.
PECSPLOT is discussed more fully in the next section..
C.2 PECS Usage
The following steps are taken to simulate a circuit and produce an output plot:
1. Build the desired circuit schematic in PECS.
397
Figure C.1: The PECS program showing a circuit schematic.
2. Set simulation parameters.
3. Run the simulation.
4. Select the desired output(s) to plot.
These will be expanded on next:
C.2.1 Building a circuit schematic in PECS
Element selection: Select the desired component to place from the component
selection bar at the bottom by left mouse clicking on the element or from the
Element menu at the top. Drag the element to the appropriate position on the
page and then left click again to place it. This action will also bring up another
copy of the element which may subsequently also be placed. Clicking the right
button will eliminate the copy (or the original selected component) if not needed.
Component Rotation: Rotation of components in 90 degree clockwise
increments can be achieved by pressing the space bar on the keyboard.
Wiring between components: Connections between components is made
by rst left clicking on the wire icon available in both the bottom component
selection bar and in the top menu bar of PECS. This action causes the mouse
cursor to change to a pen shape. Vertical and/or horizontal lines can now be
398 © Richard Tymerski and Frank Rytkonen, 2017
drawn between element nodes to connect them. Note that only connections be-
tween nodes of an element will constitute a valid connection. To exit this mode
of operation one can either right click the mouse or left click on the arrow icon
in the top menu icon bar.
Selection of previously placed components: After a component has
been placed in the schematic it can be selected by either left clicking on it or
by depressing the left mouse button in the vicinity of the component and then,
with the left button depressed, dragging the mouse over the component which
will bring up a rectangle. Releasing the button will select any component which
was fully enclosed in the rectangular area. The selected components will now
appear in red.
Movement of previously placed components: First select components
to be moved using the procedure discussed immediately above. These selected
components may now be moved by depressing the left button on any of the se-
lected components and, while depressed, dragging to the new desired position.
After the components have been moved, deselect them as discussed next.
Deselection of components: Previously selected components can be de-
selected by either right clicking the mouse or left clicking anywhere away from
the area occupied by the selected components.
Deletion of selected components: A component or a number of com-
ponents can be simultaneously deleted from a schematic by rst selecting them
and then right clicking on the scissors icon in the top component icon bar or
pressing the Delete button on the keyboard.
Outputs: Output variables to be plotted can be any voltage or current in
the schematic. These are identi ed in the schematic by an appropriately place
voltage port element or a current port element. A voltage port is placed in paral-
lel across the two points in the schematic for which the voltage will output. On
the other hand a current port is placed in series with line in which the current
will be monitored.
Ground node: PECS requires that a ground node be placed in the circuit.
This is the left most icon in the bottom element icon bar. Output ports: PECS
requires that at least one voltage or current port appear in the circuit. Ports
indicate to PECS which variables are to be stored for latter plotting.
Components available: The following are the most used components
available in PECS. (This does not cover the complete set of components avail-
able in PECS).
Basic passive elements: R (resistor), C (capacitor) and L (inductor)
Sources: VDC (DC voltage), IDC (DC current), VAC (AC voltage)
© Richard Tymerski and Frank Rytkonen, 2017 399
Ports: Vport (voltage port) and Iport (current port)
Switches: Sw (controlled switch) and D (diode)
Switch control elements: Clk (Clock) and (MOD) PWM Modulator
Miscellaneous: OPAMP (operational ampli er), current sensor (no symbol
name), ground node (no symbol name) and wire (no symbol name)
These available components will be further discussed in greater detail be-
low. There are range of other components that PECS features, such the four
controlled sources, but these will not be discussed here as they will not be used.
Assigning component parameter values: Any time after a component
has been placed it may be assigned with speci c values. Double left clicking on
the placed component will bring up the component dialog window. Note that
PECS will not run a simulation if any component values haven't been adequately
assigned. An error message will be given alerting to this fact and unassigned
components will be highlighted in red. There is no need to specify component
names as these are automatically assigned.
Saving a schematic: A schematic can be saved to disk at any time. A
default name of Untitled.ckt is assigned and so a more appropriate named should
be substituted. Note that during the construction/editing of a schematic, PECS
periodically saves a backup le which is given the name backup.ckt. If need be,
this le can be read back into PECS by using the File → Open ... menu item.
C.2.2 Setting simulation parameters
Before a simulation is run, appropriate simulation parameters should be as-
signed. This is achieved by bringing up the appropriate dialog window through
the menu item Simulation → Parameters ... . This dialog window appears as
shown in Figure C.2.
The simulation parameters are:
i Final Time: the total length of time of the simulation.
ii Step Size: this should be increased/decreased to decrease/increase, re-
spectively, the number of points at which the response will be determined.
It is important to use a small enough value here so as to smoothen the
output. Note that plotting between response points is achieved by using
straight line segments. The points in time in the simulation interval that
are actually saved to hard disk is speci ed by the Save interval parameters:
iii Start time: this is the time from which the output is saved to disk.
iv End time: this is the time to which the output is saved to disk. Generally
this should be the same as the simulation nal time.
400 © Richard Tymerski and Frank Rytkonen, 2017
Figure C.2: Simulation parameters dialog window showing the default values.
v # of points: This speci es the number of evenly-spaced points that are
saved in the save interval. This value rarely needs to be changed from
its default as generally it is best to maximize the number of points saved
which will lead to a smoother looking plot.
C.2.3 Running the simulation
After the above two steps have been completed, one can run the simulation by
left clicking on the script R icon in the top icon bar. Alternatively, this can be
initiated through the menu by selecting Simulation → Run.
Assuming the schematic has been constituted properly the simulation will
start and a progress bar at the bottom of PECS will appear. At the end of
the simulation a dialog window appears indicating the total real time used to
perform the simulation. When this dialog is dismissed PECSPLOT will auto-
matically be called.
C.2.4 Selecting the desired output(s) to plot
When PECSPLOT appears a number of outputs will appear in the left column.
These output having previously been speci ed by the voltage and current ports
in the PECS schematic. Moving the output port names from the left to the right
column speci es the plot to be viewed. This is achieved by double clicking the
left mouse button on the selected output variable. Alternatively, one can move
an output variable from the left column by selecting it (or a number of outputs)
and then left clicking on the Add button between the columns. Any number
of output variables can be displayed in one plot but generally it is best that
© Richard Tymerski and Frank Rytkonen, 2017 401
dierent variables appear in their own plot so as to the accommodate scaling
for the plot, which is automatic. This is achieved by using the Add menu item
in PECSPLPOT.
402 © Richard Tymerski and Frank Rytkonen, 2017
C.3 Elements
C.3.1 Basic passive elements: R (resistor), C (capacitor)
and L (inductor)
Resistor:
The schematic symbol of a resistor is shown in Figure C.3. The resistance value
is the only parameter value that needs to be speci ed the dialog window shown
in Figure C.4.
Figure C.3: Resistor schematic symbol
Figure C.4: Resistor dialog window
Capacitor:
The schematic symbol of a capacitor is shown in Figure C.5. The capacitor
value and an initial voltage are the parameters that need to be speci ed in the
dialog window shown in Figure C.6.
Figure C.5: Capacitor schematic symbol
© Richard Tymerski and Frank Rytkonen, 2017 403
Figure C.6: Capacitor dialog window
Inductor:
The schematic symbol of an inductor is shown in Figure C.7. The inductor
value and an initial current are the parameters that need to be speci ed in the
dialog window shown in Figure C.8.
Figure C.7: Inductor schematic symbol
Figure C.8: Inductor dialog window
C.3.2 Sources: VDC (DC voltage), IDC (DC current),
VAC (AC voltage)
DC Voltage Source:
The schematic symbol of a DC voltage source is shown in Figure C.9. The value
of the voltage is a user speci ed parameter that is entered in the dialog window,
shown in Figure C.10.
404 © Richard Tymerski and Frank Rytkonen, 2017
Figure C.9: DC Voltage Source schematic symbol
Figure C.10: DC Voltage Source
Voltage sources can be stepped in value at a limited number of user speci ed
times. Clicking on the Steps button will open the bottom section of the dialog
window where one is able to enter up to ve time and associated step values
which the voltage source will assume during the simulation. This is shown in
Figure C.11. If step values are present, the dialog window will appear fully
expanded on initiation.
Figure C.11: DC Voltage Source, showing voltage step times and values
DC Current Source:
The schematic symbol of a DC current source is shown in Figure C.12. The
value of the current is a user speci ed parameter that is entered in the dialog
window, shown in Figure C.13.
© Richard Tymerski and Frank Rytkonen, 2017 405
Figure C.12: DC Current Source schematic symbol
Figure C.13: DC Current Source dialog window
Current sources can be stepped in value at a limited number of user speci ed
times. Clicking on the Steps button will open the bottom section of the dialog
window where one is able to enter up to ve time and associated step values
which the current source will assume during the simulation. This is shown in
Figure C.14. If step values are present, the dialog window will appear fully
expanded on initiation.
Figure C.14: DC Current Source dialog window, showing voltage step times and
values
AC Voltage Source:
The schematic symbol of an AC voltage source is shown in Figure C.15. This
element produces a sinusoidal voltage waveform. The peak amplitude (volts),
frequency (Hz) and phase (degrees) comprise the parameters that are entered
into the dialog window, see Figure C.16, which will specify its characteristics.
406 © Richard Tymerski and Frank Rytkonen, 2017
Figure C.15: AC Voltage Source schematic symbol
Figure C.16: AC Voltage Source dialog window
C.3.3 Ports: Vport (voltage port) and Iport (current port)
Voltage Port:
The schematic symbol of a voltage port is shown in Figure C.17. The purpose
of voltage port is to monitor the voltage across two points in the circuit being
simulated. This voltage will be saved in the output le which will be read by the
plotting program. There are no parameters required for this element, however
as with most of the other elements the name may be changed from its default
via the dialog window, see Figure C.18.
Figure C.17: Voltage port schematic symbol
Figure C.18: Voltage Port dialog window
Current Port:
The schematic symbol of a current port is shown in Figure C.19. The purpose
© Richard Tymerski and Frank Rytkonen, 2017 407
of a current port is to monitor the current in a branch in the circuit being
simulated. This current will be saved in the output le which will be read
by the plotting program. There are no parameters required for this element,
however as with most of the other elements the name may be changed from its
default via the dialog window, see Figure C.20.
Figure C.19: Current Port schematic symbol
Figure C.20: Current Port dialog window
C.3.4 Switches: Sw (controlled switch) and D (diode)
Switch:
The schematic symbol for a switch is shown in Figure C.21.
Figure C.21: Switch schematic symbol
A switch features two electrical terminals and two control terminals which
are labeled ON and OFF. The connection to the control terminals is not electri-
cal. Only speci c switch control elements may be connected to these terminals.
The switch control elements that are discussed here are:
1. Clock
2. PWM Modulator
Note that once a switch turns ON or OFF by the (conceptual) impulses driv-
ing it, it remains in this state until the time instant of a counter-acting control
signal.
408 © Richard Tymerski and Frank Rytkonen, 2017
Double clicking on the switch symbol will bring up the dialog window which
is shown in Figure C.22. An initial state can be selected and is provided to
de ne the starting point for a cycle for use in the accelerated steady state
determination feature available in PECS. (This feature is not discussed here.)
If the selected initial state is not correct, the program will alter the state.
Figure C.22: Switch dialog window
Diode:
The schematic symbol of a diode is shown in Figure C.23, with the dialog window
shown in Figure C.24. As with the switch element, there is facility to stipulate
the initial state of the diode which is used to de ne the starting state at the
beginning of a switching cycle. Should this state be incompatible with current
circuit conditions the simulator will change the diode state.
Figure C.23: Diode schematic symbol
Figure C.24: Diode dialog window
© Richard Tymerski and Frank Rytkonen, 2017 409
C.3.5 Switch control elements: Clk (Clock) and (MOD)
PWM Modulator
Clock:
The schematic symbol for a clock is shown in Figure C.25.
Figure C.25: Clock schematic symbol
A clock has only one terminal which can only be connected to a switch ON
or OFF node. The parameters of a clock element are:
1. Delay time
2. Period
With reference to Figure C.26, we see that after an initial delay of Delay
seconds the switch is then turned ON (OFF). Following this initial signal, sub-
sequent signals are issued every Period seconds. Thus, if the clock element is
connected to the ON (OFF) terminal of the switch, these subsequent signals
repeatedly turn the switch ON (OFF).
The Delay and Period parameters are entered into the dialog window as seen
in Figure C.27.
Figure C.26: Delay and period parameters shown pictorially
Figure C.27: Clock dialog window
410 © Richard Tymerski and Frank Rytkonen, 2017
Pulse Width Modulator:
Figure C.28: Pulse Width Modulator schematic symbol
The schematic symbol of a PWM modulator is shown in Figure C.28. This
symbol pictorially shows a four input comparator and a sawtooth generator.
Whenever the sum of the four inputs (three are added and one is subtracted)
becomes negative, the output (which can only be connected to a switch control
terminal) will issue an appropriate turn ON or OFF signal. Two external inputs
are provided to the modulator. These inputs are fed through gain blocks K1
and K2 The third input to the comparator is a constant K3 . K1 , K2 and K3 are
all input parameters of the modulator element. The last comparator input is
from a (conceptual) sawtooth generator where the peak-to-peak voltage ampli-
tude, Vpk−pk , period of the sawtooth are the nal two parameters of this element.
If we consider voltages v1 and v2 to be connected to the K1 and K2 in-
puts, respectively, then an output switching signal is issued from the modulator
whenever
K1 · v1 + K2 · v2 + K3 − VRAM P < 0
The PWM dialog window is shown in Figure C.29 where the input gains,
K1 , K2 and K3 , and sawtooth parameters, the peak to peak voltage (Vpk−pk
and period can be entered.
© Richard Tymerski and Frank Rytkonen, 2017 411
Figure C.29: Pulse Width Modulator dialog window
C.3.6 Miscellaneous: OPAMP (operational ampli er), cur-
rent sensor (no symbol name), ground node (no
symbol name)
Operational Ampli er:
The schematic symbol of an op-amp is shown in Figure C.30.
Figure C.30: Operational Ampli er schematic symbol
The model of the op-amp used in PECS is shown in Figure C.31. There
are three parameters that characterize this model: 1) input resistance, Ri , 2)
output resistance, Ro , and 3) op-amp gain. The values of these parameters
can be changed via the element dialog window which is shown in Figure C.32.
Generally the default values will need not be changed.
Figure C.31: (a) Op-amp, and (b) its corresponding model
412 © Richard Tymerski and Frank Rytkonen, 2017
Figure C.32: Operational Ampli er dialog window, showing the default param-
eter values.
Current sensor:
The schematic symbol for a current sensor element is shown in Figure C.33.
There are no user de ned parameters for this device and so there is no associated
dialog window.
Figure C.33: Current sensor schematic symbol
Ground node:
The schematic symbol for a ground node element is shown in Figure C.34. There
are no user de ned parameters for this device and so there is no associated dialog
window.
Figure C.34: Ground node schematic symbol
© Richard Tymerski and Frank Rytkonen, 2017 413
C.4 PECSPLOT
This section provides a comprehensive overview of PECSLOT, which is the pro-
gram that PECS calls to plot the waveforms that were generated by simulation
in PECS. PECSPLOT is automatically called by PECS at the end of a simu-
lation. However, it may also be user initiated which subsequently requires the
user to choose the desired data le (which has extension *.plt) which contains
the waveform data.
PECSPLOT has the following features:
1. Multiple plots, stacked vertically, are possible.
2. Multiple waveforms can appear in each plot.
3. Zooming into a desired time interval is possible.
4. Accurate measurements of time and amplitude are possible.
5. Auto-scaling of the amplitude axis for single and multiple waveform plots.
6. Full customization of font size, waveform and background colors is pro-
vided.
C.5 Terminology:
1. Waveform - a signal that is shown within a plot. Multiple waveforms can
be shown within the same plot. Necessarily all waveforms share the same
scaling of the vertical axis.
2. Plot - A time and amplitude axis pair within which waveforms appear.
Waveforms of widely diering amplitudes are best graphed in separate
plots with their own individual vertical scaling.
To illustrate these terms, let us consider Figure C.35 which shows PEC-
SPLOT displaying a number of waveforms. Speci cally there are two plots.
The top plot shows the waveforms VP1 in red and VP2 in green. The bottom
plot shows only the VP2 waveform. Because the scaling in the top plot is dom-
inated by the amplitude of the VP1 waveform not much detail can be seen for
the VP2 waveform. However, this detail is available in the bottom plot where
the vertical scaling accommodates for the amplitude of the VP2 alone.
C.6 General use
Before delving into the functionality oered by PECSPLOT under the dierent
menu items, we'll rst look at the overall general use.
414 © Richard Tymerski and Frank Rytkonen, 2017
After PECS completes a simulation it stores the data points to the hard drive
and subsequently calls PECSPLOT which reads the le. The waveform names
are then displayed to the user who then selects how they are to be plotted, that
is, the number of plots desired and the grouping of waveforms. This waveform
selection dialog window is shown in Figure C.36.
Figure C.35: PECSPLOT displaying two plots. The top plot show two wave-
forms and the bottom show only one.
C.7 Menu items
As seen in Figure C.35 the following menu items appear across the top of the
application:
1. File menu
2. Edit menu
3. Plots menu
4. View menu
5. Options menu
6. Help menu
© Richard Tymerski and Frank Rytkonen, 2017 415
The functionality provided under each of these menu items will be presented
next.
C.7.1 File menu commands
The File menu oers the following commands:
1. Open: Opens a PECSPLOT le.
2. Reload: Reloads an opened PECSPLOT le.
3. Save: Saves an opened PECSPLOT le using the same le name. Only
currently displayed waveforms will be saved, other waveforms appearing
in the le will be deleted.
4. Save As: Saves a PECSPLOT le to a speci ed le name.
5. Print: Prints the currently displayed plot(s).
6. Print Preview: Displays the current plot(s) seen on the screen as it would
appear printed.
7. Print Setup: Selects a printer and printer connection.
8. Exit: Exits PECSPLOT
Figure C.36: Selection of waveforms dialog window.
416 © Richard Tymerski and Frank Rytkonen, 2017
C.7.2 Edit menu commands
The Edit menu oers the following commands:
1. Copy to Clipboard: Copies data from the currently displayed plot(s) to
the clipboard.
2. Edit Title: Two captions that appear on the top left and top right positions
of the printout may be edited. The default are the PECSPLOT le name
(top left) and the current date and time (top right).
C.7.3 Plots Menu commands
The Plots menu oers the following commands:
1. Add/Delete Waveform: Add or delete a waveform to the chosen plot.
2. Add Plot: Add an extra plot.
3. Delete Plot: Delete a plot.
4. Measure: Enable measurement of displayed waveforms.
5. Max: Show the maximum value of all waveforms (as well as the times at
which they occur) in the chosen plot. Measure mode must rst be chosen
to un-gray this menu item.
6. Min: Show the minimum value of all waveforms (as well as the time at
which they occur) in the chosen plot. Measure mode must rst be chosen
to un-gray this menu item.
Selecting the Plots → Measure menu item (or alternatively clicking on the
calipers icon in the icon bar) will bring up the measurement display screen as
shown in Figure C.37. Measurement is undertaken by rst left and/or right
clicking inside a plot at the desired position(s). Accurate placement of the mea-
surement lines may be obtained using the left and right keyboard arrow keys.
This aects movement of the measurement lines on a data point by point basis.
Waveforms may be manipulated mathematically. This is done through the
waveform selection dialog which was shown in Figure C.36. The following op-
erators may be used: +, -, *, /, and ^ where '^' refers to exponentiation. The
following functions are provided: sin, cos, tan, sqrt, fabs, exp,atan, log and log10.
These functions use the standard C language implementations. Each requires
a single argument and caution should be exercised for the range of values that
the functions will see as some functions may not be de ned for some range of
values. For example, sqrt, log and log10 are not de ned for negative values.
The constant pi (= 3.141592654) is recognized. Also engineering su xes may
be used and are listed in Table C.1.
© Richard Tymerski and Frank Rytkonen, 2017 417
Table C.1: Su xes and corresponding values.
Su x M k m u n p
Value 1E+6 1E+3 1E-3 1E-6 1E-9 1E-12
For example, 10k = 10,000. Be sure not to use any waveform names that
correspond to these su xes.
Any level of parenthetical expression with "(" and ")" may be used. An
example of a valid expression is:
(I(L2)+sin(2*pi*10k*vo))-1, where "I(L2)" and "vo" are valid waveform
names.
Figure C.37: The measure display dialog usually appears at the lower left corner
of the computer screen. Here it has been moved to the position shown for display
purposes. Clicking the left and right mouse buttons in the bottom plot area at
the appropriate positions results in the vertical lines appearing and the value of
the waveform(s), as well as the time values, being displayed. The third column
indicates the dierence between the two values, which in this case results in a
measurement of the peak-to-peak amplitude of the displayed waveform.
418 © Richard Tymerski and Frank Rytkonen, 2017
C.7.4 View menu commands
The View menu oers the following commands:
1. Zoom: Zooms in on the x-axis limits. These limits are established by
the user left clicking inside a plot and then dragging to another position.
Only the x values of the initial and nal positions are used. The y-axis
limits of the zoomed plot(s) are automatically scaled commensurate with
the currently displayed waveforms in the selected x value range.
2. Zoom All: Use maximum x-axis limits given by the data in the PEC-
SPLOT le.
3. Redraw: Redraw without altering the zoom factor (if any).
4. Toolbar: Shows or hides the toolbar.
5. Status Bar: Shows or hides the status bar.
C.7.5 Options menu commands
The Options menu oers the following commands, which enable you to cus-
tomize the plots appearance:
1. Text Settings: Change the font style, font size, font color.
2. Background Color: Change the background color.
3. Waveform Color: Change individual waveform colors. To un-gray this
menu item, rst select a waveform by left clicking on a waveform title from
those appearing above each plot. Note that all plots using the selected
waveform color will be changed to the new color.
4. Grid: Toggle grid on or o.
C.7.6 Help menu commands
The Help menu oers the following commands, which provide assistance with
PECSPLOT:
1. Index: Oers an index to topics on which help can be obtained.
2. About: Displays the version number of PECSPLOT as well as contact
information.
© Richard Tymerski and Frank Rytkonen, 2017 419
C.8 References
1. PECS - Power Electronics Circuit Simulator, Duwang Li, R. Tymerski,
and T. Ninomiya, IEEE Workshop on Computers in Power Electronics
(COMPEL '00), Blacksburg, Virginia, July, 2000, pp. 159-165.
2. PECS - An E cacious Solution for Simulating Switched Networks with
Nonlinear Elements, Duwang Li, R. Tymerski, and T. Ninomiya, IEEE
Power Electronics Specialists Conference (PESC '00), Galway, Ireland,
June, 2000, pp. 274-279.
3. PECS - An E cient Solution for Simulating Switched Networks with Non-
linear Elements, D. Li, R.P.E. Tymerski and T. Ninomiya, IEEE Trans-
actions on Industrial Electronics, April 2001, pp. 367-376.
420 © Richard Tymerski and Frank Rytkonen, 2017
You might also like
- K.J.astrom - 2002 - Control System DesignNo ratings yetK.J.astrom - 2002 - Control System Design333 pages
- TU Braunschwieg Automatic Control NotesNo ratings yetTU Braunschwieg Automatic Control Notes134 pages
- Effective Stiffness of Reinforced Concrete ColumnsNo ratings yetEffective Stiffness of Reinforced Concrete Columns9 pages
- ECE311S Dynamic Systems & Control: Course Notes by Bruce Francis January 2010No ratings yetECE311S Dynamic Systems & Control: Course Notes by Bruce Francis January 2010116 pages
- Fuzzy Control Systems - (Ch5 of Dynamics of Controlled Systems)100% (1)Fuzzy Control Systems - (Ch5 of Dynamics of Controlled Systems)322 pages
- An Introduction To Control Theory Applications With Matlab100% (1)An Introduction To Control Theory Applications With Matlab152 pages
- Introduction To Control Engineering: Andy Pomfret and Tim Clarke100% (1)Introduction To Control Engineering: Andy Pomfret and Tim Clarke54 pages
- Operational Amplifiers: Theory and PracticeNo ratings yetOperational Amplifiers: Theory and Practice104 pages
- ECE311S Dynamic Systems & Control: Course Notes by Bruce Francis January 2010No ratings yetECE311S Dynamic Systems & Control: Course Notes by Bruce Francis January 2010116 pages
- Control System Theory and Design: ECE 515 Class NotesNo ratings yetControl System Theory and Design: ECE 515 Class Notes238 pages
- Starr Introduction To Applied Digital ControlNo ratings yetStarr Introduction To Applied Digital Control197 pages
- Pragmatic Electrical Engineering: Systems and InstrumentsNo ratings yetPragmatic Electrical Engineering: Systems and Instruments145 pages
- TOS - Statistics and Probability - 3rd Quarter ExaminationNo ratings yetTOS - Statistics and Probability - 3rd Quarter Examination2 pages
- Black Spot Study and Accident Prediction Model Using Multiple Liner Regression PDFNo ratings yetBlack Spot Study and Accident Prediction Model Using Multiple Liner Regression PDF16 pages
- Digital and Optimal Control Data Book: Prepared by Themistoklis Charalambous and Ammar KhanNo ratings yetDigital and Optimal Control Data Book: Prepared by Themistoklis Charalambous and Ammar Khan20 pages
- MIL 11 - 12 Q3 0102 What Is Media and Information Literacy PSNo ratings yetMIL 11 - 12 Q3 0102 What Is Media and Information Literacy PS14 pages
- Pilot Project No: CZ/02/B/F/PP/134001: Education and CultureNo ratings yetPilot Project No: CZ/02/B/F/PP/134001: Education and Culture264 pages
- Energy and Cost Savings Through Pumping Stations Rehabilitation. Case Study in BucharestNo ratings yetEnergy and Cost Savings Through Pumping Stations Rehabilitation. Case Study in Bucharest8 pages
- Class 10 - Maths - Arithmetic ProgressionsNo ratings yetClass 10 - Maths - Arithmetic Progressions51 pages
- World Vision - Education - Unlock-LiteracyNo ratings yetWorld Vision - Education - Unlock-Literacy2 pages
- Mining Industry Business Plan by SlidesgoNo ratings yetMining Industry Business Plan by Slidesgo58 pages
- (FREE PDF Sample) Rhetorical Criticism Exploration and Practice Fifth Edition. Edition Sonja K. Foss Ebooks100% (2)(FREE PDF Sample) Rhetorical Criticism Exploration and Practice Fifth Edition. Edition Sonja K. Foss Ebooks84 pages
- DVB Conditional Access System - CAS & SMS - CryptoGuard AB CryptoGuard ABNo ratings yetDVB Conditional Access System - CAS & SMS - CryptoGuard AB CryptoGuard AB7 pages
- Data Class Nist SP 1800 39a Preliminary DraftNo ratings yetData Class Nist SP 1800 39a Preliminary Draft4 pages
- S20G Low Headroom Hoist/geared Trolley CombinationNo ratings yetS20G Low Headroom Hoist/geared Trolley Combination5 pages
- Advanced Multiplayer Game Development with Ureal Engine 5: A Comprehensive Guide to C++ ScriptingFrom EverandAdvanced Multiplayer Game Development with Ureal Engine 5: A Comprehensive Guide to C++ ScriptingNo ratings yet
- The Linux Terminal for Advanced Users - The Command Line Made Easy: First EditionFrom EverandThe Linux Terminal for Advanced Users - The Command Line Made Easy: First EditionNo ratings yet
- Securing ChatGPT: Best Practices for Protecting Sensitive Data in AI Language ModelsFrom EverandSecuring ChatGPT: Best Practices for Protecting Sensitive Data in AI Language ModelsNo ratings yet
