UNIT-4

Peripheral interfacing

By:
ATIFA AQUEEL
Electronics Engg. Section
University Women’s Polytechnic, Amu
 INTRODUCTION
• A microprocessor combined with memory and I/O devices forms the
microcomputer.
• The microprocessor is the heart of microcomputer.
• The primary function of microcomputer are
1. To accept the data from input devices such as keyboard and A/D converter.
2. Read instructions from memory.
3. Process data according to the instruction.
4. Send the result to the output devices such as LEDs, Printers and video
monitors.
• These I/P and O/P devices are called either peripherals or I/Os.
• Designing logic circuits (hardware) and writing instructions (software) to
enable the microprocessor to communicate with these peripherals are known as
interfacing.
• The logic circuits are called I/O ports or interfacing devices.
 INTRODUCTION
• In microprocessor-based system the designer has to select suitable
memories and input/output devices for his task and interface them to the
microprocessor.
• The selected memories and I/O devices should be compatible with
microprocessor.
• If particular device is not compatible, an additional electronic circuit has to
be designed through which device may be interfaced to the CPU.

Memory

CPU
(Microprocessor)
I/O Port I/O devices
• The microprocessor obviously is not used as a single unit. It needs to be
linked with memory, extra peripherals, or I/O devices.
• This linking can also be called as Interfacing.
• An interface acts as a communication channel between the processor and
the externally interfaced device.
• I/O interfacing is the link between the processor or CPU and the various
I/O peripherals such as the keyboard, printer, mouse, etc. Such type of
interfacing is referred to as I/O Interfacing.
• The interfacing of the I/O devices can be done in two ways:
1. Memory-Mapped I/O Interfacing
2. Standard I/O Mapped I/O Interfacing (also known as isolated I/O
interfacing).
 I/O mapped I/O
• Every microprocessor is going to be interfaced with memory and some
external I/O devices.
• How do we access these two from the microprocessor?
• How do we, for example, store some data in the interfaced memory? Or
send some output to an interfaced device?
• We use some form of address and then transfer or output the data at that
particular address.
• That implies that these devices have an address space (say from 0000H to
FFFFH).
• The size of this address space, of course, depends on the number of pins
that are used to connect. (2^n, where n is the number of pins).
• In I/O mapped I/O or isolated I/O mapping, the I/O devices are given a
separate addressing region. Separate from what? Separate from the
memory. These separate address spaces are known as ‘Ports’.
• In 8085, we use 8-bit address lines for creating this special address space
for the I/O devices. That means that we can have an address space of 2^8 =
256 bytes (In hexadecimal, this implies a memory range from 00H to FFH.
FF is 255).
• The I/O devices which are interfaced with the processor are provided with
a ‘port number’ among the entire 8-bit address range (ranging from 00H to
FFH).
• Since there is a dedicated address region for I/Os, it makes sense to have
dedicated I/O instructions too. These I/O mapped I/Os can send/receive
data from the processor using IN and OUT commands only.
• However, none of the ALU operations can be directly applied to the data of
the I/O mapped I/O devices.
 Memory Mapped I/O?
• In memory-mapped I/O, the I/O devices are treated just like any other
memory device. No special address space and no special instructions.
• Under the Memory-mapped I/O interfacing, the processor treats the I/O
devices like any other memory location. The I/O devices are efficiently
mapped into the system memory along with the RAM and ROM memory.
These devices are assigned with a 16-bit address value within the entire
address range of the Intel 8085 Microprocessor.
• If data is to be exchanged with these devices, they follow the data transfer
instructions that we usually use when we work with memory. Thus, a user
can use the same instruction commands for data transfer to/from an I/O as
they use for memory.
• The I/O device information can also be sent to the Arithmetic Logical Unit.
The LOAD and STORE instructions are executed to read from and write to
the I/O devices, just like they are utilized for the memory.
Differences between I/O mapped I/O
and Memory-mapped I/O
 8255 Programmable Peripheral
Interface
• We know that a processor has a finite number of pins that it can use to
interface with external devices. What happens in the case of having more
I/O devices than pins? That’s where Programmable Peripheral Interface
chips come into the picture.
• The 8255 is a programmable chip used for interfacing peripheral devices. It
connects with a processor or a controller and increases the number of I/O
pins that can be used in the system. It has three 8-bit ports used to connect
I/O devices.
• What does that mean?
• That means we have 24-pins for interfacing I/O devices that are divided
into three ports. Why? For additional control and features.
• Thus, a programmable peripheral interface is a multiport device. The ports
may be programmed in a variety of ways as required by the programmer.
This device is very useful for interfacing peripheral devices.
 Features of 8255 Programmable
Peripheral Interface
• 8255 is a Programmable Peripheral Interface, available in the form of a 40
pin IC which works on a power supply of +5 V DC.
• It is compatible with a wide range of microprocessors and microcontrollers,
making it widely popular.
• It has three 8-bit I/O: Ports A, B, and C.
• Port A and port B can function as 8-bit input or output ports.
• Bits of port C are divided into two subgroups of 4 bits each – port C upper
and port C lower.
• There are other control pins which are used to specify and control the flow
of data and operation of the 8255. We’ll check them out soon.
• The port pins have the ability to source 1 mA current at 1.5 V when
programmed to function as output pins. This provides the capability of
driving Darlington transistors for applications such as printers and high
voltage displays.
 Features of 8255 Programmable
Peripheral Interface
• The most important feature of 8255 is that it is ‘programmable.’ This
means that the operation of 8255 can be controlled by programming the
microprocessor appropriately. This gives us the freedom to use 8255 in a
number of ways without having to change the wiring and connections.
• It has a few different modes of operation. This is awesome because we get
the freedom to choose from a bunch of different functionalities.
 Programmable Peripheral Interface
(8255 PPI)
• PPI 8255 is a general purpose programmable I/O device designed to
interface the CPU with its outside world such as ADC, DAC, keyboard etc.
• We can program it according to the given condition. It can be used with
almost any microprocessor.
• The block diagram of Intel 8255 PPI is shown in figure.
• It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and
PORT C. We can assign different ports as input or output functions.
• Port C is further divided into two 4-bit ports i.e. Port C lower (PC3-PC0)
and Port C upper (PC7-PC4).
• Port C can work in either BSR (bit set reset) mode or in mode 0 of input-
output mode of 8255.
• Port B can work in either mode 0 or in mode 1 of input-output mode.
• Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.
Block Diagram (8255 PPI)
• The data bus buffer is used to interface the internal data bus of 8255 to the
system data bus by reading and writing operations.
• It has two control groups, control group A and control group B.
• Control group A consist of port A and port C upper. Control group B consists
of port C lower and port B.
• There are separate control units for Group A and Group B that get their control
signals from the main read-write logic control logic block. The control logic
receives individual control signals as inputs and responds accordingly.
• Group A control and Group B control blocks are connected to their respective
Group blocks. They control the flow of data and modes of operation at those
ports.
• Controls of group A and group B, represented by the control blocks ‘group A
control‘ and ‘group B control‘ together make up ‘the control port.’
• This port is used to specify the modes of operations and is manipulated by the
microprocessor (by writing control word). Hence, these two blocks are
connected by the data bus in the above diagram.
• These control blocks play a crucial role as they ensure that ports can be used in
a number of ways. Hence, 8255 gives a lot of freedom and control to the user
• Read/write control logic accepts the input from the address bus and issues
commands to the individual group blocks. also issues appropriate enabling
signals to access the required data/control words/status words.
• Depending upon the value if 𝐶𝐶𝐶𝐶, A1 and A0 we can select different ports in
different modes as input-output function or BSR. This is done by writing a
suitable word in control register (control word D0-D7).
 Control port and control word in 8255
• The fourth port of the 8255 is the control port.
• As you would have noticed in the pin diagram, there are no pins for this
port. This is because the control port is not supposed to be used for input or
output purposes. This port is used by the microprocessor to give
instructions to 8255 about the modes in which it wants to use a specific I/O
port.
• Note: The data written at the control port by the microprocessor sets the
modes of operation and is called the Control Word.
• To communicate with this port, the microprocessor needs to make the
inputs at A1 and A2 to be both high.
• When both of these are high, 8255 knows that the microprocessor is telling
it about the modes of the I/O ports that need to be chosen.
• There are two major modes of operation.
• I/O Mode: Ports A, B, and C are used as 8-bit I/O ports.
• Bit Set-Reset (BSR) Mode: The bits of port C can also be used as
individual I/O bits and can be set and reset individually.
Schematic diagram

𝑹𝑹𝑹𝑹

WR

𝑪𝑪𝑪𝑪

Interfacing 8255 with 8085 Microprocessor

PIN DIAGRAM OF 8255 PPI
• D7-D0 (Data bus): These are bidirectional, tri-state data bus lines are connected to the
system data bus. They are used to transfer data and control word from microprocessor
(8085) to 8255 or receive data or status word from 8255 to the 8085.
• PA0-PA7 (Port A): These are 8 Bit bidirectional I/O pins used to send data to output
device and to receive data from input device. It functions as an 8 Bit data output
latch/buffer when used in output mode and as an 8 Bit data input latch/buffer when
used in input mode.
• PB0-PB7 (Port B) : These are 8 Bit bidirectional I/O pins used to send data to output
device and to receive data from input device. It functions as an 8 Bit data output
latch/buffer when used in output mode and as an 8 Bit data input latch/buffer when
used in input mode.
• PC0-PC7 (Port C) : These are 8 bit bidirectional I/O pins divided into two groups
PCL (PC3-PC) and PCU (PC7- PC4).these groups can individually transfer data in or
out when programmed for simple I/O, and used as handshake signals when
programmed for handshake or bidirectional modes.
• 𝑹𝑹𝑹𝑹: When this pin is low, the CPU can read data in the ports or the status word
through the data bus buffer.
• 𝑾𝑾𝑾𝑾: When this pin is low, the CPU can write data on the ports or in the control
register through the data bus buffer.
• 𝑪𝑪𝑪𝑪: This pin can be enabled for data transfer operation between the CPU and 8255.
• RESET: This pin is used to reset 8255.i.e control register gets cleared and
all the ports are set to the input mode.
• A0-A1 (Address bus): The selection of input port and control word
register is done by using A0 and A1 pins in conjunction with 𝑅𝑅𝑅𝑅and 𝑊𝑊𝑊𝑊
pins.
 Operating Modes Of 8255
• There are two main operational modes of 8255:
1. Input/output mode,
2. Bit set/reset mode (BSR Mode).
• Input-Output mode –
If MSB of control word (D7) is 1, PPI works in input-output
mode. I/O mode again classified into three types
1. Mode 0,
2. Mode 1,
3. Mode 2.
 Mode 0 (Simple Input/Output)
• In this mode, the ports can be used for simple input/output operations
without handshaking.
• If both port A and B are initialized in mode 0, the two halves of port C can
be either used together as an additional 8-bit port, or they can be used as
individual 4-bit ports.
• Since the two halves of port C are independent, they may be used such that
one-half is initialized as an input port while the other half is initialized as
an output port.
• The mode 0 has following features:
• O/p are latched.
• I/p are buffered not latched.
• Port do not have handshake or interrupt capability.
• This is the simplest mode of operation.
• In this mode, the I/O device cannot tell the microprocessor that it wants to
read data or give data to the microprocessor. Hence, the microprocessor
should know when to read and when to write data.
• The I/O device reads or writes data when it wants to.
• Similarly, the microprocessor reads or writes data according to the way we
programmed it.
• There is no communication between the I/O device and the microprocessor.
• From the above information, we can say that this mode is used for I/O
devices whose timing characteristics are already known. For example, we
can use this mode for an input device that wants to provide us with input
every 0.5 seconds. So we program the microprocessor to read from that
device after every 0.5 seconds without the input device actually telling the
microprocessor that it wants to send data.
• This mode can be applied when we need to read switch settings or
temperature readings from a sensor. In such cases, the readings are always
present at the input port. The microprocessor reads them when it requires
the data for processing.
 Mode 1 (Handshake I/O mode or
Strobbed I/O mode.)
• This mode uses handshaking to make the exchange of data more efficient.
But what is handshaking?
• In mode 1 and mode 2 operations of I/O ports, the I/O device and the
processor can communicate with each other apart from the exchange of
input and output data. It goes down like this:
• When the input device writes data at a port, it tells the port that new data
has entered. The port then informs the microprocessor that new unread
data is there at the port. When the microprocessor is done reading the data,
the port informs the input device that the data on the port is read and new
data can be entered. This communication happens using the ‘handshaking
signals’.
• This above process is referred to as ‘handshaking.’ It is named so because it
is similar to the handshaking between two strangers before they start
talking to each other.
• The lines of port C are used for handshaking signals. Thus, only port A and
port B can work in mode 1, while port C provides handshake signals.
• In this mode either port A or port B can work as simple input port or simple
output port, and port C bits are used for handshake signals before actual data
transmission
• In this mode six pins of port C are used for handshaking or as control bits as
shown on fig.
• For port B in this mode (irrespective of whether is acting as an input port or
output port), PC0, PC1 and PC2 pins function as handshake lines.
• If port A is operated as input, PC3, PC4 and PC5 pins are used as handshake
lines.
• The remaining pins of port C i.e. PC6 and PC7can be used either input or
output.
• If port A is operated as output, PC3, PC6 and PC7 pins are used as handshake
lines.
• The remaining pins of port C i.e. PC4 and PC5 can be used either input or
output.
Mode 1: Input Mode 1: Output
 MODE 1 INPUT

𝑆𝑆𝑆𝑆𝑆𝑆
𝑅𝑅𝑅𝑅

8085 8255 PPI PA Input Device

Microprocessor D0-D7

INTR IBF
 STEPS
• Step 1
Whenever there is new input data, there is a low going pulse on the active-low signal pin
STB*, which exists for at least 500 ns. It indicates that there is new input data. Since there is
new input data, the data is stored in the input buffer until it is read.
• Step 2
To indicate that the input buffer is occupied by the unread input data, the IBF signal goes
high. This happens after a maximum of 300 ns of starting of the pulse at STB*.
• Step 3
During all this, the data from the peripheral is available at the input port. And it is supposed to
be available for at least 180 ns after the end of the STB* pulse. It is shown in the timing
diagram above.
• Step 4
Within 300 ns of the ending of STB* pulse, the INT signal goes high, interrupting the
microprocessor. The microprocessor should be programmed to read the data from the port
using IN instruction on receiving this interrupt signal.
• Step 5
As the microprocessor takes action (reads the data from the input port) when it is interrupted,
the RD* signal goes low, indicating the read operation at the port.
• Step 6
When 8255 gets RD* signal, it knows that data at the port is being read, and after the end of
RD* signal within a maximum of 300 ns, the INT signal goes low too.
 MODE 1 OUTPUT

𝐴𝐴𝐴𝐴𝐴𝐴
𝑊𝑊𝑊𝑊

8085 8255 PPI PA Input Device

Microprocessor D0-D7

INTR OBF
 STEPS
• Step 1
When output devices want to read data, it reads from the output buffer and sends a low going pulse to the
active low input pin ACK*, indicating that it has received the output data. This pulse is at least 300 ns in
width.
• Step 2
After a maximum of 350 ns from the start of the ACK* pulse, OBF* system goes from 0 to 1 (from active
to inactive), indicating that the data in the buffer has been read and it no more contains new data.
• To visualize properly, refer to the above timing diagram for every step.
• Step 3
After a maximum of 350 ns from the end of the ACK* pulse, the INT signal goes high. By doing this, 8255
interrupts the microprocessor and tells it that “the data at the output buffer has been read and you need to
write new data into it before the output device needs new data.
• Step 4
After getting the interrupt signal from 8255, the microprocessor will take proper action (service the
subroutine for that particular interrupt) and write data on the output port. The data will be stored in the
output buffer. For writing this data, the input signal to 8255 WR* goes low, indicating that a write operation
takes place.
• Step 5
Now, since the write operation has taken place and the new data has not been read by the output device yet,
there is no need for the INT signal to be high. So, the INT signal goes low after a maximum of 850
nanoseconds from the activation of WR* signal (or from the start of the WR* pulse, as you can observe
from the timing diagram).
• Step 6
Also, since there is unread data at the output buffer, the OBF* signal should also become 0. The OBF*
signal goes from high to low after a maximum of 650 ns from the end of WR* pulse.
 Mode 2 (Strobbed bidirectional mode)
• Only group A can be initialized in this mode.
• Port A can be used for bidirectional handshake data transfer. This means
that data can be input or output on the same eight lines (PA0 - PA7).
• Five pins of port C i.e. PC3 - PC7 are used as handshake lines for port A.
• The remaining pins of port C (PC0 - PC2) can be used as simple
input/output lines if port B is initialized in mode 0 or handshake for Port B
if port B is initialized in mode 1.

PC2
PC1
I/O Modes of 8255
 CONTROL WORD
• 8255 ports can be programmed to act either as an input port or an output
port.
• For programming the ports of 8255 a control word is formed.
• Control word is written in control word register which is present within
8255.
• No read operation of the control word register is allowed.
• The control word bits corresponding to particular port is set or reset
according to the requirements whether it is to be made input or output port.
• To program 8255 a user must know how to write the control word..
• The method to write the control word is shown on next slide
 Control Word Format in I/O Mode

• This mode is selected when the most

significant bit (D7) in the control register is
1.
• It has three modes:
• Mode 0: Simple Input/output.
• Mode 1 : Handshake or strobbed I/O
• Mode 2: Bidirectional I/O
 Control Word Format in BSR Mode

• Bit Set Reset (BSR) mode – This mode is used to set or reset the bits of
port C only, and selected when the most significant bit (D7) in the control
register is 0. Control register is given below.
• This mode affects only one bit of port C at a time because, as user set the
bit, it remains set until and unless user changes it. User needs to load the bit
pattern in control register to change the bit.
• The bits in this mode doesn’t affect the functionality of I/O mode.

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
 Numericals
1. Find the control word for the register arrangement of the ports of
intel 8255 for mode 0 operation.
• Port A: Input, Port B: Input,
• Port CU: Input, Port CL: Input
Solution:
D7 D6 D5 D4 D3 D2 D1 D0 Bit No.
1 0 0 1 1 0 1 1 Control Word
Bits = 9BH
2. Write control word for mode 1 Output.
Solution:

D7 D6 D5 D4 D3 D2 D1 D0 Bit No.
1 0 1 0 0 1 0 0 Control Word
Bits = A4H
3. Make control word for the following configuration of the ports of Intel
8255 for mode 1 operation.
• PORT A-INPUT
• PORT B-OUTPUT
• Remaining pins of port C upper- INPUT
D7 D6 D5 D4 D3 D2 D1 D0 Bit No.
1 0 1 1 1 1 0 X Control Word
Bits
4. Write a program to initialize 8255 in the configuration below.(assume
address of the CW register as 23H). (1) Port A: output with handshake (2)
Port B: input with handshake (3) Port CL: output (4)Port CU: input

D7 D6 D5 D4 D3 D2 D1 D0 Bit No.
1 0 1 0 1 1 1 0 Control Word
Bits= AEH

PROGRAM: MVI A,AEH ; LOAD CONTROL WORD

OUT 23H ; SEND CONTROL WORD
 What is DMA and Why it is used?
• Direct memory access (DMA) is a mode of data transfer between the memory
and I/O devices. This happens without the involvement of the processor. We
have two other methods of data transfer, programmed I/O and Interrupt
driven I/O.
• In programmed I/O, the processor keeps on scanning whether any device is
ready for data transfer. If an I/O device is ready, the processor fully
dedicates itself in transferring the data between I/O and memory. It transfers
data at a high rate, but it can’t get involved in any other activity during data
transfer. This is the major drawback of programmed I/O.
• In Interrupt driven I/O, whenever the device is ready for data transfer, then it
raises an interrupt to processor. Processor completes executing its ongoing
instruction and saves its current state. It then switches to data transfer which
causes a delay. Here, the processor doesn’t keep scanning for peripherals ready
for data transfer. But, it is fully involved in the data transfer process. So, it is
also not an effective way of data transfer.
• The above two modes of data transfer are not useful for transferring a large
block of data. But, the DMA controller completes this task at a faster rate and is
also effective for transfer of large data block.
 DMA DATA TRANSFER
• Generally in microprocessor, the transfer of information between the I/O
device and the mass storage device/memory is via the Accumulator register.
But if there is a bulk amount of data to be transferred between the I/O
device and the microprocessor, then these methods are unworthy of the
investment being put into them, and even time – consuming.
• To overcome such circumstances, the Direct Memory Access Data Transfer
is put into use. This is an ideal method used for data transfer of a
considerable amount between the microprocessor and the I/O device.
• The Direct Memory Access or DMA mode of data transfer the fastest data
transfer scheme.
• In this mode the device may transfer data directly to/from memory without
any interference from the microprocessor.
• In program controlled I/O or Interrupt driven I/O the speed of data transfer
is slow mainly because instructions need to be decoded and then executed
transfer.
• DMA transfers a software independent and hence much faster.
• A device known as DMA controller or DMAC is responsible for the DMA
transfer.
• In the DMA scheme, the data is transferred between the I/O device (or
DMA controller, a special IC) and the external memory directly without
having any interference by the accumulator register.
• The processor gives up its control over the address bus as well as the data
bus to the I/O device or DMA controller, thus aiding the exchange of
information between the source and the destination directly.
DMA DATA TRANSFER
 We will now understand the working principle of the Direct
Memory Access Data Transfer method.

• First of all, we need to inform the microprocessor before beginning the process.
For this, an I/O device first sends a request to a DMA controller using the
DMARQ signal, which in turn forwards it to the processor in the form of a
HOLD signal.
• Once such a request is received by the microprocessor, it ceases its control over
the address bus and data bus. It then informs the DMA Controller of the
situation by sending an acknowledgment signal using the HLDA command.
• The controller then informs the external peripheral by sending a DMACK
signal.
• The DMA controller then gains control over the two buses and monitors the
transfer of information between the two locations (Memory and I/O).
• Once the entire data transfer between the I/O device and the external memory
gets over, the DMA Controller withdraws its request for using the data and
address bus by disabling the HOLD and DMACK signals, and thus the
microprocessor gains control over them again.
 8257- DMA CONTROLLER
• DMA stands for Direct Memory Access.
• It is designed by Intel to transfer data at the fastest rate.
• It allows the device to transfer the data directly to/from memory without
any interference of the CPU.
• DMA transfer is hardware controlled I/O transfer scheme.
• In programmed controlled I/O, status or interrupt driven I/O the speed of
transfer is slow mainly because instructions need to be decoded and then
executed for the transfer.
• DMA transfer is software independent and hence much faster.
• A device known as DMA controller (DMAC) is responsible for DMA
transfer.
• Using a DMA controller, the device requests the CPU to hold its data,
address and control bus, so the device is free to transfer data directly
to/from the memory.
• The DMA data transfer is initiated only after receiving HLDA signal from
the CPU.
 Block Diagram
8257-DMA Controller
 Features of 8257
• Intel 8257 is a programmable 4-channel DMA controller, so it can be used to
provide DMA to four I/O devices and their request priorities are determined
internally.
• Each channel has one 16 bit address register (to store the starting address for the
transfer) and one 14 bit count register (to store the number of bytes to be
transferred)
• The remaining two msbs of the count register give the type of DMA operation:

S.No. Bit 15 Bit 14 Type of DMA operation

1 0 0 Verify or Initialize DMA cycle

2 0 1 Write DMA cycle
3 1 0 Read DMA cycle
4 1 1 Invalid (Don’t care)

• Each channel can transfer data up to 64kb.

• Each channel can be programmed independently.
 Features of 8257
• Each channel can independently perform read transfer, write transfer and
verify transfer operations.
• It generates MARK signal to the peripheral device that 128 bytes have been
transferred.
• DMAC is a 40 pin IC.
• The process of data transfer from the peripheral to the memory under the
DMA controller can be classified in two modes i.e. Master
mode and Slave mode.
SLAVE MODE: In this mode the DMA controller is treated as a peripheral
and performs the following steps:
• The microprocessor selects the DMA controller chip through 𝐶𝐶𝐶𝐶
• Microprocessor initializes the DMAC by giving the starting address to the
16 bit address register and number of bytes to be transferred to the 14 bit
count register with the help of control signals 𝐼𝐼𝐼𝐼𝐼𝐼 and 𝐼𝐼𝐼𝐼𝑊𝑊.

MASTER MODE: After initialization the 8257 enters in master mode and
continuously checking the DMA request from the peripheral and perform the
following steps:
• When the I/O device is ready for data transfer, it sends a DMA request
signal to the DMAC through DREQ line.
• The DMA in turn sends a request signal to the µP through the HOLD line.
• The µP finishes the current machine cycle and releases the system bus
(disconnected from it) and acknowledge the I/O device by sending a signal
through HLDA line.
• After receiving the HLDA signal the DMA controller acknowledge the I/O
device by sending a low signal on 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷. In the mean time the 8257 make
use of AEN and ADSTB signals to take control over buses. After that the
DMA transfer begins.
• After every byte is transferred, the address register is incremented and the
count register decremented.
• This continues till the count reaches zero (Terminal Count=1). Now the
DMA transfer is completed.
• At the end of the transfer, the system bus is released by the DMAC by
making the HOLD=0. Then µP takes control over the system buses and
continues its operation.
 Direct Memory Access Diagram
• After exploring the working of DMA controller, let us discuss the block
diagram of the DMA controller. Below we have a block diagram of DMA
controller.
• Whenever a processor is requested to read or write a block of data, i.e.
transfer a block of data, it instructs the DMA controller by sending the
following information.
• The first information is whether the data has to be read from memory or the
data has to be written to the memory. It passes this information via read or
write control lines that is between the processor and DMA
controllers control logic unit.
• The processor also provides the starting address of/ for the data block in
the memory, from where the data block in memory has to be read or where
the data block has to be written in memory. DMA controller stores this in
its address register. It is also called the starting address register.
• The processor also sends the word count, i.e. how many words are to be
read or written. It stores this information in the data count or the word
count register.
• The most important is the address of I/O device that wants to read or write
data. This information is stored in the data register.
 8257 Pin Description
• DRQ0−DRQ3: These are the four individual channel DMA request inputs,
which are used by the peripheral devices for using DMA services.
• DACK0 − DACK3: These are the active-low DMA acknowledge lines,
which updates the requesting peripheral about the status of their request by
the CPU.
• Do − D7: These are bidirectional, data lines which are used to interface the
system bus with the internal data bus of DMA controller.
• IOR: It is an active-low bidirectional tri-state input line, which is used by
the CPU to read internal registers of 8257 in the Slave mode. In the master
mode, it is used to read data from the peripheral devices during a memory
write cycle.
• IOW: It is an active low bi-direction tri-state line, which is used to load the
contents of the data bus to the 8-bit mode register or upper/lower byte of a
16-bit DMA address register or terminal count register. In the master mode,
it is used to load the data to the peripheral devices during DMA memory
read cycle.
• CLK: It is a clock frequency signal which is required for the internal
operation of 8257
• RESET: This signal is used to RESET the DMA controller by disabling all
the DMA channels.
• Ao - A3: These are the four least significant address lines. In the
slave mode, they act as an input, which selects one of the registers to
be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.
• CS: It is an active-low chip select line. In the Slave mode, it enables
the read/write operations to/from 8257. In the master mode, it
disables the read/write operations to/from 8257.
• A4 - A7: These are the higher nibble of the lower byte address
generated by DMA in the master mode.
• READY: It is an active-high asynchronous input signal, which
makes DMA ready by inserting wait states.
• HRQ: This signal is used to receive the hold request signal from the
output device. In the slave mode, it is connected with a DRQ input
line 8257. In Master mode, it is connected with HOLD input of the
CPU.
• HLDA: It is the hold acknowledgement signal which indicates the
DMA controller that the bus has been granted to the requesting
peripheral by the CPU when it is set to 1.
• MEMR: It is the low memory read signal, which is used to read the data
from the addressed memory locations during DMA read cycles.
• MEMW: It is the active-low three state signal which is used to write the
data to the addressed memory location during DMA write operation.
• ADSTB: This signal is used to convert the higher byte of the memory
address generated by the DMA controller into the latches.
• AEN: This signal is used to disable the address bus/data bus.
• TC: It stands for ‘Terminal Count’, which indicates the present DMA cycle
to the present peripheral devices.
• MARK: The mark will be activated after each 128 cycles or integral
multiples of it from the beginning. It indicates the current DMA cycle is the
128th cycle since the previous MARK output to the selected peripheral
device.
• Vcc: It is the power signal which is required for the operation of the circuit.
 INTRODUCTION
• 8086 Microprocessor is an enhanced version of 8085Microprocessor that
was designed by Intel in 1976.
• It is a 16-bit Microprocessor having 16-bit data bus. It can read or write
data to a memory or port either 16 bits or 8 bit at a time.
• 8086 has 20 bit address bus which means it can address up to 220 = 1MB
memory location.
• It consists of powerful instruction set, which provides operations like
multiplication and division easily.
• It supports two modes of operation, i.e. Maximum mode and Minimum
mode.
• Maximum mode is suitable for system having multiple processors and
Minimum mode is suitable for system having a single processor.
 FEATURES OF 8086
The most prominent features of a 8086 microprocessor are as follows −
• It has an instruction queue, which is capable of storing six instruction bytes
from the memory resulting in faster processing.
• It was the first 16-bit processor having 16-bit ALU, 16-bit registers,
internal data bus, and 16-bit external data bus resulting in faster processing.
• It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which
improves performance.
• Fetch stage can pre-fetch up to 6 bytes of instructions and stores them in
the queue.
• Execute stage executes these instructions.
• It has 256 vectored interrupts.
• It consists of 29,000 transistors.
 COMPARISON BETWEEN 8085 & 8086
MICROPROCESSOR
• Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit
microprocessor.
• Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address
bus.
• Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1
Mb of memory.
• Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an
instruction queue.
• Pipelining − 8085 doesn’t support a pipelined architecture while 8086
supports a pipelined architecture.
• I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 =
65,536 I/O's.
• Cost − The cost of 8085 is low whereas that of 8086 is high.
Architecture of 8086 Microprocessor
 Architecture of 8085 Microprocessor:
Functional Units
• 8086 Microprocessor is divided into two functional units, i.e., EU (Execution
Unit) and BIU (Bus Interface Unit).
1. Bus Interfacing Unit (BIU)
2. Execution Unit (EU)
• Bus Interfacing Unit (BIU):
• It provides the interface of 8086 to external memory and I/O devices.
• It performs all the bus operations such as instruction fetching, reading and
writing operands for memory and calculating the addresses of the memory
operands.
• BIU performs the following functions-
– It generates the 20 bit physical address for memory access.
– It fetches instruction from memory.
– It transfers data to and from the memory and I/O.
– It supports pipelining using the 6 byte instruction queue.
• The main components of the BIU are as follows:
• Segment registers-
1. CS register: CS holds the base address for the Code Segment. All programs
are stored in the Code Segment. CS is multiplied by 10H to give the 20 bit
physical address of the Code Segment. E.g. If CS = 4321H then CS x 10H =
43210H→ Starting address of Code Segment.
2. DS register: DS holds the base address for the Data Segment. It consists of
data used by program. It is multiplied by 10H to give the 20 bit physical
address of the Data Segment. E.g. If DS = 4321H then DS x 10H =
43210H→ Starting address of Data Segment.
3. SS register: SS holds the base address for the Stack Segment. It handles
memory to store data and addresses during execution. It is multiplied by 10H
to give the 20 bit physical address of the Stack Segment. E.g. If SS = 4321H
then SS x 10H = 43210H→ Starting address of Stack Segment.
4. ES register: ES holds the base address for the Extra Segment. It is used to
hold the extra destination data. It is multiplied by 10H to give the 20 bit
physical address of the Extra Segment. E.g. If ES = 4321H then ES x 10H =
43210H→ Starting address of Code Segment.
• Instruction Pointer (IP)-
– It is a 16 bit register. It holds offset of the next instructions in the Code
Segment.
– Address of the next instruction is calculated as CS x 10H + IP.
– IP is incremented after every instruction byte is fetched.
– IP gets a new value whenever a branch occurs.
• Address Generation Circuit-
– The BIU has a Physical Address Generation Circuit. It generates the 20
bit physical address using Segment and Offset addresses using the
formula: Physical Address = Segment Address x 10H + Offset Address.
• Instruction queue − BIU contains the instruction queue. BIU gets up to 6
bytes of next instructions and stores them in the instruction queue. When
EU executes instructions and is ready for its next instruction, then it simply
reads the instruction from this instruction queue resulting in increased
execution speed.
• Fetching the next instruction while the current instruction executes is
called pipelining.
 Execution Unit (EU)
• It fetches instructions from the Queue in BIU, decodes and executes them.
• It performs arithmetic, logic and internal data transfer operations within the
microprocessor.
• It sends request signals to the BIU to perform the read or write cycles to
memory or I/O and perform the operation specified by the instruction on
the operands.
• It operates with respect to T-stats (clock cycles) and does not depend upon
which machine cycle is being performed by the BIU.
• The main components of the EU are as follows:
• General purpose registers- 8086 microprocessor has four 16 bit
general purpose registers AX, BX, CX and DX. These are available
to the programmer for storing values during programs. Each of these
can be divided into two 8 bit registers such as AH, Al; BH, BL; etc.
Beside their general use, these registers also have some specific
functions.
• AX register (16 bits): It holds operands and results during
multiplication and division operations. All I/O data transfers
using IN and OUT instructions use A register (AL/AH or AX). It
functions as accumulator during string operations.
• BX register (16 bits): It holds the memory address (offset
address) in indirect addressing modes.
• CX register (16 bits): It holds count for instructions like loop,
rotate, shift and string operations.
• DX register (16 bits): It is used with AX to hold 32 bit values
during multiplication and division. It is used to hold the address
of the I/O port in indirect I/O addressing mode.
• Special purpose registers-
• Stack Pointer (SP 16 bits): It holds offset address of the top of the Stack.
Stack is a set of memory locations operating in LIFO manner. Stack is
present in the memory in Stack Segment. It is used during instructions like
PUSH, POP, CALL, RET etc.
• Base Pointer (BP 16 bits): BP can hold offset address of any location in
the stack segment. It is used to access random locations of the stack.
• Source Index (SI 16 bits): It is normally used to hold the offset address for
Data Segment but can also be used for other segments using Segment
Overriding. It holds offset address of source data in Data Segment during
string operations.
• Destination Index (DI 16 bits): It is normally used to hold the offset
address for Extra Segment but can also be used for other segments using
Segment Overriding. It holds offset address of destination in Extra Segment
during string operations.
• ALU (Arithmetic Logic Unit) - It has a 16 bit ALU. It performs 8 and 16
bit arithmetic and logic operations.
• Operand register- It is a 16 bit register used by the control register to hold
the operands temporarily. It is not available to the programmer.
• Instruction Register and Instruction Decoder- The EU fetches an
opcode from the queue into the instruction register. The instruction decoder
decodes it and sends the information to the control circuit for execution.
• Flag register (16 bits)-
– It has 9 flags.
– These flags are of two types: 6 Status flags namely carry flag, parity
flag, auxiliary carry flag, zero flag, sign flag and 3 Control flags
namely trap flag, interrupt flag and direction flag.
– Status flags are affected by the ALU after every arithmetic or logic
operation. They give the status of the current result.
– The Control flags are used to control certain operations. They are
changed by the programmer.
• Status Flags
• It represents the result of the last arithmetic or logical instruction executed.
Following is the list of conditional flags −
• Carry flag − This flag indicates an overflow condition for arithmetic
operations.
• Auxiliary flag − When an operation is performed at ALU, it results in a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 –
D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The
processor uses this flag to perform binary to BCD conversion.
• Parity flag − This flag is used to indicate the parity of the result, i.e. when
the lower order 8-bits of the result contains even number of 1’s, then the
Parity Flag is set. For odd number of 1’s, the Parity Flag is reset.
• Zero flag − This flag is set to 1 when the result of arithmetic or logical
operation is zero else it is set to 0.
• Sign flag − This flag holds the sign of the result, i.e. when the result of the
operation is negative, then the sign flag is set to 1 else set to 0.
• Overflow flag − This flag represents the result when the system capacity is
exceeded.
• Control Flags
• Control flags controls the operations of the execution unit. Following is the
list of control flags −
• Trap flag − It is used for single step control and allows the user to execute
one instruction at a time for debugging. If it is set, then the program can be
run in a single step mode.
• Interrupt flag − It is an interrupt enable/disable flag, i.e. used to
allow/prohibit the interruption of a program. It is set to 1 for interrupt
enabled condition and set to 0 for interrupt disabled condition.
• Direction flag − It is used in string operation. As the name suggests when
it is set then string bytes are accessed from the higher memory address to
the lower memory address and vice-a-versa.