10/22/2023

CS 207 Computer Organization and Architecture

(Section-B)

Central Processing Unit

CPU Organization
A instruction is of various length depending upon the number of addresses it contain.
Generally CPU organization are of three types on the basis of number of address fields:
• Single accumulator organization
• General register Organization
• Stack organization

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Single Accumulator Organization

Example: 1
One-Address Instructions:
• Instruction format requires only one
address field.
• One address can be a register name or
memory address.
• It uses implied AC register for all data Example: 2 X = (A+B)*(C+D)
manipulation. One operand is in
accumulator and other is in register or
memory location.
• Implied means that the CPU already
know that one operand is in
accumulator so there is no need to
specify it.

General register Organization

Instruction format requires two or three address fields.
Two address instruction format: Three address instruction format:
• Specify either two registers or one • Two registers and one memory or
register and a memory location. three registers and two memory
Assumes that the destination address is locations and one register are
the same as that of the first operand specified.
Example 1: • Assumes that the destination address is
ADD R1 , R2 the same as that of the first operand
Micro-operation: R1 R1+R2 Example 1:
ADD R1 , R2 , R3
Example 2: X = (A+B)*(C+D)
Micro-operation: R1 R2+R3
Example 2:
X = (A+B)*(C+D)

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Stack Organization
• The computers which use Stack-based CPU Organization are
based on a data structure called stack. The stack is a list of
data words. It uses Last In First Out (LIFO) access method
which is the most popular access method in most of the CPU.
• A register is used to store the address of the topmost element
of the stack which is known as Stack pointer (SP).
• In this organization, ALU operations are performed on stack
data. It means both the operands are always required on the
stack. After manipulation, the result is placed in the stack.
Zero Address instructions:
• Can be found in a stack-organized computer.
Push Operation: Pop Operation:

Stack Organization
• A stack based computer do not use address field in instruction. To evaluate a expression
first it is converted to revere Polish Notation i.e. Post fix Notation.
• Expression: X = (A+B)*(C+D)
• Postfix : X = AB+CD+*
• TOS means top of stack
• M[X] is any memory location

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Problem and Discussion

Addressing Modes
• Addressing modes are the ways by which the operand of an instruction is
specified. It is a rule for interpreting or modifying the address field of the
instruction before the operand is actually executed.
• Implied Mode: (Stack Oriented Addressing Mode)
 Operands implicitly specified in the definition of the instruction.
 All register reference instruction that use accumulator are implied-mode
instruction.
 Zero address instructions in a stack organized computer are implied mode
instructions.
Example: CLA, CMA, INC,CLE

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Addressing Modes
• Immediate Mode:
• Operands is specified in the instruction itself.
• Immediate mode instruction has an operand field rather
than an address field.
• Useful for initializing registers to a constant value.
• Operand field: Actual Operand + Operation
Example: 1
MOV AL, 35H (move the data 35H into AL register)
ADD, 7

Addressing Modes
• Register Mode:
• Operands are in Registers that reside with in the CPU.
• Any one of 2k Registers are selected from the k-bit of the
register field in the instruction.
Example: AC ← AC + [R]

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Addressing Modes
• Register Indirect Mode:
• Instruction specifies a register in the CPU whose
content give the address of the operand in the memory.
• Selected register contains the address of the operand
rather than the operand itself.
• Example: AC ← AC + M[R]

Addressing Modes
• Auto-increment or Auto-decrement Mode:
• Register is incremented (after) or decremented (before) its value is used to
access memory (the execution of the instruction).
• Special mode that automatically increments or decrements the register
content.
• Add R1, -(R2) // OR R2 = R2 - d , R1 = R1 + M[R2]
• Add R1, (R2)+ // OR R1 = R1 +M[R2], R2 = R2 + d

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Addressing Modes
• Direct Addressing Mode:
• The operand resides in memory and its address is given
directly by the address field of the instruction (Effective
address).
• Single memory reference to access data.
• Effective address is equal to the address part of the
instruction.

Example: ADD R1, 4000

Addressing Modes
• Indirect Address Mode:
• Address field of the instruction gives the address where the
effective address is stored in memory.
• Two references to memory are required to fetch the
operand.

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Addressing Modes
• Displacement addressing Mode:
• In this the contents of the indexed register is added to the Address part of the
instruction, to obtain the effective address of operand.
• EA = A + (R), In this the address field holds two values, A(which is the base
value) and R(that holds the displacement), or vice versa.

Addressing Modes
• Relative Addressing Mode:
• It is a modified version of Displacement addressing mode.
• In this the contents of PC(Program Counter) is added to address part of
instruction to obtain the effective address.
• EA = A + (PC), where EA is effective address and PC is program counter.
(Relative to the address of the next instruction).
• The operand is A cells away from the current cell (the one pointed to by PC)

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Addressing Modes
• Base register addressing mode:
• It is again a version of Displacement addressing mode.
• Effective address : address part of the instruction + content of a
base register.
• This can be defined as EA = A + (R), where A is displacement
and R holds pointer to base address.

Problem and Discussion

In this figure, two-word instruction at address 201 and 201 is a load to AC instruction with
an address field equal to 500. Determine the effective address and the content of AC.
Addressing Mode:
Direct Address:
Immediate Operand:
Indirect address:
Relative address:
Indexed address: Register:
Register indirect:
Auto-increment:
Auto-decrement:

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CS 207 Computer Organization and Architecture

(Section-B)

Pipelining

Parallel Processing
 Arrange the hardware such that more than one operation can be performed
at the same time.
 Provide simultaneous data-processing tasks to increase the computational
speed of a computer system.
 Instead of processing each instruction sequentially as in a conventional
computer, a parallel processing system is able to perform concurrent data
processing to achieve faster execution time and its throughput.

– Pipeline processing
– Vector Processing
– Array Processing

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Pipelining
• It is a process of arrangement of hardware elements of the
CPU such that its overall performance is increased.
• Simultaneous execution of more than one instruction takes
place in a pipelined processor.
• To increase their instruction throughput (the number
of instructions that can be executed in a unit of time).

Laundry example
Washer takes 30 minutes, Drier takes 40 minutes, Folder takes 20 minutes.

Total time required =360 minutes.

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Laundry example: Pipelining

Washer takes 30 minutes, Drier takes 40 minutes, Folder takes 20 minutes.

Total time required =210 minutes!!!...

Pipelining

A technique of decomposing a sequential process into sub-

operations, with each sub-process being executed in a special
dedicated segment that operates concurrently with all other
segments.

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Pipelining Example: Problem

• Suppose we need to perform multiply and add operation with a
stream of numbers

• Each sub-operation is implemented in a segment within the

pipeline.
• Each segment has one or two registers and a combinational circuit.
• The sub-operations performed in each segment of the pipeline are
as follows:

Pipelining: Hardware Realization

Clock

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Contents of registers in Pipelining Example

Arithmetic Pipeline

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Arithmetic Pipeline
 It is used to implement floating-point operations, multiplications of fixed-point
numbers, and similar computations encountered in scientific problems.
 It is found in very high speed computers.
 Pipeline unit for floating-point addition and subtraction.

 The inputs to the floating-point adder pipeline are two normalized floating-
point binary numbers.

Here, A and B are two fractions that represent the mantissas and a and b are the
exponents.

The floating-point addition and

subtraction can be performed in four
segments.
The registers labeled R are placed
between the segments to store
intermediate results. The sub-operations
that are performed in the four-segments
are:
1. Compare the exponents
2. Align the mantissas
3. Add or subtract the mantissas
4. Normalize the result

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Example: Consider two normalized

floating-point numbers:

Segment 1: two exponents are

subtracted; 3-2=1.
Segment 2: Larger exponent is chosen as
the exponent of the result. The next
segment shifts the mantissa of Y to the
right to obtain

 Segment 3: This aligns the two

mantissas under the same exponent.
The addition of the two mantissas in
segment 3 produces the sum

 Segment 4: The sum is adjusted by

normalizing the result so that it has a
fraction with a nonzero first digit. This
is done by shifting the mantissa once
to the right and incrementing the
exponent by one to obtain the
normalized sum.

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 The comparator, shifter, adder-subtractor, incrementer, and decrementer in the

floating-point pipeline are implemented with combinational circuits.
 Suppose that the time delays of the four segments are
t1= 60ns, t2=70ns, t3=100ns, t4=80ns, and interface registers have a delay of tr=10 ns.
 The clock cycle is chosen to be tp=t3+tr=110 ns (Assume)
 Then an equivalent non-pipeline floating-point adder-subtractor will have a delay
time tn=t1+t2+t3+t4+tr=320ns.
 In this case the pipelined adder has a speedup of 320/110 =2.9 over the non-pipelined
adder.

Instruction Pipeline

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Instruction Pipeline
 The instruction cycle in the CPU can be
processed with a four-segment pipeline.
 The current instruction is being executed in
segment 4(EX), the next instruction in
sequence is busy fetching an operand from
memory in segment 3(FO).
 The effective address may be calculated in a
separate arithmetic circuit for the third
instruction, and whenever the memory is
available, the fourth and all subsequent
instructions can be fetched and placed in an
instruction FIFO.
 Up-to four sub-operations in the instruction
cycle can overlap and up to four different
instructions can be in progress of being
processed at the same time.

Timing Diagram

Stall : A stall is a cycle in the pipeline without new input.

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Pipeline Conflicts
• Resource Conflicts (Structural Dependency):
• More than one instruction tries to access the same
resource in the same cycle
• Caused due to memory access by two segments at the
same time.
• Data/Address Dependency :
• Instruction depends on the result of a previous
instruction.
• Control Dependency (Branch Difficulties):
• Caused by the branch and other instructions (BRANCH,
CALL, JMP, etc) that transfer the program control.

RISC Pipeline

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RISC and CISC architecture

RISC (Reduced Instruction Set Computer) – To make hardware simpler.
 It uses LOAD and STORE instruction to access the memory location.
 Simple and limited instruction reduces the execution time of a process.
 Supports simple addressing modes, one-word size instruction
 Single clock cycle: For executing each instruction in a computer, the RISC
processors require one CPI (Clock per cycle). And each CPI includes the fetch,
decode and execute method applied in computer instruction.
 Efficient Pipeline: The pipelining technique is used in the RISC processors to
execute multiple parts or stages of instructions to perform more efficiently.
 Advantages: Simpler instructions, Faster execution, Lower power consumption,
 Disadvantages: More instructions required, Increased memory usage, Higher cost.
 A large number of registers: RISC processors are optimized with multiple registers
that can be used to store instruction and quickly respond to the computer and
minimize interaction with computer memory.
 Hardwired rather than micro-programmed control
 Example: Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, and SPARC.

RISC and CISC Characteristics

CISC (Complex Instruction Set Computer): Single instruction will do all.
 Uses complex instruction sets to write a program for an application.
 Variable-length instruction format (larger than one-word size)
 CISC or complex instructions may take longer than a single clock cycle to
execute the code.
 The length of the code is shorts, so it requires less size of RAM.
 Less number of general purpose registers.
 Easy compilation of high-level programming languages.
 It is composed of fewer registers, more data types and complex addressing
modes, typically 5 to 20.
 Evolved during assembly language programming.
 Advantages: Reduced code size, More memory efficient, Widely used.
 Disadvantages: Slower execution, More complex design, Higher power
consumption.
 Example: VAX, AMD, Intel x86 and the System/360.

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RISC Instructions
• Reduced instruction set computer (RISC) is restricted to the use of load and store
instructions when communication between memory and CPU. All other instructions
are executed within the registers of the CPU without referring to memory.
• It uses LOAD and STORE instructions that have one memory and one register
address, and computational type instructions that have three addresses with all three
specifying processors registers.

CPU Performance Evaluation

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RISC Pipeline
 The reduced instruction set computer (RISC) uses an efficient
instruction pipeline.
 Three-Segment Instruction Pipeline:
 The instruction load or store the data from a selected register
in the register file. The instruction cycle can be divided into
three sub-operations and implemented in three segments:

I: Instruction fetch
A: ALU operation (Instruction decoding,
operation/determine (EA/Branch address)
E: Execute Instruction

RISC Pipeline
Consider the operation of the following four
instructions:

Here, data conflict in instruction 3

because the operand in R2 is not yet
available in the A segment.
The E segment in clock cycle 4 is using
the data from R2, but the value in R2
will not be the correct value since it has
not yet been transferred from memory.
This concept of delaying the use of the data loaded from memory is referred to as delayed load

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Data Transfer and Manipulation

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Questions

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