Gateway

User’s Manual

Silvaco, Inc.
4701 Patrick Henry Drive, Bldg. 2 September 28, 2015
Santa Clara, CA 95054
Phone: (408) 567-1000
Web: www.silvaco.com
 Notice

The information contained in this document is subject to change without notice.

Silvaco, Inc. MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY
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Copyright © 1984 - 2015, Silvaco, Inc.

2 Gateway User’s Manual

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3 Gateway User’s Manual

 Table of Contents

Chapter 1 
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 What is Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Gateway Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 QuickStart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.1 Loading Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.2 Checking the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.3 Netlisting and Control Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.4 Input Deck and Pre-Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.5 Simulation and Cross-Probing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3.6 Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 2 
File Operations and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1 GUI Environment and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1.1 Windows and Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2 Preferences Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.2 Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.2.3 Number Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.2.4 Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.5 Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.2.6 Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.7 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.2.8 Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.2.9 User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.2.10 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.2.11 Managing Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3 Special Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.4 File Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.4.1 Loading a Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.4.2 Opening a Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.4.3 Create a New Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.4.4 Saving Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.4.5 Exporting Drawings to Picture Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.4.6 Printing from Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.5 Importing and Exporting Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.5.1 Exporting Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.5.2 Importing Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.6 Help Menu and User Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Chapter 3 
Schematic Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.1 Gateway Design Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.1.1 Flat Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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3.1.2 Hierarchical Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.2 Navigating between Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.3 Sheet to Sheet Connecting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 4 
Libraries and Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1 Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2 Workspace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.1 Changing Workspaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.2.2 Saving Workspaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3 Library Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.1 Library Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.2 Library Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.3 Modifying Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.4 Version Control System (VCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Chapter 5 
Schematic Editing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.1 Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.2 Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.3 Filtering Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.1.4 Switching Design Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.2 Placing Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2.1 Selecting and Deselecting Objects/Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2.2 Rotating and Mirroring Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.2.3 Moving Symbols and Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2.4 Copying and Pasting Objects and Symbol Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2.5 Deleting Wires, Objects, or Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2.6 Disconnecting Wires and Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3 Attribute Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.4 Editing Symbol Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.4.1 Ordering and Positioning Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.5 Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.5.1 Wiring Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.5.2 Creating Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.5.3 Wire Snapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.5.4 Diagonal Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.6 Inherited Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.6.1 Net Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.6.2 The netInherit Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.6.3 Net Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.6.4 Inherited Net Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.7 Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.7.1 Bus Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.7.2 Bus Ripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.7.3 The Chord Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.7.4 Buses and Iterative Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

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5.8 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

5.8.1 Opening and Creating Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.8.2 Editing Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.8.3 Primitive Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.8.4 Special Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.8.5 Embedded, Attached, and Schematic Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.9 Generating and Regenerating Object Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.9.1 Regenerating Symbol Instance Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.9.2 Regenerating Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5.9.3 Regenerating Net Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.10 Creating Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.11 Generating Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
5.11.1 Generating Symbols from Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.12 Descending to Subcircuits from Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.13 Change Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
5.13.1 Change Symbol Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.14 Reload All Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.15 Miscellaneous Editing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
5.15.1 Adding Wire Stubs and Wire Stubs with Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
5.15.2 Adding Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
5.15.3 Adding Drawing Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
5.15.4 Edit Color and Reset Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
5.15.5 Object Alignment and Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
5.15.6 Frames and Sheet Borders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
5.16 Find Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.16.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.17 File Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Chapter 6 
Viewing and Navigating Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.1 The View Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.1.1 Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.1.2 Ascending and Descending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.1.3 Design Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.1.4 Showing Node and Symbol Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.1.5 Viewing Net Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.1.6 Viewing the Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Chapter 7 
Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.2 Checking a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.2.1 Error Handling and Viewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.2.2 Enabling and Disabling Warnings and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.3 Netlisting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
7.3.1 Rebuild Netlist Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
7.3.2 Creating a Specific Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.4 Control Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.4.1 Simulation Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

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7.4.2 Guardian Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.4.3 NDL Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7.4.4 Atlas Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7.4.5 CDL Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7.5 Viewing the Input Deck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
7.6 Pre-processor Schematic Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.7 Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Chapter 8 
Simulation and Post-Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
8.1 Pre-Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
8.2 Analog Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
8.2.1 Marking the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
8.2.2 Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
8.2.3 Calculating DC Operating Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8.2.4 DC Bias Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.2.5 Threshold Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
8.2.6 SmartSpice Status and Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
8.2.7 Post-Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
8.3 Digital Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Chapter 9 
EDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
9.2 EDIF Import Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
9.2.1 Importing an EDIF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
9.3 Conversion of Imported Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
9.3.1 Conversion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
9.4 Exporting EDIF 2 0 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Chapter 10 
Schematic Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.1 Importing Verilog and SPICE into Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.2 Example 1 – Importing Verilog to a New Symbol Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.3 Example 2 – Importing Spice to an Existing Symbol Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Chapter 11 
Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
11.1 Javascript in Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.1 Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.2 Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.3 Run Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.4 Run Script with Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.5 Command line Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.2 Callback Scripting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
11.2.1 Attaching Callback Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
11.2.2 Specifying the Callback Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
11.2.3 Callback API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
11.2.4 Attribute Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

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11.2.5 Visibility Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Appendix A 
Communications Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
A.1 Common Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
A.1.1 Cannot create input deck/netlist/control deck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
A.1.2 Simulation Does Not Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
A.1.3 Cannot Plot Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
A.1.4 DC Bias markers Not Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
A.1.5 Output/Error File Not Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
A.1.6 Licensing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
A.1.7 Nameservice Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

8 Gateway User’s Manual

 Chapter 1
Getting Started
What is Gateway Getting Started

1.1 What is Gateway

Gateway is a schematic capture tool and is the entry point for the IC design flow. Gateway
consists of a GUI for schematic entry and is integrated with the following simulators:
• Silvaco SmartSpice (Analog)
• Silvaco SmartSpice RF (RF)
• Silvaco Silos (Verilog)
• Silvaco Atlas (TCAD MixedMode)
• Synopsys HSPICE (Analog)
Gateway is the entry point of the design as its main purpose is generating a netlist that can be
loaded into circuit simulators. Schematics are drawn in Gateway and then transformed into a
specified netlist format. This netlist is an ASCII file describing the circuit connectivity. This
is the first file needed for the simulation flow. The next file used in the design process is the
control file, which can be created for each simulator that Gateway will run. This control file
contains all model and simulation options and parameters. When you create a netlist and a
control file, they merge to form the main portion of the input file.
At this point, Gateway can be switched into the simulation mode before running the
simulation. The simulation mode is used for marking node voltages and branch currents to be
plotted. These markers complete the input file that is submitted to the simulator for
simulation. Then, the simulator loads and simulates the input file and displays the progress of
the simulation in a dialog. Following the completion of the simulation, output and rawfiles
may be generated for viewing. The output file contains the text output of the simulation and
all the statistics and results of the run. The rawfile contains all the raw graphical data for
viewing the waveforms in SmartView. When the simulation finishes and generates the
rawfile, SmartView launches automatically and loads the rawfile with waveforms plotted.
At this point, it is common to have the Gateway Schematic window open and the SmartView
Plot window open with the waveforms. Any vectors (traces) that were saved into the rawfile
can then be marked back on the schematic and plotted, or cross-probed, from there. With
cross-probing, you can select and plot any combination of saved vectors on the schematic
following the simulation.

Note: Waveforms are plotted for the SmartSpice family of simulators.

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What is Gateway Getting Started

Figure 1-1 describes the file handling in Gateway.

Figure 1-1 Gateway File Flow

11 Gateway User’s Manual

Gateway Window Getting Started

1.2 Gateway Window

To run the latest version of Gateway, double-click the shortcut or select it from the Start
Menu. Gateway has two modes of operation: Capture and Simulation. Capture mode shows
the symbol libraries and is used to construct drawings. Simulation mode has settings for
plotting options and simulation presets. Figure 1-2 shows Gateway when first launched. In
addition to the main schematic drawing window, there are several paned areas that you can
resize, dock, undock, or hide. These areas include:
• Capture/Simulation displays symbol libraries in Capture mode and the simulation
options in Simulation mode.
• Preview shows the entire sheet indicating the current viewport.
• Session/Cross Probes/Review Errors/Output
• Session displays real-time information from the schematic capture, editing, and
actions when running a simulation.
• Cross Probes displays a list of markers to be saved, marched, or plotted.
• Review Errors displays a list of warnings or errors found after a drawing check.
• Output displays runtime output from simulations.
• Thresholds displays settings for showing device currents and voltages to be shown
between specified thresholds while in the DC bias mode.
• Design Browser is the tree view of the hierarchical structure for the schematic.
• Property Pane displays the attributes of the selected object on the drawing for viewing
and editing.

Figure 1-2 Gateway Window

12 Gateway User’s Manual

QuickStart Getting Started

1.3 QuickStart
1.3.1 Loading Files
This quickstart section describes the basic steps of using Gateway by going through the
current mirror example that is shipped with the software. First, launch Gateway and then
proceed to open the workspace for the current mirror. To do this, first select
FileOpenWorkspace. Then, browse to the following directory:
<installation_directory>\examples\gateway\<date>\analog\006_current_mirror

Select current_mirror.workspace and finally click OK. When the workspace loads, the
available libraries will appear in the library pane. Clicking one of these libraries in the pane
displays the list of symbols available below in the symbol pane. You can change the display
view of the symbols by clicking the pulldown menu and choosing a view. The large icon view
is the default.
Now, select FileOpenSchematic and select current_mirror.schlr from the dialog
and click OK. The Gateway window will appear as shown in Figure 1-3.

Figure 1-3 Gateway Example current_mirror.schlr

13 Gateway User’s Manual

QuickStart Getting Started

Click the spicelib library name in the library pane and the symbols will appear in the symbol
pane. Click on any symbol in the symbol pane and then move the mouse over the schematic.
The symbol will be attached to the pointer for placement. Press the ESC key to return to the
default select mode.

1.3.2 Checking the Design

You should check the design before netlisting. A clean drawing check is likely to generate a
netlist without errors. To illustrate how Gateway handles errors, delete the wire between R3
and Q1 and click the Check Drawing icon (Figure 1-4).

Figure 1-4 Check Drawing Icon

Figure 1-5 shows the errors generated in the error pane.

Figure 1-5 Review Errors Pane

Click on the first error and the schematic will zoom in and highlight the device with the error
(see Figure 1-6).

14 Gateway User’s Manual

QuickStart Getting Started

Figure 1-6 current_mirror.schlr showing an error

Click the undo icon (Figure 1-7).

Figure 1-7 Undo Icon

The wire is restored. Then, click the Fit to Window icon (Figure 1-8) to see the entire
schematic again.

Figure 1-8 Fit to Window Icon

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QuickStart Getting Started

Click again to check the drawing and then click the Session tab. The following
message will appear in the Session Pane.
"Checking 'This level'...
Check 'This level' successful".

1.3.3 Netlisting and Control Cards

The design is now ready to netlist. Click the Create Netlist icon (Figure 1-9) and the netlist
will appear.

Figure 1-9 Create Netlist Icon

Figure 1-10 Netlist Example

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The netlist has been created successfully. Now click the Edit Control File icon (Figure 1-11)
to look at the control statements and the Control File window will appear (Figure 1-12).

Figure 1-11 Edit Control File Icon

Figure 1-12 Control File Window

The control file (*.ctr) is a file containing information and statements about what to run in
the target simulator For example, if the chosen simulator is SmartSpice, then the control file
becomes a SPICE file. You can create the file by either typing in the statements or by using
dialog boxes to aid in writing some analysis statements. Usually, at least one analysis
statement is required. You can use any number of .OPTIONS or other SPICE statements to
build a simulation profile. Also, any library files or other files needed for the simulation are
added here by using .LIB or .INCLUDE statements.
The Analysis Toolbar (Figure 1-13) launches dialog boxes for most SPICE analysis
statements.

Figure 1-13 Analyses Toolbar

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For example, to generate a .TRAN statement, click the transient icon (Figure 1-14) and type
the parameters into the Transient dialog (Figure 1-15).

Figure 1-14 Transient Icon

Figure 1-15 Transient Dialog

In this example, close the dialogs without entering any information. The information in the
ex1.ctr file has already been generated for the examples.

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1.3.4 Input Deck and Pre-Simulation

The simulation runs the input deck file, which consists of three parts: the netlist, control file,
and the cross-probe marker file. Each target simulator has its own unique set of files that are
used in building the input file. For example, when the simulator=SmartSpice, the control
file is a *.ctr file and the netlist is a *.net file. If the simulator=Silos, then the control
file is a *.ctrv file and the netlist is a *.v file. In each case, the input file is generated based
on the netlists and control files for the simulator.
For the cross probes, click the Simulation tab below the Symbol pane (see Figure 1-16). The
pane changes to show the simulation profile. Clicking the mouse on a wire creates a voltage
marker, and clicking on a pin creates a current marker.
The cross-probe toolbar has buttons to indicate which type of marker will be placed on the
node or pin. By default, the node voltage or branch current will be saved. Using this toolbar,
you can change the markers to save db, phase, or differences between any voltage or current
markers.
These currents and voltages will be plotted in SmartView after the run. In this example, notice
the voltages for NET6 and NET5 are marked and will be plotted for all valid analyses in the
control file. Gateway inserts .SAVE statements into the deck for all markers (SmartSpice
family of simulators only).

Figure 1-16 current_mirror.schlr in Simulation Mode

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Notice that the statements in the control file appear in the Analyses pane of Figure 1-16.
Moving the mouse over that pane displays a tooltip of the entire statements for quick viewing.
This shows exactly what is set to run without having to open the control file. Figure 1-18
shows the tooltip.
On the Cross Probe pane, there are columns for the name of the vector, the type of vector, and
the schematic and sheet where they exist. A check in the Save column means the vector will
be saved for the analyses run. A check in the Plot column means that vector will be plotted
after simulation. A check in the March column means the vector will be plotted real-time
using SmartSpice’s interactive plotting. The vectors update as the simulation progresses.
To the right side of the cross probe pane, there are some checkboxes enclosed in a box named
Save. These checkboxes are used to save vectors by type but not to plot them unless chosen
after the simulation. By default, nothing is saved unless marked on the schematic or checked
by these checkboxes. All vectors that are marked (have cross probes) will be plotted while the
vectors saved by the checkboxes will be available in SmartView’s data browser for plotting
after the simulation. After the simulation, any vector saved can be probed on the schematic
and plotted by dropping the marker on the schematic and clicking the Plot button (see Figure
1-17).

Figure 1-17 Plot Button

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Figure 1-18 current_mirror.schlr with the Tooltip for Analysis Pane

To view the input file, click the View Input File icon (Figure 1-19). The input file will then
appear (Figure 1-20).

Figure 1-19 View Input File Icon

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Figure 1-20 The Input File ex1.in

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1.3.5 Simulation and Cross-Probing

To simulate, press the Run button (Figure 1-21). When the simulation begins, the Simulation
dialog appears with the runtime statistics (Figure 1-22). Following the simulation, SmartView
appears with the waveform plots. This simulation had two vectors marked: V(NET5) and
V(NET6). There is a .ALTER statement in the deck that runs the simulation twice. Also, there
are three analyses: .TRAN, .DC, and .AC. Therefore, there are a total of (223)=12 vectors
plotted, 4 for the transient, 4 for the DC, and 4 for the AC. See Figure 1-23 for an example.

Figure 1-21 Run Icon

Figure 1-22 Simulation Dialog

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Figure 1-23 SmartView Example

1.3.6 Sessions
A Session consists of the environment that is open and loaded into Gateway at any time. This
can be a workspace only, or a workspace plus any number of drawings. When Gateway is
exited, the session is automatically saved so that next time the application is launched, the
session may be resumed as it was before it was closed. This saves time in loading workspaces
and opening drawings if it is desired to resume the previous session.
When Gateway is launched, a dialog may appear, depending on the Session settings in the
user preferences (see Figure 1-24). Clicking Yes resumes the previous session. Clicking No
opens Gateway without anything being pre-loaded. Clicking Exit closes Gateway.

Figure 1-24 Resume Session dialog

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 Chapter 2
File Operations and Settings
GUI Environment and Settings File Operations and Settings

2.1 GUI Environment and Settings

2.1.1 Windows and Panes
The main drawing window serves as the canvas window for both symbols and schematics.
You can minimize, maximize, and resize these windows as with most applications. You can
also tile and cascade by using the commands in the Window menu.
Other GUI areas such as the Symbols and Preview panes can be docked, undocked, shown, or
hidden. To undock the symbols pane, for example, move the mouse to the top of the pane
until the cursor changes to a 4-way arrow (see Figure 2-1). Then click, hold and drag the pane
anywhere you desire and release the mouse button. To dock this pane where it was before,
click and hold the mouse and drag it back to its original location.

Figure 2-1 4-way arrow moving Symbol Pane

Figure 2-5 shows a symbols pane undocked and floating on the main application. This
floating pane can be resized and is movable. To dock the pane, drag the pane back to its
original location and it will dock itself as it was before.
All dockable areas may be hidden to maximize the drawing area by clicking ViewFull
Screen (see Figure 2-3). The result is what is shown in Figure 2-4. To view the dockable
areas again, click ViewFull Screen and they will restore to the original view.

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The Session tab (Figure 2-2) can contain multiple types of information. These can be filtered
by the icons in the top left.

Information Shows/Hides information text.

Warning Shows/Hides warnings.
Error Shows/Hides errors.
Script Shows/Hides the echoing of script commands.

Figure 2-2 Session Tab

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Figure 2-3 Before Full Screen View

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Figure 2-4 In Full Screen View

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Figure 2-5 Schematic Window with Symbol Pane floating

To hide the paned areas, click the small ‘x’ in the corner of the pane. To show it again, right
click on any gray space in the toolbar area and then select it from the list (see Figure 2-6).
Alternatively, use the View menu and then use either the Windows or Toolbars submenu. You
can also hide the paned areas and all toolbars using this right-click menu.

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Figure 2-6 Right Mouse Toolbar

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Preferences Dialog File Operations and Settings

2.2 Preferences Dialog

The Preferences dialog can either be opened from the Edit menu or by pressing the default
keyboard shortcut (F5). The preferences allow you to customize the Gateway application to
make it as productive for you as possible.
• Application
• Auto-Save
• Colors
• Drawing Checks
• Frame
• Grid
• Information
• Naming
• Netlist
• Atlas
• CDL
• LVS/Guardian
• NDL
• SPICE
• Verilog
• Number Format
• Reporting
• Session
• Shortcuts
• Technology
• Toolbars
• User Interface
• Tools
• Layout Editor
• Simulator
• Text Editor
• Waveform Viewer

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2.2.1 Application
These are the options that affect Gateway. These are the settings:
• Auto-Save
• Colors
• Drawing Checks
• Frame
• Grid
• Information
• Naming
Auto-Save
Turn Auto-Save On by setting the Enable property to True and all open drawing(s) will be
saved at the interval specified in the Interval box. The smallest interval to Auto-Save is 1
minute. The default is 5 minutes. If the Auto-Save is Off, the recovery system is turned off
and the changes are lost if Gateway exits unexpectedly. The other options on this dialog are
• Save Drawings when simulating - Saves all active open drawings when a simulation is
run.
• Save Drawings when checking - Saves all active open drawings when a drawing check
is run.
• Show conversion warning - Shows warnings if saving the drawings will result in a file
conversion format change.

Figure 2-7 Auto-Save Settings

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Colors
Figure 2-8 shows the color settings.

Figure 2-8 Color Settings Dialog

Note: The checkbox at the bottom left of the Preferences dialog is checked by default to save the preferences settings
upon exit.

This is the dialog where all colors for the Gateway application can be changed. The pull-
down menu called Color Scheme is set to the black color scheme by default. There are four
preset schemes: Black, White, Printer, and Custom. The colors for the selected scheme are
shown below in the palette. To modify any color, select the item and click the Change Color
button or double-click on a row in the table.
There is a Preview window at the bottom of the dialog that displays the effect of both the
items selected in the list and the effect of the current color scheme.
The Editing Colors are
• Background - The color of the drawing canvas background.
• Grid - The color of the grid on the schematic.
• Cursor - The cursor color applies to the snap diamond only.
• Select - The color of a selected object.
• Wire - The color of wires and buses on the schematic.

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• Dot - The color of wire solder dots.

• Ripper - The color associated with bus rippers that occur when a set of signals are ripped
from a bus.
• Pin - The color of symbol pins.
• Symbol - The color of symbols on the schematic.
• Implicit Pin - The Color with an implicit connections.
• Unconnected OK Pin - The Color for an unconnected pin, which is allowed to be
unconnected.
• Attribute - The color of symbol attribute text.
• Instance Name - The color of symbol reference designators.
• Net Name - The color of net names.
• Disconnect - The color of the "X" designator for disconnected instances or wires.
• Text - The color of any added text on drawings.
• Graphic - This is the color that all graphics (e.g., arcs and lines) are drawn in.
• Frame - The color of frame and sheet border objects.
• Highlight1 - The color of the first highlighted net. Also, the color of the bounding box on
Preview pane.
• Highlight2 - The color of the second highlighted net.
• Highlight3 - The color of the third highlighted net.
• Highlight4 - The color of the fourth highlighted net.
• Net Info - The color of the net information bubbles.
• Symbol Info - The color of the symbol information bubbles.
• Active Simulation - The color of the cross probe markers that are set to plot for active
simulation.
• Inactive Simulation - The color of the cross probe markers that are disabled or not in the
active simulation.
• Device Parameters - The color device parameter test is rendered in.
• DC Bias Voltage - The color of the DC bias voltage marker bubbles.
• DC Bias Current - The color of the DC bias current marker bubbles.
• Fixed Text - The color of fixed attribute text. This color applies to the tables and not to
drawings.
• Missing Cell – The color of cells in the workspace settings that have invalid library paths
set. Also, the color of cells in the search dialog where attributes do not exist for certain
symbol instances.

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Drawing Checks
Figure 2-9 shows the settings for warnings and errors. The dialog is broken down into two
sections: System Drawing Checks and Configurable Drawing Checks.
System Drawing Checks consist of errors only and cannot be downgraded to warnings. These
are marked by a red icon ( ) and each has an index number to reference the error. Errors
prevent a netlist from being generated.
Configurable Drawing Checks can be either warnings or errors, depending on how severe you
want to label each drawing check. Warnings are marked by ( ) yellow icons. To toggle a
specific drawing check, click the box in the Status column. In the Severity Column, all checks
are set as warnings unless you check the box and set to Error status. You can also turn off the
status of configurable checks using the Review Errors pane by right-clicking on a given
drawing check and selecting Disable.

Figure 2-9 Drawing Checks Error Settings

The Highlight option is used for setting the zoom level on the schematic when an error
occurs.

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Frame
Figure 2-10 shows the frame settings.

Figure 2-10 Frame Settings Dialog

This dialog formats settings for sheet borders and all properties of them. These are the default
settings:
• Company - The company name.
• Title - Title of schematic drawing.
• Sub Title - Subtitle or sub category of schematic drawing.
• Drawing # - Schematic drawing or part number.
• Sheet Size - Sheet border size in standard sizes A through E (A is the default). If the
Style is Custom, then you may specify the Custom Width and Custom Height using the
appropriate controls.
• Style - Specifies which corner of the sheet border to place the legend box with the fields
(bottom-right is the default).
• Origin - Chooses placement of Frame with respect to the origin (0,0) of the drawing.
• Draw Legend - When set to True, the legend will be shown on the frame (default).

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• Add Frame by Default - When set to True, Gateway places a frame by default with all
parameters from the Frames tab onto a new schematic. If unchecked, you must add the
frames manually.
• Legend Columns - Set the number columns the legend is split into. Frame fields can
span multiple of these columns.
Frame Fields
The frame fields table contains the fields for the frame legend. The order, column span,
height span, visibility and default contents of the frame fields can be set here. For the
standard fields, they cannot be deleted, only made invisible, and the name of the field cannot
be edited.
• Company - The company name.
• Title - Title of schematic drawing. (Defaults to the location of the schematic).
• Sub Title - Subtitle or sub category of schematic drawing. (Defaults to the file name of
the schematic.)
• Drawing # - Schematic drawing or part number.
• Size - Size of the Frame.
• Modified Date - Last date the drawing was modified.
• Author - Name of the last author to modify the drawing.
• Sheet - Page number of current page in the format "1 of 2".
• Custom fields can be added using the add button and removed using the delete button.
All fields can be moved up and down in the list, moving its location in the legend.

Note: ** indicates the field is generated and updated automatically by Gateway.

Note: If the Title and Subtitle fields are left empty, Gateway inserts the file path for the Title and Filename for the Subtitle.

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Grid
Figure 2-11 shows the grid settings.

Figure 2-11 Grid Settings Dialog

The grid is a guide for making schematic capture productive. This is done with lines that
provide guidance for lining up device pins and wires. To change the grid settings, use the
Grid tab window (see Figure 2-11). The main unit of the grid is in inches. The default snap
spacing (0.0625 inches or 1/16th of an inch) is the minimum distance a symbol can be moved.
Symbol pins and wires must snap on this invisible grid.
The Draw grid is True by default. Choosing False will hide the grid but wiring and moving
symbols are still snapped. Choosing True will display the grid. There are visible grid settings
for both schematics and symbols. Symbols may have a finer grid setting for adding more
precision or detail in symbol editing. Regardless of settings for the symbol grid, the pins will
always snap.
The Minor Multiplier (Schematic or Symbol) is set to 2 by default. This number is used in
calculating the Minor Grid distance. The minor grid is network of smaller squares on the grid.
Minor Grid distance (Schematic or Symbol) = ( Snap Spacing Minor multiplier )
= ( 0.0625  2)
= 0.125 or 1/8th inch

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The Major Multiplier (Schematic or Symbol) is set to 8 by default. This number is used in
calculating the Major Grid distance. The major grid is outlined with darker lines on the grid
(the grid color).
Major Grid distance = ( Snap Spacing  Minor multiplier  Major multiplier )
= ( 0.0625  2  8 )
= 1 inch
See Figure 2-12 for a graphical representation of the default grid.
• Show as Grid (Schematic) - Grid is drawn on the Schematic view as either Dots or
Lines.
• Dots - Dots drawn at the Major and Minor X and Y Grid intersections.
• Lines - Lines drawn on the Major and Minor X and Y grid lines.
• Show as Grid (Symbol) - Grid is drawn on the Symbol view as either Dots or Lines.
• Dots - Dots drawn at the Major and Minor X and Y Grid intersections.
• Lines - Lines drawn on the Major and Minor X and Y grid lines.

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Figure 2-12 Graphical Representation of the Default Grid

Note: Do not change the snap spacing for the grid. All symbols in the Gateway default library and many symbols that are
imported from EDIF use this grid. Changing the 0.0625 inch default may result in a schematic with wiring problems and
netlisting problems.

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Information
This shows the tooltips or the information bubbles.

Figure 2-13 Information Settings

• Display only one wire marker - Shows only one wire marker per net when in View Info
mode.
• Use highlight color - Uses the same color for both the marker and the highlghted object.
• Enable Net Names Tooltips - Highlights nets and shows netname when the cursor rolls
over the wires (on).
• Enable Symbol Info Tooltips - Highlights symbol instances and shows reference
designator and name of library of origin when the cursor rolls over the instance (on).
• Show marker bubbles as:
• Opaque - Shows the value on a solid background color.
• Transparent - Shows the value with a transparent background and a border.
• Invisible - Shows the value with an invisible background.

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Naming
This specifies the net naming format that is generated by Gateway.

Figure 2-14 Naming Settings

The Naming options set default prefixes for specific pin names as follows:
• Input Pin prefix : IN
• Output Pin Prefix: OUT
• Bi-directinoal pin prefix: BI
The Symbol Name Separator field is for specifying a string that will go between the symbol
prefix and referemce designator for the netlist. The Net name format option sets the naming
scheme for system-generated nets.

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2.2.2 Netlist
These options control the generation of the supported netlists in Gateway. These are the
settings:
• Atlas
• CDL
• LVS/Guardian
• NDL
• SPICE
• Verilog

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Atlas
Figure 2-15 shows the settings that can be used to generate the Atlas netlist.

Figure 2-15 Atlas Settings Dialog

These settings affect the netlist that Gateway generates for Atlas MixedMode simulation.
• 3D Mode - Adds .begin 3d at the top of the netlist to place Atlas in 3D mode.
• Include Atlas control file - Includes the Atlas control file in the netlist. The control file
will be appended to the netlist. If you enter a .end statement in their Atlas control file,
then Gateway will not add one. If Gateway detects that a .end is missing, it will add one
to the end of the netlist.
• Use quotation marks where neccessary - If checked, Gateway will put quotation marks
around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or contain
spaces.
• Default File Extension - Sets the default file extension for the Atlas netlist. The default is
.in.
• Line length - Sets the maximum number of characters per line in the netlist.
• Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.

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• Order Pins
• Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
• by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
• by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
• Manual editing - When True, the generated files (.net and .in) will be writable.

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Preferences Dialog File Operations and Settings

CDL
Figure 2-16 shows the settings that can be used to generate the CDL (Circuit Desciption
Language) netlist.

Figure 2-16 CDL Settings Dialog

These settings affect the netlist that Gateway generates for the Cadence CDL format:
• Include CDL control file - If True, this adds the contents of the CDL control file to the
netlist.
• Use quotation marks where neccessary - If True, Gateway will put quotation marks
around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or contain
spaces.
• Line length - Sets the maximum number of characters per line in the netlist.
• Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
• Order Pins
• Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
• by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
• by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
• Manual editing - When True, the generated files (.net and .in) will be writable.

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LVS/Guardian
Figure 2-17 shows the settings that can be used to generate the LVS and Guardian netlist.

Figure 2-17 LVS/Guardian Settings Dialog

These settings affect the LVS/Guardian netlist that Gateway generates.
• Add .SUBCKT around top level - Creates a subcircuit of the entire design by placing a
.SUBCKT and .ENDS around the contents of the design.
• Include LVS control file - Adds any statements (model, dotcard, or other types) written
in the Guardian control file into the Guardian netlist. This includes anything defining
pcells or model related that is unrelated to the actual simulation.
• Use quotation marks where neccessary - If True, Gateway will put quotation marks
around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or contain
spaces.
• Line length - Sets the maximum number of characters per line in the netlist.
• Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
• Order Pins
• Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
• by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).

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• by Verilog definition - Orders pin names on subcircuits by their Verilog string

definition.
• Manual editing - When True, the generated files (.net and .in) will be writable.

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NDL
Figure 2-18 shows the settings that can be used to generate the Netlist Driven Layout (NDL)
netlist.

Figure 2-18 NDL Settings Dialog

These settings affect the NDL netlist that Gateway generates.
• Add .SUBCKT around top level - Creates a subcircuit of the entire design by placing a
.SUBCKT and .ENDS around the contents of the design.
• Include NDL control file in netlist - Adds any statements (model, dotcard, or other
types) written in the NDL control file into the NDL netlist. This includes anything
defining pcells or model related that is unrelated to the actual simulation.
• Use quotation marks where neccessary - If set to True, Gateway will put quotation
marks around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or
contain spaces.
• Line length - Sets the maximum number of characters per line in the netlist.
• Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.

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• Order Pins
• Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
• by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
• by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
• Manual editing - When set to True, the generated files (.net and .in) will be writable.

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SPICE
Figure 2-19 shows the settings that can be used to generate the SPICE netlist.

Figure 2-19 Spice Settings Dialog

These settings affect the netlist that Gateway generates for the SmartSpice format:
• Use quotation marks where neccessary - If set to True, Gateway will put quotation
marks around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or
contain spaces.
• Line length - Sets the maximum number of characters per line in the netlist.
• Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
• Order Pins
• Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
• by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
• by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
• Manual editing - When True, the generated files (.net and .in) will be writable.

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Verilog
Figure 2-20 shows the settings that can be used to generate the Verilog netlist.

Figure 2-20 Verilog Settings Dialog

These settings affect the netlist that Gateway generates for the Verilog format.
• Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
• Order Pins
• Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
• by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
• by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
• Manual editing - When True, the generated files (.net and .in) will be writable.
• Generate one argument per line - This option splits all Verilog statements into separate
lines with only one argument per line, instead of having them be separated by commas.

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2.2.3 Number Format

Figure 2-21 shows the Number Format settings used when displaying result calculations.

Figure 2-21 Number Format Dialog

The Number Format dialog formats the display of symbol instance attributes on the
schematic, bias format, and device parameter display from simulation results. Symbols that
have attributes set to the visibility Name=Result or Result will be shown according to the
settings in this dialog. Equation properties control calculated values. Bias properties control
the formatting of Bias values. Device Parameter properties control the formatting of Device
parameter values. The results can be formatted as follows:
• Equation:Display Result In - Specifies the display format for equation calculated
values. The following choices to display the results are
• Decimal Places - Displays the result as a real number (e.g., 1.23).
• Engineering - Displays the result as an engineering number, exponent is a factor of
3 (e.g., 1.23e-06).
• Nearest S.I prefix - Displays the result as the closest S.I. prefix (e.g, 12.3k).
• Specific S.I prefix - Displays the result in a specific S.I. prefix ranging from Yotta
to Yacto (e.g., 12345.6k).
• Scientific Notation - Displays the result in scientific notation, exponent can be any
integer (e.g., 1.23e-04).
The default is the nearest Systeme Internationale (S.I.) prefix. For example, the number
1e-006 will be displayed as 1u.

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• Equation:Precision - Specifies the precision of the result for values calculated by and
equation.

2.2.4 Reporting
This controls the reporting level and what to show in the Session Window.

Figure 2-22 Reporting Dialog

The reporting level describes how much detail will be reported.
• Level - Sets the detail level of reports. The default is Off.
• Off - No report.
• Brief - Reports the total number of instances that have been modified by an action
in the Session pane.
• Detailed - Reports the change of each instance in detail in the Session pane.
• Time Stamp Session - Marks each reported action with a time stamp.
• Show license status - Shows the current status of the licenses being accessed.
• Maximum Message queue size - Sets the buffer for number of messages to be reported
in a session.

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2.2.5 Session
This controls whether to resume the previous session.

Figure 2-23 Session Dialog

These settings affect the Session in Gateway.
• Resume previous session - Only reloads the workspace from the last session, not
the schematics.
• Always - Automatically loads the last Gateway session when launching a new
session. The session is the workspace and all open schematics (default).
• Never - Opens Gateway without loading the prior session.
• Query - Asks you when running Gateway whether you want to resume the last
session.
• Working Directory - Sets the location of the current working directory.
• Use workspace directory - Sets the current working directory to the location of
the currently loaded workspace.
• Use current working directory - Sets the working directory to directory gateway
was started from.
• User defined working directory - Sets the current working directory to the path
set in the User defined directory property.
• User defined directory - This is the path to the user defined location to use for the
current working directory.

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The Ask Before Qutting option ensures the session option will be set before exiting
Gateway.

2.2.6 Shortcuts
Figure 2-24 shows the Shortcuts settings in the Preferences dialog.

Figure 2-24 Shortcuts Settings Dialog

You can assign any item that appears in the main menus in Gateway a keyboard shortcut to
perform the action. Single key as well as bindkey shortcuts are allowed.

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2.2.7 Technology
Figure 2-25 shows the Technology settings in the Preferences dialog.

Figure 2-25 Technology Settings Dialog

The Global Nodes property is for inserting a .GLOBAL statement into each input deck for all
simulations. Type the node names in the box and separate them with either commas or spaces.
If the Enable gloabl nodes is True, the .GLOBAL statement is automatically inserted in the
input decks. If the property is set to False, the statement is not inserted.
The Bulk Nodes property assigns default bulk pin names for devices using the bulk pins in
their symbol definitions. These are for symbols such as pmos_b.symbol. The variables in the
symbols are named:
STANDARD_NBULK_NODE
STANDARD_PBULK_NODE.
Assigning the name GND to the NBulk node or PBulk node box in the preferences means that
GND will be the node name put in the netlist for the bulk pins on these symbols. These
symbols usually only have three physical pins for wiring. Using these bulk definitions,
however, allows these symbols to netlist as four pin devices with a bulk node.

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2.2.8 Toolbars
Figure 2-26 shows the Toolbars settings in the Preferences dialog.

Figure 2-26 Toolbar Settings Dialog

You can customize the toolbars by selecting the toolbar name and clicking the Customize
button. The Customize Toolbar dialog will appear (Figure 2-27). Use this dialog to add or
remove buttons and to sort the order of buttons in the toolbar. Reset sets the toolbar to the
Gateway defaults. The toolbar icons can be shown in small or large sizes. The actions can
have tool tips and text labels.

Figure 2-27 Customize Toolbar Dialog

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2.2.9 User Interface

This controls the viewing options in the user interface.

Figure 2-28 User Interface Settings

• Zoom % - The percentage of the total screen area for zooming in/out (Range 1-100).
• Pan % - The percentage of the total screen area for panning (Range 1-100).
• Mouse Pointer Style
• Standard Mode - Uses the standard mouse cursor from your operating system
(default).
• Mode-dependent - Mouse cursor changes depending on the mode or sub-mode.
• Pin Graphics
• Square - Uses square pins.
• Round - Uses round pins.
• Selection Style
• partial selection - Selects any part of the object(s) that intersects the selection box.
• full selection - Selects objects that are entirely within the selection box.
• Selection filter enabled - Enables the filtering of drawing objects that can be selected by
clicking or drag selection events.
• Selection filter - Sets which drawing objects are selectable (On) or not selectable (Off).
• Default font - The font used for on screen text when not specified by another property.

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• User-Defined font - The font given to user-defined attributes and netnames.

• Attribute Font Size - The default font size for symbol attributes.
• Comment Font Size - The default font size for comment text on drawings
• DC Bias font size - The font size used to display DC Bias values on drawings.
• Cross probe font size - The font size used for cross probe marker text.
• View info font size - The font size used for view info text.
• Pin size - The default size for pins.
• Dot Size - Size of wire join dots.
• Ripper size - Size of Ripper dots.
• Short alert - This boolean property controls whether the Warning dialog will appear
stating that connectivity has changed from sequential edits. This is used to prevent
inadvertent connections when drawing dense schematics or moving wires and symbols
drawn closely together. This option slows down editing on large schematics.

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2.2.10 Tools
This controls the external applications (e.g., SmartSpice) that you run. These are the settings:
• Tools
• Layout Editor
• Simulator
• Text Editor
• Waveform Viewer
Layout Editor
Figure 2-29 shows the Layout Editor settings in the Preferences dialog. This dialog is used to
set the version and path of Expert. When checked, the Use Default Path box sets the path to
the same location where Gateway is installed. If this checkbox is unchecked, you can set the
path to another location to point to the directory where Expert is installed. The combo-box
allows you to select the version. Default is the latest version.

Figure 2-29 Layout Editor Settings Dialog

• Annotate Options - The annotate slider bar sets the zoom level in Gateway when objects
are selected in Expert and cross-probed back into Gateway. Setting the slider to No Zoom
will not zoom. Setting it to Full Zoom will zoom in to the maximum level on the
device(s), which are highlighted.

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Simulator
The Simulator settings in the Preferences allows the choice of target simulator, version, path,
and various startup options for the following simulators:
SmartSpice and SmartSpice RF
SmartSpice is set as the default simulator. When checked, the Use Default Path box sets the
path to the same location where Gateway is installed. If this checkbox is unchecked, you can
set the path to another location to point to the directory where the simulator is installed. The
combo-box allows you to select the version. Default is the latest version. The Host combo-
box allows you to choose whether to run SmartSpice locally or remote. If running remotely,
you will need to enter the host, user, password, and executable location on the remote
machine. A valid SSH server will need to be installed on the remote machine for this
functionality to work. The settings described in this section apply to the complete SmartSpice
family of simulators.

Figure 2-30 SmartSpice Settings Dialog

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Figure 2-31 SmartSpice Remote Settings Dialog

Remote Options
• Hostname – The name of the host machine to run the SmartSpice simulation on. This
machine must have SSH installed and be capable of running SmartSpice.
• Username – The username of the valid account that SmartSpice runs under on the
remote host machine.
• Password – The valid password for the user account that SmartSpice will run under on
the host machine. This will be encrypted before being stored on the local machine. You
will be prompted for the password if not supplied.
• Executable – The path to the executable on the host machine for SmartSpice. This path
must be supplied. The installation location maybe different on the remote host.
Advanced properties shared by Smartspice, Smartspice RF local, and Remote
• Plot Vectors every – The number of points calculated by SPICE and then plotted at a
time. This number of points is calculated and held in memory. It is then released to the
disk when the number has been reached.
• Raw File Directory – The directory to write raw file. The default is the working
directory.
• Output File Directory – The directory to write output file. The default is the working
directory.
• Suppress Rawfile – If checked, a rawfile will not be written. When SmartView is closed,
all data will be lost. If unchecked, a raw file will be written.

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• Load DC Bias points – If enabled, Gateway will load the DC Bias points generated by
the last run of this simulation.
• Generate DC Bias points – If enabled, Gateway will request the simulator to generate
the DC Bias points and will store them with the simulation.
• Startup File
• Do Not Read – This will not read a startup file when launching SmartSpice.
• Default – This will use the default SmartSpice initialization file.
• User-defined – If enabled, this specifies the path to the file to be read on the
startup for SmartSpice.
• Timeout – The number of seconds to wait for SmartSpice to start.
• User-defined startup file - The file to be read on Smartspice startup.
• Number of core processors – Specifies the number of processors SmartSpice will use.
• Number of solver processors – Specifies the number of processors SmartSpice will use
when solving.
• Command Line – Any additional command line options can be specified here (e.g., -
hspice).

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Atlas (DeckBuild)
Figure 2-32 shows the Atlas and DeckBuild tool settings in the Preferences dialog. This
dialog is used to set the version and path of DeckBuild. When checked, the Use Default Path
box sets the path to the same location where Gateway is installed. If this checkbox is
unchecked, you can set the path to another location to point to the directory where DeckBuild
is installed. The combo-box allows you to select the version. Default is the latest version.

Figure 2-32 Atlas (DeckBuild) Settings Dialog

I/O Settings
• Output file directory: Specifies the directory where the output file generated by Atlas
will reside. If Suppress output file is checked, this preference is ignored.
• Suppress output file: Specifies whether you want an output file from Atlas or to just run
the simulation.
• Silent Mode: DeckBuild will run in the background if you check this option.
• Specify number of processors - When True, Atlas is instructed while running the
simulation to use the number of processors specified in the Number of processors
property.
• Number of processors - Specifies the number of processors the simulation should use
when multiple processors is enabled.

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HSPICE
Figure 2-33 shows the HSPICE tool settings. In the simulator text box, specify the path to the
HSPICE executable. By default, the Generate log file box is True, which generates an ASCII
*.lis file.

Figure 2-33 HSPICE Settings Dialog

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Silos
Figure 2-34 shows the Silos tool settings. When checked, the Use Default Path box sets the
path to the same location where Silos is installed. If this checkbox is unchecked, you can set
the path to another location to point to the directory where the simulator is installed. The
combo-box allows you to select the version. Default is the latest version.

Figure 2-34 Silos Settings Dialog

Generate one argument per line - This option splits all Verilog statements into separate
lines with only one argument per line, instead of having them be separated by commas.

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Text Editor
Figure 2-35 shows the Text Editor settings in the Preferences dialog. This dialog is used to set
the text editor for supporting all text files that run in Gateway. This includes the netlist
(.net), control file (.ctr), input deck (.in), output file (.out), and error file (.err). The
default text editor is the Silvaco Text Editor. To choose a different editor, click the Other
Editor and then the Browse button to specify the path to the executable.

Figure 2-35 Editor Preferences Dialog

To run a console application like edit (Windows) or vi (UNIX) you must use cmd /c
start edit or xterm -e vi respectively.

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Waveform Viewer
The Waveform Viewer settings in the Preferences allows the choice of target waveform
viewer, version, path, and various startup options for the following viewers:
SmartView
Figure 2-36 shows the SmartView settings in the Preferences dialog. When checked, the Use
Default Path box sets the path to the same location where Silvaco EDA tools are installed. If
this checkbox is unchecked, you can set the path to another location to point to the directory
where SmartView is installed. The combo-box allows you to select the version. Default is the
latest version.

Figure 2-36 SmartView Settings Dialog

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TonyPlot
Figure 2-37 shows the TonyPlot Viewer settings in the Preferences dialog. TonyPlot is the
viewer used for analyzing Atlas MixedMode simulations. This dialog is used to set the
version and path of TonyPlot. When checked, the Use Default Path box sets the path to the
same location where Silvaco and Silvaco EDA tools are installed. If this checkbox is
unchecked, you can set the path to another location to point to the directory where TonyPlot is
installed. The combo-box allows you to select the version. Default is the latest version.

Figure 2-37 TonyPlot Settings Dialog

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AvanWaves
Figure 2-38 shows the AvanWaves Viewer settings in the Preferences dialog. AvanWaves is
the viewer used for analyzing HSPICE simulations. This dialog is used to set the version and
path of AvanWaves. Use the Browse button lo locate the path for the awaves executable.

Figure 2-38 AvanWaves Settings Dialog

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2.2.11 Managing Preferences

The Preferences dialog provides the means to import and export settings.
Exporting Preferences
Figure 2-39 shows the Manage Preferences settings in the Preferences dialog.

Figure 2-39 Manage Preferences Dialog

To export settings to a file (*.spf), click the Export button. The Export Preferences dialog
will then appears (Figure 2-40).
This dialog has two parts: the name of the file to be exported and the desired preferences to
export. First, browse to the desired path and type a filename in the dialog. Then, use the tree
to expand and collapse the preferences to export. Checking the box next to All checks all
preferences boxes in the tree. Unchecking the box next to All unchecks all preferences boxes.
If the checkbox next to All has a gray background, some box or boxes below were unchecked.
The example in Figure 2-40 will export all preferences except the Recovery preferences as
they are unchecked. Finally, click the Export button. The *.spf file is written with all
desired preferences. This file can be distributed to other users and then imported into
Gateway to acquire the preferences.

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Figure 2-40 Export Preferences Dialog

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Importing Preferences
After settings are exported to a *.spf file, they may be imported into Gateway on any
computer. To import a preferences file, click the Import button on the Manage Settings
window of the Preferences dialog. The Import Preferences dialog will appear (Figure 2-41).
In this example in Figure 2-41, only the colors from the blk_031605.spf preferences file
will import into the existing Gateway preferences. This makes it easy to pick and choose
which settings you may want to import from different preferences files. To import preferences
from multiple files, repeat the steps to import, checking only the preferences you want from
each specified file.

Figure 2-41 Import Preferences Dialog

Factory Settings
To reset the preferences back to the original Gateway defaults, click the Factory Settings
button. The dialog in Figure 2-42 appears to confirm whether you want to reset to the default
settings.

Figure 2-42 Factory Setting Dialog

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Recent Files
To clear the recent file menus from memory, press the Recent Files button. Then click Yes on
the confirmation dialog. That clears the recent file menu and the recent workspace menus.

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2.3 Special Keys

There are some keys that are reserved for special use in Gateway. These are listed and
explained below.
• Esc – Pressing the escape key returns Gateway to the default mode, the select mode.
• S – The “s” key is reserved for wire snapping or auto wiring
• Shift – This modifier key has multiple purposes:
• Breaking Connectivity (select mode) – By default, wires maintain connection and
stretch when symbols are moved. Holding the Shift key will break the wire
connectivity when moving symbols, wires, or a combination of both.
• Pasting Net Names (paste mode) – By default, wires will paste without the names
of the copied wires to prevent inadvertent implicit connections. Holding the Shift
key will paste the net names with the wires.
• Pasting Pin Names on symbols (paste mode) – By default, pin names are not
copied when pins are copied in symbol files. Holding the Shift key pastes the pin
names.
• Add Stubby Wires (add symbol mode) – By default, when a symbol is placed on a
schematic, it will have floating pins. Pressing the Shift key in this mode will add
stubby wires on each pin and name them according to the pin name.
• Paste Reference Designator (paste mode) – By default the reference designators are
not copied and pasted with symbol instances to prevent duplicate naming. Pressing
the Shift key when pasting will paste the copied reference designator as long as it is
unique.

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2.4 File Operations

2.4.1 Loading a Workspace
The workspace file (*.workspace) contains the libraries and paths to be used in the design.
A workspace must be loaded before creating a design. The Gateway Examples Directory
contains sets of design examples. Each design example has its own workspace.
The first step in any design is to load the workspace by selecting FileOpen Workspace
(Figure 2-43). Then, browse the design example folder and choose the workspace to open.

Figure 2-43 Open Workspace Dialog

For more information about workspaces, see Chapter 4 “Libraries and Workspace ”.

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2.4.2 Opening a Drawing

After loading a workspace, you can open any drawings. Schematic drawings have a *.schlr
file extension and symbol drawings have a *.symbol extension. To open a drawing, select
FileOpenThen, select the type by clicking either Schematic or Symbol. Figures 2-44 and
2-45 show the open dialogs for each.

Figure 2-44 Open Schematic Dialog

Figure 2-45 Open Symbol Dialog

Note the checkbox at the bottom of each dialog that says Open as read only. Checking this
box opens the drawing for viewing only and allows other users to open it for edit.

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2.4.3 Create a New Drawing

To create a new schematic or symbol, select FileNew. Then, select either Schematic or
Symbol from the sub-menu. Choose Schematic to create a schematic.

Figure 2-46 New Schematic Drawing

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2.4.4 Saving Drawings

To save a drawing, click FileSave. To save the current drawing as another file, click
FileSave As. The Save Schematic dialog will appear (Figure 2-47). Then, type the new file
name in the dialog. If you try to save a file that already exists, the dialog in Figure 2-48
appears and asks whether you want to overwrite the file.

Figure 2-47 Save Schematic Dialog

Figure 2-48 Question Dialog

When you close edited drawings in Gateway, you will be prompted to save them (see Figure
2-49).

Figure 2-49 Saving Changes Dialog with one drawing

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If you edit multiple drawings and then close Gateway, you will be prompted once to save all
edited files (see Figure 2-50).

Figure 2-50 Saving Changes Dialog with multiple drawings

The Yes button saves the entries in the dialog that are highlighted. The No button won’t save
highlighted entries. The Cancel button closes the dialog and returns to the drawings.

2.4.5 Exporting Drawings to Picture Formats

Gateway exports drawings (both symbols and schematics) to the following picture file
formats.

Table 2-1 Picture File Formats

Image Types File Types

*.bmp Windows or OS/2 Bitmap

*.jpeg, *jpg Joint Photographic Experts Group
*.pbm Portable Bitmap
*.pdf Portable Document Format
*.pgm Portable Graymap
*.png Portable Network Graphics
*.ppm Portable Pixmap
*.xbm X Bitmap
*.xpm X Pixmap

To export the drawing, open the drawing, click FileExportTo File, and type the name of
the desired file. Then, select the type as shown in Figure 2-51.

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Figure 2-51 Export Image Dialog

The resulting file will show the view seen in the drawing window. For example, if the
drawing is zoomed or panned, the file will reflect that.

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2.4.6 Printing from Gateway

Gateway can print any schematic or symbol file. Design hierarchies can also be printed from
top to bottom. To see exactly what will be sent to the printer, select FilePrint Setup. The
dialog in Figure 2-52 will appear. The dialog has two tabs for controlling output – Selection
and Exclusion.

Figure 2-52 Print Setup Dialog

In the Selection tab, there are two setting groups: Print From and Print Options.
The Print From settings group contain these options:
• Current Sheet – Prints the current sheet in its entire view.
• All Sheets – Prints all sheets in a flat design.
• Include subcircuits – Prints the entire design hierarchy top-down.
• Current View – Prints only the view in the window as zoomed or panned.

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The Print Options settings group contains these options:

• Draw sheet border – Draws a rectangular border around the drawing.
• Best fit orientation – Adjusts the drawing to portrait or landscape depending on the
situation.
• Scale each page – Scales up to fit the drawing to the largest size on a sheet.
• Black on white – Disables the color scheme pull-down menu and sets printing to
monochrome mode.
• Color Scheme – Sets the color scheme to be printed as set in the user preferences for:
• Black
• White
• Printer
• Custom
The Show Preview checkbox displays the preview window when checked and hides it when
unchecked.
The Exclusion tab is used to exclude cells from specific libraries to be printed. To exclude a
library from printing, click the Add button and then type the name of the library in the Add
Exclusion Library text box.

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2.5 Importing and Exporting Designs

The FileExportDesign and FileImportDesign menus make it simple for Gateway
users who want to share entire designs or portions of designs. These features allow customers,
foundry members, or vendors to quickly and easily bundle designs and exchange them with
one another. On the importing side, the design can be unpackaged to any working directory
and then automatically replicated as it was on the sender’s computer. This ensures that all
appropriate files necessary to examine and possibly simulate the design should be already in
their proper places and reduces the manual labor of checking file paths and setting up the
design.

2.5.1 Exporting Designs

To export a design in Gateway, select FileExportDesign. The Export Design dialog is
shown in Figure 2-53.

Figure 2-53 Export Design Dialog

The dialog is a tree control and reflects the contents of what is loaded in the session that can
be exported from Gateway. At minimum, a workspace must be loaded before anything can be
exported from Gateway. Most often, a schematic design will be open for export. In Figure 2-
53, the Export Design dialog shows a session box that is unchecked and a workspace box that
is checked. In this case, there was a workspace that was loaded but no schematics open at the
time when the Export Design was launched. The entire workspace, or selected libraries, can
be selected for export.
Figure 2-54 shows that the tree can be expanded to show contents of anything in the tree. All
checked items are to be exported and unchecked items are not. To complete the export, click
on the Browse button and browse to a desired directory to export the file. Then, type in a
filename for the design and press OK. The file type is a *.tar.gz.

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Figure 2-54 Library Expanded to See Contents

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When a schematic design is open and the Export Design is selected, the dialog will look
similar to Figure 2-55.

Figure 2-55 Exporting a Design

In this case, the session is checked by default. Expanding the session (Figure 2-56) shows the
contents of the design by group (design, input files, schematic, and symbols).

Figure 2-56 Session Details for Exporting

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Expanding even further (Figure 2-57) reveals the individual files that are to be exported with
the active selection. Notice that when a schematic design is exported, only the required
symbols that are found on the schematic design are exported instead of the entire symbol
libraries. The reason is to export only what is needed for the design. To export the entire
libraries, select from the libraries listed under Workspace in the tree.

Figure 2-57 File Level Detail for Exporting

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Figure 2-58 shows the Export Design dialog for a design after a simulation was run and
completed. Now in addition to everything that existed in the dialog from before the
simulation, there are additional input files (netlist and input file) and an output file category to
include any raw, output, and error files. The Export Design tool is versatile in that it allows
you to export the entire design or any portion thereof by selecting only what you want to
export.

Figure 2-58 Post-Simulation Files Added to Export

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2.5.2 Importing Designs

Figure 2-59 shows the Import Design dialog that appears when you select
FileImportDesign. In the dialog, browse to the location of the archive file that was sent
to you, and then choose the location where the design will extract. When you press the
Import button, the workspace will automatically load and the design is ready to be examined,
continued, or simulated.

Figure 2-59 Import Design Dialog

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2.6 Help Menu and User Manuals

The Help menu in Gateway has menus that open the Gateway User’s Manual in PDF form. It
also has menus that open any application and modeling manuals for the simulator that are
loaded in the preferences. Release notes and a preview at what is new in the current baseline
version are also available in the Help menu.

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 Chapter 3
Schematic Structures
Gateway Design Sheets Schematic Structures

3.1 Gateway Design Sheets

Each schematic design is constructed on a design sheet. The design sheet is an area that
contains the drawing information related to the schematic. Each sheet may contain a frame
(sheet border).
Frames have legends where you can place information about the design, such as the
designer’s name, the drawing title, drawing number, the sheet number, and the total number
of sheets. For more information about frames, see Section “Frame”.

3.1.1 Flat Schematic Design

A flat schematic in Gateway connects sheets together on the same level. This may be one or
more schematic sheets that are bridged by common signals or on/off sheet connectors. These
connectors are called pageschpin symbols and are available from the $default library. There
are no levels of hierarchy in flat designs. They are useful when the area of the schematic is
large enough to span more than one sheet but are not block-type or hierarchical design.
Figure 3-1 shows a flat schematic design that covers 2 sheets with pageschpin symbols to
transfer signals from one sheet to the other. An alternative to using pageschpin symbols is to
use implicit net names. These names imply a physical connection by name even though the
wires are not physically joined on the schematic.

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Figure 3-1 Two-Sheet Flat Schematic connected with pageschpin symbols

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3.1.2 Hierarchical Schematic Design

A common approach for bottom-up block design is the hierarchical design method. In this
approach, a schematic is created and then the schematic can generate a corresponding symbol
with the same pinouts. This symbol/schematic pair can be used repeatedly for use in other
designs.
Figure 3-2 shows an RSFF hierarchical design. The drawing marked ‘1’ is the top level
simulation schematic with input sources. The RSFF symbol descends into the RSFF
schematic with the 2 and 3 input NAND gates shown in drawing ‘2’. Drawing number ‘3’ is
the 3 input NAND schematic. Drawing number ‘4’ is the 2 input NAND schematic. Both
drawings ‘3’ and ‘4’ are the end of the hierarchy as they cannot descend further. Typically,
drawings ‘3’ and ‘4’ will be created first. Then, those drawings will be symbolized and used
to construct drawing ‘2’. Drawing ‘2’ can then be symbolized and that symbol is placed at
the top level on drawing ‘1’.

Figure 3-2 Three-layered Schematic

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In Gateway’s Design Browser window, the top level of any design is the root branch. From
there, the tree expands down for each level of hierarchy. You can select any symbol that has a
sub-schematic on the drawing and descend into it. You can ascend/descend through the
hierarchy using the View menu options or the Design Browser. Figure 3-3 shows the Design
Browser window for this example.

Figure 3-3 Hierarchy Browser

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3.2 Navigating between Sheets

The Sheet menu (Figure 3-4) is used to add, delete, or navigate through sheets of a design. To
create a new sheet, select SheetNew. The new blank sheet will then appear and its title bar
will now show Sheet 2.

Figure 3-4 Sheet Menu

To view the previous sheet(s), select SheetPrevious. The window will now display Sheet
1. To view a particular sheet, select SheetGo to and the Go to Sheet dialog will appear (see
Figure 3-5).
Select a sheet in the dialog and it will appear in the Gateway Window. You can also view a
particular sheet by clicking on the sheet number in the Hierarchy Browser pane. It will show
all sheets created in the schematic. To insert a sheet, select SheetInsert. The inserted sheet
will now become the active sheet in the Schematic Area and will change the numbers of the
other sheets, depending on where it’s inserted. So if you create a new design and select
SheetNew, the new sheet will be placed after the original sheet as Sheet 2. Alternatively,
selecting SheetInsert places the new sheet before the original sheet as Sheet 1.
To delete a sheet of a schematic:
1. Select the window containing the sheet to be deleted.
2. Select SheetDelete and the sheet will be removed. To undo the deletion, click
EditUndo.

Figure 3-5 Go to Sheet Dialog

Note: When a sheet is created or inserted, it becomes the active window.

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3.3 Sheet to Sheet Connecting

For schematics that are used in hierarchical design, use inschpin, outschpin, and bischpin
symbols from the basiclib library. These pins are named after the direction of signal flow
between the drawings. Any of these can be used in any combination on the same drawing to
compose a schematic that will be used in part of a hierarchy or even stand-alone. Drawing
conventions usually specify the input pins to be at the left side and output pins to the right
side of schematics.
There is another symbol in the basiclib library that is used for sheet-to-sheet connections.
This is the pageschpin. These pins connect two or more nodes or wires that have the same
name on different sheets but are not visually connected on the schematic. Although you can
place them anywhere on the schematic, they are commonly placed to the right and left edges
of the sheets they bridge the signals to and from. To connect sheets, select a pageschpin from
the basiclib and place it on the wire of the signal you want to continue on another sheet. Once
placed, double-click the pin and name it. Then, go to the other sheet and place another
pageschpin and give it the same name as the other.

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 Chapter 4
Libraries and Workspace
Libraries Libraries and Workspace

4.1 Libraries
A library in Gateway is a directory on an operating system that contains schematics or
symbols or both. Schematics have a .schlr file extension and symbol files have a .symbol file
extension. The library structure in Gateway is flat, meaning that each directory must be
mapped individually in the workspace to be valid. Subdirectories are ignored if they are not
mapped with their own paths in the workspace. The symbols in the Library/Symbol pane are
listed alphabetically. The default view is the Large Icon view. You can choose from one of the
four available views to display the available symbols by using the combo box in the symbol
pane.
The spicelib is the default library in Gateway. This contains the active and passive
SmartSpice symbols needed for simulating any simple design using SmartSpice. The spicelib
library contains subcircuit cells for the examples. Although schematics are contained in
libraries, they are not visible in the library or symbol pane areas. Only symbols appear in the
symbols pane. If there is a symbol and schematic with the same name in a same library, such
as inverter.symbol and inverter.schlr, the inverter symbol appears in the symbol pane
for that library. This also describes a descendable pair, or a symbol file that descends into its
schematic view, as the files have the same base name and are in the same library.
There is an examples folder under your Silvaco installation directory. From there, choose the
Gateway folder. The following describes the structure of that directory:
There is a libraries directory has five library folders:
• spicelib
• rflib
• digilib
• atlas
• vprims
There are also examples contained in the following folders:
• analog
• digital
• rf
• tcad
Inside each these are examples that contain:
• example schematics, control files, and simulations.
• cross-probe files that contain cross-probe markers for the SmartSpice family of
simulators.

Note: For libraries containing more than 1000 symbols, Gateway will create sub-libraries up to 1000 symbols in
each for best performance in searching and sorting symbols.

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4.2 Workspace
The workspace is a file containing the libraries that will be used in creating a schematic. The
workspace file in Gateway has a file extension *.workspace. You must create or load a
workspace before creating a schematic or symbol drawing. To create a new workspace, select
FileNewWorkspace and the New Workspace dialog will appear (Figure 4-1).

Figure 4-1 New Workspace Dialog

Type a filename and click OK. The Workspace Settings dialog will then appear (Figure 4-2).

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Figure 4-2 Workspace Settings Dialog

When this dialog appears, press Add (+) to add the first library (Figure 4-3).

Figure 4-3 Workspace Settings Dialog with a new row to add a library

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There is a blank row inserted in the dialog. To name the library, click on the library with the
left mouse button and type in another name. Once the library is named, the file path to the
library folder must be specified. If symbol files in the library refer to a callback file, enter the
file name in Callback Script. To specify a path, either type the path in the Path field or press
Browse to find the path where the folder resides. When you use the Browse button, Gateway
specifies that file path as a relative path (see Figure 4-4). The path may also contain
environment variables. This is achieved by adding chevrons around the environment variable
(e.g., <S_INSTALL_ROOT>/examples/gateway/libraries/spicelib).

Figure 4-4 Workspace Setting Dialog with relative path

To delete a library, click on the library or path and press Delete (-). The libraries can be
arranged in any order using the Move Up () and Move Down () buttons in the dialog.
When the libraries have been added with their respective paths, press OK to accept the
changes and close the dialog. If a specified path does not exist, the cell containing the path
changes color. The workspace can be loaded but libraries with invalid paths will not show in
the Gateway library pane. For example, Figure 4-5 shows a workspace with the $default
library, one valid library (newlibrary), and one invalid library (newlibrary2). Unless the
path for newlibrary2 has been redirected to a correct path, that library cannot be used in the
session.

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Figure 4-5 Workspace Settings Dialog with a valid library and an invalid library

4.2.1 Changing Workspaces

To modify the workspace, select FileWorkspace Settings. The workspace is modified by
adding, changing, or deleting libraries and paths from the dialog.

Note: To change the workspace settings, such as modifying or deleting a library, all schematics must be closed
and reopened.

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4.2.2 Saving Workspaces

To save a newly created workspace, select FileSave Workspace and the workspace loaded
in the session will be saved (Figure 4-6). If you make changes to the workspace and end the
Gateway session without saving, you will be prompted to save the workspace.
To save the workspace to another file or location, select FileSave Workspace As... and the
Save Workspace dialog will appear (also Figure 4-6). Then, browse to the directory of choice,
type a filename in the Filename field and press Save.

Figure 4-6 Save Workspace Dialog

Note: All library names in the workspace must be unique.

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4.3 Library Management

4.3.1 Library Paths
Library paths can be either fixed paths or relative paths. An advantage of using relative paths
is that a working directory can be moved to another location without the need to rename the
paths. This is easier for moving designs or sending a complete design to another group or
location. Unzip the file and load the workspace into Gateway. All the paths relative to the new
working directory and all the libraries are ready for use. The workspace examples that are
bundled with Gateway use relative paths, making it simple to install the software anywhere
and use the tool without redirecting paths. Fixed library paths have the advantage of retaining
a secure library where symbols are available to use and check out but not to modify. In reality,
most designs involving a group will have a mixture of both relative and fixed paths.

4.3.2 Library Structures

There are several strategies for mapping out your libraries for design. Some designers will use
an example workspace as a starting point and then create new folders and name them
according to the new library names. This can work for small designs but may not be
productive for managing designs for different projects and processes.
One of the easiest ways to manage designs is by projects. In this case, create a new directory
for each project. In a structure like this, each project can have its own workspace containing
the spicelib library for basic SPICE symbols and then multiple libraries that are project
specific.
Another method is to manage the designs by process. Create a folder for each foundry and a
subfolder for each process. In the process folder, create subfolders for projects and proceed as
mentioned above. There can be workspaces specific to each foundry or each process,
depending on the need. In either case, when you save new symbols and schematics, save them
into a directory that’s mapped in the workspace. Otherwise, you won’t be able to see the
symbols in the libraries that are loaded. As stated earlier, each folder must have a path to be
recognized as a library. Hierarchical directory structures are not recognized.

4.3.3 Modifying Libraries

Any change to the symbols or the structure of the library will affect all schematics that use
that library. If users outside of a Gateway session modified symbols in a workspace you are
using, select ToolsReload All Libraries. This will update the libraries and instances that
were modified on your drawings. Otherwise, they won’t update until you exit the session and
begin a new session.

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4.3.4 Version Control System (VCS)

The libraries should all be under the control of a Version Control System (VCS) with a
designated user given the role of Library Administrator to handle any changes or updates to
the libraries. The common and primitive libraries should be kept in one place either on a
designated computer or a specific area of the network. It is not recommended to allow a user
to have local copies of the design libraries on their workstation. Keeping the libraries in a
designated area and allowing permissions for proper use ensures common and standard
symbols used on a schematic will be the same and up to date. This also prevents a user from
changing the structure of the libraries and producing schematics that can't be read by the rest
of the team.
The only time a user should have local copies of any library in a design team environment is
when they are developing their own library and the development will be local. The user will
also have a local copy of the library when their workstation is stand-alone.

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4.4 Security
When opening a schematic (.schlr) or symbol file (.symbol), Gateway locks the file to
ensure that another user cannot change the file while making edits. When the file is closed,
the lock is released, and other users may edit the file.
Gateway creates a file with the same name as the schematic or symbol with the extension
".lck". This file contains lock information (e.g., User and process). This file is deleted when
the lock is released.
The drawing window title will display the following:
• "[Locked by <user>]" - If another user has the lock file and is not available for edit.
• "[Available]" - If the drawing is opened for read purpose but not locked by another
user.
• "[Read-only]" - If the drawing is tagged read-only at the OS level
If there is a problem with the lock file, i.e., the user has edited it and changed the format,
Gateway will display:
• "[Lock file error]" - This will only occur if the lock file is badly formatted
To release the lock on a drawing so another user may open for edit, select FileRelease
Lock. To obtain a lock on an available drawing for editing purposes, select FileGet Lock.

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 Chapter 5
Schematic Editing
Overview Schematic Editing

5.1 Overview
This chapter describes the principles of schematic editing. It covers placing symbols on the
schematic, editing instance attributes, and wiring a drawing. Symbols are also covered in this
chapter. Some useful editing utilities are also described. These include automatic symbol
generation from schematics, automatic pin name generation, and other miscellaneous editing
features.

5.1.1 Workspace
A workspace must be loaded before any schematic or symbol can be opened. For more
information about workspaces, see Section 4.2 “Workspace”.

5.1.2 Libraries
Figure 5-1 shows the library pane of the main Symbol/Options Window. The libraries must be
flat (non-hierarchical) and this is indicated by the layout of the library pane. When a library is
selected by clicking on it, the symbols in that library are displayed in the symbol pane below.
Gateway automatically generates symbol icons to reflect the actual footprint of the symbol.
All symbols that come with Gateway or created by a designer will show in this pane. Figure
5-2 shows the large icon view for library symbols, which is the default. Figure 5-3 shows the
small icon view. Figure 5-4 shows the list view with name only. Figure 5-5 shows the list icon
view has the full symbol name and small icon in a list. Use the scrollbars to browse through
the lists of symbols. Use the slider bars to resize the areas of both windows.

Figure 5-1 Library Pane

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Figure 5-2 Large Icon View of Symbols

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Figure 5-3 Small Icon View of Symbols

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Figure 5-4 List View of Symbols

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Figure 5-5 Icon List of Symbols

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5.1.3 Filtering Libraries

At the bottom of the symbol pane, there are two combo boxes for filtering libraries. The first
one is the Category field. To add a specific category, enter it in the Category field in the
symbol file. If multiple symbols have the same category, they will be grouped together. The
default is set to (all). The second combo box is the Filter field, which filters the symbol files
in a library by name. Wildcard characters are accepted.

Figure 5-6 Symbols filtered on all symbols beginning with letter i

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5.1.4 Switching Design Views

If both symbol and schematic views of a cell exist, the right mouse menu will contain the
option to toggle to the other view. For example, if the nand21 symbol from the spicelib
library is open, you can toggle to the schematic view by right clicking and selecting
Schematic from the menu (see Figure 5-7). Then, the view toggles to the schematic view of
the cell (see Figure 5-8). To toggle back, right click and use the menu (see Figure 5-9).

Figure 5-7 Selecting the schematic view from the symbol view

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Figure 5-8 Schematic view of the cell

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Figure 5-9 Toggling back to the symbol view

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Placing Symbols Schematic Editing

5.2 Placing Symbols

To place a symbol on a schematic:
1. Select a library. For this example, use spicelib.
2. Click on the symbol name from the list in the Symbol Window. For this example, select
vpulse. The symbol name will be highlighted and the symbol will be attached to the
cursor, floating around the Schematic Area until it is placed.
The symbol may be rotated or mirrored as it is moving by clicking the right mouse button
to use the Symbol Orientation Menu. Rotate it until you have the desired orientation of
the symbol. See Section 5.2.2 “Rotating and Mirroring Symbols” for more information.
3. Click the left mouse button to drop the symbol on the schematic. The symbol will have
question marks (?) beside it. This means these attributes need to be defined. See Section
5.4 “Editing Symbol Attributes” for more information.
Once the symbol is placed, another symbol, which will be the same type, will be attached
to the cursor. To place another symbol, click the left mouse button again. To place a
different type of symbol, click on another symbol name from the Symbol Window and
repeat the same steps described above.

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4. Press the ESC key or click the middle mouse button to return to the Select mode. The
cursor no longer has a symbol attached to it. The vpulse symbol is placed and the
schematic should have one symbol as shown in Figure 5-10.

Figure 5-10 Vpulse symbol being placed

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5.2.1 Selecting and Deselecting Objects/Symbols

To select a symbol/object, click on a symbol or object in the schematic. You can select more
than one symbol or object, which can be done in two ways. The first way is to click on the
symbol or objects while holding down the Ctrl key and then clicking on other symbols or
objects to add them into the selection. The second way is to hold down the left mouse button
and draw a box around the symbols or objects to be selected. The Ctrl+click combination
toggles between selecting/deselecting objects.
To select the contents of an entire schematic, select EditSelect All. To deselect any objects,
click in any other space than the selected area and the objects will be deselected. To deselect
all the objects in the schematic, select EditDeselect All.
You can also toggle selection between objects and symbols. To toggle the selection, select the
EditInvert Selection. Figures 5-11 and 5-12 show an example of inverting a selection.

Figure 5-11 A selection of objects

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Figure 5-12 Inversion of selected objects

5.2.2 Rotating and Mirroring Symbols

You can rotate or mirror symbols after they have been placed. Rotation is in increments of 90°
from 0° to 270°.
To rotate a selected object, either:
• Select Rotate Clockwise or Rotate Counter-Clockwise from the Edit menu to perform
a rotation (rotate as many times as needed).
• Use the Right Mouse menu and select Orientation and choose which way you want to
rotate the object.
To mirror a selected symbol, either:
• Select Mirror Horizontally or Mirror Vertically from the Edit menu.
• Select Orientation from the Right Mouse menu and choose either Mirror Horizontally
or Mirror Vertically.

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5.2.3 Moving Symbols and Objects

To move a single symbol or object:
1. Left-click on a symbol or object and keep the left-mouse button pressed.
2. Move the selection with the mouse and then release the left-mouse button at the desired
place.
To move a selection of symbols or objects:
1. Select the symbols or objects.
2. Click the left-mouse button and hold it down.
3. Move the selection with the mouse and then release the left mouse button at the desired
place.

Note: Symbols attached to wires stretch the wires when they are moved. To break connectivity and move what is only
selected without stretching wires, hold the SHIFT key and then move the selection.

5.2.4 Copying and Pasting Objects and Symbol Instances

To copy an object or symbol:
1. Select the object(s) and symbol(s) to be copied.
2. Click on the Toolbar or select Copy from the right mouse menu.

To paste objects or symbols:

1. Click from the Toolbar or select Paste from the right mouse menu.
The object(s) or symbol(s) copied will now be floating on the schematic.
2. Click the left-mouse button to place the object(s) or symbol(s) at the desired position or
location.

Note: Pressing the Shift key while pasting will also paste the symbol instance names. If Shift is not pressed, they will be
automatically named.

5.2.5 Deleting Wires, Objects, or Symbols

To delete any object (wire, symbol, text), select the wire(s), object(s), or symbol(s) and select
Delete. You can either click or select EditDelete. You can also press the Delete key to
delete the objects.

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5.2.6 Disconnecting Wires and Instances

A disconnected device is excluded from the design during netlisting and simulation. When a
component is disconnected, an “X” marker is drawn over the instance. You can set the marker
color in the Preferences dialog as the Disconnect color.
A disconnected wire is similar but instead of the wire being removed from the drawing, it is
split into two nets: the original net and a new unique net. The effect in the netlist and
simulation is that these resulting nets will be present.
To disconnect a device or device(s):
1. Select the instances to be disconnected.
2. Either right-click and choose Disconnect or select EditConnectionDisconnect.
To disconnect a wire:
1. Select the wire(s) to be disconnected.
2. Either right-click and choose Disconnect or select EditConnectionDisconnect.
To reconnect, either right-click on the wire/device or use the Edit menu. The selection
EditConnectionConnect All re-establishes connections for all wires and devices.
Figure 5-13 displays a portion of a schematic. Figure 5-14 shows it after some objects are
disconnected.

Figure 5-13 Portion of the Schematic Before Disconnect

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Figure 5-14 Portion of the Schematic After Disconnect

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Attribute Editing Schematic Editing

5.3 Attribute Editing

In Gateway, there are two way to edit object attributes:
• Using property panes
• Using instance attribute dialogs
Property pane editing is done by selecting an object on the drawing (e.g., wire, symbol) and
then editing the fields in the Property Editor pane. This is for single instance editing and is
generally a quick method to edit attributes for a single selection.
The instance attributes dialog shows a table of attributes for the selected objects and the
attribute fields with them that may be edited. Double-clicking on an object opens the instance
attribute dialog. You can edit single or multiple selected objects. To set the number of
instances to apply the edits, use the Scope combo box.

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5.4 Editing Symbol Attributes

Once symbols are placed, there may be question marks (?) beside it. A question mark denotes
a placeholder for a value. You must input values in these placeholders before completing a
drawing check. The data you need to enter for these placeholders is necessary for compiling a
correct netlist.
Examples of these are attributes, such as model names, parameter and attribute values,
expressions, and device geometry parameters. If these attributes are not given a value (they
are left with a ?), a netlist cannot be generated. The question mark (?) denotes a mandatory
value that must be included in the netlist and is set by the creator of the symbol.
Attributes are used to define each symbol instance. Gateway uses these attributes when
constructing the netlist and subsequently passes them on into the input deck and then into the
SmartSpice simulation. To edit the attributes of a symbol, either double-click on the symbol,
right-click on the symbol and choose Properties or select the symbol and choose
AttributesEdit and the Properties dialog for the symbol (Figure 5-15) will appear.

Figure 5-15 Properties Dialog (Symbol Instance)

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The top panel (Symbol Details) of this dialog shows the detailed information about the
symbol. The Symbol Details panel contains the following fields.
• Symbol: Symbol Name.
• Instance: Instance name or Reference Designator.
• Library: The library of origin for the symbol.
By default, the Instance field has a box next to it with a value assigned by Gateway. You can
always change that value to something else.
There is a combo box that selects the scope of the design that the edits will apply to. The
choices for scope are:
• Current: Edits to dialog apply only to the current instance.
• Selected: Edits to dialog apply to selected instances.
• Matching: Edits to dialog apply for all instances that have the same symbol name and
originate from the same library as the instance being edited in the dialog.
The Netlist Preview button is used to preview how the device statement will appear in the
netlist. The netlists that Gateway can generate are Verilog, SmartSpice, Guardian, NDL,
CDL, and Atlas. Using the preview gives you a look at how that device is written for each
netlist string. For example, Figure 5-16 shows the netlist preview for a vsin symbol.

Figure 5-16 Netlist Preview for a vsin symbol

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The lower panel (Attributes) of the dialog shows the name of the attributes for the symbol in
the Name column. The Value column shows the value for each attribute. To adjust or create a
value, click on a cell and enter in a value. The Visibility column is used to show the visibility
of these attributes on the schematic. To set the visibility, click on the cell to right of the value.
Here are the following visibility settings.
• None: Nothing is displayed.
• Name: Displays the name of the attribute.
• Value: Displays the value of the attribute.
• Result: Displays the numerical result of an expression in the value field of the attribute.
• Name=Value: Displays the name equal to its value of the attribute.
• Name=Result: Displays the name equal to its numerical result of an expression in the
value field of the attribute. Next to the Name and Value fields, the Default field shows
the default value for any attribute if specified in the symbol file.
The icons showing the orange arrows reset the attribute’s current value back to its default
when pressed. The Reset All button in the dialog resets all attribute values back to their
defaults.
When you complete the changes, press one of the following:
• Apply to make these changes.
• OK to accept these changes and close the dialog.
• Cancel to discard all changes and close the dialog.

5.4.1 Ordering and Positioning Attributes

The attributes for a symbol will appear beside it once they have been defined. Most of the
time, the attributes will be aligned near the symbol. For symbols that have many visible
attributes, the attributes may not be spaced evenly. To order the attributes, first select the
symbol. Then, select EditAttribute OrderOrder Alphabetically. This will order them
with the reference designator in first in line.
For multiple symbols that need alignment of attributes, select multiple symbols or a selection
of symbols with a bounding box and then select EditAttribute OrderOrder
Alphabetically. Attributes will be ordered according the ordering scheme selected The
attributes positions will be swapped to create the correct ordering.
There are three ordering options:
• Alphabetically
• by Definition (in the Edit Properties dialog)
• by SPICE String
To align and evenly space the attributes select EditPosition and Align AttributesFixed.
This will position, align, and evenly space the attributes to the right of the Symbol as drawn in
the Symbol View. The attributes current ordering will be maintained but with the Designator
moved to the top position.

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Figure 5-17 shows the original drawing before it was aligned.

Figure 5-17 Original Drawing Before Aligning Attributes

Figure 5-18 shows the drawing after selecting EditOrder AttributesOrder by
Location and EditPosition and Align AttributesFixed.

Figure 5-18 Drawing After Aligning Attributes

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Figure 5-19 shows the drawing after selecting EditAlign Attributes by Definition.

Figure 5-19 Drawing After Aligning Attributes by Definition

Figure 5-20 shows the icons for aligning attributes.

Figure 5-20 Aligning Attributes Icons

• – Order by Definition

• – Order Alphabetically

• – Order by SPICE String

Figure 5-21 shows the icons for positioning attributes.

Figure 5-21 Position Attributes Icons

• – Top Right

• – Top Center

• – Top Left

• – Middle Right

• – Middle Left

• – Bottom Right

• – Bottom Center

• – Bottom Left

• – Fixed

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You can also align attributes for net names, wires, and for pins. Sometimes, you can
inadvertently move net names away from their parent wires. Instead of manually moving
them all to their original location, you can select EditSelect all and then use one of the
position actions. The result is that all attributes will become aligned to their parent objects,
regardless if the parent object is a pin, wire, or symbol instance.

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Wires Schematic Editing

5.5 Wires
5.5.1 Wiring Rules
Terminology
• Node – A single wire that may or may not be connected to other wires.
• Net – A collection of nodes that are connected together.
• Super-Net – A collection of nets that are connected together by their names.
• Implicit – When a wire is connected to another wire by name but not physically.
• Global – A wire name can be global which allows all levels of the schematic to implicitly
connect to it.
• Synonym – An alias wire name.
• Signal – The primary name that will be used for netlisting purpose.
Net Merging Rules
Gateway classifies netlist precedence for the following list of signals in order of highest to
lowest:
1. width (2 bit width higher priority than single bit wide)
2. pins (user-defined)
3. global nets
4. implicit nets
5. pins (system generated)
6. alpha-numeric nets (user-defined)
7. alpha-numeric nets (system-generated)
When two or more signals are joined (from the first four items in the list above), a synonym
will be created. A synonym is a net alias. Therefore, the signal of higher alphanumeric value
is retained for the physical netlist, and the other is noted as a synonym to the first net.
Naming Rules
1. Nodes can have the following properties:
• Ability to be left unconnected
• Net name may be always shown
• .GLOBAL definition
• Node may be implicitly connected
2. The netlist engine will only name super-nets that do not already have a name.
3. Gateway will validate against having implicit and global flags set without having a name.
4. A signal attached to a pin has priority over all other names in a Super-Net.
5. A node will only be named if it differs from the signal attached to a pin. The exception is
if a node was already named the same as the signal and is either implicit or global and is
then merged with the pin.
6. When changing the implicit or global flags for a node name, the changes will be applied
to all names attached to nodes on the same Super-Net.
7. The following non-alphanumeric characters are allowed in net and node names:

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• exclamation (!)
• left chevron (<)
• right chevron (>)
• hyphen (-)
• plus sign (+)
• forward slash (/)
• asterisk (*)
• high hat (^)
• ampersand (&)
• pound or hash symbol (#)
• underscore (_)
• left square bracket ([)
• right square bracket (])
8. Any net or signal name that ends in an exclamation mark (!) is considered to be a globally
defined node and will behave as such for simulation. This includes single bit signals and
buses.
Graphical Rules
1. A Single Node That Is Named
When a single node is named, the name remains part of the node until it is deleted.
Double-clicking on the name can change it.

When performing a ViewInfo action, the result would be

2. Two Nodes Connected Together

When two nodes are connected together to create a net and one of them is named, you can
move the name from one node to the other by double-clicking the name.

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When performing a View Info action, the result would be

3. Multiple Signals on a Net

If multiple nodes are named, the signal that has the highest precedence (see “Naming
Rules” on page 134) remains on the net.
• Case A
Both signals have the same precedence. NET2 is deleted due to NET1 having
alphabetical precedence.

• Case B
NET2 has a higher precedence level than NET1(e.g., NET2 is implicit whereas
NET1 isn’t).

• Case C
NET1 is not an implicit or global signal.

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• Case D
NET1 is implicit.

5.5.2 Creating Wires

Once the symbols are placed, they will need to be wired together. To create a wire:

1. Press or select DrawWire.

2. Begin the wire by placing the cursor where the wire will start and click the left-mouse
button.
3. Move the mouse in the direction to the end point for the wire and double-click the left-
mouse button to end the wire.
4. Click the right-mouse button to exit the wire mode.
To change the direction of a wire or make a vertex, click the left-mouse button while drawing
the wire and change direction with the mouse.

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5.5.3 Wire Snapping

Wire snapping is a feature to make wire drawing faster and easier. It places a small diamond-
shaped marker on the closest pin or wire to the mouse pointer. Wire-snapping is on by default.
To turn it off, select EditPreferences and choose the Options tab.

To draw wires with wire-snapping, enter the wire mode by clicking . As the mouse
moves, the diamond-shaped marker will also move. Pressing the S key snaps the wire from
the mouse pointer to the diamond-shaped marker. Figure 5-22 shows a wire connecting two
resistors by using the wire snapping method.
The dotted line shown in Figure 5-22 is the preview of the completed wire. To apply the
dotted-line, press the S key. To apply the solid line, press the left-mouse button.

Figure 5-22 Resistors connecting through Wire Snapping

Repeat the steps to create another wire. To delete a wire, select it and press Delete. To stretch
or rubber-band a wire, select it and then stretch it by holding down the left mouse button and
moving it. To move a wire and retain symbol connections, click the wire and drag it. To move
a wire and break the connection from the symbols, hold the Shift key down, click the wire,
and drag it. To modify attributes, double-click a wire and the Properties dialog for the wire
will appear (Figure 5-23).

Figure 5-23 Properties Dialog (Wire)

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The Properties dialog for the wire has the following options:
• Name: This is the name of the wire. This name will be the net name in the netlist.
• Rip/Add Signal - Designates that the wire segment in context is ripped from a bus or
bundle.
• Type – The combo box for choosing net declarations. By default, wire type is set. The
other type declarations supprted for Verilog and Verilog-A are reg, tri, tri0, tri1, triand,
trior, trireg, supply0, supply1, wand, wire, wor, electrical, voltage, current, integer,
real, and wreal.
• Assignment - Used to allow you to assign values to wires in Verilog mode. For example,
if the wire type is set to reg and the value is set to 1'b1, then the Verilog file will contain
the declaration reg a=1'b1;, assuming the name of the wire is called “a”.
• Connection - The type of connection must be one of the following:
• Normal: Normal connection without dependencies.
• Implicit connection: Creates connectivity between nodes without actually wiring
them together.
• Global connection: Defines the net as a global net or makes these nodes directly
available in all subcircuits. This is generally used for PWR supplies and clocks and
larger circuits. Any internal subcircuit node that has the same name as a global
node assumes that it refers to the global node. For example:
VCC NET1 0 4V
.GLOBAL VCC
The .GLOBAL statement defines the power supply VCC as a global node,
connecting it to all VCC nodes on internal subcircuits.
• Rename: when an existing net is being renamed, it can be renamed as follows:
• Local Net - Renames the local net that is the context of the dialog box.
• Super Net - Renames the entire net, including segments that are implicit in type
(not physically connected, but electrically connected).
• Width - Sets the graphical width of the wire from 1 (thinnest) to 5 (thickest).
• Show name always: Displays the net name even if net names are turned off in the
customize settings or if the nets have been toggled off. When two or more wires are
drawn and labeled with the same name and the Implicit connection box is checked,
selecting ViewInfo verifies that these wires have the same net name.

5.5.4 Diagonal Wires

Wires are drawn either straight or diagonally. By default, all wires are drawn as straight wire
segments in the vertical or horizontal direction. To draw wires diagonally, select

DrawDiagonal Wire from the menu or click .

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5.6 Inherited Nets

The inherited net feature provides a way to manually override a global signal in a design. This
can be also used to integrate multiple power supplies and rails into a design and to override
substrate connections. The inherited net feature has these two main components:
• Net Properties - This is defined on symbol instances including the netInherit symbol.
• Net Expressions - This is defined on wires and nets.

5.6.1 Net Properties

The syntax for a net property on a symbol instance is:
[property]=[value]
where the [property] is the name of the property used throughout the design and the
[value] is the assigned value at any location.
An example of a net property is:
[POWER]=[VCC!]
where [POWER] is a property and [VCC!] is assigned in this instance.
Figure 5-24 shows net properties set for an inverter symbol. To add net properties for symbol
instances, first double-click the instance, then select the Inherited Nets tab, and press the
Add button.

Figure 5-24 Net Properties set for an inverter symbol

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5.6.2 The netInherit Symbol

The $default library contains a special symbol named netInherit.symbol. netInherit symbol is
used to define a net property to be assigned on the schematic level. Net properties defined on
the netInherit symbol propagate over the entire schematic and the next level down. Figure 5-
25 shows the properties of a netInherit symbol with a net property defined as:
[POWER]=[VDDA]
which means VDDA overrides any signal wherever the [POWER] property is used on the
schematic and below.

Figure 5-25 Net properties of the netInherit symbol

5.6.3 Net Expressions

Net expressions are used on wires and nets to define properties that can be inherited. The
syntax of a net expression is:
[property]:[value]
where [property] is the name of the property that is passed in and [value] is what is actually
passed in and used.
You can setup these net expressions in two ways to accomplish the desired connectivity:
• Using default signals - If the net should be given a name that is used always unless a net
property overrides it. The syntax is:
[property]:[netname]
An example of this is a net expression defined as [POWER]:[vcc]. This will use vcc
always unless the [POWER] property is defined above. If defined, vcc will be overridden.
• Using default connections - If no specific node name will be used for default. Instead, the
connection as the circuit is wired should be used as a name. The syntax is:
[property]:[%]
In this case, % means to use the netname of the given wire where the net expression
resides unless a net property overrides it.
An example of this is shown in Figure 5-26 where a net property [PWR]:[%] exists on a wire.
If the [PWR] property exists above, this net will use the value defined for it. If it’s not defined
above, Gateway resorts to the name of the physical wire. In this case, the wire is connected to
the VDD pin. Therefore, VDD is used.

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Figure 5-26 [PWR]:[%] on a wire

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5.6.4 Inherited Net Examples

Figure 5-27 shows a schematic with three inverters. The schematic contains a netInherit
symbol with a net property defined as:
[POWER]=[VDDA]
This makes VDDA overrides the [POWER] property on the cmos circuit below. Instead of using
VDD, all three instances use VDDA.

Figure 5-27 VDDA passed down for the POWER property

Figure 5-28 shows a modification of this example. In this case, inverter X3 contains a net
property defined at that instance. The net property on X3 is defined as:
[POWER]=[VDD2]
For this case, the net property at the instance has a higher precedence than the netInherit
symbol. The result is that X1 and X2 use VDDA for [POWER], but X3 uses VDD2 for [POWER].
Examples illustrating inherited net use are found in the Gateway examples directory that is
included with the software. The three example directories all begin with the string “netInh”.

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Figure 5-28 X3 POWER property overrides the netInherit symbol for the X3 instance

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5.7 Buses
5.7.1 Bus Naming Conventions
There are multiple ways to define buses and wire bundles in Gateway. The bus naming
supports the following syntax styles:
• Separator
• Square Brackets
• Angle Brackets
• Multiplier
• Parentheses
• Prefix Repeat operator
Separator
The separator character is a comma (,) and allows the ability to specify multiple signals on the
same wire.
Example

Bus Name Bus Name Expanded

A, B A, B
A, B<0:2, 5>, C*2 A, B<0>, B<1>, B<2>, B<5>, C, C
ENABLE, S1, S2 ENABLE, S1, S2
Angle and Square Brackets
Angle brackets (<>) and square brackets ([ ]) are used to denote bits of a bus range and a bus
range. The SmartSpice family of simulators supports the angle bracket notation, and Silos and
Verilog support square bracket notation.

Note: You can use square bracket or angle bracket notation (or a mixture of the two) when capturing schematics in
Gateway. The Gateway netlister will convert them to the correct type based on the simulator that is chosen.

Example

Bus Name Bus Name Expanded

A<0> A<0>
B<0:2> B<0>, B<1>, B<2>
BUSA<3:0> BUSA<3>, BUSA<2>, BUSA<1>, BUSA<0>
SCAN<4,0,1> SCAN<4>, SCAN<0>, SCAN<1>
Bus ranges also support step operators that are specified by adding a second colon (:)
character.

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Example

Bus Name Bus Name Expanded

A<4:0:2> A<4>, A<2>, A<0>

B<0:6:2> B<0>, B<2>, B<4>, B<6>
SCAN<0:3:2> SCAN<0>, SCAN<2>
SCAN<0:3:1> SCAN<0>, SCAN<1>, SCAN<2>, SCAN<3>
Multiplier
The multiplier operator gives the ability to repeat a name or bit.
Example

Bus Name Bus Name Expanded

A*5 A, A, A, A, A
B<0, 1, 2*2> B<0>, B<1>, B<2>, B<2>
Parentheses
Parentheses, (), allow you to group different signalsand then use an operator on them. For
example, the Prefix Repeat operator or Multiplier.
Example

Bus Name Bus Name Expanded

B<(0,2)*2> B<0>, B<2>, B<0>, B<2>

<*5>(A, B), C A, B, A, B, A, B, A, B, A, B, C
Prefix Repeat Operator
The Prefix Repeat operator (<*n>) allows you the ability to repeat the following name n
number of times, where n is an integer number.
Example

Bus Name Bus Name Expanded

<*3>A A, A ,A
<*5>(A, B) A, B, A, B, A, B, A, B, A, B
<*2>(DATA_IN, <*2>(A,B)), C DATA_IN, A, B, A, B, DATA_IN, A, B, A, B, C

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5.7.2 Bus Ripping

A single or multiple bit wire may be tapped from a bus by drawing a wire to intersect the bus,
and then by double-clicking on that wire segment. Figure 5-29 shows a bus that is ripped into
segments. In the example, the first three bits of Z are ripped, then X and Y, followed by X, the
eighth bit of Z, and finally X, Y and the fourth bit of Z. The Wire Attributes dialog is used to
define the ripped components. To rip a name from the main bus, check the Rip/Add box. If
the box is not checked, the node will be merged into whatever name is typed in the box.

Figure 5-29 Editing ripped segments from the bus

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Figure 5-30 shows the completed bus with all ripped component segments.

Figure 5-30 Bus and ripped signals

To merge bus components, use any of the bus naming conventions as described in Section
5.7.1 “Bus Naming Conventions”. The most common use to merge is by using a comma
separation that can specify multiple signals on any given wire.

5.7.3 The Chord Symbol

The chord symbol from the $default library is a special symbol that aliases signals from
different buses and allows them to be reordered. Where multiple nets are sometimes joined
together to form a supernet, the netlister only can use one name for the net while assigning the
others as synonyms. Use the chord symbol for this purpose.
The chord symbol is a two-pin symbol and has two properties, ORDER and PRECEDENCE,
that closely work together.
ORDER and PRECEDENCE
The ORDER property defines the bit mapping order from the signals attached to the origin
pin to the signals attached to the destination pin. The origin pin is always pin A, and the
destination pin is always pin B. The PRECEDENCE property defines which net is given the
priority name in the netlist. The three choices are
• A - Forces the net on the origin side to be the name in the netlist.
• B - Forces the net on the destination side to be the name in the netlist.
• PRIMARY - Resolves the supernet to the primary signal name that is determined by the
following list of importance, from highest to lowest:
• width (2 bit width higher priority than single bit wide)
• pins (user-defined)
• global nets

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• implicit nets
• pins (system generated)
• alpha-numeric nets (user-defined)
• alpha-numeric nets (system-generated)
Figure 5-31 shows a four bit bus x aliased to a four bit bus y. That is, the four bits in
ascending order are aliased to the four bits on the right in ascending order.

Figure 5-31 aliasing with PRECEDENCE set to side A

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Figure 5-32 shows the setup in a sample circuit that yields the following netlist:
R<0> X<0> GND 1k
R<1> X<1> GND 1k
R<2> X<2> GND 1k
R<3> X<3> GND 1k
R<4> X<0> GND 2k
R<5> X<1> GND 2k
R<6> X<2> GND 2k
R<7> X<3> GND 2k

Figure 5-32 PRECEDENCE set to left and bit order retained

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Figure 5-33 shows the circuit with the PRECEDENCE changed to the right side. This forces the
netlist to write in terms of the right-hand side bus, or in this case: y<0:3>.

Figure 5-33 PRECEDENCE set to the right and bit order retained
That change produces the following netlist:

R<0> Y<0> GND 1k

R<1> Y<1> GND 1k
R<2> Y<2> GND 1k
R<3> Y<3> GND 1k
R<4> Y<0> GND 2k
R<5> Y<1> GND 2k
R<6> Y<2> GND 2k
R<7> Y<3> GND 2k

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Figure 5-34 shows the circuit where the ORDER has changed to reverse the bit order from left
to right, and still shows the PRECEDENCE for the netlist as the right side.

Figure 5-34 Bit order reversed, PRECEDENCE still to the right

This produces this netlist:
R<0> Y<3> GND 1k
R<1> Y<2> GND 1k
R<2> Y<1> GND 1k
R<3> Y<0> GND 1k
R<4> Y<0> GND 2k
R<5> Y<1> GND 2k
R<6> Y<2> GND 2k
R<7> Y<3> GND 2k

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Figure 5-35 shows the circuit with the PRECEDENCE changed to the side A.

Figure 5-35 PRECEDENCE changed to the left

Here is the resulting netlist:

R<0> X<0> GND 1k

R<1> X<1> GND 1k
R<2> X<2> GND 1k
R<3> X<3> GND 1k
R<4> X<3> GND 2k
R<5> X<2> GND 2k
R<6> X<1> GND 2k
R<7> X<0> GND 2k
If you set the PREDECENCE to Primary instead of A or B, then Gateway uses the signal
derived from the wire merging that is described in the beginning of this section.

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5.7.4 Buses and Iterative Instances

You can also use commas as separators for buses in designs where iterative instantiation
reduces a number of instances to one physical instance on the schematic. In Figure 5-36, the
ripple counter uses four JK flip flops. Figure 5-37 shows the same design captured with one
flip flop that actually names four of them. This method of iteration saves space on a schematic
but produces an equivalent netlist. In Figure 5-37, the CLK input to X1 is CLK, and the
output of Q is n1, and so on. This is electrically the same circuit as in Figure 5-36.

Figure 5-36 Ripple Counter with Four JK Flip Flops

Figure 5-37 One Flip Flop Instance naming four iterated instances

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5.8 Symbols
Gateway symbols are files with a *.symbol file extension.
Symbols may or may not have a PREFIX attribute. The PREFIX attribute of a symbol
designates the type of symbol it will represent in the target simulator. The PATH attribute of a
symbol designates the instance name of a particular instance. Together, the PREFIX and PATH
form a reference designator (also known as the instance designator).
An example of a reference designator for a MOSFET transistor would be M5, representing
the fifth instance of type MOSFET. In this case, the PREFIX for the symbol is set to ‘M’, and
the PATH is numbered automatically by Gateway as devices are placed.
An example of a reference designator for a digital symbol would be I2, where the PREFIX is
‘I’, and the 2 represents the second instance on the drawing.
The $default library symbols represent ports, pins, connection symbols, power rails, grounds,
and other special symbols that add information to schematics. The spicelib library symbols
contain the active and passive devices that are native to SPICE. The digilib library of symbols
contains primitive digital devices for capturing on schematics.

5.8.1 Opening and Creating Symbols

To open or create a symbol:
1. Load a workspace into Gateway
2. Select FileOpenSymbol or FileNewSymbol (Figure 5-38).
3. Enter a filename and click Open to open a symbol file or OK to create a new one.

Figure 5-38 Open Symbol Dialog

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5.8.2 Editing Symbols

To edit a symbol from a schematic view, right-click on the symbol instance on a schematic
and then click Symbol Drawing. Also, you can access a symbol for edit by right-clicking the
symbol in the symbol pane, or by right-clicking a symbol in the Design Browser and choosing
Goto Symbol.
There are also several approaches to creating symbols. You can create one from scratch and
add pins, graphics, and attributes all manually. A second approach is to create a symbol from
another by opening an existing symbol and then selecting FileSave As and saving as
another and then making modifications. A third approach is to create a new symbol and then
choose ToolsGenerate Symbol to use a GUI for adding graphics and sizing the footprint
automatically. To create a symbol from a schematic, open the schematic containing pins and
click ToolsGenerate Symbol. Finally, symbols and symbol libraries can be created
automatically from SPICE subcircuits or Verilog RTL and behavioral modules by using the
ImportSPICE and ImportVerilog menus respectively.
To edit the symbol graphically (Figure 5-41), use the Draw menu to add lines, pins, circles,
arcs, and text. Pins will always be placed on the snap grid to ensure that the symbols and
wires will line up on the schematic. Other objects such as lines, text, and circles can be moved
off the grid for more precise placement. For precise placement of objects while editing
symbols, you can move these off the snap grid by selecting DrawSnap to Grid (off) and
then moving the objects. Symbol pins must have unique names and must be named to save the
file.
To edit a symbol pin, double-click the pin and the Properties dialog for the pin will appear
(Figure 5-39).

Figure 5-39 Properties Dialog (Pin)

This dialog assigns three possible behaviors to a pin.
• Normal: A pin with a name and no signal information associated with it.
• Unconnected_OK: Allows the pin to be unconnected (unwired). If the SIGNAME text box
is empty, Gateway will ignore the pin for the netlist. If the SIGNAME box has a value and
the pin is not wired, Gateway will use that SIGNAME value for the node name at that pin. If
the pin is wired, the signal name of the wire will become the node name at that pin for
netlisting purposes.

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• Implicit: Assigns an implicit connection from the pin to a node name elsewhere on the
schematic. The SIGNAME can be VCC, GND, or any node that exists in the simulation. Its
visibility will always be on. If the pin is wired, the implicit SIGNAME will override the
existing wire name due to procedure.
Figure 5-40 describes all possible cases. In addition to the other pin attributes, there are pin
direction and vlg discipline attributes. The pin direction assigns directional behavior to the
pins as input, output, bidirectional, or undefined. By default, the pins are input type. If the pin
types in the symbol do not match pin types for the schematic view of the same cell, Gateway
will issue a warning at drawing check and netlist times. For simulators where pin direction
does matter (i.e., Verilog), make sure you assign the correct direction attribute for the pins.
The Vlg discipline field is used for assigning VerilogAMS disciplines to a node or a pin. This
is optional.

Figure 5-40 Instance Level Possibilities

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To add, delete, or modify symbol attributes, click EditProperties... when the symbol file is
open (Figure 5-41).

Figure 5-41 Symbol

Figure 5-42 Properties Dialog ( Symbol File)

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The Properties dialog for the Symbol file has five fields at the top:
• Designator Prefix - Specifies the prefix of the symbol which represents its type for the
simulator
• Category - This can be used optionally to assign the symbol to a category of symbols,
such as MOS, for example. This field is then used in the symbol pane in the editor for
filtering
• Init Callback- Executes the callback when the symbol or instance properties dialog is
initialized (populated).
• Value Changed Callback - Executes the callback when a value changes on the dialog.
• Done Callback - Executes the callback when the dialog/property is finished by pressing
OK on the dialog.
This dialog does the following:
• Adding attributes to or removing them from a symbol definition.
• Setting attributes to have default values.
• Assigning expressions for attributes.
• Setting default attribute visibility.
• Setting MIN and MAX value assignments for any attribute.
• Settings attributes to be hidden from the Instance Attributes dialog.
To add an attribute, click the Add button and then a new row in the dialog will appear.
Navigate through the dialog with the tab or arrow keys. Click in a cell to modify its contents.
As attributes are added, they can be ordered in the dialog. This order from top to bottom will
be the order the attributes are shown in the instance dialogs from top to bottom. Usually for
SPICE primitives, they will be in the order the attributes appear in the SPICE string. In the
row of navigation buttons on the right side of the dialog, there are options to move attributes
one up or down at a time, or move to the top or bottom of the list, and also one to reverse the
current order.
The columns in this dialog are defined as follows:
• Name: Name of attribute.
• Description: This is an optional field for giving a description about the attribute.
• Value: Value of attribute. A ? in the Value field denotes a mandatory parameter that must
be specified at the instance level. For example, if the design requires input for specific
values for the W and L for a device, set the value field for the W and L attributes to the ?.
Gateway will not generate a netlist unless these are given values at the instance level on
the schematic.
• Visibility: The visibility settings for these attributes reflect their visibility at the instance
level on the schematic. To change the visibility of an attribute, click the cell under the
Visibility column for the specific attribute and change the visibility settings from the pull
down menu. This dialog has the following visibility settings.
• None: Not displayed.
• Name: The name of the attribute will be visible.
• Value: The value of the attribute will be visible.
• Name=Value: The schematic will display the attribute's Name=Value. For
example, W=12u.

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• Result: The calculated numerical result of an expression will be visible.

• Name=Result: The schematic will display the attribute's Name=result. For
example, R=12.48 kohms.
• Type - Specifies data type (i.e., boolean, string, integer, or double).
• Unit - The default unit for the attribute.
• Fixed - Determines whether an attribute is changeable at the instance level. Here are the
following guidelines for a fixed attribute:
• A fixed attribute in the symbol file will always be in the symbol instance.
• The value of a fixed attribute in a symbol instance must always be the same value
as in the symbol file.
• The name and value of a fixed attribute cannot be changed at the symbol instance
level (i.e., you can't bring up the symbol instance attributes and edit a fixed
attribute).
• Fixed attributes cannot be deleted at the instance level.
• Show on Instance - If clicked Yes, the attribute will appear in the Instance dialog. Many
attributes used for intermediate calculations do not need to be seen at the instance level
• MIN and MAX Attributes - The MIN and MAX Attributes are used for limiting
the scope of values. These may be set in the symbol file definition to limit values
set at the instance level.
Default Attributes
The following is the definition of a default attribute:
• An attribute in the symbol file.
• An attribute that cannot be deleted from a symbol instance or have its name edited.
• An attribute that can be either fixed or non-fixed.
Rules for Merging of Attributes
The following rules for merging the attributes of updated or changed symbol instances.
• Attributes in the symbol instance that aren't present in the symbol definition will remain.
The attribute, however, can be deleted using the Symbol Instance Properties dialog.
• Attributes in the symbol definition that aren't present in the symbol instance are added.
• Fixed Attributes in the symbol definition will overwrite matching attributes in the symbol
instance.
• Non-fixed attributes in the symbol instance will overwrite matching non-fixed attributes
of the symbol definition.
MIN and MAX Attributes
The MIN and MAX attributes are used for limiting the scope of values. These may be set in the
symbol file definition to limit values set at the instance level.
Netlist String Attributes
Each Symbol has the following string attributes that determine how the symbol will netlist for
the available simulators. The info strings are for adding extra information to each specific
netlist, which could be links to models, comments, or anything that the simulator can parse
for simulation purposes. Though the Guardian and NDL strings are not for generating

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simulation-type netlists, they do provide a means to convey instance information on the

schematic into a format that the LVS and netlist-driven-layout require.
• SMART_SPICE - SmartSpice template string (used for SmartSpice family of simulators).
• SPICE_INFO_TEMPLATE - SmartSpice extra information string, which is added to the end
of the control file.
• GUARDIAN - Guardian (LVS) template string (used for Layout vs. Schematic comparison).
• GUARDIAN_INFO_TEMPLATE - Guardian extra information string, added to the end of the
control file.
• NDL - NDL (Netlist Driven Layout) template string (used for generating initial placement
for Expert).
• NDL_INFO_TEMPLATE - NDL extra information string, which is added to the end of the
control file.
• ATLAS - Atlas template string (used for creating Atlas MixedMode simulations).
• ATLAS_INFO_TEMPLATE - Atlas extra information string, added to the end of the control
file.
• VERILOG - Verilog template string (used for Silos simulator).
• VERILOG_INFO_TEMPLATE - Verilog extra information string, added to the end of the
control file.
• CDL - Circuit Description Language format string.

Note: Symbols having blank Guardian or NDL strings will use Smart_Spice strings in their place when a Guardian or NDL
netlist is created.

To edit these strings, assign characters that denote how the string will parse variables and
arguments to create the string. There is a legend that describes these metatokens that can be
seen by clicking the Show Legend box on any string editor dialog as shown in Figure 5-43.
There are two mechanisms for specifying these strings as shown in Figure 5-43. The function
mechanism is the first method, since the functions are named to represent what role they play
in the string definitions. The second mechanism is the metatoken approach.

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Figure 5-43 SPICE String Editor Showing the Legend

Figure 5-44 shows an example of a symbol that netlists differently for SmartSpice and
Guardian is the special nmostub case.
Figure 5-45 shows the SMARTSPICE string definition that is used to netlist the symbol for the
SmartSpice netlist. From looking at Figure 5-44, you can see that the PREFIX for this symbol
is XM. Therefore, a subcircuit type of device is netlisted when Gateway uses this string.
Figure 5-46 shows that the Guardian string refers to a true mosfet primitive and also two
primitive diode instances. This means that when the Guardian netlist is generated, this symbol
netlists as three separate devices: one transistor and two diodes.
The SmartSpice netlist then uses a subcircuit call for this instance and the Guardian netlist
uses a bipolar junction transistor for the instance.
The following lines display what this instance will produce for each netlist. The first is for
SmartSpice. The second is for Guardian.
Smartspice netlist:
XM6 NET2 NET2 GND GND NET2 GND NMOSTUB
+ W='(10)*1E-6' L='((4)*1E-6)' PFXNF='(1)'M='(1)'
Guardian netlist:
M_6 NET2 NET2 GND GND NMOSTUB W='(10)*1E-6' L='((4)*1E-6)'
M='(1)*(1)'
+ DP_XM6 GND NET2 PTUBCON DN_XM6 GND NET2 NTUBCON

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Figure 5-44 Special NMOS Symbol

Figure 5-45 SmartSpice String

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Figure 5-46 Guardian String

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5.8.3 Primitive Symbols

Primitive symbols in Gateway are symbols that behave as device primitives in context of the
simulator. As such, there are SPICE primitive symbols and Verilog primitive symbols.
SPICE primitive symbols are contained in the spicelib library. These symbols, such as voltage
sources, will have a unique DESIGNATOR PREFIX attribute that designates the type of symbol
it represents in the netlist. The DESIGNATOR PREFIX attribute for SPICE primitive symbols
may be anything except X and YVLG, which are reserved for other symbol types. A resistor has
a DESIGNATOR PREFIX of R, and a voltage source has a PREFIX of V, and so on. These
symbols will have SmartSpice string attributes defined to specify how the device will netlist.
Figure 5-47 shows an example of the SPICE npn primitive device for a bipolar junction
transistor.

Figure 5-47 npn bipolar transistor

Verilog primitive symbols in Gateway reside in the diglilb library. The primitive symbols use
a prefix of I and all are referenced to the primitives.v file that contains all primitive
module definitions. For example, the nand21 symbol references the primitives.v file and
calls the nand21 module definition, which uses the Verilog nand primitive. Figure 5-48 shows
an example of the nand21 symbol that references the Verilog nand primitive.

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Figure 5-48 nand21 Device using Verilog nand Primitive

5.8.4 Special Symbols

Special symbols are symbols that do not have a SMARTSPICE or Verilog attribute and are
used in adding extra information to the design.
Examples of special symbols are the chord and netInherit symbols that deal with wire naming
that matter for netlisting. Other special symbols are classified as power rails, schematic pins,
and grounds. The Gateway special symbols are generally found in the $default library.

5.8.5 Embedded, Attached, and Schematic Definitions

With the exception of special symbols, all other symbols (including primitive symbols) may
have a specified definition per simulator string. There are four possible definitions that are
available for each instance string:
• No definition
• Embedded Definition
• Attached Definition
• Generated Definition (from schematic)

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Each symbol can use only one definition per simulator string. An example of this is a symbol
that may behave as a primitive for SPICE, but for Verilog it can behave as a behavioral
module coming from an attached file. In the case of this symbol, all instances of the symbol
must behave the same way. Changing the symbol definition for a symbol propagates the
change to all instances of the symbol on all schematics.
No Definition
When this option is chosen, there is no underlying or attached circuit that is used. This is the
case for special symbols (e.g., many of the symbols found in the $default) and the analog
primitive symbols, whose definitions are derived only from the SPICE string.
Embedded Definition
An embedded definition is the case where the definition entered and stored in the symbol file.
This can be typed in or copied and pasted in. The embedded definition means is that there are
no external file path dependencies. The definitions can be edited by opening the symbol and
making changes, and saving.
Figure 5-49 shows an ideal opamp symbol and its embedded file definition. After opening the
symbol for edit, click the SmartSpice button and click the Definition tab. Then, choose
Embedded Definition from the pulldown menu. The definition of the ideal opamp subcircuit
is entered in, saved, and becomes the definition now for SmartSpice simulations.

Figure 5-49 Opamp Using Embedded Definition

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After completing the definition, you can automatically format the netlist instance string so
that the string and definition are compatible for the netlist and simulation. To do this, click the
Instance tab and press the button. After that is pressed, the dialog now looks like Figure
5-50 and the instance string and definition are complete. Press OK on the string editor dialog,
then press OK again on the Symbol Properties dialog, and then save the file.

Figure 5-50 Netlist String for the Ideal Opamp

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Figure 5-51 shows an embedded file definition that uses a Verilog module for the Verilog
string of a symbol. Then, clicking the Instance tab on the dialog and pressing the Generate
String from Definition button to generate the instance string results in Figure 5-52.

Figure 5-51 Embedded Definition of Verilog Module

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Figure 5-52 Netlist String for nor41

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Attached Definition
The Attached Definition option is used to attach a subcircuit definition or module definition
to the symbol by using a separate file. The file may have one or more subcircuits or module
definitions included in it. But the Instance tab on the dialog is used to isolate the specific
subcircuit or module definition to be used. The attached definition method is the only method
where encrypted definitions may be used.
Attached Files Containing Single Definition
To use the attached definition, open a symbol file or create one new. Then, open the symbol
properties dialog and then click one of the simulator strings. When the next dialog opens,
select the Definition tab. Then, choose Attached File from the pulldown menu and click the
Add button (plus sign). In the File box, click the Browse button and browse to the file. Then,
click OK and the dialog will look like Figure 5-53.

Figure 5-53 Attached File Definition for NAND2

As an alternative to browsing to the file and using the file path, there is another approach to
use if the files to be attached reside in a workspace library. The advantage to this is that the
design becomes more portable in that wherever the design is relocated, the definition files are
always stored with the symbol libraries instead of somewhere else on the local machine or
network. Because the symbol libraries are required for the designs, the definition files
automatically come with them.

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To use this method, the $$ metatoken is used to denote a direct reference to the library. In
this case, when you use $$libraryname, Gateway resolves the paths automatically and
ensures the files are available for netlist and simulation. In this example, there is a library
named design and a file named primitives that has a subcircuit definition for the 2-input
nand subcircuit.
There are two other fields in the Attached File Definition: Type and Entryname. The Type
field is for setting what type of file is added here. Choose the .INCLUDE option for only
including a file. For attaching SPICE libraries, use the .LIB option and then type in the
library entryname in the Entryname field. For attaching Verilog-A files, use the .VERILOG
option. For Verilog string types, there are no Type and Entryname fields in the dialog.
Regardless of which method was used, the instance string needs to be created to complete the
symbol. To do this, click the Instance tab and press the Generate String from Definition
button to create the netlist string. The result is Figure 5-54.

Figure 5-54 Instance String for NAND2

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Attached Files Containing Multiple Definitions

It is also common that there can be multiple subcircuit or module definitions residing in the
same file. The procedure to attach the file is similar to the one previously described, except
there is an extra step involving choosing the specific subcircuit or module to be used. In this
method, when generating the simulator string, there is a pulldown menu for choosing the
specific subcircuit or module. Figure 5-55 shows the dialog for choosing a module definition
from the file primitives.v that contains several dozen module definitions. Once the correct
module is chosen, Gateway knows how to format the netlist string.

Figure 5-55 Choosing Module Definition from Attached File

Using Multiple Attached Files
Multiple files may be attached for dependencies. If more than one attached file contains a
subcircuit or module definition with the same name, Gateway always will use the first file
shown in the list. Use the up and down arrow buttons on the dialog to move files up or down
in the list.

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Generated Definition (from Schematic)

The Generated Definition is used for symbols that use schematic drawings to derive the
netlist for them. Figure 5-56 shows a symbol set to use a schematic definition and shows the
schematic that goes with it. Gateway automatically uses the schematic with the same base
name as the symbol to derive the netlist. In the case of Figure 5-56, symbol inv.symbol uses
the schematic definition for inv.schlr to derive its netlist. The Generated Definition
option does not need an instance string as Gateway automatically generates the instance
string from the schematic.

Figure 5-56 Inverter Definition Using Generated Schematic Option

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Figure 5-57 shows the Instance tab for the inverter symbol with the Generate String button
grayed out for this reason.

Figure 5-57 Generated View that does not need an Instance String

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Passing Parameters From Symbol to Schematics

To illustrate this section, refer to the symbol and the schematic in Figure 5-58.

Figure 5-58 inverter.symbol and inverter.schlr

To pass parameters:
1. Define the parameters in the symbol file. Click Add in the Edit Symbol Attributes dialog.
For the inverter, click Add four times.
2. Add the four attribute names, values, and visibility as shown in Figure 5-59 and press
OK.
3. Move the parameters to the desired location on the symbol (Figure 5-60).
4. Add a parameters.symbol symbol from the spicelib on the inverter.schlr
schematic.
5. Double-click the parameters.symbol instance and edit as shown in Figure 5-61.
The inverter.symbol and inverter.schlr files in Figure 5-62 can pass parameters down
the hierarchy.

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Figure 5-59 Properties Dialog (for Symbol File) shows width and length attributes for n-type and p-type

Figure 5-60 Passable parameters aligned on the inverter

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Figure 5-61 Instance Properties Dialog for the parameters symbol

Figure 5-62 Passing Parameters to inverter.schlr

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Passing Parameters from Symbols to Attached File Definitions

In the case where symbols have an attached file definition, Gateway will automatically add
the parameters to the symbol and netlist string from parsing the subcircuit or module
definition in the attached file. In case the subcircuit definition in the file did not use the
PARAMS keyword, you still can get the symbol to pass parameters locally by these steps:
1. Add the parameters to the symbol file.
2. In the SPICE string, add the keyword PARAMS: followed by the parameters.
Figure 5-63 shows W and L being added to the string so that values of W and L can be passed
into the subcircuit from the instance level. The dollar sign ($) metatoken preceeding the
attributes means that the netlist will specify the NAME=VALUE representation for each one. For
example, if W were set to 4u and L were set to 1.8u for one instance of the symbol, the netlist
line would read: W=4u Lu1.8u.

Figure 5-63 Syntax for Passing W and L from Symbol to Subschematic

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Defparams
The defparam statement must be used when passing instance specific parameter results. The
syntax of the defparam statement is $(defparam(n, n1)), where n is the name of the
attribute whose result is placed in the defparam and n1 is an optional parameter to the
statement in cases where the result needs a different name.
For instance, $(defparam(r, res)) will create .defparam X1.R1.res = 10k in SPICE,
assuming the instance level is X1 and the instance name is R1.
Other examples of using the .defparam statement for SPICE netlists are
.defparam x1.x4.wn=10u
.defparam l=5u
The first example overrides the wn parameter on the level x1.x4.
The second example overrides the l parameter on the top level.
Gateway will automatically add defparam statements when needed for SPICE and Verilog
netlists. The defparam statements will be placed in an included file.

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5.9 Generating and Regenerating Object Names

Gateway has utilities for renaming symbol instances, pins, and nets. These dialogs are found
under the Tools menu. They are the Regenerate Symbol Names dialog, the Regenerate Pin
Names dialog, and the Regenerate Net Names dialog.The Regenerate Symbol Names dialog
shown in Figure 5-64.

Figure 5-64 Regenerate Symbol Names Dialog

Each of the three regenerate dialogs has some common fields. They are
• Begin at – This is the first number of the renaming sequence. For example, to start
renaming nets with net1, set this field to 1.
• Increment by – This the number added to the number in the Begin at field or the number
the sequence will increment for each instance. For example, if you set this field to 1 for
the example above, the next items in sequence will be renamed as net2, net3, and so on.
• Direction – Choosing X renames the objects in a horizontal direction. Choosing Y
renames the objects in a vertical direction.
• Assign from – Choose from Top left, Top right, Bottom left, or Bottom right to choose
the starting point of the selection for the renaming sequence.

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5.9.1 Regenerating Symbol Instance Names

The names of the instance designators (reference designators) for symbols are regenerated by
the options in the dialog shown in Figure 5-64. In the Type area, there are choices for System
generated and User defined names. System generated names are names given to symbol
instances by Gateway that have not been renamed by any user. For example, placing a new
resistor symbol down and doing nothing else, Gateway automatically names the resistor R1.
But if you double click on that resistor and change the name to Rout, it becomes a user
defined name. You can choose to regenerate instances with either type or both.
The Matching symbol prefix text box controls the scope of which symbol names to
regenerate. By default, there is a wildcard character (*) in the box. The wildcard character
means there is no restriction on which symbol names may be regenerated. To restrict the
scope of which individual symbols will be renamed, type the prefix(es) in this text box. For
example, if you want to limit the renaming only to resistors, type R in the box. To limit to only
resistors and diodes, type R D, or R, D.
The Ignore Subscripts option does not include symbol instances that have subscripts in their
names. Subscripts are enclosed with angle brackets (< >) and signify single bits of a bus or a
range of bits. If you check the Only Subscripts box, only symbol instances with subscripts in
their names will be regenerated.
The Symbol Name Separator field provides characters that will appear between the prefix
and the incrementor. If there is nothing in this field, names will appear like R1 and R2. To
place a hyphen in the box, the regenerated names will appear like R-1 and R-2.

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5.9.2 Regenerating Pin Names

Figure 5-65 shows the Regeneratie Pin Names dialog. The three pin types that can be
regenerated are input, output, and bidirectional pins. These are directly tied to the inschpin,
outschpin, and bischpin symbols from spicelib respectively. Each pin type also has a default
prefix that will result from the dialog. To regenerate the type(s) of pins to be regenerated,
check the boxes. You can then modify the prefixes for any symbol type.

Figure 5-65 Regenerate Pin Names Dialog

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5.9.3 Regenerating Net Names

Figure 5-66 shows the Regeneration dialog with the Nets tab selected. The Type section
shows the options for choosing the type of nets to be regenerated. System generated net
names are names assigned to nets by Gateway. If you name or rename any wire or net, the net
has a user-defined net name. Choose either type or both accordingly by checking the
appropriate box(es). You can also refine the choices by including nets to have implicit or
global attributes associated with them. Check the appropriate boxes in the dialog to these
include these nets in the regeneration. The filter can be used to select which nets to
regenerate.
The net name pattern string is set to net%1 by default, the %1 will be substituted with the next
available index. Following these settings, nets will be generated as net1, net2, and so on.
Finally, if you make changes in any part of the entire dialog and you want to go back to the
Gateway default settings, click the Default Settings button on the dialog.

Figure 5-66 Regenerate Names Dialog

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5.10 Creating Arrays

Gateway can setup one or two dimensional array design using the Array Paste dialog. First,
choose a symbol from one of the symbol libraries and place it on the schematic. Then, select
it and copy it.
Now select EditArray Paste from the main menus, and then view the Array Paste dialog as
shown in Figure 5-67.

Figure 5-67 The Array Paste Dialog

The X Copies field represents the number of elements representing the X dimension in the
array. The Y Copies field represents the number of elements representing the Y dimension in
the array. To create a single row of five resistors, set the dialog as shown in Figure 5-68.

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Figure 5-68 Array Paste Setup for a Row of 5 Devices

After pressing OK, the resulting schematic will look like Figure 5-69.

Figure 5-69 Single Row of 5 Resistors

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To create a single column of resistors, set the dialog as shown in Figure 5-70.

Figure 5-70 Array Paste Setup for a Column of 5 Devices

After pressing OK, the resulting schematic will look like Figure 5-71.

Figure 5-71 Single Column of 5 Resistors

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To create an array of 55 resistor devices, set the dialog as shown in Figure 5-72. The
resulting schematic will then look like Figure 5-73.

Figure 5-72 Array Paste setup for a 5x5 array of devices

Figure 5-73 55 Array Named in the X Direction

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The Instance Name Order section of the dialog controls how the instances will be named.
The default is the X direction beginning from the top left of the array. Figure 5-73 shows this
as the instances begin at R1 on the top left and progress in the X direction.
The X Offset and Y Offset fields tell Gateway how much to separate the elements in the
array (in pixels) in either dimension. A 55 array is shown in Figure 5-74 where the offset
distances for both X and Y are doubled from 60 to 120.

Figure 5-74 55 Array with Spacing Doubled

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Figure 5-75 shows how the array will be named if the Instance Name Order Direction was
set to Y and beginning at the top left.

Figure 5-75 55 Array Named in the Y Direction

The instance designator fields control how the instance names are incremented. The Start
field sets the number for the first instance in the array. The Increment field sets the amount
each instance is incremented. If that number is set to 2, for example, and the Start field is set
to 1, then the array will be numbered 1, 3, 5, 7, and so on.

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5.11 Generating Symbols

The Generate Symbol tool can be used to generate new symbols, to automatically generate
symbols from schematic views, or to rework or modify existing symbols. The Symbol
Generator can set the footprint to one of fourteen different shapes, including standard logic
shapes. The dialog also can add and remove pins and move pins around the symbol to
customize where they should be placed. The height and width of the symbol can be manually
changed as well as placement of the title and instance designator of the symbol.
Figure 5-76 shows the Symbol Generator when launched for a new symbol. All buttons on the
dialog have tooltips to provide a guide to what each one does. On the left side of the dialog,
there are four areas to represent the top, bottom, left, and right side of the symbol. This is the
area for showing where the pins are located. To create a pin, click one of the buttons on
one of the sides. This creates a pin with a default name, and depending on which area it is
created, sets the directional attribute for the pin. On the left side, the pins are created as input
pins. On the right side, they are output pins. If a pin is created on the top or bottom side, they
are set to be bi-directional. To move a pin from one side to another, select the pin in the list
and press one of the directional arrows to move the pin to another place. Moving a pin from
one side to another does not change the type (input, output, or bi-directional); it only changes
where the pin resides on the symbol footprint. To remove a pin, select the pin(s) and press the
button. To reorder pins on any one side, select the pin(s) and press one of the arrows
( ). To rotate text orientation on the pin, select the pin(s) and press the button.

Figure 5-76 Symbol Generator

The right side of the dialog contains the various options for the symbols. The pulldown menu
for shape contains fourteen standard footprint shapes for setting the symbol. By default, the
shape is set to be rectangular. At any time, the shape can be modified by changing the shape
to one of the options in the list. You can set the height and width by changing their values on
the dialog. The height and width can also be automatically scaled by the numbers of pins and
other parameters that are taken into account to meet all the requirements as set in the dialog.
The text size is also set manually. For width, height, and text size, pressing the button
next to any of these sets this to the optimal value for each.

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The Place Pins option is for setting the pin names to be inside or outside of the symbol
footprint. The Place Title option specifies where the title (if applicable) of the symbol should
be placed. By default, it is in the center of the symbol. The Place PATH option specifies
where the instance designator is to be placed for the symbol. By default, it is located on the
bottom-right of the footprint.
There are two options that are related to the calculation of how the symbol is automatically
sized. These options are:
• Include Title in dimension calculation – With this option ON, the symbol having long
names will scale to be large enough to encompass the name of the symbol within the
footprint. With the option OFF, the symbol names can overlap the footprint.
• Include Pin names in dimension calculation – With this option ON, pin names are
taken into consideration in calculating the symbol dimensions to prevent text from
overlapping on the symbol.

5.11.1 Generating Symbols from Schematics

To generate a symbol from a schematic drawing, open the schematic and click
ToolsGenerate Symbol. Use the controls described in the section above to customize the
symbol as needed. When finished, press OK. If a symbol view already exists for a schematic
and ToolsGenerate Symbol is pressed, a warning message like Figure 5-77 will appear to
ask whether you want to overwrite the symbol or now.

Figure 5-77 Warning Message Dialog

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5.12 Descending to Subcircuits from Symbols

Any schematic may contain symbols that descend into sub-schematics. To descend into a sub-
schematic, right-click on the symbol and select Descend from the Right Mouse menu or click
the shortcut D. The View menu also contains actions for Ascend and Descend. To ascend
back to the parent schematic, click the shortcut A or right click the symbol and select Ascend.
Also, the Design Browser pane is very useful for descending and ascending up and down
through a hierarchy by expanding and collapsing the tree. You can open a schematic many
levels down in a hierarchy by simply expanding the tree down to the appropriate level and
then clicking on the node in the tree.
To change the view of a cell, right-click on the background of the drawing and select the
alternate view. For example, if a symbol is open for edit, right-click the background of the
drawing and select Schematic to change to the schematic view.

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5.13 Change Symbol

The Change Symbol dialog (Figure 5-78) is for updating and changing symbol instances.
There are several uses for this dialog. They are as follows:
• Converting schematics after EDIF import
• Changing technologies on the same design cell
• Updating specific instances on a cell
• Changing specific instances to instances of a different type
• Changing libraries over an entire design
The Change Symbol dialog is designed to quickly and efficiently process the changes either
globally or on a per instance level. Follow the sequence of sections in this dialog from top to
bottom.

1. Select to merge or replace the attributes for the targeted instances.

2. Decide which instances are going to be affected by the Selection Filter. The Selection
Filter also specifies the scope of the target instances in terms of the design scope.
3. Use the Existing Symbol Filter to show the specifics of the symbol and libraries of the
selected instances.
4. Use the New Symbol Filter to choose the new symbols and from what library they are to
come from.
This choice of merging or replacing is important. Merging them will retain attribute values
from the original symbols if those attributes exist in the new symbols. Replacing instances is
the equivalent of actually deleting and re-instantiating the instances. Therefore, nothing from
the original instances is retained.

Figure 5-78 Change Symbol Dialog

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5.13.1 Change Symbol Dialog

To open the Change Symbol dialog, select ToolsChange Symbol(s) or right-click on the
schematic canvas and choose Change Symbol. The Change Symbol dialog has three areas:
Selection Filter Area, Existing Symbol Filter Area, and the New Symbol Filter Area.
The Selection Filter Area is at the top of the dialog. In this area, there are two pull-down
menus: Change and On. The Change menu (Figure 5-79) chooses what instances are to be
changed. The On menu (Figure 5-80) chooses where these instances will be replaced in terms
of the scope of the design hierarchy.

Figure 5-79 Change Menu

Figure 5-80 On Menu

Selection Filter Area
ALL - Affects all symbols whether they are in the current selection or not. If this is selected,
all symbols will be changed. For example, change all symbols to a newer version in a
different library.
ALL Placeholders - Affects all <placeholder> symbols whether they are in the current
selection or not. Placeholder symbol instances have <brackets> around them. For example,
change any placeholders to valid symbols from a library in the workspace.
ALL Selected - Changes all selected symbols to a specific symbol from a specific library,
regardless of the different symbol types in the selection. For example, change a selection of
instances of different types (i.e., Resistors and Capacitors) to one type (only Rs).
Selected - Changes and filters a specific symbol from a specific library. For example, select
different symbol instances (Rs and Cs) and filter which one to change (Rs or Cs).
Matching - Changes all the matching symbols. Matching symbols are symbol with the same
name from the same library. For example, change all resistors from library A to resistors from
library B.
Matching & Selected - Changes any matching symbols in the selection to new symbols from
a library of choice. For example, making a selection of Rs and Cs and changing all matching
Rs and Cs to another symbol type.
Current Sheet - Changes the desired symbol instance(s) on the current sheet only.
All Sheets - Changes the desired symbol instance(s) on all sheets of a flat design.
Descend Hierarchy - Changes the desired symbol instance(s) from the current level of the
design and down throughout the hierarchy.

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Entire Simulation - Changes the desired symbol instance(s) on the current level, down the
hierarchies, and the parent cells. This is for schematics that are open and the active schematic
is other than the top cell.
Existing Symbol Filter Area
The Existing Symbol Filter Area contains the selection of symbols to be changed. When
symbols are selected on the schematic and the Change Symbol dialog is opened, the menu
items are filled with specifics for the selection. The library of origin and symbol name reflect
what has been selected on the drawing. For certain cases, these fields will be enabled to re-
filter selection. This depends on the choices made in the Selection Filter Area.
New Symbol Filter Area
The New Symbol Filter Area contains the pull-down menus to choose which library and sub-
library the desired replacement symbols will come from. The new symbol name menu will fill
symbols in the library that is displayed in the Library field.

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5.14 Reload All Libraries

After editing and then saving symbols, there are cases when the symbol definition has not
reloaded for its instances on the schematic. For example, if another user has updated a symbol
file, the instances on the schematic may not reflect the last changes. To update all symbol
definitions, select ToolsReload All Libraries and the Reload All Libraries dialog will
appear (Figure 5-81). This will reload all symbol definitions in the workspace and update
them on the schematics. This operation cannot be undone. Click the checkbox in the dialog to
prevent the window from popping up for subsequent reloading actions.

Figure 5-81 Reload All Libraries Dialog

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5.15 Miscellaneous Editing Options

5.15.1 Adding Wire Stubs and Wire Stubs with Pins
You can add stub wires to placed symbols that are not yet connected to anything. Selecting
DrawAdd Wire Stubs places short wire segments on the bare pins and labels the wires
with names of the symbol pins. To add stub wires and pins to the device, select DrawAdd
Wire Stubs with Pins. Right-clicking on the symbol will also open up these two menu
options. If you place a symbol while holding down the Shift key, it will also place stub wires
with the symbol.

5.15.2 Adding Text

Text and labels may be added to the schematic. To add text to the schematic:

1. Press or select DrawText and the Enter Text Window will appear.
2. Type in the text and press OK. The text will now be floating with the cursor.
3. Click the left mouse button to place it at the desired location.

5.15.3 Adding Drawing Objects

To add drawing objects to open drawings, click the Draw menu and choose from the
following object types:
• Lines
• Circles
• Semi-circles
• Quarter-circles
• Arc by 3 points
Use the left mouse button to begin drawing. Then, click the left mouse button again to finish.
Lines can be drawn vertically, horizontally, or diagonally. Circles and arcs are drawn using
the radius of the circle. Once you place an object, double-click on the object to edit the size
and thickness of the object.

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Figure 5-82 shows the dialog for line properties of a line drawn on a schematic. Figure 5-83
shows the dialog for changing the properties of a circle object.

Figure 5-82 Line Properties Dialog

Figure 5-83 Circle Properties Dialog

5.15.4 Edit Color and Reset Color

You can change the color of a wire or symbol object to a desired color. To do so, select the
wire or symbol, select EditColor, and choose the new color. You can also change the color
from the menu by right-clicking on the object. To reset back the object to its default color,
either select EditReset Color or right-click the object and select Reset Color.

5.15.5 Object Alignment and Spacing

The following shows you how to neatly place objects and spacing in schematics. Selecting
EditAlignTop will align the bounding boxes of all the selected objects to the top most
selected object. If the an attribute and its symbol is selected with , it will not be realigned.
To evenly space objects, select EditAlignHorizontal Spacing. The objects will be
arranged evenly in the horizontal direction. You can have better control of the spacing by
selecting EditManual Spacing. This allows you to specify the size of the space between
objectsor space objects on a constant pitch (object center to object center) in the vertical or
horizontal directions.
Figure 5-84 shows the Align Object icons. They are Top, Right, Left, Bottom, Horizontal
Center, and Vertical Center.

Figure 5-84 Object Alignment Icons

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• – Top

• – Right

• – Left

• – Bottom

• – Horizontal Center

• – Vertical Center
Figure 5-85 shows the space evenly icons Horizontal spacing on the left and Vertical spacing
on the right.

Figure 5-85 Space Evenly Icons

Figure 5-86 shows the Manual Space Evenly dialog. This allows you to select the direction,
type of spacing or pitch, and the size of the spacing or pitch.

Figure 5-86 Manual Space Evenly Dialog

5.15.6 Frames and Sheet Borders

Gateway schematics can have sheet borders, or "frames" placed on any schematics in the
design. These frames have a border and a legend. Section 2.2 “Preferences Dialog” describes
the frame settings in detail, since they can be stored as a user preference. To add a frame to a
schematic, select ToolsFrameAdd to This Sheet. The frame is then placed on the
schematic according to the settings in the preferences. By default, the title is set to the full
directory path of the schematic. The subtitle by default is set to the name of the schematic.
To change any settings of the frame once it has been placed, select ToolsFrameSettings
and then make changes as required. This includes changing any text in the text fields,
changing the frame size, the style (location of the legend), and the origin (origin point of the
frame with respect to the center (0,0) coordinate of the schematic).
The legend size can be increased and decreased for readability on large schematics. To
increase the legend size, select ToolsFrameLegendIncrease Size. To decrease the
legend size, select ToolsFrameLegendDecrease Size.

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For schematics that are multisheet, you can add sheet frames to all sheets at once by selecting
ToolsFrameAdd to All Sheets. Sheet Frames may be deleted by selecting
ToolsFrameDelete from This Sheet or ToolsFrameDelete From All Sheets.

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5.16 Find Dialog

When a drawing is opened, press Ctrl+F or choose EditFind will open the Find dialog
(Figure 5-87). The dialog operates using filters to specify what object types you are trying to
find. These are shown in the Filters section of the dialog, and include Symbols, Attributes,
Signals, and Comments. There are options for matching the case, matching the whole word,
and searching up (reverse order). Also, you can set the scope to search only the current
schematic, or all open schematics, of the current simulation.

Figure 5-87 Find Dialog

5.16.1 Example
To find a specific resistor (R5) on a schematic, enter R5 into the Find What field and press
the Find Next button.. The R5 instance will be highlighed and selected, and the Properties
pane will reflect the selection.
To find all resistors, type R in the Find What field and press Find Next. Each time you press
Find Next, Gateway will highlight the next resistor found, and the context will be shown in
the Properties pane.

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5.17 File Details

Selecting FileDetails opens the Details dialog box. Figure 5-88 shows the Details dialog
when opened from the example RSFF_simulation.schlr. There are some basic properties
shown at the top such as the file name, the size of the file, and version. The dialog has two
tabs: Schematic and Simulation. The Schematic tab shows a count of only device types and
nets on the current schematic.

Figure 5-88 Details Dialog

Figure 5-89 shows the Details dialog with the Detailed box checked. This in addition shows
each a count for all symbols used in the design by symbol name and library of origin. This
shows each symbol used in the schematic and how many instances of each are there. For
example, there may be a count of 2 capacitors shown in the basic view. But the detailed view
will reveal if those were 2 instances of the same capacitor symbol or whether they were
different symbols or even from different libraries.
The Simulation tab contains total device counts for the entire simulation.

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Figure 5-89 Detail Dialog with Detailed box checked

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 Chapter 6
Viewing and Navigating Designs
The View Options Viewing and Navigating Designs

6.1 The View Options

Figure 6-1 shows the View pull-down menu in Gateway. Table 6-1 describes what each
option in the menu does.

Figure 6-1 View Menu

Table 6-1 View Menu Options

Menu Option Description

Zoom In Zooms in on the current drawing

Zoom Out Zooms out on the current drawing
Zoom Full Fits entire drawing in view in current drawing
Zoom to Area Zooms to selected area on current drawing
Ascend Ascends up hierarchy to parent drawing
Descend Descends down hierarchy to child drawing
Symbol Opens symbol file for edit
Schematic Opens schematic for edit
Net NamesAll Shows all signals on one net of wires
Net NamesUnique Shows only the unique signals on one net of wires

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Table 6-1 View Menu Options

Net NamesNone Hides all net names on the schematic unless the “Show
Name Always” flag is set on any net

Net NamesShow Generated Toggles whether to display net names generated by

Names Gateway.

Grid Toggles grid to be visible or not

Info Displays information on selected nets or symbols
Capture/Simulation Toggles between Capture and Simulation mode
Full Screen Toggles on/off all paned areas
Refresh Refreshes current drawing
Re-center Re-centers current drawing
Clear Clears session pane or output pane contents
Windows Selects window panes to show/hide
Toolbars Selects toolbars to show/hide

6.1.1 Zooming and Panning

The parameters tab of the Preferences dialog contains the zoom and pan percentage. By
default, these are set to 20% zoom factor and 10% pan factor but they can be changed. This
factor is the percentage of the total drawing area to be navigated by the zoom or pan action.
The zooming functions are performed by using the keyboard shortcuts, toolbars, or from the
menu in Figure 6-1. To pan the drawing, use the arrow keys on the keyboard to pan the
drawing in the desired direction.
There is also a Preview pane that acts as a panning device. Figure 6-2 shows the preview pane
in the bottom right corner of the Gateway window. The rectangle is showing the part of the
preview pane that is displayed on the schematic window. Dragging the rectangle in the
preview pane will pan the schematic. Clicking another area in the preview pane moves the
rectangle to that area and displays that part of the drawing in the schematic window. Figure 6-
3 shows the result of dragging the rectangle from where it was in Figure 6-2 and how the
schematic view changed. This is useful on large schematics where you can pan from one end
of the design to the other quickly.
As the schematic is zoomed in further and further, the rectangle will grow smaller and smaller
as a smaller portion of the overall schematic is in focus. At any time, you can bring the
drawing back to the default size, which will then fit the entire drawing to the window. To do
that, click the ‘f’ key or ViewZoom Full.

Note: The scroll wheel on a mouse zooms in and out on drawings when the cursor is placed over the drawing area.

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Figure 6-2 Gateway Window showing Preview Pane

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Figure 6-3 Gateway Window with Panning Effect

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6.1.2 Ascending and Descending

For hierarchical schematics, the descend and ascend actions from the view menu will open
the schematic at the adjacent level. From a top level drawing, click a symbol that descends
and then click ‘d’ or right click the symbol and select ViewDescend (Figure 6-4). To go
back up to the parent schematic, click ‘a’ or right click the schematic background and select
ViewAscend (Figure 6-5).

Figure 6-4 Descending into the Schematic

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Figure 6-5 Ascending up to higher schematic level

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6.1.3 Design Browser

The Design Browser is another useful tool for navigating through the schematic hierarchy.
Figure 6-6 shows the tree expanded in the Design Browser pane on the right side of the
Gateway window. The Design Browser makes it possible to open lower levels of the design
without having to descend and open each level. To achieve this, expand the node of the tree at
the top level in the design browser. Then, continue to expand down without clicking the
branches. Finally, select the branch to be opened. You can select the branches while
expanding, which will open the schematics along the way. Double-clicking on any branch
also expands the tree to show levels below.
Figure 6-7 shows the Design Browser in detail. The panel of icons on the top of the browser is
to set the target netlist environment for the design. By default, the target netlist is set to
SmartSpice. In this case, the icons in the Design Browser are red to designate the analog
domain. The browser works the same for all domains in terms of navigation ability. It differs
in that changing netlist types uses different views for the same design. If the target netlist is
switched to Silos, for example, the icons turn green and the default Verilog views of the cells
are then used for the design.
In the tree of the Design Browser window, the top level of the design is named at the top of
the tree. From that level, the design can be navigated to any level by expanding levels of the
tree. The schematic icons designate that the level of the tree is a schematic, and the symbols
designate instances of cells placed on a parent schematic. The area to the far right in the
Design Browser shows the cell pins when a symbol instance is in context and shows ports and
wires when a schematic instance is in context. Double-clicking on those ports or wires (as
shown in Figure 6-8) allows you to change their properties.
The Scope box allows you to type in a hierarchcal reference designator and Gateway will
then goto the device. For example, to locate a transistor 'M7' that is three levels down in the
hierarchy, the path may be entered such as X1.X2.X11.M7 and then press the Enter key.
Gateway will first expand X1 on the top level, then expand X2 on the level below. Then,
expands X11 and finally highlight M7 on that drawing. Once a scope has been entered, it is
stored and can be revisited using the pulldown menu.
Right-clicking on any object in the tree will open a context menu shown in Figure 6-9. These
options work as follows:
• Goto Instance – Highlights and centers the selected instance on the active drawing.
• Goto Definition – Opens the definition of the selected instance in its active view
(schematic definition, embedded definition, or file definition).
• Goto Symbol – Opens the selected symbol for editing.
• Properties – Opens the instance attributes dialog for the selected instance.

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Figure 6-6 Gateway Window with Design Browser

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Figure 6-7 Design Browser in Detail

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Figure 6-8 Changing the Properties in Design Browser

Figure 6-9 Context Menu

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6.1.4 Showing Node and Symbol Information

Selecting ViewInfo displays names of symbols and nodes on the schematic. This mode can
select up to four nodes or symbols or a combination of both at one time. To see node
information, click ViewInfo and click on any wire. The node is highlighted as shown in
Figure 6-10. To select more than one node, hold the Ctrl key down and select up to three more
nodes. To see symbol information, click ViewInfo and click a symbol as shown in Figure
6-11. The symbol information shows the reference designator, library of origin, and name of
symbol.

Figure 6-10 Highlighted node with information

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Figure 6-11 Highlighted Symbol with information

6.1.5 Viewing Net Names

The View menu has three options for viewing the net names on schematic drawings. To set
these, click ViewNet Names and then choose one of the following:
• All – Shows all names for all named segments of the net.
• Unique – Shows the main name of the net and hides the other segments of the same
name.
• None – Toggles off all net names unless the "Show Name Always" flag is set for the
specific net.
• Show Generated Names – Toggles on or off the visibility of net names generated by
Gateway.

6.1.6 Viewing the Grid

To toggle the visibility of the grid, select ViewGrid or click the (Toggle Grid) icon.

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 Chapter 7
Design Flow
Overview Design Flow

7.1 Overview
Once the schematic has been defined and captured, it’s ready for a design flow. Figure 7-1
shows the design flow in Gateway. To perform a design flow, begin with the schematic
capture and proceed as follows:

1. Choose a simulator and a domain. This can be done later but choosing at this point in the
flow means that all instance views will be set as defined at the time they are placed on the
schematic.
2. Check the schematic design.
3. Review any errors and make changes to the schematic. If there are errors creating the
netlist, review the errors and correct them. If there are no errors, go to step 4.
4. Generate and view the netlist.
5. Create a simulation profile. A control file is then created for the active simulator
preference. Specify any analysis, model information, options, or additional information
needed in the control file.
6. Place markers on the schematic for saving vectors (for the SmartSpice family of
simulators only).
7. Create and view the input file. This is the file that assembles the netlist, control file, and
associated files for simulation.
8. Run the simulation.
9. View the waveforms in the waveform viewer, and post process the data.
10. Cross probe between waveform viewer and schematic (for the SmartSpice family of
simulators only).

Figure 7-1 Gateway Design Flow

Note: Viewing the Netlist and Input File is optional.

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7.2 Checking a Schematic

To check a schematic, press . Gateway will then parse the schematic and check for
illegal operations. If there are illegal operations, Gateway will display them in Session tab
and Review Errors tab (Figures 2-2 and 7-2). The Output tab has a summary of the number
of errors or warnings or both generated and whether the drawing check passed or failed. The
Review Error tab has precise information on the individual errors.

Figure 7-2 Review Errors Tab

There are two other drawing checks:

1. Check this level and below checks the current drawing and all hierarchy below if
applicable.

2. Check all levels checks the entire simulation even though the drawing in focus
may not be the top level drawing.

7.2.1 Error Handling and Viewing

The Review Errors tab displays the illegal operations in the order Gateway found them. To
review the errors, click on one of the errors listed in the window (see Figure 7-3). Gateway
will then zoom to the location of the error (if available) and highlight the wire, pin, or symbol
with the error. Figure 7-3 shows only unconnected pin errors without device warning.
Clicking any of these shows the error on the drawing. You can use the arrow keys on the
keyboard to step up and down through the errors as Gateway displays them on the drawing
when selected. This makes it possible to fix the errors as you review them, including entering
the wire mode and fixing wiring problems.
Figure 7-4 shows the wire mode active as you fix the second error. Once you step through the
errors and fix them all, run another drawing check to see if there are still problems.

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Figure 7-3 Clicking on a Error

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Figure 7-4 Wire Mode active while fixing the Error

There are two types of illegal operations that will appear in the Reviews Errors dialog:
Warnings and Errors.

Warnings ( ): Warnings will not affect the ability to netlist the schematic or the simulation
but will show potential errors in the netlist.

Errors ( ) will most likely cause SmartSpice to malfunction, such as preventing a

schematic from simulating or will prevent the netlist from being generated.
You can upgrade Warnings to Errors to allow certain design checks to flag as errors to prevent
common mistakes in the schematic.

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7.2.2 Enabling and Disabling Warnings and Errors

Figure 7-5 shows the settings for warnings and errors. The dialog has two sections: System
Drawing Checks and Configurable Drawing Checks.
System Drawing Checks consist of errors only and cannot be downgraded to warnings.
System Drawing Checks are set by Gateway and the status of these is full-time On. These are
marked by a red icon ( ) and each has an index number to reference the error. Errors
prevent a netlist from being generated.
Configurable Drawing Checks can be either warnings or errors, depending on how severe you
want to label each drawing check.

Warnings are marked by ( ) yellow icons. To turn a specific drawing check on or off,
check the box in the Status column. In the Severity column, all checks are set as warnings
unless the box is checked and set to error status. You can also turn off the status of
configurable checks using the Review Errors pane by right-clicking on a given drawing
check and selecting Disable.

Figure 7-5 Drawing Checks in Preferences

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7.3 Netlisting
A netlist is a file created by Gateway containing connectivity information between symbols,
signals, wires, and pins of a schematic. The types of netlists Gateway can generate are as
follows:
• SmartSpice: The SmartSpice netlist is the simulation netlist for running the SmartSpice
analog circuit simulator. As an example, if the schematic design is named RSFF.schlr,
then the SmartSpice netlist is RSFF.net.
• SmartSpice 200: The SmartSpice 200 netlist is for simulating using SmartSpice 200.
• SmartSpice RF: The SmartSpice RF netlist is used for simulation with SmartSpice RF.
• Silos: The Silos netlist is a Verilog netlist and used for running Verilog simulations in
Silos.
• HSPICE: The HSPICE netlist format is used for running analog designs in HSPICE.
• Atlas: The Atlas netlist is generated for running TCAD Atlas MixedMode simulations.
• NDL: The NDL (Netlist Driven Layout) is the netlist that has directives for higher
productivity in pre-layout.
• Guardian: The Guardian netlist reflects the physical layout for LVS. Using the RSFF
example, the Guardian netlist is RSFF_lvs.net.
• CDL: The CDL netlist is the Cadence CDL netlist option.
Figure 7-7 shows an example of a SPICE netlist after selecting SimulationCreate Netlist
when the simulator is set to SmartSpice. Figure 7-8 shows an example of a Verilog netlist of
a design when the simulator is set to Silos.
By default, netlists are created in read-only mode to synchronize to the schematic drawing.
This ensures that the schematic and netlist are equivalent at simulation time and prevents
inadvertent discrepancies between the two.
To edit the netlist files for use outside the Gateway environment, go to the Preferences and
check the Manual editing of .net files option in the applicable tab for each netlist type.

7.3.1 Rebuild Netlist Option

In the simulation mode of Gateway, there is a Rebuild Netlist checkbox option. By default,
this is checked and the netlist will always be rebuilt when creating an input deck and when
any simulation is run. If the box is not checked, the netlist will not be rebuilt when creating an
input deck or running a simulation.
This option is used to suspend the re-creation of the netlist when running consective
simulations on large schematics where the only thing that changes is the cross probes or the
control deck entries.
If the Rebuild Netlist option is not checked and the schematics change, the next time an
action to create a netlist, input deck, or run a simulation will result in a dialog to appear
(Figure 7-6). Also, a comment in the input deck always specifies whether the netlist was
rebuilt at runtime or not.

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Figure 7-6 Confirmation Dialog

Figure 7-7 SPICE Netlist

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Figure 7-8 Verilog Netlist

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7.3.2 Creating a Specific Netlist

Gateway can netlist hierarchical schematic drawings from any level of the design to generate
a functional netlist from that point and below. This makes it possible to create a netlist for a
lower level functionality in the design and use it in other designs as an included block of
circuitry, regardless of whether it is SPICE or Verilog. You can use these blocks in design
input files running outside the Gateway environment or as included files for other designs.
To create these specific netlists, descend to some level of your design and then select
SimulationCreate Specific Netlist. Another way to create a specific netlist is to use the
Design Browser to expand down and select a level of the design. The Create Specific Netlist
Dialog will then appear (Figure 7-9). Choose the type of netlist to create with the pulldown
menu named Type. The active simulator is set to match the netlist type by default.
If the netlist type is set to anything other than Verilog, the Make .SUBCKT box is available.
By checking this, the netlist will have a .SUBCKT statement set around the netlist contents.
The name of the active schematic will be used as the default name of the subcircuit, but you
can change the name in the dialog. Then, press the Order Pins button and the Order Pins
Dialog will appear (Figure 7-10).

Figure 7-9 Create Specific Netlist Dialog

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Figure 7-10 Order Pins Dialog

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Example
Assume there is a hierarchical drawing for a phase locked loop. One of the blocks on the
drawing is a divide-by-N counter. The counter clock is made up of JK flip flops. This flip flop
subcircuit may be useful to include in a .SUBCKT netlist form for input decks running outside
of Gateway (i.e., Batch or Interactive Mode, SmartSpice). If used, the top level D_PLL circuit
is now opened. Then, use hierarchy browser to open the JK_FF schematic you wish and then
open the Create Specific Netlist dialog. Check the Make .SUBCKT box and press the Netlist
button. The result is shown in Figure 7-11. The JK_FF subcircuit will be in .SUBCKT form.

Figure 7-11 JKFF Netlist in .SUBCKT form

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Control Files Design Flow

7.4 Control Files

Control files are used in Gateway to provide information detail for the simulation. Because
the netlist files are based purely on connectivity, the control files add other statements, paths
to models or modules necessary for the run, device and analysis descriptions, and other
parameters that are needed for use in simulation, pre-layout, and other parts of the design
flow.

7.4.1 Simulation Control File

The control file for a design is specific to the active simulator. This means that if a design will
run a SmartSpice simulation and a Silos simulation, it will have a *.ctr file and a *.ctrv
file. Depending on the active simulator, the control file is generated with its proper file
extension when SimulationEdit Control File is selected. For example, if the RSFF design
is simulated with SmartSpice and Silos, it requires both an RSFF.ctr and an RSFF.ctrv so
that the correct information is provided to the correct input file for the target simulator.
An example SmartSpice control file for the RSFF simulation is shown in Figure 7-12. For the
same design, an example of a Verilog control file is shown in Figure 7-13.

Figure 7-12 SmartSpice Control File for RSFF Simulation

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Figure 7-13 Verilog Control File

This file must contain at least one analysis statement to run anything. This file is commonly
used as a test bench to include stimulus definitions and elements as well as loading elements
so that the schematic to be run can stand alone as a device under test. In addition to that,
runtime parameters and options can be added. Typically, these control files can consist of:
• analyses to simulate
• models
• libraries
• parameters
• parametric and corner analysis
• statements for calculating measurements
• SPICE options (including RF)
• include files
• statements for saving specific vectors
If the default text editor (Sedit) is used, then there are toolbars (for example Figure 7-14) and
dialogs that aid in building statements for the SmartSpice family of simulators. Examples of
these can be seen in Figures 7-15, 7-16, and 7-17. From these, the following SPICE analysis
statements can be generated:
• Transient
• DC

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• AC
• Noise
• Distortion
• Transfer Function
• Network
• OP (Operating Point)
• PZ (Pole-Zero)
• .MODIF
• Fourier
For SmartSpice RF (SSRF) analysis, the SPICESmartSpice RF Analysis options are
available through the Sedit menu. The SSRF analyses that are included in this series of
dialogs are:
• ENVELOPE analysis
• HAC (Periodic Steady-State AC Analysis)
• HARMONIC (Periodic Steady-State Analysis)
• HNET (Periodic Steady-State Two-Port Analysis)
• HNOISE (Periodic Steady-State Noise Analysis)
• HOSCIL (Periodic Steady-State Oscillator Analysis
• HTF (Periodic Steady-State Transfer Function Analysis)
• SPAC (Quasi-Periodic Steady-State AC Analysis)
• SPECTRAL (Quasi-Periodic Steady-State Analysis)
• SPNET (Quasi-Periodic Steady-State Two-Port Analysis)
• SPNOISE (Quasi-Periodic Steady-State Noise Analysis)
• SPTF (Quasi-Periodic Steady-State TF Analysis)
• PSS-Shooting (Periodic Steady-State Oscillator Analysis by Shooting Method)
• PSS-HB (Periodic Steady-State Oscillator Analysis by Harmonic Balance Method)
• PHASENOISE analysis
For more information about the control card statements, see SmartSpice User's manual Vol. 1.

Figure 7-14 Analysis Toolbar

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Figure 7-15 Transient Analysis Dialog

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The set of dialogs is shown in Figure 7-16.

Figure 7-16 SSRF Analyses Dialog

For any of the analysis statements, complete the fields in the dialog and press OK to write the
statement into the control file. To save the statement for future sessions or for loading in other
simulations than the current one, press the Save button. The analysis will then appear under
the Load Simulation Parameters tab as shown in Figure 7-17.

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Figure 7-17 Analyses Manager -- Load Simulation Parameters

Then, select on one of the saved analysis and press Load to load the statement into the dialogs
for editing. Finally, press Edit to edit the statement or press OK to write it to the control file.

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To Run RF Oscillator simulations, select SPICESmartSpice RF Oscillator Analysis and

use the dialog shown in Figure 7-18.

Figure 7-18 RF Oscillator Simulation Dialog

Note: If any other text editor is used in the Gateway environment, this analysis toolbar will not be available

Note: When saving a schematic to another file name, the control file is automatically copied also with the copied
schematic.

7.4.2 Guardian Control File

This is the control file used for information and statements regarding LVS. Again, if the
schematic is RSFF.schlr, then the LVS control file is named RSFF_lvs.ctr.

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7.4.3 NDL Control File

This is the control file containing model and device definitions regarding the physical layout.
It also may contain pcell information and directives to assist in setting up the layout.
Following the RSFF example, the NDL control file is named RSFF_ndl.ctr. In the user
preferences, there is an option that can include the contents of the NDL control file directly in
the NDL netlist so that the layout can read from one file.

7.4.4 Atlas Control File

This is the control file used for specifying models, nodeset information, options, and other
statements for running the TCAD Atlas MixedMode simulations. Using the RSFF example,
the Atlas control file is named RSFF_atl.ctr. In the user preferences, there is an option that
can include the contents of the Atlas control file directly in the Atlas netlist so that the
simulator can read from one file.

7.4.5 CDL Control File

This is the control file used for adding any statements and directives for the Cadence CDL
netlists.

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7.5 Viewing the Input Deck

The input file is assembled once the netlist and the control files have been created. To view
the complete input file, select SimulationView Input File. The input files are different
types for different simulators.

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7.6 Pre-processor Schematic Marking

Nodes and pins on the schematic can be marked before the simulation is run. Voltages and
currents are saved for the places on the schematic that are marked. Additional macros for
saving these, such as phase and db, can be applied by using the appropriate markers. These
vectors will be saved and then plotted when the simulation is finished. For more information
about the markers, see Section 8.2.1 “Marking the Schematic”.

Note: This applies only to the SmartSpice family of simulators.

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7.7 Running the Simulation

To run the simulation, press and the Run Time Dialog will appear (Figure 7-19). This
will display the simulation information, such as timestepping, the current time, and end time
of the simulation. When parametric simulations are running, some of the parametric content
is shown in the dialog as parameters change.

Figure 7-19 Run-Time Dialog

To stop the simulation, press . To pause the simulation, press . To resume a

simulation, press again. For more information about the simulation, see Chapter 8
“Simulation and Post-Processing,”.

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Simulation and Post-Processing
Pre-Simulation Simulation and Post-Processing

8.1 Pre-Simulation
The simulation menu in Gateway consists of actions that cover the entire flow. Figure 8-1
shows the Simulation Toolbar. It begins with the drawing checks that were covered in Section
7.2 “Checking a Schematic” along with the creation of the netlist, control, and input files. The
next step in the progression of the flow is the simulation itself. Gateway is integrated with the
following list of simulators:
• Silvaco SmartSpice
• Silvaco SmartSpice 200
• Silvaco SmartSpice RF
• Silvaco Silos
• Silvaco Atlas TCAD MixedMode
• Synopsys HSPICE

Figure 8-1 Simulation Toolbar

Table 8-1. Simulation Toolbar Buttons

Buttons Description

Drawing checks (this level, down hierarchy, entire simulation) as covered in Section
7.2 “Checking a Schematic”.

Generates and displays the netlist.

Edits Control File for models, options, analyses, and statements.

Creates and displays the input file.

Sets Plot Options.

Runs, pauses, and stops the simulation.

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Table 8-1. Simulation Toolbar Buttons

Calculates DC bias points without running a simulation.

Displays simulation error file.

Displays simulation error.

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8.2 Analog Simulation

Figure 8-2 shows Gateway in Simulation mode as the interface changes from the Capture
mode by dropping out the design libraries. Instead, it displays the Analyses and Plot options.

Figure 8-2 SmartSpice Interface with Pre-Simulation Options

In Gateway, first click the Simulation tab under the symbol browser or select
ViewCapture/Simulation. This will switch Gateway from the capture mode and enter the
simulation mode where the options can be seen and changed. Now beginning with the pane
on the left of the Gateway window, there are two sub panes named Analyses and Plot
Options.

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The Analyses pane shows the contents of the control file, if one exists. If one does not exist
yet (for a new schematic), the pane will reflect that there are no control statements or
analyses. Figure 8-3 shows the control file contents for the current mirror example schematic.
This pane filters out all the comment lines to condense the amount of data shown and only
displays what is “live” or active for the simulation.

Figure 8-3 Analyses Pane

Below the Analyses pane, the Plot Options pane (Figure 8-4) contains the settings for
choosing how the traces will plot following the simulation. Clicking the Edit link in the pane
opens the Set Plot Options dialog (Figure 8-5). You can also open this dialog by selecting
SimulationSet Plot Options.

Figure 8-4 Plot Options Pane

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Figure 8-5 Set Plot Options Dialog

The Plot Options choices are saved in .sso file and loaded when you open the schematic file.
The options are as follows:
• Analysis Type: Sets the analysis that you want to plot. If more than one, select All
Analyses.
• Plot to:
• Create a New Chart – Creates new chart and plots data there.
• Replace Existing Chart – Replaces data in existing chart with new data after each
run.
• Add to Existing Chart – Adds to data in existing chart after each run.
• Replace Existing Simulation – Replaces old simulation data after each run for all
analyses in the deck.
• Overlay on Existing Simulation – Overlays new simulation data on top of older
data for all analyses in the deck.
• Existing Chart: Allows you to select the chart to replace or add the traces onto. It queries
SmartView for all the available charts. This option is enabled if Plot To is set to Replace
the Existing Chart or Add to the Existing Chart.
• Existing Simulation: Allows you to select the simulation to replace or overlay the new
simulations traces onto. It queries SmartView for all the available simulations. If a
simulation contains parametrics (i.e., multiple analyses) and plotted on different charts in
SmartView, the option allows you to select which one of the charts per analysis type will
be replaced/overlayed. This option is enabled if Plot To is set to Replace the Existing
Simulation or Overlay on Existing Simulation
• Chart Layout: Chooses the layout display of the charts (e.g., vertical or horizontal).
• Plot Parametric to Same Chart: Specifies whether to plot all the analyses of the same
type for a parametric simulation (e.g., .ALTER, .TEMP, .MODIF, .ST) to the same chart.

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8.2.1 Marking the Schematic

The schematic may be marked in the simulation mode for the currents and voltages you want
to plot. If you are using mode-dependent cursors (selecting PreferencesUser Interface),
the mouse cursor reflects a probe and clicking symbols or wires drops these markers. The
default marker type will place a current marker on a pin when you click a pin and a voltage
marker on a wire when you click a wire. To remove a marker, click the existing marker and it
will be removed from the schematic. Figure 8-6 shows the Cross Probe Toolbar that is active
only when Gateway is in the Simulation mode. The first four buttons from left to right are the
marker icons.
Cross probe markers may be dragged around for convenience. When they are dragged from
their initial points, flight lines are drawn to point back to the wire or pin where they were
originally placed. To reset them all back to their original locations, select PostprocessReset
Markers.

Figure 8-6 Cross Probe Toolbar

The (default marker type) is for marking voltages and currents. The is for marking

DB currents and voltages. The is for marking phase currents and voltages. The is
for measuring the difference in voltages or currents. The cursor will have a plus sign next to it
when you drop the first marker (Figure 8-7). The cursor will have a minus sign next to it when
you drop the second marker (Figure 8-8). The resulting marker will look like Figure 8-9,
which shows the difference between the first and last marker. You can also select these
markers using the Post-Process menu in Gateway.

Figure 8-7 Positive Marker

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Figure 8-8 Negative Marker

Figure 8-9 The Resulting Difference Marker

Figure 8-10 shows another pane at the bottom of the Gateway window. It shows a vector that
is listed to plot. This pane contains the Session, Review Errors, Cross Probe, and Output
tabs. The Session tab displays messages from Gateway and streams messages in from
SmartSpice during a simulation. The Output tab contains the true SmartSpice runtime output
data as if the simulation were run in the interactive GUI mode.

Figure 8-10 Output/Cross Probes/Errors Pane

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This Cross Probe tab shows the information about each marker, including the name, the
schematic drawing that the marker resides on, the sheet number, and whether the vector
should be plotted or marched. If there is a check in the checkbox in the Save column, this
indicates that the vector will be saved by the simulation into raw data for postprocessing. If a
vector is checked in the Plot column, it will be plotted following the completion of the run. If
the checkbox in the March column is checked, the vector will be marched or plotted
progressively in real time during the simulation.
The four checkboxes in the Save area are for saving groups of data. They are as follows:
• ALL(V): Saves all node voltages on top level of schematic
• ALL(I): Saves all branch currents on top level of schematic
• ALL_SUB(I): Saves all subcircuit currents
• ALL_SUB(V): Saves all subcircuit voltages
If you check any of these, these vectors will be saved but not plotted. This means that after the
simulation is complete, these vectors will be available in SmartView’s Data Browser window
for selecting and plotting. The only vectors that will be plotted from the schematic are the
ones that are listed in the Cross Probe pane. Otherwise, anything that is saved can be plotted
after the simulation in SmartView.
The crb file (crossprobe markers file) contains the crossprobes that were marked for the
simulation. This includes all markers on subcircuits and all marker types. In other words, db,
phase, diff and normal. The crb file is stored at the same location as the top level schematic of
the simulation. For example, if the top level schematic was named ex2.schlr and a marker
is placed on its subcircuit then a crb file named ex2.crb will contain the marker.

Note: Cross-probing and Save checkboxes only apply to the SmartSpice family of simulators.

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8.2.2 Running the Simulation

To run the simulation, press and the Run Time Dialog will appear (Figure 8-11). This
will display the timestep SmartSpice is using, the current time, and end time of the
simulation. To stop the simulation, press . That will stop the simulation and release the
SmartSpice license. To pause the simulation, press . Pausing the simulation suspends the
SmartSpice license. To resume a simulation, press again. Press Hide to hide the Run-
Time Dialog. The Run-Time Dialog will disappear but the simulation will continue.
Alternatively, you can select these actions from the Simulation menu in Gateway.

Figure 8-11 Run TIme Dialog

SPICE Run Actions
The SPICE run performs the following actions before loading the SPICE deck into
SmartSpice.
• The current schematic will be netlisted to include the latest changes in the SPICE deck.
• A list of voltages and currents to be saved by SmartSpice will be incorporated into the
SPICE deck along with the user-defined control cards.
• SmartSpice will be started if it’s not already running in the system. The SPICE deck will
be loaded into SmartSpice once it’s running. At this point, any control card or netlist
errors in the deck will be detected by SmartSpice and will appear in the Session Window.
Figure 8-12 shows the schematic marked and ready for simulation. The only things that
should plotted are the voltages for NET5 and NET6 as shown. After running the simulation,
Figure 8-13 shows those voltages for each analysis. When the simulation completes, the
output file will be ready for viewing. To view this file, click and see the output (see
Figure 8-14). You can also click the Output tab to see the SmartSpice output. If there are fatal
errors from SmartSpice and a separate error file is created, this file can be viewed by selecting
SimulationView .ERR File.

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Figure 8-12 Marked Schematic Before Simulation

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Figure 8-13 SmartView Displaying Simulation Results (Waveforms)

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Figure 8-14 Output File

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8.2.3 Calculating DC Operating Points

When SmartSpice begins a simulation, it first calculates the DCOP (DC Operating Point) to
begin simulation. When the DCOP calculation finishes, the DC bias information is available
for viewing on the schematic. To recalculate and display these operating points without
running the additional analyses specified in your control file, select SimulationCalculate
DC Bias Points. This can save time when you are only focused on the bias of the circuit. The
options Load DC Bias points and Generate DC Bias points in your preferences can be used
to choose to enable whether to load or generate the DC Bias points respectively.
DC Operating Points and Simulation States
When the DC operating point calculation is run, the data is stored in the *.dcb file in the
working directory of the top-level simulation. The filename will be the same as the top-level
schematic except that the file extension is .dcb. The title bar in the Gateway window displays
the state of the DC bias data that exists in the file as compared to the active schematic.
Here are the following DC bias states shown in the title bar:
• Current - DC bias data exists and is up-to-date. No schematics in the simulation have
been modified since the last simulation run or since Gateway was launched.

• Running - Simulation is actively running. New DC bias data is in process of being

calculated.

• Stale – DC bias data exists but is out-of date. At least one drawing in the simulation has
been modified since the last simulation run. DC bias markers may still be displayed. The
Stale status indicates the values from the previous run.

If a simulation has not been run, the title bar will not show any status.

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8.2.4 DC Bias Display

Gateway displays DC operating point voltages and currents after DCOP simulations are
complete. To view these values on the schematic, click one of the buttons on the toolbar
shown in Figure 8-15.

Figure 8-15 DC Bias Buttons

The button marked V toggles node voltages on all nodes for any open schematics in the
simulation (see Figure 8-16).

Figure 8-16 Node Voltages

The button marked I toggles device currents for all open schematics in the simulation (see
Figure 8-17).

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Figure 8-17 Device Currents

The button on the far right is for setting specific nodes or pins to be marked. When you click
that button, clicking on any wire will drop a voltage marker with the DCOP voltage displayed
(see Figure 8-18).

Figure 8-18 DC bias currents and voltages as selected by designer

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Also, clicking any pin will drop a current marker with the DCOP current displayed on the
marker. Additionally in this mode, rolling the mouse over a pin or wire will highlight the
object and show the DCOP voltage or current in a tooltip (see Figure 8-23).
For transient simulations, transient data can be seen for any node or device current as long as
they were specified to be saved before running the simulation. To show these values on the
schematic, turn on the voltage or current markers by pressing the V or I icons, and then select
ViewWindowsBias Display. The window pane in Figure 8-19 is displayed.

Figure 8-19 Bias Display Pane

The Time field represents transient time. After the transient simulation is complete, the dialog
shows Time:0 as the DC operating point (Figure 8-20).

Figure 8-20 Bias Display Pane at DC Bias Condition

Now, type in a time value from some point in the transient window and press the Display
button. As shown in Figure 8-21, the values on the schematic change to reflect the current
time point. In this example, Figure 8-21 shows values for the voltage and current at 100ns
into the run.

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Figure 8-21 Bias Display at 100ns

To step through the transient analysis at an intended interval, enter the time interval in the
Step box. In this example, we will use a step of 50ns. Each time the Step button is pressed,
50ns is added to the value in the Time field and transient data is updated each time. Figure 8-
22 shows the schematic and dialog at time=200ns, which is the initial time of 100ns stepped
twice in 50ns intervals.

Figure 8-22 Bias Display at 200ns and 50ns step

The step also can be set to a negative number to step backwards through a transient
simulation until t=0.

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Figure 8-23 Voltage Marker with Tooltip

As all these images show, if you move markers from their default location, arrows and flight
lines will be drawn from the marker to the node or symbol to identify them. You can move
any marker in any DC bias mode.

Note: To print schematics with the DC bias display, select the Current View option in the Print Setup dialog box.

8.2.5 Threshold Tab

The Threshold tab on the bottom window pane is used during the DC bias display mode to
show node voltages or branch currents that fall within thresholds specified for each line.
When DC bias display is enabled, these thresholds will highlight the DC bias markers in the
colors specified in the Thresholds tab for each created threshold. To create a new threshold,
click on the + icon. Specify a name, and then the type whether it is for current or for voltage.
Enter the minimum and maximum threshold values and set a color.
Then, the DC marker bubbles will turn to the appropriate threshold colors when appropriate.
They will also change as the Bias Display pane is stepped through using units of time.

8.2.6 SmartSpice Status and Information

In the lower right portion of the baseframe on the Gateway window, there are a series of status
displays that provide connection information about the simulator and other applications that
are connected to Gateway. Figure 8-24 shows this area of the Gateway window, which
includes the version number of Gateway that is running.

Figure 8-24 Simulator and Tool Status Bar

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In Figure 8-24, the Simulator is set to SmartSpice. The first icon in the series of three icons is
the simulator icon. The second icon is the waveform viewer icon. In this case, SmartView is
shown as the Waveform Viewer chosen for this session. The third icon is for the layout editor,
and in this session it is set to Expert. Figure 8-24 shows all three icons are lighted which
indicate that Gateway is connected to all three applications. If one of them is disconnected or
closed, the icon will turn gray. Figure 8-25 shows Gateway disconnected from Expert.

Figure 8-25 Status Bar Showing Expert Disconnected

To show advanced connection details, roll the mouse over one of the icons and the tooltip
whose more information. Figure 8-26 shows advanced information for the SmartSpice
connection, including the status and version of SmartSpice that is running.

Figure 8-26 Status Bar Showing Advanced SmartSpice Information

SmartSpice Device Information
Gateway can show simulation device parameters at the instance level. To show these values,
double-click on a symbol instance and click the Device Parameters tab as shown in Figure 8-
27. Scroll through the list and check the box to show the desired parameters as shown in
Figure 8-28. Press OK and then view the attributes on the schematic as shown in Figure 8-29.
To show the parameters for devices of matching type, set the scope to “matching instances” in
the Properties dialog for the symbol instance.

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Figure 8-27 Properties Dialog (Symbol Instance)

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Figure 8-28 Properties Dialog (for the Symbol Instance) with Parameters Selected

Figure 8-29 nmos Device Simulation Parameters Shown

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Symbols can be setup to show their simulation device parameters simulations on all designs
where they are used. To do that, first open the symbol for edit. Then, open the symbol
properties and click on the Device Parameters tab. Click the Add button to add parameters
to the list, and enter their names. Figure 8-30 shows the parameters “region” and “vth”
being added to the PMOS symbol. After the symbol is saved, all designs using the PMOS
symbol will show values for the region of operation and the vth on the schematics following
the simulations.

Figure 8-30 “region” and “vth” parameters added to the PMOS Symbol

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8.2.7 Post-Processing
The Cross Probe Toolbar (Figure 8-31) shows the icons that post-process the data.

Figure 8-31 Cross Probe Toolbar

To plot data after a simulation, mark the nodes or pins on the schematic and click . To

delete markers from the stack in the Cross Probe pane, click and all checked markers
will be deleted. All post processing and plotting uses the settings stored in the Plot Options
pane. To launch SmartView, click on . To reset markers back to their original positions,
select PostprocessReset Markers.

The Plot from Archive button ( ) opens the last saved rawfile for the loaded top level
schematic simulation and allows you to plot vector data from that run or runs. Note that when
simulations run in sequence, although you can see all simulation runs in the current session,
the rawfile only retains the final run to be viewable in the next session. If you ever want
access to all data from the previous session, you need to save the rawfile before exiting
SmartView.
The term cross-probing refers to the marking and plotting of vectors from Gateway to
SmartView aside from the simulation. This is when the simulation has been completed and
the resulting data is stored in raw data in SmartView. The cross probe is a graphical way to
select a vector on the schematic and quickly turn it into a waveform.

Note: Only vectors that have been saved in the raw data from the simulation can be cross-probed. Otherwise, the
simulation must be re-run to generate the requested vector data.

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8.3 Digital Simulation

Running Digital simulations from Gateway is very similar to running analog simulations with
the exception of the markers and cross probing. To run a digital simulator, go to Simulator
tab on the EditPreferences dialog and choose Silos. Or from the Design Browser in the
Gateway window, click the Silos icon as shown in Figure 8-32. That puts Gateway in the
mode to netlist Verilog.

Figure 8-32 Design Browser with Silos Button Selected

Load the desired workspace containing the digital design and then open a schematic as shown
in Figure 8-33. The Design Browser can be used to navigate up and down any level of the
design and to create specific Verilog netlists from any level. Figure 8-34 shows the Design
Browser illustrating the contents of the design.

Figure 8-33 Example Digital Design in Gateway

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Figure 8-34 Digital Design Expanded

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Generate the Verilog netlist shown in Figure 8-35 by selecting SimulationCreate Netlist.
Then, view the Verilog control file shown in Figure 8-36 by selecting SimulationEdit
Control File. You can also view the input file shown in Figure 8-37 by selecting
SimulationView Input File.

Figure 8-35 Verilog Netlist

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Figure 8-36 Verilog Control File

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Figure 8-37 Silos Configuration File

To run the simulation, press . Silos launches and then the Runtime dialog shows
simulation progress as shown in Figure 8-38. Finally, when the simulation is complete, the
digital raw data is loaded automatically into SmartView. Then, choose vectors from the tree in
SmartView and drag them into the plot area as shown in Figure 8-39.

Figure 8-38 Runtime Dialog

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Figure 8-39 SmartView showing Digital Vectors from the Verilog simulation

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Chapter 9
EDIF
Overview EDIF

9.1 Overview
EDIF (Electronic Design Interchange Format) is an ANSI/EIA (American National Standard
Institute/Electronic Industries Association) standard file format that is used to transfer data
from one CAD/CAE system to another. In Gateway, the EDIF file format transfers schematic
drawings from other tool vendor schematics into Gateway. Gateway only supports importing
and exporting of EDIF Version 2 0 0 files.

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EDIF Import Options EDIF

9.2 EDIF Import Options

Figure 9-1 shows the EDIF Import Dialog box. The options and groups of options are
described below.

Figure 9-1 EDIF Import Dialog

General Options
• Fix case sensitivity conflicts – Resolves conflicts for library, cell, and net names that
have duplicate alphanumeric strings in the EDIF file by naming them uniquely.
• Discard invalid characters in node names – Strips out node name characters that are
invalid for SmartSpice.
• Verbose output – Produces extra information during import that may be useful in
diagnosing import errors. If an import fails for some reason, you may want to turn on
Verbose output and try importing again. The verbose messages might help to locate the
problem.
• Filter attributes – Ignores specified attribute names during the EDIF import and prevent
them from importing. To specify these attributes, click the Edit button on the dialog.

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• Add default Attributes – Adds default values to attributes in symbol files that are
importing into Gateway. To add values to the list or to edit the list, click the Edit button
on the dialog.
Cadence Options
• Convert iPar/pPar parameters - Attempts to find iPar/pPar attributes on symbol
instances and adds them as properties of a parameters symbol instance on the parent
schematic. This sets up the feature for adding passable parameters down a hierarchy.
• Discard Cadence cds annotations - Throws away symbol drawing annotations starting
with the "cds" prefix. For example, "cdsTerm("G")", "cdsName()", and
"cdsParam(1)".
• Retain case of identifiers - Retains the case of the Cadence identifiers from the EDIF
file, including cell and library names.
• Discard Cadence sheet borders - Ignores any Cadence sheet borders that are defined in
the EDIF file.
• Fix Cadence Colors - Produces schematic colors as close as possible to the Cadence
original colors.
Viewdraw/Mentor Graphics Options
• Add Viewdraw pins – Adds pins to schematic files where necessary for the purpose of
hierarchical connectivity and netlisting.
• Retain Viewdraw snap spacing - Converts Viewdraw schematics/symbols from the
imported file to the Gateway schematic grid.
OrCAD Options
• Retain OrCAD snap spacing - Converts MicroSIM PSPICE and OrCAD schematics/
symbols from the imported file to the Gateway schematic grid.

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9.2.1 Importing an EDIF File

When importing EDIF files, you must load a workspace that contains the $default library. The
following examples will have a workspace loaded with the $default library.
To import an EDIF file into Gateway:
1. Load a workspace containing at least the Silvaco $default library.
2. Select FileImportEDIF 2 0 0 to open the EDIF Import dialog (Figure 9-1).
3. Click the Browse button and browse to the file you want to import (Figure 9-2). EDIF
files have these file extensions: *.edn, *.eds, *.edf, and *.edif.

Figure 9-2 EDIF File Dialog

4. Click on the Open button.
5. Now the dialog will look like Figure 9-3. If you want to import it as is, click the Import
button. Otherwise, you can turn on any of the available checkbox switches before
importing. These are described in Section 9.2 “EDIF Import Options”.

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Figure 9-3 EDIF Import Dialog with imported file.

When you press the Import button, Gateway loads the file into the importer with the options
and processes the file. As the import progresses, you may see libraries being added to the
Library pane on the Gateway window. These are the design libraries from the original design
that are being written into Gateway’s workspace, along with the cells and files that belong in
those libraries. Also during the import, the Session pane will scroll automatically with
messages about the import progress and files that are being imported. Warnings and errors
can be seen in the session pane regarding the import. For a complete log of the import, you
can view the edif_in.log file that is generated in the directory where the imported file
resides. Here is an example of what kind of information is generated from an edif_in.log
file:
Simucad EDIF Importer

Import started at 4/21/2008 10:57:05 AM

Importing EDIF file: N:\examples\current_mirror.edn

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Fix case sensitivity conflicts? No

Filter attributes? No
Discard invalid characters in node names? No
Automatic schematic pin conversion? No
Convert iPar/pPar Parameters? No
Discard Cadence cds annotations? No
Add Viewdraw pins? No
Retain OrCAD/Viewdraw snap spacing? No
Beginning parsing phase...
0 errors, 0 messages

Parsing complete
Beginning phase 2...
Phase 2 complete
Beginning phase 3...
File uses EDIF Version 2 0 0 Level 0
Time Stamp 3/31/2004 12:24:13 PM UTC
Author 'Cadence Design Systems'
Data Origin 'carmel'
Program 'edifout' Version 't version 5.0.0 09/26/2003 18:20
(cds12107) $'
Processing library 'analoglib' (EDIF level 0)
Processing cell 'cap'
Processing schematic view
Saving symbol drawing to file N:\examples\main\analoglib\cap.symbol
Symbol drawing saved
Processing cell 'gnd'
Processing schematic view
Saving symbol drawing to file N:\examples\main\analoglib\gnd.symbol
Symbol drawing saved
Saving schematic drawing to file
N:\examples\main\analoglib\gnd.schlr
Schematic drawing saved
Processing cell 'npn'
Processing schematic view
Saving symbol drawing to file N:\examples\main\analoglib\npn.symbol
Symbol drawing saved

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Processing cell 'res'

Processing schematic view
Saving symbol drawing to file N:\examples\main\analoglib\res.symbol
Symbol drawing saved
Processing cell 'vcc'
Processing schematic view
Saving symbol drawing to file N:\examples\main\analoglib\vcc.symbol
Symbol drawing saved
Saving schematic drawing to file
N:\examples\main\analoglib\vcc.schlr
Schematic drawing saved
Processing cell 'vdc'
Processing schematic view
Saving symbol drawing to file N:\examples\main\analoglib\vdc.symbol
Symbol drawing saved
Processing cell 'vsin'
Processing schematic view
Saving symbol drawing to file
N:\examples\main\analoglib\vsin.symbol
Symbol drawing saved
Processing cell 'vss'
Processing schematic view
Saving symbol drawing to file N:\examples\main\analoglib\vss.symbol
Symbol drawing saved
Saving schematic drawing to file
N:\examples\main\analoglib\vss.schlr
Schematic drawing saved
Processing library 'test' (EDIF level 0)
Processing cell 'current_mirror'
Processing schematic view
Processing instance of analoglib::res
Processing instance of analoglib::res
Processing instance of analoglib::vdc
Processing instance of analoglib::npn
Processing instance of analoglib::vss
Processing instance of analoglib::res
Processing instance of analoglib::vcc

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Processing instance of analoglib::gnd

Processing instance of analoglib::cap
Processing instance of analoglib::vss
Processing instance of analoglib::npn
Processing instance of analoglib::res
Processing instance of analoglib::npn
Processing instance of analoglib::gnd
Processing instance of analoglib::vdc
Processing instance of analoglib::vsin
Processing instance of analoglib::gnd
Processing instance of analoglib::vcc
Processing instance of analoglib::res
Processing instance of analoglib::gnd
Processing instance of analoglib::npn
Saving schematic drawing to file
N:\examples\main\test\current_mirror.schlr
Schematic drawing saved
Phase 3 complete
Total number of warnings: 0
Total number of errors: 0
EDIF import completed successfully
If the file import is successful, the dialog in Figure 9-4 will show at the end of the import.

Figure 9-4 EDIF Import Successful

If you have imported a design and made changes to cells in a library, you may lose your
changes if you import another EDIF file containing the same library and cells. If a new EDIF
import contains a library such as this, Gateway will show a dialog like in Figure 9-5. An
example is if you import multiple EDIF files and all contain an analoglib library. Any edits
done to cells in that library are at risk of being overwritten unless you choose No or No to All
in the dialog.

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Figure 9-5 File Already Exists Popup

In this case, you would either click No to decide whether to overwrite or not on a per-file
basis or click No To All to prevent anything from being overwritten.
The next step is to now convert the imported schematics and symbols into something useful
and meaningful for SmartSpice and other Silvaco simulators.

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9.3 Conversion of Imported Files

Since EDIF is not a foundry driven standard, the look, feel, and scope of what is transferred
by the EDIF process varies greatly between software vendors. This is one way that the EDIF
standard is different from the GDSII standard. For this reason, it is unlikely that a schematic
may be able to netlist or simulate after import without some amount of editing. For example,
the original schematic may have parameters defined using a specific syntax. The importing
tool uses another simulator with a completely different engine and syntax. In this case, there
is no definition in the EDIF standard to translate them into meaningful attributes for the
imported design. In many cases, the imported drawing is only a drawing of symbols and wires
but unable to netlist or run a simulation. This section covers some of the basics of how to get
the raw imported EDIF schematic into a condition that is useful.
The Gateway EDIF importer uses all available information from the imported file to
regenerate the same information on cellviews in Gateway. This includes wire connectivity,
net and node naming (where possible), symbol reference designators, and symbol attributes
with their instance values. In addition to that, schematic hierarchies should be imported and
capable of descending and ascending through the hierarchy. The few exceptions are other
cellviews such as netlist views. If netlist views were present on the original drawing, attach
the netlist in the control deck (*.ctr file) and manually create the symbol (*.symbol file) as
described in Chapter 5 “Schematic Editing ”.

9.3.1 Conversion Example

The following is a general rule to follow for conversions.
If a symbol behaved as a primitive device before import, you must convert it to behave as a
primitive device after import. If a symbol was a black-box type that only descends to
subschematics without passing parameters, you do not need to do anything. If it is a black-
box type that does pass parameters, you need to do minimal editing for conversion.
The following example is a current mirror schematic that was drawn in a Cadence
environment and then exported to a EDIF file. The example imports and then converts the
schematic.
1. Load a workspace.
2. Import the EDIF file with these options as shown in Figure 9-6.
3. Press Import.
4. Press OK on successful import notification dialog.
5. Open the imported schematic. The imported drawing now looks like Figure 9-7.

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Figure 9-6 EDIF Import Dialog with file

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Figure 9-7 Imported Schematic

6. Since this schematic contains mostly primitive devices, it is worth showing what these
symbols lack and why conversion is needed. Double-clicking on one of the resistor
instances and then clicking the Netlist Preview button shows Figure 9-8 where there is an
empty SmartSpice string.
7. Begin with one primitive type, in this case, the resistor. The res.symbol in the analoglib
library needs information from res.symbol in the spicelib. Open both files up in a text
editor to compare as shown in Figure 9-9. The file on the left is from the analoglib and
the one on the right is from spicelib. It is noted that the file from analoglib only has one
line tagged <attributes/> with no contents. The file has no attributes for
SmartSpice and therefore must be copied in.
8. Copy the parameters and definitions (all lines between tags <attributes>
</attributes> and replace the lines between <definitions> </definitions>) from
the spicelib resistor to the analoglib resistor. Now the files should look like Figure 9-10.
Save the file.
9. Do the same as steps 7 and 8 for the rest of the primitives: cap.symbol, npn.symbol,
vdc.symbol, and vsin.symbol.

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Figure 9-8 Imported Schematic with Netlist Preview and Empty SmartSpice String

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Figure 9-9 Resistor symbols before edit: (Left: spicelib and Right: analoglib)

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Figure 9-10 Resistor symbols after edit: (Left: spicelib and Right: analoglib)
10. After you convert step 9, click ToolsReload All Libraries. The schematic shows the
primitives converted. Resistors that were named Xr0 and Xr1 are now Rr0 and Rr1,
respectively, and will now behave as primitive resistors.
11. To convert the other symbols (special symbols), such as the ground pins and voltage
references, begin by right clicking a ground symbol and choosing Change Symbol.
12. Change all analoglib ground symbols to ground symbols from $default.
13. Repeat step 12 for the vcc and vss symbols, replacing all the analoglib vcc and vss
symbols with symbols from $default.
14. Since there are question marks beside the transistors, double-click one of the transistors
and in the MNAME field, type a model name there. Then, set the scope pull-down to
Matching. Click OK.

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15. To finish, browse through the symbol instances to see if there are any attribute values you
want to set or attribute visibilities you want to enable or disable. Then, press F3 that runs
a drawing check and displays the netlist. Figure 9-11 shows the final resulting netlist.

Figure 9-11 Resulting SmartSpice Netlist

After this, the primitive symbols in steps 7 though 9 are converted for future use as well.
Using the Change Symbol dialog with a scope across single cells or down through a hierarchy
can be used to replace imported instances quickly with converted ones. Be careful not to
overwrite converted symbols on new imports as mentioned in Section 9.2.1 “Importing an
EDIF File”.

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9.4 Exporting EDIF 2 0 0

Gateway also exports drawings out to the EDIF 2 0 0 standard. To export a drawing from
Gateway, select FileExportEDIF 2 0 0. The EDIF Export dialog in Figure 9-12 appears.
First, browse to the directory you want to export to by clicking the Browse button. The dialog
in Figure 9-13 will appear. Then, type a File name in and select Save.

Figure 9-12 EDIF Export Dialog

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Figure 9-13 EDIF File Dialog

The dialog will now look like Figure 9-14. Clicking the Export button writes out the EDIF
file without any options. To add any of the options that are described below, first check the
boxes first and then click on the Export button.

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Figure 9-14 EDIF Export Dialog writing .edn File

General Export Options
• External Libraries - Specifies the “external” libraries. In EDIF, an external library is
assumed to already exist in the target design system. The exported EDIF file will have
what are essentially placeholders for all cells in the external libraries.
• Write Netlist Views Only - Writes out EDIF netlist views instead of schematic views
(i.e., connectivity only, no graphical representation).
• Supplies Sheet Frames - Ignores all Gateway sheet frames and excludes them from the
EDIF export.
• Filter Attributes - When selected, this option prevents writing attributes (specified in the
Edit box) into the EDIF file.
• Modify Attributes - When selected, this option specified attributes for exporting. Click
the Edit button to modify the attributes.
• Top level library name - The top level library name allows the ability to specify the
library where the top level (current) schematic will be put. The default is top_level.

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Cadence Export Options

• Automatic Schematic pin conversion - Replaces $default bischpin/inschpin/outschpin
instances with Cadence "basic" library iopin/ipin/opin instances. The "basic" library is
declared as external in the EDIF file as it is assumed that this library is already available
in Cadence.
• Lowercase instance identifiers and attribute names - Forces all of the instance
identifiers and attribute names to be in lowercase.
• Create Cadence-style symbol pins - Adds Cadence-style graphics around symbol
instance pins.

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 Chapter 10
Schematic Design Examples
Importing Verilog and SPICE into Gateway Schematic Design Examples

10.1 Importing Verilog and SPICE into Gateway

There are several ways to bring Verilog modules and SPICE subcircuits into the schematic
capture. The most automated way is to use the FileImport Verilog and FileImport
SPICE menus in Gateway. These features can import the data and create symbol libraries for
these files that are ready for use in the design capture. Also, if symbol libraries exist from
other schematic vendors, foundries, or IC vendors in EDIF 200 format, they can be
automatically matched up with the correct module or subcircuits.
To Import Verilog or SPICE into Gateway, click FileImport Verilog or FileImport
SPICE respectively. Figures 10-1 and 10-2 show these two dialogs. The dialogs are similar in
appearance but internally are different in how they format the netlist strings.

Figure 10-1 Import Verilog Dialog

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Figure 10-2 Import SPICE Dialog

As seen in Figures 10-1 and 10-2, the dialogs are divided into two vertical sections. The left
side of the dialog has the file and library information. The toolbar on the dialog has actions
for adding a file, removing a file, editing the file, and moving the file up or down in a list of
files. Each button has a tooltip that describes the button. Below the File section is the Library
section. The main option here is whether to attach the imported Verilog to an existing symbol
library or whether to have gateway create a new library and attach the definitions. To begin
importing, click the plus icon in the toolbar, then click on the new line and type the path to the
Verilog or SPICE file, or click the Browse button. The Type can be set to Spice or
Verilog-A. These choices affect whether the file is parsed as a Spice or Verilog-A file
respectively. Model library files should be set to the Spice type.
To create a new symbol library, click the New option and specify the library name and path.
Upon completing the import, the new library is then added to the workspace. To import to an
existing symbol library, select the Place in option and then choose a library from the first
pulldown menu. In this case, there are now two options in the second pulldown menu as
shown in Figure 10-3: Create Symbols and Update Symbol Properties.

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Figure 10-3 Import Options For Importing To An Existing Library

The Create Symbol option creates new symbols for any module or subcircuit definition that
Gateway finds in the definition files. It also formats the symbol properly to include
parameters, pins, and netlist string. The Update Symbol Properties option will scan the
library for symbols that match subcircuit or module names. That is, if there are symbols in the
library whose names match the names of subcircuits or modules in the definition files, the
symbol graphics are left intact but the netlist strings are formatted accordingly along with any
parameters.
The right hand side of the Import Verilog dialog has options for creating the symbols. Most of
these options are the same as the options explained in Section 5.11 “Generating Symbols”.
The controls here are for making the most optimally sized and shaped symbols for each
imported module.

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10.2 Example 1 – Importing Verilog to a New Symbol Library

In this example, a Verilog file containing several dozen modules will be imported by
Gateway’s Import Verilog tool and a new symbol library will be created.
1. Run Gateway and click FileImport Verilog.
2. Select the file to be imported. See Figure 10-4. In this example, the file is called
primitives.v.

Figure 10-4 Importing Verilog

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3. Choose a name for the new library and directory path where the library will reside. In this
case, the library is named example_digital. See Figure 10-5.

Figure 10-5 Creating a New Library

4. If you want to set all symbols to be rectanglar, then choose the Rectangle shape as shown
in Figure 10-6.

Figure 10-6 Choosing Rectangular Style Symbols

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5. Since this is a primitive digital library in this example, the shape will be set to Use Filter
so that logic symbols can be used wherever applicable (Figure 10-7).

Figure 10-7 Choosing Use Filter Shape Option

6. Press the Import button. Gateway then imports the Verilog and creates the symbol
library. The session pane shows progress messages on all modules that it processes into
symbols.

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7. After all data has been imported, the Import dialog closes. In the Gateway library and
symbol panes, the new library can be selected and resulting symbols shown (Figure 10-8).

Figure 10-8 Gateway Window after Import

8. This library now needs to be saved into a workspace. To do this, click FileSave
Workspace As and enter a name and press Save.
If this new library and workspace are not in the desired directory or computer, there is a
simple way to export the workspace (and libraries) to any other location. To export the design,
click FileExportDesign. The Export Design dialog appears as shown in Figure 10-9.

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Figure 10-9 Export Design Dialog

The only items checked are the workspace and its library, since there is no active schematic or
design open. To see the full contents of the library to be exported, expand the library and the
symbols are individually as shown in Figure 10-10. Finally, click the Browse button and
choose a location and type a file name in the dialog. Then press OK and Gateway exports this
to a *.tar.gz file. Now using FileImport Design, the design can be imported to any
desired location that exists on the network and is ready for use.

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Figure 10-10 Export Design with Library Expanded

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Example 2 – Importing Spice to an Existing Symbol Library Schematic Design Examples

10.3 Example 2 – Importing Spice to an Existing Symbol Library

It is common to import design data from other schematic capture tools in the EDIF 200
format. This saves design capture time and keeps the graphics the same as they appeared in
the original tool. Unfortunately, the symbols are only drawings and have very little
information about how they are used in designs for netlisting and simulation. The Import
SPICE and Import Verilog tools in Gateway solve the task of importing the module and
subcircuit definitions and formatting the attributes and netlist strings accordingly to the EDIF
imported symbols. Example 2 shows how to accomplish this by beginning with a symbol
library that has been EDIFed into Gateway.
1. Open the workspace that contains the library of EDIF imported symbols. In this example,
there are three symbols that reside in a library named example_analog. See Figure 10-
11.

Figure 10-11 Gateway with Library from EDIF Import

2. Select FileImport SPICE.
3. In the dialog, browse to the file containing the subcircuit definitions, and then choose the
library option of Updating Symbol Properties in the library as shown in Figure 10-12.

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Figure 10-12 Import SPICE Options to Update Symbol Properties

4. Press the Import button and the symbols are now formatted with parameters and netlist
strings to match the subcircuit definitions.

Note: Figure 10-12 shows that there are matching symbols and definitions from the model file. If there are any differences
between the symbol names and subcircuit definitions, Gateway allows you to specify a definition for any given symbol and
then Gateway will automatically format the symbol. Figure 10-13 shows a case where there is a symbol in the library
named nand21 but the model file does not contain a subcircuit with the same name. Using the pulldown menu, you can
select the right one.

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Figure 10-13 Manually Selecting the Correct Definition to Match the Symbol

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Chapter 11
Scripting
Javascript in Gateway Scripting

11.1 Javascript in Gateway

11.1.1 Scripting
The Gateway scripting engine is designed to allow you to automate common GUI operations
using Javascript enhanced with Gateway specific API (see the Gateway JavaScript API
Reference Guide). There are four ways to access the Javascript environment.
• Use the command line text box at the bottom of the main window.
• Write a script file and execute the commands by selecting ToolsRun Script .
• Use the debug environment by using ToolsRun Script with Debugger.
• Pass a script file into Gateway at startup using either the -mnu or -jscript command
line arguments.

11.1.2 Command Line

The command line allows complete access to the Javascript scripting environment. All the
API calls in the Gateway JavaScript API Reference Guide are available from here

11.1.3 Run Script

Longer commands or more complex automation can be performed by writing the script
commands to a file. You can then load and execute the file by using ToolsRun Script.
You can add a command as a menu item on the Tools menu (see the Gateway JavaScript API
Reference Guide) or create its own GUI dialog using the scripting API.

11.1.4 Run Script with Debugger

Loading a script file to run with the debugger allows you to place breakpoints in the script file
and examine the value of variables during breaks in the script execution. A complete
reference for the debugger environment can be found in the IWorkbench User’s Manual.

11.1.5 Command line Arguments

To execute javascript commands at start-up, use the -jscript command line argument. This
will execute the javascript file in the application. You can chain more scripts together by
passing them as additional -jscript command line arguments. The scripts will be executed
in reverse order.
The -mnu command line argument is used perform GUI customization operations on
application start-up, such as adding Menus and Action items and associated callbacks
functions. See the Gateway JavaScript API Reference Guide for more information on GUI
customization functions.

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11.2 Callback Scripting

Callback scripting in Gateway allows you to have Javascript script functionality executed
when a particular action is done on a symbol instance. The actions supported by callback
scripting are:
• Init
• Value Changed
• Done
The Init action is called when you first interact with the symbol (i.e., selects the symbol). This
gives the ability for instance to the symbol designer to decide which attributes to show to you
depending on the value of other attribute.
The Value Changed callback will run the script when the value is being committed to the
schematic instance.
The Done callback is run when all editing has been changed. If editing with the Properties
editor on the design browser, this callback is fired on a lost focus event. If in the properties
dialog, this callback is fired when all the current changes have been applied. Typically, this
action is used to allow validation to take place.

11.2.1 Attaching Callback Script

Figure 11-1 shows how to set a callback script for the spicelib symbols in the workspace.
When an attribute in one of the spicelib symbols is changed and a callback function has been
specified, the appropriate callback function will be instantiated from this file.

Figure 11-1 Attaching Callback Script

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11.2.2 Specifying the Callback Function

For Gateway to call the appropriate callback function, specify in the symbol which function
will be invoked when a change occurs to one of its attributes (Figure 11-2). The callback
property of the symbol must specify the name of the function in the callback script associated
with the library. In this case, we are using the res_callback function.

Figure 11-2 Symbol Properties pane

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11.2.3 Callback API

Below is the Application Programmer’s Interface (API) used when Gateway calls one of the
callbacks.
Init
This is called when the symbol instance initializes the properties editor/dialog.
Syntax
function <myfunc>(hSymbol, attributes);
Parameters

Name Description

hSymbol The symbol instance object that is being initialized.

attributes An array of attribute objects.

Return Value
None
Example

with (Silvaco.Gateway)
{
function resInit(hSymbol, attributes)
{
if(attributes.R.value < 10) // value, enable, visible
{
attributes.SCALE.visible = true;
attributes.SCALE.enable = true;
attributes.SCALE.drawing_visibility = NVV_NAME_VALUE ;
}
else if(attributes.R.value > 10)
{
attributes.SCALE.visible = false ;
attributes.SCALE.drawing_visibility = NVV_INVISIBLE;
}
}
}

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Value Changed
This is called when a value has changed on the symbol instance.
Syntax
function <myfunc>(hSymbol, changed, attributes);
Parameters

Name Description

hSymbol The symbol instance object that is being changed.

changed An array of attribute names that have changed.
attributes An array of attribute objects

Return Value
None
Example

with (Silvaco.Gateway)
{
function isChanged(changed, name)
{
for (p in changed)
{
if (changed[p] === name)
return true;
}

return false
}

function resValueChanged(hRes, changed, attributes)

{
const rho = 200;
var W = parseFloat(attributes.W.value);
var L = parseFloat(attributes.L.value);
if (isChanged(changed,"W"))
{
display("Width changed: Calculating R");
R = rho * L / W;
}
attributes.R.value = R;
}
}

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Done
This is called when you finish editing an attribute or, in the case of the dialog, when a set of
attributes have been applied.
Syntax
function <myfunc>(hSymbol, attributes);
Parameters

Name Description

hSymbol The symbol instance object that is being initialized.

attributes An array of attribute objects.

Return Value
Boolean. If failure, the attribute changes are not committed.
Example

with (Silvaco.Gateway)
{
function resDone(hSymbol, attributes)
{
if(attributes.R.value < 10)
{
attributes.SCALE.visible = true;
attributes.SCALE.enabled= true;
attributes.SCALE.drawing_visibility = NVV_NAME_VALUE ;
}
else if(attributes.R.value > 10)
{
attributes.SCALE.visible = false ;
attributes.SCALE.enable = false;
attributes.SCALE.drawing_visibility = NVV_INVISIBLE;
}
}
}

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11.2.4 Attribute Object

The Attribute object used in the above callbacks is used to get/set values of the attributes
belonging to Symbol Instances when a callback script is run.
Properties

Property Description

value String or Number. The value assigned to the attribute.

enabled Boolean. Specifies whether the value can be changed in
the property editors.
visible Boolean. Specifies whether the attribute is shown in the
property editors.
drawing_visibility Integer. Controls the visiblity of the attribute label on the
schematic drawing. This may be one of the "NVV_..."
constants.

11.2.5 Visibility Constants

The following visibility constants are used for the drawing_visibility property of an
Attribute object.
Constants

Constant Description

NVV_INVISIBLE Hides the attribute on the drawing.

NVV_VALUE Shows the value of the attribute.
NVV_RESULT Shows the resultant value of the attribute.
NVV_NAME Shows the name of the attribute.
NVV_NAME_VALUE Shows the name and value of the attribute
(i.e., name=value).
NVV_NAME_RESULT Shows the name and resultant value of the attribute
(i.e., name=result).
NVV_DESCRIP Shows the description of the attribute.
NVV_DESCRIP_VALUE Shows the description and value of the attribute
(i.e., description=value).
NVV_DESCRIP_RESULT Shows the description and resultant value of the
attribute (i.e., description=result).

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 Appendix A
Communications
Troubleshooting
Common Issues Communications Troubleshooting

A.1 Common Issues

Following is a list of the common issues associated with the communication between
Gateway, SmartSpice and SmartView. To get detailed information and solutions on how to fix
the problem, click on the issue.
• Cannot create input deck/netlist/control deck (see Section A.1.1 Cannot create input deck/
netlist/control deck)
• Simulation does not run (Section A.1.2 Simulation Does Not Run)
• Cannot plot vectors (Section A.1.3 Cannot Plot Vectors)
• DC Bias markers not present (Section A.1.4 DC Bias markers Not Present)
• Output/error file not present (Section A.1.5 Output/Error File Not Present)
• Licensing issues (Section A.1.6 Licensing Issues)
• Nameservice issues (Section A.1.7 Nameservice Issues)

A.1.1 Cannot create input deck/netlist/control deck

This problem usually arises due to a file permission issue. Therefore, check the following:
• Check the user’s permissions
• Check the disk space
• Contact your system administrator to help with access control list (ACL) permissions and
network drive permission.
Check the user’s permissions
On UNIX, use the command ‘ls –al .’ in the directory where the schematic is to get its
base permissions and search for the . entry. For example:
drwxr-xr-x 67 username silvaco 4608 Sep 14 13:58.
the first part of the line shows the user permissions (i.e., drwxr-xr-x). This particular
example shows that the user username has read (r), write (w), and execute (x) permissions on
this directory. It also shows that any one in the Silvaco group has read (r) and execute (x)
permissions and all other users also have read (r) and execute (x) permissions.
On Windows platforms, right-click on the directory in Explorer and choose Properties
(see Figure A-1).

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Figure A-1 Directory Properties

Check the disk space
On UNIX to check the disk space, use the command ‘df –k <mount point of
directory>’ to get the disk space of the directory where the schematic is located. If the
mount point of the directory is not known, then specify ‘df –k’ and search for the directory.
For example:
‘df –k /home/username’

Filesystem kbytes used avail capacity Mounted on phoenix:/

export/data1/users/username
70565698 25885917 43974125 38% /home/username
On Windows platforms, right-click on the drive in Explorer and choose Properties (see
Figure A-2).

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Figure A-2 Disk Space

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A.1.2 Simulation Does Not Run

There can be many reasons why a simulation doesn’t run from Gateway.
• Check that the version of SmartSpice exists and will run
• Check that the nameservice is running (see Section A.1.7 Nameservice Issues).
• Check that the licensing server is running (see Section A.1.6 Licensing Issues).
• Confirm that the input deck is present and can be read by the user.
• Check to see if there are any errors present in the Gateway Session window, such as
model errors, unable to converge, and so on.
Check that the version of SmartSpice exists
To check that the version of SmartSpice exists go to the Silvaco installation directory (e.g.,
c:\sedatools) and look in the directory:
<InstallationDirectory>/lib/smartspice/<version>/<platform>
where <version> is the version that you are interested in and <platform> is the platform
that you are on. For example, if you were looking for 2.17.0.R on Windows the directory
would be c:\sedatools\lib\smartspice\2.17.0.R\x86-nt and the executable name
would be smartspice.exe. As an added security measure, SIPC can only launch
applications listed in $S_INSTALL_ROOT/var/sipcclients.cnf.
Typical sipcclients.cnf file
This file contains the programs that can be launched through the SIPC Communications.
# ----------------------------
# Sipc authorized applications
#
# File syntax:
# -----------
# - All the fields of this file must be separated by 1 or
# more TAB char. SPACE char is not a separator.
#
# - Quote are allowed but you don't need to quote Application name
if
# it contains spaces because spaces are not considered as
separators.
#
# - The App Type column is a single letter in ['S'|'C'|'N']:
# + 'S' means : the application is a Sipc Server (with Sipc >=
0.3.0)
# + 'C' means : the application is a Sipc pure Client
# + 'N' means : the application is not a Sipc application.
#

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# - Trailling or leading SPACEs, TAB char are removed from a whole

line.
#
# - Environment variables should be enclosed by < and >.
#
# - The first parsed line must be
# SIPC_TEMPLATE_VERSION 1.0
# The version number format is X.Y and is separated by a TAB.
# ----------------------------
SIPC_TEMPLATE_VERSION 1.0
# +---------------+----+----------------+------------
# |ALIAS |App | Application| Optional
# | NAME |Type| Name| arguments
# +---------------+----+----------------+------------
# | | | |
smartspice S <S_INSTALL_ROOT>/bin/smartspice
smartview S <S_INSTALL_ROOT>/bin/smartview
scholar S <S_INSTALL_ROOT>/bin/scholar
vwf S <S_INSTALL_ROOT>/bin/vwf -d -fg
+
Confirm that the input deck is present and can be read by the user
To confirm that the input deck is present and can be read by the user, go to the directory where
the schematic file is placed (e.g., c:\examples) and look for the file <schematic name>.in
(e.g., RSFF_Simulation.in which corresponds with RSFF_Simulation.schlr).
To confirm if the user can read input deck, do the following:
On UNIX, use the command ‘ls –l <inputdeck>’ in the schematic directory to get its
base permissions. For example:
-rw-r--r-- 1 username silvaco 2791 Nov 14 15:52
RSFF_Simulation.in
On Windows platforms, right-click on the directory in Explorer and choose Properties (see
Figure A-3).

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Figure A-3 File Properties

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Check to see if there are any errors present in the Gateway Session window
Another reason for the simulation not running could be due to actual simulation errors, such
as cannot find model, cannot converge, and no control statements present. These errors will
be displayed in the Gateway Session Window (see Figure A-4).

Figure A-4 Gateway Session Window Errors

A.1.3 Cannot Plot Vectors

There can be many reasons why Gateway cannot plot vectors.
• Check that the version of SmartView exists and will run.
• Check that the nameservice is running (see Section A.1.7 Nameservice Issues).
• Check that the licensing server is running (see Section A.1.6 Licensing Issues).
• Check to see if there are any errors present in the Gateway Session Window, such as
vector not found, simulation issues, and so on.
• Verify what the setting of plot options. For example, Analysis Type filter is set to All
Analyses or the analysis you want to plot.
Check that the version of SmartView exists
To check that the version of SmartView exists go to the Silvaco installation directory (e.g.,
c:\sedatools) and look in the directory:
<InstallationDirectory>/lib/smartview/<version>/<platform>
where <version> is the version that you are interested in and <platform> is the platform
that you are on. For example if you were looking for 2.9.38.R on Windows, the directory
would be c:\sedatools\lib\smartview\2.9.38.R\x86-nt and the executable name
would be smartview.exe. Due to added security to the SIPC launching of a program,
specifically not allowing the ability to launch any program (unless the Administrator has
authorized it), there is an alias file, $S_INSTALL_ROOT/var/sipcclients.cnf .

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Typical sipcclients.cnf file

This file contains the programs that can be launched through the SIPC Communications.
# ----------------------------
# Sipc authorized applications
#
# File syntax:
# -----------
# - All the fields of this file must be separated by 1 or
# more TAB char. SPACE char is not a separator.
#
# - Quote are allowed but you don't need to quote Application name
if
# it contains spaces because spaces are not considered as
separators.
#
# - The App Type column is a single letter in ['S'|'C'|'N']:
# + 'S' means : the application is a Sipc Server (with Sipc >=
0.3.0)
# + 'C' means : the application is a Sipc pure Client
# + 'N' means : the application is not a Sipc application.
#
# - Trailling or leading SPACEs, TAB char are removed from a whole
line.
#
# - Environment variables should be enclosed by < and >.
#
# - The first parsed line must be
# SIPC_TEMPLATE_VERSION 1.0
# The version number format is X.Y and is separated by a TAB.
# ----------------------------
SIPC_TEMPLATE_VERSION 1.0
# +---------------+----+----------------+------------
# |ALIAS |App | Application| Optional
# | NAME |Type| Name| arguments
# +---------------+----+----------------+------------
# | | | |
smartspice S <S_INSTALL_ROOT>/bin/smartspice

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smartview S <S_INSTALL_ROOT>/bin/smartview
scholar S <S_INSTALL_ROOT>/bin/scholar
vwf S <S_INSTALL_ROOT>/bin/vwf -d -fg
+
Check to see if there are any errors present in the Gateway Session Window
Another reason that can cause vectors not to be plotted could be due to actual simulation
errors. For example, cannot find vector, cannot converge, or no control statements present.
These errors will be displayed in the Gateway Session Window (see Figure A-4).
Verify the Setting of Plot Options
The plot options in Gateway decide how to plot the vectors specified. If the user chose to set
the Analysis Type filter on the plot dialog to Transient Analyses and there are no transient
analyses in the simulation, then the vectors will not be plotted.

A.1.4 DC Bias markers Not Present

If there are no DC Bias markers on the schematic after running the simulation, then try one of
the following suggestions.
• Check that the version of SmartSpice exists
• Check that the nameservice is running (see Nameservice issues)
• Check that the licensing server is running (see Licensing issues)
• Check to see if there are any errors present in the Gateway Session Window, such as
model errors or unable to converge.
Check that the version of SmartSpice exists
To check that the version of SmartSpice exists, go to the Silvaco installation directory (e.g.,
c:\sedatools) and look in the directory:
<installation directory>/lib/smartspice/<version>/<platform>
where <version> is the version that you are interested in and <platform> is the platform
that you are on. For example if you were looking for 2.17.0.R on Windows, the directory
would be c:\sedatools\lib\smartspice\2.17.0.R\x86-nt and the executable name
would be smartspice.exe.
Check to see if there are any errors present in the Gateway Session Window
The DC Bias markers may not be present due to actual simulation errors, such as cannot find
model, cannot converge, and no control statements present. These errors will be displayed in
the Gateway Session Window (see Figure A-4).

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A.1.5 Output/Error File Not Present

If the output/error file may not be present, try one of the following suggestions:
• Check to see if there are any errors present in the Gateway Session Window after running
the simulation, such as model errors and unable to converge.
• Make sure the user has write permissions in the output/error directory
Check to see if there are any errors present in the Gateway Session Window
If there are no errors present in the Session window, then the error file may not be present or
will be empty. If this occurs, then Gateway will not allow you to view the error file. These
errors will be displayed in the Gateway Session Window (see Figure A-4).
Make sure the user has write permissions in the output/error directory
The output/error file can be absent due to write permissions in the output/error directory. To
confirm the write permissions for the output/error directory, do the following:
On UNIX use the command ‘ls –al .’ in the output/error directory to get its base
permissions and search for the . entry. For example:
drwxr-xr-x 67 username silvaco 4608 Sep 14 13:58 .
the first part of the line shows the user permissions (i.e., drwxr-xr-x). This particular
example shows that the user username has read (r), write (w), and execute (x) permissions on
this directory. It also shows that any one in the Silvaco group has read (r) and execute (x)
permissions and all other users also have read (r) and execute (x) permissions.
On Windows platforms, right-click on the directory in Explorer and choose Properties (see
Figure A-5).

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Figure A-5 Directory Properties

The output/error directories are specified in the Preferences in Gateway. If they are blank,
then the output/error directories are the same as the schematic directory.

A.1.6 Licensing Issues

Silvaco programs can fail to start due to several licensing issues. This section explains briefly
how to check that the license server is working correctly and how to solve the common
licensing issues.
Detecting if the license server is running
To detect if the license server is running, run the Silvaco Management Console (SMAN) by
typing the following command:
<S_INSTALL_ROOT>/bin/sman – where <S_INSTALL_ROOT> is the
installation directory.
When the Silvaco Management Console appears, select SystemLicensing (see Figure A-
6). The Licensing tab will show which server the license monitoring program is using and
what licenses are currently checked out.

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Figure A-6 Licensing screen

Detecting if a license is available
To detect if a license is available, run the Silvaco Management Console and select
SystemLicensingManagement (see Figure A-7).

Figure A-7 License Management screen

Once the License Management screen appears, select the Show Valid License(s) option and
look for the license. For all other licensing issues, please consult the SFLM Installation
Guide.

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A.1.7 Nameservice Issues

Nameservice issues account for the majority of communication related issues between the
products. The nameservice is responsible for storing the unique identifiers of each of the
products.
When a Silvaco product starts, it attempts to start a new nameservice (SIPC Console)
program, which then verifies if a nameservice is already running. If so, then it can exit as the
products can use the already running nameservice.
The reasons why the nameservice (SIPC Console) program fail to start are:
• Confirm that the program exists
• Check that the configuration file is installed
• Make sure that there is no conflict with other CORBA Servers
• Confirm that the SIPC Console is running
Confirm the program exists
Go to the $S_INSTALL_ROOT/lib/sipc/<version no>/<platform> and see if the
program is present in this directory. The Windows executable is called sipc_console.exe
whereas the UNIX executable is sipc.exe.
Check that the Configuration File is installed
The SIPC Console program has a configuration file to handle the serverserver
communication, notification/broadcast messages. This file is placed in the S_COMMON_DIR.
In other words $S_INSTALL_ROOT/lib/sipc/<version no>/common and contains
information and settings about the queue size, timeout values, and other information. This file
should not be modified.
Make sure that there is no conflict with other CORBA Servers
This is a rare case and even when it happens should not cause any complications as long as
the other program that is using the previous CORBA Server is 2.6 compliant. This means that
as long as the other program follows the naming standard for CORBA 2.6 then there will not
be a problem. Simply stop the conflicting CORBA Server (it will be listening on port 2809)
and start the SIPC Console program. The program that was using the other server can now use
the SIPC Console program without problems.
The reason why we have to use the SIPC Console is due to the serverserver
communications, which are tied to OmniOrb’s implementation of the CORBA 2.6 Naming
Server.
Confirm that the SIPC Console is running
To confirm that the SIPC Console is running we can use the Silvaco Management Console
(SMAN).
1. Run SMAN by issuing the command, $S_INSTALL_ROOT/bin/sman.
2. When it appears, select SystemCommunications tab. SMAN will report whether there
are any issues with contacting the SIPC Console.
For more information on the SMAN program, please see the SMAN manual. This can be
accessed through the Silvaco Resource Center or by running the SMAN program and
selecting the manual from the Help menu.

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 Index

A Netlisting ......................................................................224
Template String .............................................................161
Adding
Changing Symbols .....................................................194–196
Diagonal Wires .............................................................. 139
Drawing Objects ............................................................ 198 Checking Designs ............................14–16, 36, 220–223, 242
Symbols ....................................................................... 120 Chord Symbol ...........................................................148–153
Text ............................................................................ 198 Colors ...............................................................................34
Wires ................................................................... 134–139 Editing and Resetting to Default .........................................199
Analog ............................................................................ 244 Control ............................................................................237
Analyses Toolbar ................................................................. 17 Control Cards ........................................................16–17, 250
Application Settings Group Control Files
Auto-Save ...................................................................... 33 Atlas ............................................................................237
Colors ...................................................................... 34–35 CDL ............................................................................237
Drawing Checks ............................................................... 36 Guardian ......................................................................236
Frame ...................................................................... 37–38 NDL ............................................................................237
Grid ......................................................................... 39–41 Simulation ............................................................230–237
Number Format ............................................................... 54 SmartSpice ...................................................................230
Shortcuts ........................................................................ 57 Verilog .........................................................................231
Technology ..................................................................... 58 Window ..........................................................................17
Toolbars ......................................................................... 59 Converting from EDIF .................................................281–287
Arrays ..................................................................... 185–190 Copying ...........................................................................124
Atlas ................................................................................. 45 Creating
Control File ................................................................... 237 Control Files ..........................................................230–237
Netlisting ...................................................................... 224 Schematic Drawings .........................................................80
Preferences .............................................................. 45, 66 Specific Netlists .....................................................227–229
Template String ............................................................. 161 Symbols ...............................................................155–164
Attribute Object ................................................................. 312 Symbols from Schematic ..................................................192
attributes Cross Probing ...........................................................247–249
editing ......................................................... 127, 128–130
ordering and positioning ........................................... 130–133 D
symbol ................................................................. 158–161
symbol pin .................................................................... 156 DC Bias ...................................................................254–259
wires ................................................................... 138–139 Deck ...............................................................................238
AvanWaves DeckBuild ...........................................................................66
Preferences .................................................................... 72 Deleting ...........................................................................124
Descending ......................................................................193
B Deselecting ......................................................................122
Buses Design Checking ..............................14–16, 36, 220–223, 242
Chord Symbol ....................................................... 148–153 Design Flow
Iterative Instances .......................................................... 154 Control Files ..........................................................230–237
Naming Conventions ............................................... 145–146 Error Checking .......................................................220–223
Ripping ................................................................ 147–148 Input Deck ....................................................................238
Netlisting ..............................................................224–229
C Simulation ....................................................................240
Callback API ............................................................. 309–312 Designs
Exporting ..................................................86–90, 299–300
Callback Script
Importing ........................................................91, 302–304
Attaching ...................................................................... 307
Disconnecting ...........................................................125–126
Callback Scripting
Specifying .................................................................... 308 Done ...............................................................................311
CDL Drawing .............................................................................36
Control File ................................................................... 237 Drawings

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 Index

Creating ......................................................................... 80 Netlisting ......................................................................224

Exporting ........................................................................ 82 Preferences ..............................................................52, 67
Opening ......................................................................... 79 Template String .............................................................161
Printing .................................................................... 84–85
Saving ..................................................................... 81–82 I
Importing
E Designs ..........................................................91, 302–304
EDIF EDIF ....................................................................273–280
Converting Imported Files ........................................ 281–287 SPICE .................................................................293–298
Exporting .............................................................. 288–291 Verilog .................................................................293–298
Importing Files ....................................................... 275–280 Inherited Nets
Edit Symbol Attributes Dialog ............................... 128–130, 158 Examples .............................................................143–144
Editing Expressions ..................................................................141
Schematics ........................................................... 110–204 Properties .....................................................................140
Symbols ............................................................... 156–164 Init ..................................................................................309
Errors .............................................................................. 222 Input Deck ............................................................19–22, 238
Disabling and Enabling .................................................... 223 Instance Attributes Dialog ....................................................127
Review Errors Pane .................................................. 14, 220 Instances
Expert ....................................................................... 62, 260 Attributes Dialog .............................................................128
Exporting Disconnecting ........................................................125–126
Designs ................................................... 86–90, 299–300 Inverting Selection ......................................................122, 123
EDIF ................................................................... 288–291
Picture Formats ............................................................... 82
L
F Layout Editor ..............................................................62, 260
Libraries
File Details ............................................................... 203–204 Filtering ........................................................................116
File Operations Modifying ......................................................................107
Create Drawings .............................................................. 80 Reloading .....................................................................197
Exporting Designs ...................................................... 86–90 Spicelib ........................................................................101
Exporting Drawings ..................................................... 82–83 Structures .....................................................................107
Loading Workspaces ......................................................... 78 Version Control System (VCS) ..........................................108
Opening Drawings ............................................................ 79 Licensing .................................................................324–325
Printing Drawings ....................................................... 84–85
LVS ..................................................................................48
Saving Drawings ........................................................ 81–82
Control File ...................................................................236
Files ................................................................................. 90 Netlisting ......................................................................224
Preferences ..............................................................48–??
G Template String .............................................................161
Gateway Window ................................................................. 12
Generating M
Names ................................................................. 181–184 Mirroring ..........................................................................123
Symbols ............................................................... 191–192 MixedMode .........................................45, 161, 224, 237, 242
Go to Sheet Dialog ............................................................... 98
Guardian N
Control File ................................................................... 236
Netlisting ...................................................................... 224 Nameservice .....................................................................326
Preferences .................................................................... 48 NDL
Template String ............................................................. 161 Control File ...................................................................237
GUI Environment and Settings Netlisting ......................................................................224
Panes ...................................................................... 26–31 Preferences ....................................................................50
Preferences Dialog ..................................................... 32–69 Template String .............................................................161
Windows .................................................................. 26–31 netInherit ..........................................................................141
Netlists
H Atlas ......................................................................45, 224
CDL ......................................................................47, 224
Help .................................................................................. 92 LVS/Guardian ..........................................................48, 224
HSPICE NDL ......................................................................50, 224

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 Index

Rebuilding .................................................................... 224 Pin Names ....................................................................183

Specific Netlist ....................................................... 227–229 Symbol Instance Names ..................................................182
Spice ..................................................................... 52, 224 Wire (Net) Names ...........................................................184
Nets Reloading Libraries ............................................................197
Inherited ............................................................... 140–144 Review Errors Pane ......................................................14, 220
Terminology .................................................................. 134 RF
Viewing Names .............................................................. 217 Analyses ..............................................................232–234
Nodes Netlisting ......................................................................224
Showing Information ....................................................... 216 Preferences ....................................................................52
Terminology .................................................................. 134 Simulator ........................................................................63
Number Format ................................................................... 54 Template String .............................................................161
Rotating ...........................................................................123
O
Objects S
Alignment and Spacing ............................................ 199–200 Schematic Design
Open Symbol Dialog ........................................................... 155 Design Browser .....................................................212–215
Options ............................................................................ 274 Design Flow ..........................................................219–240
Ordering Pins for Netlisting .......................................... 227–228 Design Sheets. ..........................................................94–99
Editing .................................................................111–204
Output Tab ................................................................. 12, 220
Example ...............................................................293–304
File Details ............................................................203–204
P Miscellaneous Editing Options ...................................198–201
Panning ................................................................... 207–209 Showing Node and Symbol Information ...............................216
Viewing ................................................................206–217
Pasting ............................................................................ 124
Schematics .......................................................................176
Pins
Attributes Dialog ............................................................ 156 Selecting ..........................................................................122
Bi-Directional ................................................................. 183 Session Tab .......................................................12, 220, 248
Input ............................................................................ 183 Setting Plot Options ....................................242, 244–246, 322
Page ................................................................. 94–95, 99 Sheets
Regenerating Names ...................................................... 183 Adding ...........................................................................98
Plot ................................................................................. 244 Connecting .....................................................................99
Plotting Deleting .........................................................................98
From Archive ................................................................. 264 Navigating ......................................................................98
Options ........................................................................ 244 Pins ..............................................................................99
Vectors .................................................... 20, 64, 249, 264 Silos
Preferences Example ...............................................................265–270
Exporting .................................................................. 73–74 Netlisting ......................................................................224
Importing ........................................................................ 75 Simulator ........................................................................68
Managing ................................................................. 73–75 Template String .............................................................161
Recent Files .................................................................... 76 Simulation
Resetting to Defaults ......................................................... 75 DC Bias Display .....................................................254–259
Preferences dialog Post-Processing .............................................................264
Application Settings Group ........................................... 33–59 Pre-Simulation .......................................................242–243
Netlist Settings Group ................................................. 44–52 Running .................................................23, 240, 250–253
Tools Settings Group .................................................. 62–68 Schematic Marking .................................................247–249
Printing ........................................................................ 84–85 SmartSpice Device Information ..................................260–263
SmartSpice Status ..........................................................259
Property pane editing .......................................................... 127
SmartSpice .......................................................................162
Analyses ..............................................................232–234
Q Importing to Gateway ..............................................293–295
QuickStart .................................................................... 13–24 Netlisting ......................................................................224
Preferences ....................................................................52
R Simulator ........................................................................63
Template String .....................................................161, 162
Rawfile ................................................................ 10, 64, 264
SmartSpiceRF
Rebuild ............................................................................ 224 Analyses ......................................................232–234, 236
Regenerating Netlisting ......................................................................224

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 Index

Preferences .................................................................... 52 Verilog .......................................................................53, 161

Simulator ........................................................................ 63 Example ...............................................................265–270
Template String ............................................................. 161 Importing into Gateway ............................................293–295
SmartView Netlisting ......................................................................224
Example ................................................................. 24, 270 Simulator ......................................................................173
Preferences .................................................................... 70 Template String .............................................................161
Special Keys Bindings .......................................................... 77 Viewing
Stubs Wires and Stub Wires with Pins .................................... 198 Schematics ...................................................................205
Switching Design Views ...........................................117–119
Switching ......................................................................... 117
Visibility Constants .............................................................312
Symbols
Attributes. ............................................................. 128–133 vprims .............................................................................101
Changing ............................................................. 194–196
Copying ....................................................................... 124 W
Creating ....................................................................... 155 Warnings ...................................................................36, 222
Deleting ....................................................................... 124 Disabling and Enabling ....................................................223
Deselecting ................................................................... 122 Review Errors Pane ..........................................................14
Editing ................................................................. 156–164
Waveform Viewer
Embedded, Attached, and Schematic Definitions ........... 166–178
AvanWaves ....................................................................72
Files ............................................................................ 101
SmartView ......................................................................70
Generating ........................................................... 191–192
TonyPlot .........................................................................71
Mirroring ...................................................................... 123
Moving ......................................................................... 124 Wires
Opening ....................................................................... 155 Attributes Dialog .....................................................138–139
Passing Parameters From Symbol to Schematics .......... 176–178 Creating .......................................................................137
Placing ................................................................ 120–124 Deleting .......................................................................124
Primitive ....................................................................... 165 Disconnecting ........................................................125–126
Regenerating Instance Names .......................................... 182 Merging Rules .......................................................134–137
Rotating ....................................................................... 123 Snapping ..............................................................138–139
Selecting ...................................................................... 122 Terminology ..................................................................134
Showing Information ....................................................... 216 Types ..........................................................................139
Special ........................................................................ 166 Workspaces
Subcircuits .................................................................... 193 Changing Settings ..........................................................105
Verilog-A ...................................................................... 172 Saving .........................................................................106

T Z
Thresholds ................................................................. 12, 259 Zooming ..................................................................207–209
TonyPlot
Preferences .................................................................... 71
Tools Settings Group
Layout Editor ................................................................... 62
Simulator. ................................................................. 63–68
Text Editor ...................................................................... 69
Waveform Viewer ............................................................. 70
Troubleshooting
Cannot create input deck/netlist/control deck ................ 314–316
Cannot Plot Vectors ................................................ 320–322
Common Issues ..................................................... 314–326
DC Bias Markers Not Present ........................................... 322
Licensing .............................................................. 324–325
Nameservice ................................................................. 326
Output/Error File Not Present .................................... 323–324
Simulation Does Not Run ......................................... 317–320

V
Value Changed ................................................................. 310
Vectors
Plotting .................................... 20, 64, 249, 264, 320–322

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