Logic and Computer Design Fundamentals

Chapter 2 – Combinational
Logic Circuits
Part 3 – Additional Gates and Circuits

Charles Kime & Thomas Kaminski

© 2004 Pearson Education, Inc.
Terms of Use
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Overview
§ Part 1 – Gate Circuits and Boolean Equations
• Binary Logic and Gates
• Boolean Algebra
• Standard Forms
§ Part 2 – Circuit Optimization
• Two-Level Optimization
• Map Manipulation
§ Part 3 – Additional Gates and Circuits
• Other Gate Types
• Exclusive-OR Operator and Gates
• High-Impedance Outputs

Chapter 2 - Part 3 2
Other Gate Types
§ Why?
• Implementation feasibility and low cost
• Power in implementing Boolean functions
• Convenient conceptual representation
§ Gate classifications
• Primitive gate - a gate that can be described using a
single primitive operation type (AND or OR) plus an
optional inversion(s).
• Complex gate - a gate that requires more than one
primitive operation type for its description
§ Primitive gates will be covered first
Chapter 2 - Part 3 3
Buffer
§ A buffer is a gate with the function F =
X:
X F

§ In terms of Boolean function, a buffer is

the same as a connection!
§ So why use it?
• A buffer is an electronic amplifier used to
improve circuit voltage levels and increase
the speed of circuit operation.

Chapter 2 - Part 3 4
NAND Gate
§ The basic NAND gate has the following symbol,
illustrated for three inputs:
• AND-Invert (NAND)
X
Y F( X , Y , Z ) = X × Y × Z
Z

§ NAND represents NOT AND, i. e., the AND

function with a NOT applied. The symbol
shown is an AND-Invert. The small circle
(“bubble”) represents the invert function.

Chapter 2 - Part 3 5
 NAND Gates (continued)
§ Applying DeMorgan's Law gives Invert-OR (NAND)
X
Y F( X , Y , Z ) = X + Y + Z
Z
§ This NAND symbol is called Invert-OR, since inputs
are inverted and then ORed together.
§ AND-Invert and Invert-OR both represent the
NAND gate. Having both makes visualization of
circuit function easier.
§ A NAND gate with one input degenerates to an
inverter.

Chapter 2 - Part 3 6
Transistor NAND Gate

Chapter 2 - Part 3 7
 NAND Gates (continued)
§ The NAND gate is the natural implementation for the
simplest and fastest electronic circuits
§ Universal gate - a gate type that can implement any
Boolean function.
§ The NAND gate is a universal gate as shown in
Figure 2-4 of the text.
§ NAND usually does not have a operation symbol
defined since
• the NAND operation is not associative, and
• we have difficulty dealing with non-associative
mathematics!

Chapter 2 - Part 3 8
NOR Gate
§ The basic NOR gate has the following symbol,
illustrated for three inputs:
• OR-Invert (NOR)
X
Y F(X, Y, Z) = X +Y+ Z
Z

§ NOR represents NOT - OR, i. e., the OR

function with a NOT applied. The symbol
shown is an OR-Invert. The small circle
(“bubble”) represents the invert function.

Chapter 2 - Part 3 9
NOR Gate (continued)
§ Applying DeMorgan's Law gives Invert-AND
(NOR)
X
Y
Z

§ This NOR symbol is called Invert-AND, since

inputs are inverted and then ANDed together.
§ OR-Invert and Invert-AND both represent the
NOR gate. Having both makes visualization of
circuit function easier.
§ A NOR gate with one input degenerates to an
inverter.
Chapter 2 - Part 3 10
NOR Gate (continued)
§ The NOR gate is another natural implementation
for the simplest and fastest electronic circuits
§ The NOR gate is a universal gate
§ NOR usually does not have a defined operation
symbol since
• the NOR operation is not associative, and
• we have difficulty dealing with non-associative
mathematics!

Chapter 2 - Part 3 11
Transistor NOR Gate

Chapter 2 - Part 3 12
NAND Flash & NOR Flash

Chapter 2 - Part 3 13
A Flash Memory Cell (floating-gate
transistor)

Chapter 2 - Part 3 14
 Exclusive OR/ Exclusive NOR
§ The eXclusive OR (XOR) function is an important
Boolean function used extensively in logic circuits.
§ The XOR function may be;
• implemented directly as an electronic circuit (truly a
gate) or
• implemented by interconnecting other gate types (used
as a convenient representation)
§ The eXclusive NOR function is the complement of
the XOR function
§ By our definition, XOR and XNOR gates are
complex gates.
Chapter 2 - Part 3 15
Exclusive OR/ Exclusive NOR
§ Uses for the XOR and XNORs gate include:
• Adders/subtractors/multipliers
• Counters/incrementers/decrementers
• Parity generators/checkers
§ Definitions
• The XOR function is: X Å Y = X Y + X Y
• The eXclusive NOR (XNOR) function, otherwise
known as equivalence is: X Å Y = X Y + X Y
§ Strictly speaking, XOR and XNOR gates do not
exist for more than two inputs. Instead, they are
replaced by odd and even functions.
Chapter 2 - Part 3 16
 Truth Tables for XOR/XNOR
Because it is defined as X Y + X’ Y’ that equals 1 if
§ Operator
and only if X = YRules: XORX is equivalent
implying XNOR
to Y.
X Y XÅY X Y (XÅY)
or X ºY
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
§ The XOR function means:
X OR Y, but NOT BOTH
§ Why is the XNOR function also known as the
equivalence function, denoted by the operator
º?
Chapter 2 - Part 3 17
The three-variable XOR is equal to 1 if only one
XOR/XNOR (Continued)
variable is equal to 1 or if all three variables are
equal to 1. With three or more variables
§ The XOR function can be extended to 3 or more
an odd
number of variables
variables. For moremust
than 2be equal ittois called
variables, 1. Therefore,
an odd
it’s called
Why? oddorfunction.
function modulo 2 sum (Mod 2 sum), not an XOR:
X Å YÅ Z = XYZ+ XYZ+ XYZ+ XYZ
§ The complement of the odd function is the even
function.
§ The XOR identities:
XÅ0 = X X Å1 = X
XÅX =0 XÅX =1
XÅY = YÅX
( X Å Y) Å Z = X Å ( Y Å Z ) = X Å Y Å Z

Chapter 2 - Part 3 18
Symbols For XOR and XNOR
§ XOR symbol:

§ XNOR symbol:

§ Symbols exist only for two inputs

Chapter 2 - Part 3 19
XOR Implementations
§ The simple SOP implementation uses the
following structure: X

X Y

Y
§ A NAND only implementation is:
X

X Y

Chapter 2 - Part 3 20
 Odd and Even Functions
§ The odd and even functions on a K-map form
“checkerboard” patterns.
§ The 1s of an odd function correspond to minterms
having an index with an odd number of 1s.
§ The 1s of an even function correspond to minterms
having an index with an even number of 1s.
§ Implementation of odd and even functions for
greater than 4 variables as a two-level circuit is
difficult, so we use “trees” made up of :
• 2-input XOR or XNORs
• 3- or 4-input odd or even functions
Chapter 2 - Part 3 21
Example: Odd Function Implementation
§ Design a 3-input odd function F = X + Y + Z
with 2-input XOR gates
§ Factoring, F = (X + Y) + Z
§ The circuit:
X
Y
F
Z

Chapter 2 - Part 3 22
Example: Even Function Implementation
§ Design a 4-input even function F = W + X+ Y + Z
with 2-input XOR and XNOR gates
§ Factoring, F = (W + X) + (Y + Z)
§ The circuit:
W
X
F
Y
Z

Chapter 2 - Part 3 23
 Hi-Impedance Outputs
§ Logic gates introduced thus far
• have 1 and 0 output values,
• cannot have their outputs connected together, and
• transmit signals on connections in only one direction.
§ Three-state logic adds a third logic value, Hi-
Impedance (Hi-Z), giving three states: 0, 1, and
Hi-Z on the outputs.
§ The presence of a Hi-Z state makes a gate output
as described above behave quite differently:
• “1 and 0” become “1, 0, and Hi-Z”
• “cannot” becomes “can,” and
• “only one” becomes “two”
Chapter 2 - Part 3 24
Hi-Impedance Outputs (continued)
§ What is a Hi-Z value?
• The Hi-Z value behaves as an open circuit
• This means that, looking back into the circuit, the output
appears to be disconnected.
• It is as if a switch between the internal circuitry and the
output has been opened.
§ Hi-Z may appear on the output of any gate, but we
restrict gates to:
• a 3-state buffer, or
• a transmission gate,
each of which has one data input and one control
input.
Chapter 2 - Part 3 25
The 3-State Buffer
§ For the symbol and truth table,
IN is the data input, and EN, Symbol
the control input.
IN OUT
§ For EN = 0, regardless of the
value on IN (denoted by X), the
output value is Hi-Z. EN
§ For EN = 1, the output value Truth Table
follows the input value.
EN IN OUT
§ Variations:
• Data input, IN, can be inverted 0 X Hi-Z
• Control input, EN, can be inverted 1 0 0
by addition of “bubbles” to signals.
1 1 1

Chapter 2 - Part 3 26
Resolving 3-State Values on a Connection
§ Connection of two 3-state buffer
Resolution Table
outputs, B1 and B0, to a wire, OUT
§ Assumption: Buffer data inputs B1 B0 OUT
can take on any combination of
values 0 and 1 0 Hi-Z 0
§ Resulting Rule: At least one buffer
output value must be Hi-Z. Why? 1 Hi-Z 1
§ How many valid buffer output Hi-Z 0 0
combinations exist?
§ What is the rule for n 3-state Hi-Z 1 1
buffers connected to wire, OUT?
§ How many valid buffer output Hi-Z Hi-Z Hi-Z
combinations exist?
Chapter 2 - Part 3 27
 Answers to last slide
§ One buffer output Hi-Z? Because any data combinations
including (0,1) and (1,0) can occur.
If one of these combinations occurs, and no buffers are
Hi-Z, then high currents can occur, destroying or
damaging the circuit.
§ Valid buffer output combinations? 5
§ Rule for n 3-state buffers? n-1 buffer outputs must be Hi-
Z.
§ Valid buffer output combinations? Each of the n-buffers
can have a 0 or 1 output with all others at Hi-Z. Also all
buffers can be Hi-Z. So there are 2n + 1 valid
combinations.
Chapter 2 - Part 3 28
 3-State Logic Circuit
§ Data Selection Function: If s = 0, OL = IN0, else OL = IN1
§ Performing data selection with 3-state buffers:
EN0 IN0 EN1 IN1 OL

0 X 1 0 0
IN0
0 X 1 1 1
EN0 OL
1 0 0 X 0 S

1 1 0 X 1 IN1
0 X 0 X X EN1

§ Since EN0 = S and EN1 = S, one of the two buffer outputs

is always Hi-Z plus the last row of the table never occurs.

Chapter 2 - Part 3 29
MUX using Tri-State Buffers

Chapter 2 - Part 3 30
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Chapter 2 - Part 3 31