COEN 3103 – Logic Circuits and Design

Lesson 11

by: Engr. Ricrey E. Marquez, PCpE

• At this point, you have already learned the different types
combinational logic circuit (CLC) implementations such as
arithmetic and logic functions, code converters, and data
transmission circuits.
• CLC alone requires more complex design structures, thus it is
very costly and inflexible.
• To perform flexible sequences of operations, sequential logic
circuits are needed for storing information between operations.
• At the end of this lesson, you will be able to:
1. identify the fundamental elements or parts of sequential
logic circuits (SLC),
2. describe the behavior of basic memory elements used in
sequential logic circuits, and
3. demonstrate the timing diagram of each clocked flip-flops.
• Most systems encountered in
practice include memory elements,
which require that the system be
described in terms of sequential
logic (Mano, M. & Ciletti, M., 2013).
• Sequential Logic Circuit
• Type of logic circuit that employs
memory element in addition to
combinational logic gates, whose
outputs are a function of the inputs and
the state of the memory element
(latches or flip-flop) as illustrated in
Figure
• Combinational logic gates and storage elements are
interconnected to form the sequential logic circuit
• Storage (or memory) elements
• circuits that are capable of storing binary in formation at any given
time defines the state of sequential circuit
• Used in clocked sequential circuits are called flip-flops
• Flip-flop is a binary storage device capable of storing one bit of
information which in a stable state, the output of a flip-flop is either 0
or 1.
• Combinational logic gate or circuit
• Receives binary information from external inputs, along with the present state
of the storage elements which describes the binary value of the outputs

• External inputs
• Determine the condition for changing the state in the storage elements

• Outputs
• Function not only of the inputs, but also of the present state of the storage
elements
• Next state of the storage elements is also a function of external inputs and the
present state
• Two general classification of
sequential logic circuits:
• Synchronous sequential circuit
• Circuit whose behavior can be defined from
the knowledge of its signals at discrete
instants of time
• Synchronization is achieved by a timing device
called a clock generator, which provides a
clock signal having the form of a periodic train
of clock pulses
• Clock pulses are a square wave signal that is Synchronous clocked sequential circuit
sent to each memory elements (flip-flop)
• Use clock pulses to control storage elements
are called clocked sequential circuits
• Asynchronous sequential circuit
• Depends upon the input signals at any instant of time and the order in
which the inputs change
• Storage elements commonly used in asynchronous sequential circuits
are time-delay devices.
• Storage capability of a time-delay device varies with the time it takes for
the signal to propagate through the device
• Internal propagation delay of logic gates is sufficient duration to produce
the needed delay, so that actual delay units may not be necessary
• Gate-type asynchronous systems, the storage elements consist of logic
gates whose propagation delay provides the required storage
• Level Clocking
• Type of synchronous sequential circuit that uses clock pulse in the
inputs of memory elements
• Output can be change through clock either high (1) or low (0) signal as
illustrated in Figure

a) Positive Level Clocking (PLC) b) Negative Level Clocking (NLC)

• Edge-Triggering
• As shown in Figure, an edge-triggered synchronous sequential circuit
output that can only be change on the rising or falling edge of the clock.

a) Positive Going Transition (PGT) b) Negative Going Transition (NGT)

• Mano, M. and Ciletti, M. (2013) explained that a storage element
in a digital circuit are used to maintain a binary state indefinitely
(as long as power is delivered to the circuit), until directed by an
input signal to switch states.
• Storage elements that operate with signal levels (rather than signal
transitions) are referred to as latches
• Latches are said to be level sensitive devices
• Controlled by a clock transition are flip-flops
• Flip-flops are edge-sensitive devices
• Both latch or flip-flop is a bi-stable circuit that is most often used in
applications that require data storage.
• Bi-stable circuit has two complementary outputs that can assume
either of the two logic levels 0 or 1.
• Storage elements are related because latches are the basic circuits
from which all flip-flops are constructed
• Latches are useful for storing binary information and for the design of
asynchronous sequential circuits, they are not practical for use as
storage element in synchronous sequential circuits.
• SR Latches
• The SR latch is a circuit
with two cross-coupled
SR latch with NOR gates
NOR gates or two cross-
coupled NAND gates, and
two inputs labeled S for
set and R for reset.

SR latch with NAND gates

• An SR latch with a control input is shown in Figure. It consists of the basic
SR latch and two additional NAND gates.
• Control input En acts as an enable signal for the other two inputs.
• Make note that “the outputs of the NAND gates stay at the logic 1 level as long as the
enable signal remains at 0” which is the inactive condition for the SR latch.

SR latch with control input

• One way to eliminate the undesirable condition of the indeterminate state in
the SR latch is to ensure that inputs S and R are never equal to 1 at the
same time.
• This is done in the D latch as shown in Figure with two inputs: D (data) and
En (enable)

D latch with control input

• State of a latch or flip-flop is switched by a change in the control input.
• This momentary change is called a trigger, and the transition it causes is
said to trigger the flip-flop
• D latch with pulses with control input is essentially a flip-flop that is
triggered every time the pulse goes to the logic 1 level and input remains at
this level, any changes in the data input will change the output and the
state of the latch
• Figure shows the block diagram of a D flip-flop with two D latches and an
inverter gate.
• The first latch is called the master and the second the slave.
• D input and changes its output Q only at the negative edge of the synchronizing or
controlling clock (designated as Clk).
• Edge-triggered D flip-flop output (Q) change only during the transition of the clock
from 1 to 0 (falling edge of the clock)

• According to Mano, M. and Ciletti, M. (2013), the characteristic of the

master–slave flip-flop commands the following:
1. output may change only once,
2. change in the output is triggered by the negative edge of the clock, and
3. change may occur only during the clock’s negative level.
Block diagram of master-slave D flip-flop

Circuit construction of positive edge-triggered D flip-

flop
• Figure shows the graphic symbol for
the edge-triggered D flip-flop.
• Similar symbol was used for the D
latch, except for the arrowhead-like
symbol in front of the letter Clk,
designating a dynamic input.
• Dynamic indicator (>) represents the flip-
flop responds only during edge transition
of the clock. Graphic symbol of a) positive edge-
• Bubble outside the block adjacent to the triggered D flip-flop, b) negative edge-
triggered D flip-flop
dynamic indicator designates a negative
edge for triggering the flip-flop circuit while
absence of a bubble indicates that circuit
is a positive-edge triggered D flip-flop.
• According to Mano, M. and Ciletti, M. (2007), a very large-
scale integration circuits (VLSIs) contain several thousands of
gates within one package
• These circuits are constructed by interconnecting the various
gates to provide a digital system.
• If you notice, each flip-flop is constructed from an
interconnection of logic gates
• Other types of flip-flops can be constructed by using the D flip-
flop and external logic.
• Two flip-flops less widely used in the design of digital systems
are the JK and T flip-flops.
• JK flip-flop (J as a set input, and K
as a reset input)
• Most versatile of the basic flip-flops
specially in the design of digital
counter circuit.
• When the flip-flop is enabled, it
permits the storage of a binary data
based on the combination of states
taken by the inputs J and K.
• JK flip-flop can be implemented by
using the logic circuit as shown in Basic construction of JK flip-flop
Figure.
• T flip-flop (T stands for
toggle), as shown in
Figure.
• When the T flip-flop is
enabled, its outputs change
state every time a clock
pulse is applied to the input
T.

Basic construction of T flip-flop

• JK and T flip-flops can also be constructed using edge-triggered
D flip-flop and external inputs

a) Circuit diagram of JK flip-flop with edge- a) Circuit diagram of T flip-flop with edge-
triggered D flip-flop b) graphic symbol triggered D flip-flop b) graphic symbol
• Characteristic table
• Defines the logical properties of a
flip-flop by describing its operation Characteristic table D flip-flop
in tabular form

Characteristic table of JK flip-flop

Characteristic table SR latch

Characteristic table T flip-flop

• Characteristic or next
state equation of each
type of flip-flops
• Applying k-map
simplification method, we
can derive characteristic
or next state equation of
SR, D, JK, and T flip-
flops as shown in Figure

Characteristic or next state equation of a) SR latch, b) D flip-flop, c)

JK flip-flop, and d) T flip-flop
• Some available flip-flop ICs have asynchronous inputs that are
used to force the flip-flop to a particular state independently of
the clock pulse
• These inputs are usually called direct PRECLEAR and direct
PRESET
• PRECLEAR simply clear switch input clears the flip-flop output (Q) to 0
• PRESET set switch input sets the flip-flop output (Q) to 1
• These input affects the flip-flop on a positive (or negative) value
of the input signal without the need for a clock pulse
• Useful for bringing all flip-flops in the system to a known starting state
prior to the clocked operation, because when we turned on the power
of a digital system, the state of the flip-flops is unknown (Mano, M. &
Ciletti, M., 2013).
• Figure illustrates the internal
circuit diagram, graphic symbol
and function table of direct
clear or PRECLEAR in positive
edge-triggered D flip-flop as
well as describes the operation
of the circuit

Positive edge-triggered D flip-flop with active

LOW asynchronous reset (PRECLEAR)
• Example. Draw the equivalent timing diagram of the following inputs
to each flip-flop.
• PRESET’ = 00111111
• PRECLEAR’ = 00110011
• CLK = 01010101
• J = 11100111
• K = 11001100
• D = 11110000
• T = 11000011
Assume that present state of Q is 1, draw the timing diagram of:
a) PLC JK Flip-flop with Preclear only
b) NGT JK Flip-flop with Preset & Preclear
c) NLC D Flip-flop with Preclear only
d) PGT T Flip-flop with Preclear & Preset
• a) PLC JK Flip-flop with Preclear only
• b) NGT JK Flip-flop with Preset and Preclear
• c) NLC D Flip-flop with Preclear only
• d) PGT T Flip-flop with Preset and Preclear