AHB design rules 12/10/24, 9:58 AM

AHB design rules

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AHB design rules 12/10/24, 9:58 AM

Early burst termination is not allowed for Fixed length bursts or single burst.
Single burst must be followed by IDLE or NONSEQ transfer
Only INCR burst (undefined length burst) can have early termination transfer
with BUSY transfer.
AXI does not allow early burst termination, it will do conversion from AHB INCR
burst to AXI fixed burst length.

This is why even partial access, always read 32-bit is OK, return data is the
same for all byte/half word access

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AHB design rules 12/10/24, 9:58 AM

>According to AHB protocol, AHB masters will only check HREADY response
from Slave to see if it needs to hold AHB address/control?

HREADY is used to indicate that one transaction (data phase) is completed or

not. It has complex relationship with the behavior whether master holds
address/control signals or not and required to discuss with specific scenario.
Because there are a lot of factors determine if hold address phase information
or not besides HREADY. For example, in situation that HREADY is LOW (wait
state), address and control signals can change if HTRANS is IDLE/BUSY. But
they can not change if HTRANS is NONSEQ/SEQ. When master is sending one
beat (not the first one) of burst, address signal can change while control
signals should keep constant.

So, as described below, AHB master will not only check HREADY to see if it
needs to hold AHB address/control.

>According to AHB protocol, is it required for masters to hold AHB address/

control (such as HTRANS) if slave clock is not available?

AHB protocol do not include requirement about low power state. And, as you
can see in signal list, there is no signal to indicate power state. Only one clock
HCLK is used in protocol. So, theoretically speaking, because AHB is a clock-
edge driver protocol, master will not work as well if slave clock is not available.
It is reasonable that no information should be transferred if slave can not
accept it.

In implementation view, assuming that there is a large system who contain

power controller and one AHB master is not work in same clock domain with
slave, bridge product is used for cross clock domain. And such product usually
have Q-channel and P-channel signals which is used for low power state
operation. Error response will be sent back if master tries to access a slave

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AHB design rules 12/10/24, 9:58 AM

whose clock is unavailable. However, it depends on the specific realization and

product in usage.

>Does Slave HREADY require to be asserted HIGH during address phase of the
AHB transfer to the slave?

NO, HREADY indicates the state of data phase. Slave should drive it depending
on the completion situation of data process. In AHB protocol, transfer follow a
pipeline structure that data phase is in same cycle with the address phase of
next transfer. So, when you refer to "address phase", you are also referring to
the cycle of data phase of previous transfer. HREADY only play a role in data
phase. When HREADY is asserted HIGH (indicate data phase is completed),
slave sample the address phase information of next transfer in same cycle and
enter the data phase of current transfer in next cycle.

> This means it will check HREADY + HTRANS. IF HREADY is LOW and HTRANS
is changing from non-active (IDLE/BUSY) to active (NON-SEQ/SEQ) state,
HTRANS need to be kept constant, Right?

Yes, if in active state, HTRANS should keep constant until HREADY become
HIGH or error response is indicated in HRESP signal.

>There is no way for bus masters to check if slave clock is available or not to
hold the address phase information, right?

In view of protocol, the answer is yes because power state handling is

undefined and there is no mechanism for scenario that only one side of clock is
on.

However, there are software and hardware solution which is not part of content
of AHB protocol to solve it. Software is the most flexible way if it could know
the clock on-off state in slave side and control following code not to access to
that memory region. This solution requires highly skilled and carefully
programming ability. Because the clock-off salve still can be access. It may
bring deadlock to master port if HREADY keep LOW when clock is off. Even
though HREADY is HIGH, master will misunderstand this data as correct and
bring following potential bug to execution.

Compared with software solution, hardware solution is more reliable because of

fixed handling mechanism for situation that slave clock is off in hardware level.
For example, access gate component in product SIE-200, which is put forward
slave port, can give error response(depends on configuration) to master port if
it access a clock-off slave.

>We have been using the bus more or less like this for several chips on the
markets. Do let me know your comment on our usage.

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It is ok to use software solution. Considering that it have been using for several
chips on the markets, I think the software has experienced a lot of examinations
to prove to be robust enough. As answered in the former question, software is
rely on the programer to make sure it is executed in correct way. I am sorry for
that I could not provide more comments on software.

>If the AHB slave is not selected, HREADY still need to be HIGH right?

It is recommended but not must to do so. And HREADYOUT should keep

constant when it not be selected.

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