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21BLC1374 Lab4

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18 views6 pages

21BLC1374 Lab4

Uploaded by

tanmayadmuthe22
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We take content rights seriously. If you suspect this is your content, claim it here.
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School of Electronics Engineering (SENSE)

B. Tech – Electronics & Computer Engineering

BECE406E - FPGA BASED SYSTEM DESIGN


LAB RECORD
(L33+L34)

Submitted By
21BLC1374 – Pranav Pratap Patil

Submitted To
Dr. Sahthivel S M
DATE: 12/08/2024
[21BLC1374] Lab 4 – Four Bit Up-Down Counter 12/08/2024

Slot: L33+L34

LAB - 4
Four Bit Up-Down Counter
AIM: To Design a 4bit Up-Down Counter, Interface it with a BCD to 7-segment display and
utilizing a clock divider to ensure readability of the output in both Up and Down Modes and
implement on the DE2-115 board.

Software Required: Quartus Prime, ModelSim

Hardware Required: Altera Cyclone IV E DE2-115 Kit, USB Cable, Power Supply

Procedure:
1. Start Quartus Prime Lite Edition.
2. Go To : File → New Project Wizard.
3. Set The Working Directory and Name of the Project and Create an Empty Project.
4. Set Family to “Cyclone IV E”, Package to “FBGA”, Pin Count to “780” , Core Speed
Grade to “7” and Set Device as “EP4CE115F29C7”.
5. Set Simulation Tool to “ModelSim” and Format to “Verilog HDL”.
6. Verify all details in Summary are Acurate then click Finish.
7. Go To : File → New → “Verilog HDL File”, To create a New File.
8. Code the Apropriate Verilog Program in the File and Save It.
9. Once Done, Go To : Processing → Start Compilation, To compile the Verilog Code.
10. To Perform RTL Simulation Go To : Tools → Run Simulation Tool → RTL Simulation.
11. Perform The Necessary Simulations in ModelSim and Verify The Output.
12. Once Code Is Verified Close ModelSim, Go To : Assignments → Pin Planner.
13. Assign Necessary Input Output Pins and Recompile using Step 9.
14. To Flash The Code in the Kit, Connect the Power Supply to the Kit and Connect the
Provided USB Cable.
15. Go To : Tools → Programmer, Select USB-Blaster, and Click Start.
16. On Succesful Flashing Verify The Output

[21BLC1374] BECE406E – FPGA Based Systems Design Lab Page No. 1


[21BLC1374] Lab 4 – Four Bit Up-Down Counter 12/08/2024

Code:
module main_counter(
input Clock, Reset, UpDown, // UpDown is the switch to toggle between up
and down counter
output [6:0] HEX0, // Seven-segment display output Right
output [6:0] HEX1 // Seven-segment display output Left
);
wire Slow_Clk_Out;
wire [3:0] Count_Out;

clkdivider mut (.clk(Clock), .rst(Reset), .slowclk(Slow_Clk_Out));


four_bit_counter uut (.clk(Slow_Clk_Out), .rst(Reset), .up_down(UpDown),
.q(Count_Out));
bcd_to_7segment bcd_decoder (.bcd(Count_Out), .seg0(HEX0), .seg1(HEX1));
endmodule

module clkdivider(
input clk, rst,
output slowclk
);
reg [25:0] count;
always @(posedge clk)
begin
if(rst) count <= 0;
else count <= count + 1;
end
assign slowclk = count[25];
endmodule

module four_bit_counter(
input clk, rst, up_down,
output reg [3:0] q
);
always @(posedge clk)
begin
if(rst) q <= 4'b0000;
else if(up_down) q <= q + 4'b0001; // Up counter
else q <= q - 4'b0001; // Down counter
end
endmodule

module bcd_to_7segment (
input [3:0] bcd,
output reg [6:0] seg0,
output reg [6:0] seg1
);

// BCD to 7-segment display

[21BLC1374] BECE406E – FPGA Based Systems Design Lab Page No. 2


[21BLC1374] Lab 4 – Four Bit Up-Down Counter 12/08/2024

always @ (bcd) begin


case (bcd)
4'b0000: begin seg1 = 7'b1000000; seg0 = 7'b1000000; end //00
4'b0001: begin seg1 = 7'b1000000; seg0 = 7'b1111001; end //01
4'b0010: begin seg1 = 7'b1000000; seg0 = 7'b0100100; end //02
4'b0011: begin seg1 = 7'b1000000; seg0 = 7'b0110000; end //03
4'b0100: begin seg1 = 7'b1000000; seg0 = 7'b0011001; end //04
4'b0101: begin seg1 = 7'b1000000; seg0 = 7'b0010010; end //05
4'b0110: begin seg1 = 7'b1000000; seg0 = 7'b0000010; end //06
4'b0111: begin seg1 = 7'b1000000; seg0 = 7'b1111000; end //07
4'b1000: begin seg1 = 7'b1000000; seg0 = 7'b0000000; end //08
4'b1001: begin seg1 = 7'b1000000; seg0 = 7'b0010000; end //09
4'b1010: begin seg1 = 7'b1111001; seg0 = 7'b1000000; end //10
4'b1011: begin seg1 = 7'b1111001; seg0 = 7'b1111001; end //11
4'b1100: begin seg1 = 7'b1111001; seg0 = 7'b0100100; end //12
4'b1101: begin seg1 = 7'b1111001; seg0 = 7'b0110000; end //13
4'b1110: begin seg1 = 7'b1111001; seg0 = 7'b0011001; end //14
4'b1111: begin seg1 = 7'b1111001; seg0 = 7'b0010010; end //15
default: begin seg1 = 7'b0111111; seg0 = 7'b0111111; end //Default
endcase
end
endmodule

Hardware Implementation:
Pin Planner:

[21BLC1374] BECE406E – FPGA Based Systems Design Lab Page No. 3


[21BLC1374] Lab 4 – Four Bit Up-Down Counter 12/08/2024

Output:
Case 1: 7-Segment Showing 04

Case 2: 7-Segment Showing 07

Case 3: 7-Segment Showing 09

[21BLC1374] BECE406E – FPGA Based Systems Design Lab Page No. 4


[21BLC1374] Lab 4 – Four Bit Up-Down Counter 12/08/2024

Case 4: 7-Segment Showing 14

Inference:
We have understood how to program a 4 Bit Up-Down Counter and Linked it to a Clock
Divider to Slow Down The Transitions and Connect it to a BCD to 7-Segment Module to
display the count on the 7-Segment Display on the DE2-115 Board.

Result:
Thus, we have successfully designed a 4bit Up-Down Counter, Interfaced it with a BCD to 7-
segment display and utilized a clock divider to ensure readability of the output in both Up and
Down Modes and implemented on the DE2-115 board.

[21BLC1374] BECE406E – FPGA Based Systems Design Lab Page No. 5

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