ECE 028

Electronics Devices and Circuits

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 Course Syllabus

PEN Code ECE 028

PEN Descriptive Title Electronic Devices and Circuits
Credit Units 4 units (3 units Lecture / 1 unit Laboratory)
Pre-requisite None

I. Subject Description:

Electronic Devices and Circuits is a review on semiconductor physics and an introduction

to quantum mechanics of solid-state electronics. This course deals with the principles and
operation of semiconductor devices, e.g., diode, bipolar junction transistor (BJT), and field-
effect transistor (FET), with emphasis in diode circuit analysis and applications, transistor biasing
and small- and large - signal analyses. The course introduces the operations of relevant
electronic circuit applications including, not limited to, power supply, transistor switches, and
amplifiers.

II. Objectives:

At the end of the course, the students should be able to:

1. Familiarize and solve problems on semiconductor physics, diode and diode circuit
analysis;
2. Analyze and solve problems involving bipolar junction transistors and field -effect
transistors using small- and large- signal analysis; and
3. Analyze and present relevant diode and/or transistor circuit applications with emphasis
on their operations and working principles.

III. Course Topic, Coverage Date, Activity

ECE 028 - ELECTRONIC DEVICES AND CIRCUITS

Week Meeting Activity / Evaluation Tools Topic

Introduction to Flexible Learning and General
1 General Orientation
1 Classroom Orientation
Class Discussion, Module 1: Introduction to Electronics and
2
Seatwork Semiconductors
Independent Study,
3 Module 2: Diode Fundamentals
2 Homework
Independent Study,
4 Module 3: Diode Applications - Part 1
Homework
5 Quiz 1.1 Diode Configurations and Rectifier
3
Class Discussion,
6 Module 4: Diode Applications - Part 2
Seatwork
 Independent Study,
7 Module 5: Diode Applications - Part 3
4 Homework
Independent Study, Module 6: Power Supply and Voltage
8
Homework Regulation
Laboratory Application
9 Direct-Current (DC) Power Supply
5 and Quiz 1.2
10 P1 Examination First Periodic Examination
Independent Study, Module 7: Bipolar Junction Transistor (BJT)
11
6 Homework Fundamentals
Independent Study, Module 8: BJT Biasing and Direct-Current (DC)
12
Homework Analysis - Part 1
Class Discussion, Module 9: BJT Biasing and Direct-Current (DC)
13
7 Seatwork Analysis - Part 2
Module 10: BJT Small-Signal (AC) Analysis -
14 Laboratory and Quiz 2.1
Part 1
Independent Study, Module 11: BJT Small-Signal (AC) Analysis -
15
8 Homework Part 2
Laboratory and
16 Module 12: Multiple BJT Networks
Independent Study
17 P2 Examination Second Periodic Examination
9
Class Discussion, Module 13: Field-Effect Transistor (FET)
18
Seatwork Fundamentals
Independent Study,
19 Module 14: Metal-Oxide Semiconductor FET
10 Homework
Independent Study,
20 Module 15: FET Biasing - JFET
Homework
Class Discussion,
11 21 Module 15: FET Biasing - MOSFET
Seatwork
22 Laboratory and Quiz 3.1 JFET AND MOSFET
Independent Study,
23 Module 16: Operational Amplifiers
12 Homework
Laboratory and
24 Module 17: Integrated Circuit Families
Independent Study
25 P3 Examination Third Periodic Examination
13
26 Final Examination Comprehensive Final Examination
IV. Grading System

The Final Grade is computed as follows:

Final Grade = 0.20*P1 + 0.20*P2 + 0.20*P3 + 0.40*FE

Passing score = 50%

The Periodic Grades P1, P2, and P3 are computed as follows:

Pn = 0.60*Class standing + 0.40*Periodic Exam

Class standing = 0.60 Quizzes + 0.30 Activities/Laboratory
+ 0.10 Recitation/Assignments/Homework)

Final Exam is comprehensive in nature, thus, covers all topics. Passing score = 50%

V. Textbook and References

Recommended Textbook:
Electronic Devices and Circuit Theory, 11 th Edition by R. Boylestad & L. Nashelsky (2013)

Additional References:
1. Electronic Devices: Conventional Current Version, 9th Edition by Thomas Floyd (2012)
2. Electronic Principles, 8th Edition by Albert Malvino and David J. Bates (2016);
3. Grob’s Basic Electronics, 12th Edition by Mitchel E. Schultz, (2016).
4. Electronic Demystified, 2nd Edition by Louis Frenzel (2018)
5. Teach Yourself in Electricity and Electronics, 4th Edition by Stan Gibilisco (2006)

VI. Course Requirements

Attend the class regularly.

Must pass major examinations in each periodic grading, and the final examination.
Actively participate in all class activities.
Accomplish and submit student activity sheets.

VII. Contact Information

Name:
Contact Number:
E-mail:
Consultation:
 ECE 028: Electronic Devices and Circuits
Orientation

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Lesson Title: Materials:

Orientation Pencil and paper

Active Learning, 4-10 Approach, and Flexible Learning

Course Syllabus and Grading System References:
Psychosocial Wellness and School Directory
1. Course syllabus;
2. School’s official social media
Lesson Objectives: page and related links;
3. Distance Learning Classroom
At the end of this lesson, you should be able to: (Google Classroom)
● familiarize oneself with concept of active and flexible learning;
● familiarize oneself with the course description, content, and
components, and grading system for the subject;
● provide and complete the necessary information for the distance
learning classroom and support for psychosocial wellness.

Productivity Tip:

We do learn best by doing.

A. LESSON PREVIEW/REVIEW
1) Introduction

What is the new normal for the schools under the umbrella of the PHINMA Education during this trying times?

As a PHINMA Ed student, you will experience a flexible learning setup as the school continue delivering quality
education in this transition to a new normal. The school’s learning framework remains to be Active Learning. In
response to needs, it will be adopting a flexible learning approach, which, in its initial stage, is a combination of
face-to-face or virtual classes and home-based learning. This learning mode ensures equity among students.

In order to get you familiarize with the setup, this module gives you an overview with Active Learning and the
adopted flexible learning setup and modules. This material also directs you to become more familiar and aware
of the important details in your course syllabus, especially on the grade components, the distance learning.
classroom, and the school support for your psychosocial wellness.

Let’s dig in.

This document is the property of PHINMA EDUCATION

 ECE 028: Electronic Devices and Circuits
Orientation

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

2) Activity 1: What I Know Chart, part 1

What I Know Questions: What I Learned (Activity 4)

1. What is your definition of active
learning and flexible learning?
2. What is your role as a learner in
the conduct of distance learning
class and home study?
3. What are the course components
and the grading system being
implemented in the class?

B. MAIN LESSON
1) Activity 2: Content Notes

ACTIVE LEARNING

“I hear and I forget. I see and I remember. I do, and I understand.” (old Chinese proverb)

Our world today is now known by students as a “Knowledge Society”, where people often engage in critical
thinking, problem solving with others, using evidence in reasoning, and having complex challenges in workplaces
(Cassidy et al., 2019). Therefore, the education that students need to receive must help them develop new skills,
acquire learning dispositions, and have self-direction and initiative, in addition to the usual factual knowledge
and basic skills (Acosta and Slotta, in Cassidy et al., 2019).

What then do students need to do in order to have enhanced learning experiences? What educational
researchers and practitioners have identified as a response to this challenge is active learning.

Active learning is “involving students in doing things and

thinking about what they are doing” (Bonwell and Eison, 1991).

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 ECE 028: Electronic Devices and Circuits
Orientation

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Fink (2003) further expanded the definition by delineating a “holistic view of active learning”, which consists
of three primary components (see below). Note that reflection-based activities that support both the
learning environment and student metacognition is part of active learning. It also promotes both doing and
observing experiences, in which students are engaged in the process of learning, as opposed to passively
listening to an expert (Freeman et al., 2014). Students are called to “select, organize, and integrate
information, either independently or in groups” (Singer et al., 2012); ideas are engaged through techniques
that range from listening practices to group exercises.

With more than a thousand individual studies that provide evidence of the efficacy of active learning, it is hoped
that active learning can help students and teachers achieve good outcomes in education. After all, AL involves
skills and actions crucial to success in this day and age: “solving ill-structured problems, negotiating diverse
ideas and perspectives, engaging in inquiry and critical thinking, and developing a sense of responsibility for
one’s learning” (Acosta and Slotta, 2018).

In summary, Active Learning is a process that has you, the students, learning at its center. Active learning
focuses on how students learn, not just on what they learn. Students are encouraged to ‘think hard’, rather than
passively receive information from the teacher.

Research shows us that it is not possible to transmit understanding to students by simply telling them what they
need to know. Instead, teachers need to make sure that they challenge their students’ thinking. With active
learning, students play an important part in their own learning process. They build knowledge and understanding
in response to opportunities provided by their teacher.

4-10 APPROACH AND FLEXIBLE LEARNING

Based on WHO guidelines and studies on COVID-19, the school adopts the 4-10 Approach. This Israeli science-
based, cyclic reopening strategy is the basic model for our reopening once students are allowed on campus,
with some tweaking to suit specific environment. Within the two-week period, a total of 14 days, 4 consecutive
days are scheduled for classes, 10 days for home-based learning or study.

Shift. The student population is grouped into three (3) shifts - Shift A, Shift B, and Shift C. Each shift or group
reports to campus on a specific day of the 14 days period. The cycle is repeated every two weeks or 14 days.

IMPORTANT
SINCE THE QUARANTINE PROTOCOLS ARE STILL IN EFFECT, THE FIRST FOUR (4) CONSECUTIVE
DAYS SCHEDULED FOR FACE-TO-FACE CLASSES WILL BE ALLOTED FOR VIRTUAL SESSIONS THRU
THE SELECTED DISTANCE LEARNING CLASSROOM PLATFORM. THE REMAINING TEN (10) DAYS
WILL BE FOR HOME-BASED AND INDEPENDENT LEARNING OF STUDENTS. HOWEVER, YOUR
TEACHER WILL PROVIDE REMOTE MENTORING TO STUDENTS DURING HOME STUDY PERIOD THRU
TEXT, CALL, OR THE GROUP CHAT AND CLOSED/PRIVATE GROUP PAGE FOR THE CLASS.

FLEXIBLE LEARNING MODULES AND DISTANCE LEARNING CLASSROOM

In conjunction with the adopted 4-10 Approach, students are given a detailed syllabi or most probably a set of
flexible learning modules, commonly known as Student Activity Sheets (SASs), as the primary instructional

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 ECE 028: Electronic Devices and Circuits
Orientation

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

material. The learning framework remains to be Active Learning thus, the learning experiences in the modules
are designed for full self-study in the event that students will need or be required to stay home.

The flexible learning modules or SASs are expected to be accomplished by the students in each period.
Deadlines for accomplished SASs will be determined by your teacher. However, each module should be learned
in accordance with the timeline presented in the course syllabus.

Also, remember that any additional materials you will need in the subject will be uploaded in the identified
distance learning classroom platform. Most importantly, all classwork such as accomplished quizzes, completed
modules, paperwork, and the like, will be submitted or turned in by each student using this platform.

COURSE SYLLABUS AND GRADING SYSTEM

As a student enrolled in this course, you are provided with the course syllabus containing the details of the
subject such as the description, content and the components of the grading system. You are encouraged to refer
to this material in order to keep in track with your progress in the subject.

PSYCHOSOCIAL WELLNESS
The school got you! We’ve got you!

As part of the community, your teachers and school administrators recognize that many students are undergoing
a lot of pressure due to uncertainty brought by the current situation. From what we have learned, students
perform worse in academics due to unaddressed anxiety and mismanaged effects of stress. Remember that
such stress is only beneficial to psychosocial development if properly regulated. And so, we encourage every
student to reach out to the school, through the identified advisers, whenever facing challenges triggered by
severe stress. The school have put measures in order to address these concerns because your well -being as
students will always be one of the prime concerns. Your sense of belongingness and safety help ensure a more
productive learning experience in the class. To keep with track with the programs designed for your psychosocial
wellness, follow the official pages in social media of the school. These programs will serve its intended purpose
only if students get back on the right track.

2) Activity 3: Skill-Building Activities

Complete the following details in order verify that are well aware of them.

A. Student Information

Student Number: _________________________________

Complete Name: _________________________________
Program: _________________________________
Year Level: _________________________________

Mobile Number: _________________________________

Complete Address: _________________________________
_________________________________

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 ECE 028: Electronic Devices and Circuits
Orientation

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Name of Parent/Guardian: _________________________________

Contact Number: _________________________________

School E-mail Account: _________________________________

Personal E-mail Account: _________________________________
Social Media Account Name/Link: _________________________________

B. The 4-10 Approach and Flexible Learning Shift

As part of the COLLEGE,

Shift of your College: _________________________________
Days of Virtual Classes: _________________________________
Days of Home Study: _________________________________

For this SUBJECT,

Days of Virtual Classes: _________________________________
Days of Home Study: _________________________________

C. Information on Distance Learning Classroom

Class Group Chat Name/Link: ________________________________

Already a Member (Yes/No): ________________________________

Class Private/Closed Group Name/Link: ________________________________

Already a Member (Yes/No): ________________________________

Distance Learning Platform: ________________________________

Distance Learning Classroom Name/Link: ________________________________
Already a Member (Yes/No): ________________________________

D. Course Syllabus and Grading System

Course Code and Descriptive Title: ________________________________

Credit Units (Lecture / Laboratory): ________________________________

Course Description (brief contents):

___________________________________________________________________
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________

Course Category (Board/Non-board?): ________________________________

Passing Score: ________________________________
Periodic Grade Components: ________________________________
Period Grade Computation: ________________________________
Final Grade Computation: ________________________________
5

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 ECE 028: Electronic Devices and Circuits
Orientation

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

E. Student Activity Sheets I (SASs) for the Course

Number of Modules to be Submitted Per Period

First Period (P1): ________________________________
Second Period (P2): ________________________________
Third Period (P3): ________________________________

F. School Directory Related Links

Students must be aware of these details for concerns monitoring.
Checkout the posts of school as your reference.

Schools Official Page Link:

Telephone Number:

Office of the Registrar:

Finance Department:
Center for Student Development and Leadership:

College Community Page:

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is your definition of active
learning and flexible learning?
2. What is your role as a learner
in the conduct of distance
learning class and home study?
3. What are the course
components and the grading
system being implemented in the
class?

4) Activity 5: Check for Understanding (This is an assessment.)

Answer the following items briefly.

1. Define “active learning” in own words.

2. What is the flexible learning setup?
3. Describe the design and purpose of the learning modules.
4. Cite at least three student concerns which are common and identify the offices to reach out regarding them.
5. Briefly explain why psychosocial wellness is important.

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 ECE 028: Electronic Devices and Circuits
Orientation

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.

Period 1 Period 2 Period 3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________

Which strategy worked for you, easily? With difficulty?

________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________

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 ECE 028: Electronic Devices and Circuits
Student Activity Sheet #1

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Lesson Title: Materials:

Introduction to Electronics and Semiconductors Pencil and paper

The Electronics Industry References:

Conductor, Insulator, and Semiconductor Materials 1. Electronic Devices and Circuit
Bonding and Doping Theory, 11th Edition by R.
Intrinsic and Extrinsic Semiconductor Boylestad & L. Nashelsky (2013),
Pearson
Lesson Objectives:
2. Electronic Devices:
At the end of this lesson, you should be able to: Conventional Current Version, 9th
● describe electronics and its entire scope; Edition by Thomas Floyd (2012),
● discuss conductors, insulators, and semiconductors Prentice Hall
and how they differ;
● describe how current is produced in semiconductors. 3. Electronic Demystified, 2nd
Edition by Louis Frenzel (2018)

Productivity Tip: Congratulations for taking the first step in the world of electronics.
Be encouraged to think about how electronics impacts your life!

A. LESSON PREVIEW/REVIEW
1) Introduction

How lucky you are. You live in high-tech heaven surrounded by lots of useful, entertaining, interesting, necessary,
and even addicting electronic products, products you cling to and would not want to give up. Despite the
complexity of today’s electronic products, there is something just fascinating about them. Many of you actually
want to know how they work. And despite their complexity, these products are actually understandable. It is
possible to learn how these devices work without a whole lot of trouble. This module takes the basic ideas of
electronics and reduces them down to the lowest common denominator and shows you how to use those
fundamentals and apply them to all of the fabulous electronic gadgets you have today.

2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)

1. What is the scope of the
electronics industry?
2. What is the structure of an
atom?
3. How are conductors,
insulators, and
semiconductors differ?
1

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 ECE 028: Electronic Devices and Circuits
Student Activity Sheet #1

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

B.MAIN LESSON
1) Activity 2: Content Notes
For maximum retention, you are required to highlight important terms or phrases, and take notes.

Electronics Industry: The Big Picture

Recent figures seem to show that electronics is one of the biggest, if not the biggest, markets in the entire world.
To get a grasp of how big the industry is, we normally break it down into segments of specializations. Any
electronic product or device will easily fall into one of those categories. In some cases, the product may overlap
two or more or all of those categories. There are five major fields of electronics:

[for note-taking]

Communications - both wired and wireless in forms, it is the oldest segment of electronics and still the
largest. Electronics actually started with communications and grew from there.

Computer (embedded controller) - these are small single-chip digital computers called microcomputers
or microcontrollers or just micros that are literally part of every electronic product. These are miniature
digital computers dedicated to a specific function inside the products in which they exist.

Control - a broad general term for monitoring and control. Monitoring, of course, means sensing various
physical characteristics such as temperature, humidity, physical position, motor shaft speed, or light level.
Control refers to managing and exercising some degree of influence over items such as motors, lights,
relays, heating elements, and other devices.

Instrumentation - refers to the field involved with testing and measuring electronic equipment and other
mechanical or electronic items. Instrumentation refers to test instruments, large automated test systems,
data acquisition systems, medical tests and measurements, and a wide range of other products.

Components - in the past, these refers to individual discrete components such as resistors, capacitors,
diodes, and transistors. Today most electronic equipment is made with one or more integrated circuits or
ICs surrounded by a sprinkling of those other so-called discrete components.

As part of the big picture of learning electronics, you really need to understand how the industry itself works. This
is summed up by the block diagram in Figure 1.0.

Figure 1.0 General block diagram of how the electronics industry works from raw materials to end users.
2

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 ECE 028: Electronic Devices and Circuits
Student Activity Sheet #1

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Materials Used in Electronics

Component manufacturers are centered on making electronic devices or components that are in turn made
available to the manufacturers of the end electronic equipment. Electronic devices such as diodes, transistors,
and integrated circuits are made of a semiconductive material.

Great! To understand how these devices work, you should have a basic knowledge of the structure of atoms and
the interaction of atomic particles.

An atom is the smallest particle of an element that retains the characteristics of that element.

Each element has atoms that are different from the atoms of all other
elements. This gives each element a unique atomic structure. According to
the classical Bohr model, atoms have a planetary type of structure that
consists of a central nucleus surrounded by orbiting electrons. The nucleus
consists of positively charged particles called protons and uncharged
particles called neutrons. The basic particles of negative charge are called
electrons. Refer to Figure 1.1 for the Bohr model of an atom.

Electrons with the highest energy exist in the outer- most shell of an atom
and are relatively loosely bound to the atom. This outermost shell is known
as the valence shell and electrons in this shell are called valence
electrons. For purposes of discussing electrical properties, an atom can be
represented by the valence shell and a core that consists of all the inner
shells and the nucleus, as shown in Figure 1.2.
Figure 1.1 Bohr Model of an Atom

All elements are arranged in the periodic table of the elements in order according to their atomic number. The
atomic number equals the number of protons in the nucleus, which is the same as the number of electrons in
an electrically balanced (neutral) atom.

Atomic Number, Z = Np = Ne … Equation 1.0 Atomic Number

where: Np = no. of protons & Ne = no. of electrons
Also,
Atomic Weight = Total No. of Nucleon Particles … Equation 1.1 Atomic Weight
where: protons and neutrons are known collectively as nucleons.

Fig. 1.2 The Silicon (Si) Atom

(Z = 14, W = 28, Core = +4)

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 ECE 028: Electronic Devices and Circuits
Student Activity Sheet #1

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Energy Levels and Shells. Each discrete distance (orbit) from

the nucleus corresponds to a certain energy level (see Figure
1.3). In an atom, the orbits are grouped into energy levels
known as shells. A given atom has a fixed number of shells.

Each shell has a fixed maximum number of electrons (refer

to Equation 1.2). The shells (energy levels) are designated 1,
2, 3, and so on, with 1 being closest to the nucleus.

Ne = 2n^2 … Equation 1.2 Maximum No. of Electrons

per Shell

where: Ne = maximum number of electrons in a shell Figure 1.3 Discrete energy levels
n = shell number, e.g. 1, 2, 3, …

Ionization. If a valence electron acquires a sufficient amount of energy, called ionization energy, it can actually
escape from the outer shell and the atom’s influence. The process of losing a valence electron is known as
ionization, and the resulting positively charged atom is called a positive ion. The escaped valence electron is
called a free electron.

[for note-taking]

Insulators, Conductors, and Semiconductors

Insulator Conductor Semiconductor
- a material that does not conduct - a material that easily conducts - a material that is between
electrical current under normal electrical current. conductors and insulators in its
conditions. ability to conduct electrical current.

- are compounds rather than - most metals are good - can be single-element or
single-element materials and have conductors. The best conductors compound; acts an an insulator
very high resistivities. are single-element materials. at room temperature.

- valence electrons are tightly - characterized by atoms with only - characterized by atoms with four
bound to the atoms; therefore, one valence electron very loosely valence electrons.
there are very few free electrons bound to the atom.

Examples: rubber, plastics, glass, Examples: copper (Cu), silver (Ag), Examples: antimony (Sb), arsenic
mica, and quartz. gold (Au), and aluminum (Al), (As), astatine (At), boron (B),
polonium (Po), tellurium (Te),
silicon (Si), and germanium (Ge),
gallium arsenide, indium
phosphide, gallium nitride, silicon
carbide, and silicon germanium

Table 1.0 Differences of Insulators, Conductors, and Semiconductors

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 ECE 028: Electronic Devices and Circuits
Student Activity Sheet #1

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Conduction and Valence Bands

Figure 1.4 reveals that

there is a minimum
energy level associated
with electrons in the
conduction band and a
maximum energy level
of electrons bound to
the valence shell of the
atom. Between the two
is an energy gap that
the electron in the
valence band must
overcome to become a
free carrier.

Figure 1.4 Conduction and valence bands of Insulator, Semiconductor, and Conductor

Covalent Bonding,
p-Type and n-Type Materials

As shown in Figures 1.5 and 1.6, the

bonding of atoms, strengthened by the
sharing of electrons, is called covalent
bonding. The term intrinsic is applied
to any semiconductor material that has
been carefully refined to reduce the
number of impurities to a very low
level—essentially as pure as can be
made available through modern
technology. The free electrons in a
material due only to external causes are
referred to as intrinsic carriers. Fig. 1.5 Silicon Crystal Figure 1.6 GaAs Crystal

Figure 1.7
Doping Silicon with
Antimony
(pentavalent)
Figure 1.8
Doping Silicon with
Boron (trivalent)

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 ECE 028: Electronic Devices and Circuits
Student Activity Sheet #1

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Doping. A semiconductor material that has

been subjected to the doping process is
called an extrinsic material. There are two
extrinsic materials of immeasureable
importance to semiconductor device
fabrication: n-type and p-type materials. A
pentavalent dopant (Figure 1.7) will result to
an n-type material (Figure 1.9a) while a
trivalent dopant (Figure 1.8) will produce a
p-type material (Figure 1.9b). Figure 1.9 (a) n-type and (b) p-type materials

Now that you know how semiconductive materials are formed, you now ready to learn how conduction happens
in these materials. It’s pretty simple. Just follow the arrows.

Electron and Hole Flow

When an electron jumps to the conduction band, a vacancy is left in the valence band within the crys tal. This
vacancy is called a hole. For every electron raised to the conduction band by external energy, there is one hole
left in the valence band, creating what is called an electron-hole pair. Recombination occurs when a
conduction-band electron loses energy and falls back into a hole in the valence band.

Figure 1.10 Hole and Electron Flows in Semiconductor

Notice the effect of the hole on conduction as shown in Figure 1.10. If a valence electron acquires sufficient
kinetic energy to break its covalent bond and fills the void created by a hole, then a vacancy, or hole, will be
created in the covalent bond that released the electron. There is, therefore, a transfer of holes to the left and
electrons to the right, as shown. The direction of hole flow is also known as conventional flow. Of course, the
actual flow of negative charges is known as electron flow.

Activity 3: Skill-building Activities (Answers in Key to Corrections)

a. Categorize the following electronics products and technologies according to which segment they belong.
(15 pts)

Communications Computer Control Instrumentation Components

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 ECE 028: Electronic Devices and Circuits
Student Activity Sheet #1

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Appliances Diodes Peripheral equipment Transistors

Automotive Embedded Robots Wireless systems
Aircraft diagnosis Integrated Circuits Satellites Workstations
Cable Medical Security

b. If the atomic number of a neutral atom is 6, how many electrons and protons do the atom have?
c. What is the maximum number of electrons that can exist in the 3rd shell of an atom?
d. In a silicon crystal, how many covalent bonds does a single atom form?
e. Draw the Bohr model of a Silicon (atomic number 14) and Germanium (atomic number 32) atoms. How
many valence electrons are there for each?
f. Identify the charge of the core of a Copper atom.

2) Activity 4: What I Know Chart, part 2 (2 mins)

What I Know Questions: What I Learned (Activity 4)

1. What is the scope of the
electronics industry?
2. What is the structure of an
atom?
3. How are conductors, insulators,
and semiconductors differ?

3) Activity 5: Check for Understanding (5 mins). This a short summative assessment.

True or False: Write the TRUE if the statement is correct. Otherwise, FALSE. (5 pts)

_______ 1. An atom is the smallest particle in an element.

_______ 2. An atom is made up of electrons, protons, and neutrons.
_______ 3. Valence electrons exist in the outer shell of an atom.
_______ 4. Crystals are formed by the bonding of atoms.
_______ 5. Silicon is a conductive material.

Multiple Choice: Encircle the letter of the best answer. (15 pts)
1. Every known element has
(a) the same type of atoms (c) the same number of atoms
(b) a unique type of atom (d) several different types of atoms

2. An atom consists of
(a) one nucleus and only one electron (c) one nucleus and one or more electrons
(b) protons, electrons, and neutrons (d) answers (b) and (c)

3. The nucleus of an atom is made up of

(a) protons and neutrons (c) electrons
(b) electrons and protons (d) electrons and neutrons

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4. Valence electrons are

(a) in the closest orbit to the nucleus (c) in the most distant orbit from the nucleus
(b) in various orbits around the nucleus (d) not associated with a particular atom

5. A positive ion is formed when

(a) a valence electron breaks away from the atom
(b) there are more holes than electrons in the outer orbit
(c) two atoms bond together
(d) an atom gains an extra valence electron

6. The most widely used semiconductive material in electronic devices is

(a) germanium (c) carbon
(b) copper (d) silicon

7. The difference between an insulator and a semiconductor is

(a) a wider energy gap between the valence band and the conduction band
(b) the number of free electrons
(c) the atomic structure
(d) answers (a), (b), and (c)

8. The energy band in which free electrons exist.

(a) first band (c) second band
(b) conduction band (d) valence band

9. Recombination is when
(a) an electron falls into a hole
(b) a positive and a negative ion bond together
(c) a valence electron becomes a conduction electron
(d) a crystal is formed

10. In an intrinsic semiconductor,

(a) there are no free electrons
(b) the free electrons are thermally produced
(c) there are as many electrons as there are holes
(d) answers (b) and (c)

11. The process of adding an impurity to an intrinsic semiconductor

(a) doping (c) recombination
(b) atomic modification (d) ionization

12. A trivalent impurity is added to silicon to create

(a) germanium (c) a p-type semiconductor
(b) an n-type semiconductor (d) a depletion region

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13. The purpose of a pentavalent impurity is to

(a) reduce the conductivity of silicon (c) increase the number of holes
(b) increase the number of free electrons (d) create minority carriers

14. The majority carriers in an n-type semiconductor are

(a) holes (c) valence electrons
(b) conduction electrons (d) protons

15. Holes in an n-type semiconductor are

(a) minority carriers that are thermally produced
(b) minority carriers that are produced by doping
(c) majority carriers that are thermally produced
(d) majority carriers that are produced by doping

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

What portion/s of the lesson you found easy? Difficult?

FAQs

1. What is the difference between electricity and electronics?

Answer: Electricity refers to the basic energy we use for power. It generally involves the generation and
distribution of electrical energy to homes, businesses, and factories. Electricity is energy that is produced by the
coal-fired or nuclear power plant and then sent to you over long transmission lines until it comes into your house
where you access it through your AC wall outlets. You use that energy for lighting and appliances and also to
power most of your electronic equipment. All of the principles of electricity also apply to electronics. Basic
electrical components such as resistors, capacitors, inductors, transformers, motors, and other similar devices
are also used in electronics. Electronics is the field of science that uses electrical principles to perform other
useful functions. Electronics is the control of electricity to produce radio, television, computers, robots, and MRI
machines.

2. What devices are being used to control electricity in electronics?

Answer: To control the electricity, you need more than just basic electrical components such as resistors and
capacitors. What makes electronics possible are the unique components called transistors (which are made up
of diodes). Electronics began, of course, with vacuum tubes and then switched over to transistors as the main
control devices.

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3. What is an IC, a popular word in electronics?

Answer: Transistors are now miniaturized and packaged in devices called integrated circuits that perform very
specific electronic functions, such as generating signals, amplifying signals, or performing some control function.

KEY TO CORRECTIONS
*Activity 3
a.

Communications Computer Control Instrumentation Components

Cable Workstations Automotive Medical Integrated circuits
Satellites Embedded Security Robots Diodes
Wireless systems Peripheral equipment Appliances Aircraft diagnosis Transistors

b. 6 electrons, 6 protons
c. Ne = 2n^2 = 2(3)^2 = 18 electrons
d. 4 covalent bonds, each of the four valence electrons will produce a pair

e. Bohr model of the Silicon (Z = 14) and Germanium (Z = 32) atoms; both are tetravalent (4 valence electrons)

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Lesson Title: Materials:

Diode Fundamentals Pencil and paper

The pn-Junction References:

Diode Construction, Operation, and Biasing 1. Electronic Devices and Circuit
The Diode Characteristic Curve Theory, 11th Edition by R.
Diode Equivalent Circuits Boylestad & L. Nashelsky (2013),
Pearson;
Lesson Objectives:
At the end of this lesson, you should be able to: 2. Electronic Devices:
● develop a clear understanding of the basic operation and Conventional Current Version, 9th
characteristics of a diode in the no-bias, forward-bias, and reverse- Edition by Thomas Floyd (2012),
bias regions; Prentice Hall;
● understand the impact of an equivalent circuit whether it is ideal or
practical. 3. Electronic Demystified, 2nd
Edition by Louis Frenzel (2018)

Productivity Tip: Keep your mind wide open and wonder! Gnaw and digest the fundamentals
and always get back to basics whenever you need to find your way back.

A. LESSON PREVIEW/REVIEW
1) Introduction

An amazing and one of the noteworthy things about electronics, as in many other areas of technology, is how
little the fundamental principles change over time. Systems are incredibly smaller, current speeds of operation
are truly remarkably faster, and new gadgets surface every day, leaving us to wonder where technology is taking
us.

You do not have to be a physicist, or mathematical genius to learn electronics. Just to make you more
comfortable, I have to say that it is not all that complicated or difficult to understand. There are a few basic things
that you need to know so you can understand what is going on in the circuits and equipment. With such
background you are ready to learn about the various components and circuits.

In the previous module, you learned that semiconductor devices are based on p- and n-type materials, produced
through the doping process. The first device to be introduced through this session is the simplest of all electronic
devices, yet has a range of applications that seems endless. You will learn the operation and characteristics of
the diode. Also, three diode models representing three levels of approximation are presented and testing is
discussed. The importance of the diode in electronic circuits cannot be overemphasized. Its ability to conduct
current in one direction while blocking current in the other direction is essential to the operation of many types of
circuits.

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2) Activity 1: What I Know Chart, part 1

What I Know Questions: What I Learned (Activity 4)

1. What happens when p- and n-
type materials are fused together?
2. What is a semiconductor diode?

3. How can a diode control the flow

of current in a circuit?

B. MAIN LESSON
1) Activity 2: Content Notes
For maximum retention, you are required to highlight important terms ang phrases in the discussion.

The pn-Junction
You must always remember that the n- and p-type materials represent the basic building blocks of semiconductor
devices. What happens when these materials are joined is shown in Figure 2.0.

Figure 2.0 Formation of the depletion region (its width is exaggerated for illustration purposes)

Depletion Region. The term depletion refers to the fact that the region near the pn-junction is depleted of
charge carriers (electrons and holes) due to diffusion across the junction. Keep in mind that the depletion region
is formed very quickly and is very thin compared to the n region and p region. It also acts as a barrier to the
further movement of electrons across the junction.

Barrier Potential or Knee Voltage (Vk). The potential difference of the electric field across the depletion region
is the amount of voltage required to move electrons through the electric field. This potential difference is called
2

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the barrier potential and is expressed in volts. Stated another way, a certain amount of voltage equal to the
barrier potential and with the proper polarity must be applied across a pn-junction before electrons will begin to
flow across the junction.

Diode Construction. We can construct our first solid-state electronic device: The semiconductor diode is
created by simply joining an n-type and a p-type material together, nothing more, just the joining of one material
with a majority carrier of electrons to one with a majority carrier of holes. The basic simplicity of its construction,
as shown In Figure 2.1a, simply reinforces the importance of the development of this solid-state era.

Figure 2.1 The Semiconductor Diode: Basic Structure and Symbol

Diode Operation and Biasing. If leads are connected to the ends of each material, a two-terminal device result
- the diode. Three options then become available: no bias, forward bias, and reverse bias. The term bias
refers to the application of an external voltage across the two terminals of the device to extract a response.

a. NO BIAS (VD = 0). In no-bias situation, there is no external voltage applied. It is simply a diode
with two leads sitting isolated on a laboratory bench. The absence of a voltage across a resistor
results in zero current through it. Refer to Figure 2.2

Figure 2.2 A p-n junction with no external bias:

(a) an internal distribution of charge; (b) a diode symbol, with the defined polarity and the current direction;
(c) demonstration that the net carrier flow is zero at the external terminal of the device when VD = 0 V.

b. REVERSE BIAS (VD < 0). If an external potential of V volts is applied across the p-n junction
such that the positive terminal is connected to the n-type material and the negative terminal is
connected to the p-type material the number of uncovered positive ions in the depletion region of
the n-type material will increase due to the large number of free electrons drawn to the positive
potential of the applied voltage. For similar reasons, the number of uncovered negative ions will
increase in the p-type material. The net effect, therefore, is a widening of the depletion region.
3

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This widening of the depletion region (Figure 2.3a), will establish a barrier, too great, for
the majority carriers to overcome, effectively reducing the majority carrier flow to zero. The
current that exists under reverse-bias conditions, with direction shown in Figure 2.3b with
reference to the conventional flow, is called the reverse saturation current (IS).

Figure 2.3 Reverse-biased p-n junction: (a) internal distribution of charge under reverse-bias conditions;
(b) reverse-bias polarity and direction of reverse saturation current.

c. FORWARD BIAS (V D > 0). A forward-bias or “on” condition is established by applying the positive
potential to the p-type material and the negative potential to the n-type material. The application of a
forward-bias potential VD will “pressure” electrons in the n-type material and holes in the p-type material
to recombine with the ions near the boundary and reduce the width of the depletion region. The reduction
in the width of the depletion region (Figure 2.4a) has resulted in a heavy majority flow across the junction.

Figure 2.4 Forward-biased p-n junction: (a) internal distribution of charge under forward-bias conditions;
(b) forward-bias polarity and direction of resulting current.

[for note-taking]
Diode Current, ID. It can be demonstrated through the use of solid-state physics that the general characteristics
of a semiconductor diode can be defined by the following equation for the forward- and reverse-bias regions:

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ID = IS * [e^(VD/nVT) - 1] Ampere … Equation 2.0 Shockley’s Equation

where: IS is the reverse saturation current

VD is the applied forward-bias voltage across the diode
n is an ideality factor, which is a function of the operating conditions and physical construction;
it has a range between 1 and 2 depending on a wide variety of factors (n = 1 is assumed)
Also,
VT = k*TK / q Volt … Equation 2.1 Thermal Voltage

where: k is Boltzmann’s constant = 1.38 x 10^-23 J/K

TK is the absolute temperature in kelvins = 273 + the temperature in °C
q is the magnitude of electronic charge = 1.6 x 10^-19 C

You must always remember that the defined direction of conventional current for the positive voltage
region matches the arrowhead in the diode symbol.

The Diode Characteristic Curve

When a forward-bias voltage is applied across a diode, there

is current in the diode known as forward current (IF). Also,

IF = ID = IS * [e^(VD/nVT) - 1].

For positive values of VD the first term of the above equation

will grow very quickly and totally overpower the effect of the
second term. The result is the following equation, which only
has positive values and takes on the exponential format ex.

IF = ID = IS * [e^(VD/nVT)], VD is positive

Clearly, therefore, you will see that as the value of x (diode or

forward voltage) increases, the curve becomes almost vertical,
an important conclusion to keep in mind when we examine the
change in current with increasing values of applied voltage.
Figure 2.5 Diode Characteristic Curve

For negative values of VD the exponential term drops very quickly below the level of I, and the resulting
equation for ID is simply
ID = -Is, VD is negative
At V = 0V,
ID = Is (e^0 -1) = Is(1-1) = 0 mA

Figure 2.5 clearly shows that a diode will have this plot of its characteristic curve, showing the relationship of
voltage and current (V-I) in both forward and reverse bias operations. In general, the knee voltage, V k, for
germanium and silicon diodes are 0.3V and 0.7V, respectively. Silicon is much preferred in diode
construction due to its temperature stability.
5

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Breakdown Region. In the reverse region, there is a point

where the application of too negative a voltage with the
reverse polarity will result in a sharp change in the
characteristics (refer to Figure 2.6). The current increases
at a very rapid rate in a direction opposite to that of the
positive voltage region. The reverse-bias potential that
results in this dramatic change in characteristics is called
the breakdown potential, VBV.

As the voltage across the diode increases in the reverse-

bias region, the velocity of the minority carriers responsible
for the reverse saturation current Is will also increase.
Eventually, their velocity and associated kinetic energy will
be sufficient to release additional carriers through collisions
with otherwise stable atomic structures. That is, an
ionization process will result whereby valence electrons
absorb sufficient energy to leave the parent atom. These
additional carriers can then aid the ionization process to the
point where a high avalanche current is established and the
avalanche breakdown region determined. Figure 2.6 Breakdown Region

The avalanche region (V BV) can be brought closer to the vertical axis by increasing the doping levels in the p-
and n-type materials. However, as VBV decreases to very low levels, another mechanism, called Zener
breakdown, will contribute to the sharp change in the characteristic. It occurs because there is a strong
electric field in the region of the junction that can disrupt the bonding forces within the atom and
“generate” carriers. Although the Zener breakdown mechanism is a significant contributor only at lower levels
of VBV, this sharp change in the characteristic at any level is called the Zener region, and diodes employing
this unique portion of the characteristic of a p-n junction are called Zener diodes.

The maximum reverse-bias potential that can be applied before entering the break-down region is called the
peak inverse voltage (PIV rating) or the peak reverse voltage (PRV rating).

The Ideal Diode

The semiconductor diode behaves in a manner similar to a
mechanical switch in that it can control whether current will flow
between its two terminals. However, it is important to also be aware
that: The semiconductor diode is different from a mechanical switch
in the sense that when the switch is closed it will only permit current
to flow in one direction. Ideally, if the semiconductor diode is to behave
like a closed switch in the forward-bias region (Figure 2.7a), the
resistance of the diode should be 0W. In the reverse-bias region its
resistance should be ¥W to represent the open-circuit equivalent
(Figure 2.7b).
Figure 2.7 Ideal Semiconductor Diode:
(a) forward-biased, (b) reverse-biased

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Resistance Levels. As provided in Table 2.0. you must always remember that certain amount of resistance in
a diode will be present. Its level is defined special characteristics.

Table 2.0 Summary of Diode Resistance Levels

DC or Static Resistance, RD. The application of a dc voltage to a circuit containing a semiconductor diode will
result in an operating point on the characteristic curve that will not change with time. The dc resistance levels at
the knee and below will be greater than the resistance levels obtained for the vertical rise section of the
characteristics. The resistance levels in the reverse-bias region will naturally be quite high. In general, therefore,
the higher the current through a diode, the lower is the dc resistance level.

With no applied varying signal, the point of operation would be the Q-point, determined by the applied dc levels.
The designation Q-point is derived from the word quiescent, which means “still or unvarying.”

AC or Dynamic Resistance, r d. A straight line drawn tangent to the curve through the Q-point will define a
particular change in voltage and current that can be used to determine the ac or dynamic resistance for this
region of the diode characteristics. An effort should be made to keep the change in voltage and current as small
as possible and equidistant to either side of the Q-point.

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Average AC Resistance, rav. If the input signal is sufficiently large to produce a broad swing such as indicated
in Fig. 1.28, the resistance associated with the device for this region is called the average ac resistance. The
average ac resistance is, by definition, the resistance determined by a straight line drawn between the
two intersections established by the maximum and minimum values of input voltage.

Table 2.1 Diode Equivalent Circuits (Models)

The simplified equivalent model will be employed most frequently in the analysis of electronic systems,
whereas the ideal diode is frequently applied in the analysis of power supply systems where larger voltages are
encountered.

2) Activity 3: Skill-building Activities (Answers in Key to Corrections)

a. Determine whether the following conditions fall under NO BIAS, REVERSE BIAS, or FORWARD BIAS.
____________ a.1 The condition that allows current through the pn junction.
____________ a.2 A reduction in positive and negative causes the depletion region to narrow.
____________ a.3 The free electrons are provided with enough energy from the bias-voltage source to
overcome the barrier potential and effectively “climb the energy hill” and cross the depletion region.
____________ a.4 The positive side of bias voltage is connected to the n region of the diode and the negative
side is connected to the p region.
____________ a.5 The depletion region is much wider than in equilibrium.

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b. Identification: Provide the best term or phrase being described in each item.
__________________ b.1 The region in a diode of uncovered positive and negative ions depleted of free
carriers.
__________________ b.2 In this extrinsic material, the hole is the majority carrier and the electron is the
minority carrier.
__________________ b.3 This extrinsic material is created by introducing impurity elements that have five
valence electrons ( pentavalent).
__________________ b.4 It is a semiconductor material that has been subjected to the doping process.
__________________ b.5 The characteristics of a semiconductor material can be altered significantly by the
addition of specific impurity atoms to the relatively pure semiconductor material known as?

c. True or False: Write TRUE if the statement is correct. Otherwise, write FALSE.
__________________ c.1 Ideally, there is current through a diode only when it is forward-biased.
__________________ c.2 If the bias voltage equals or exceeds the breakdown voltage in a reverse-biased
diode, avalanche occurs.
__________________ c.3 Reverse breakdown should be avoided in all diodes.
__________________ c.4 Though negligible, there is a very small current in reverse bias due to the thermally
generated minority carriers.
__________________ c.5 The practical model represents the diode as a switch in series with the barrier
potential.

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What happens when p- and n-
type materials are fused together?
2. What is a diode?

3. How can a diode control the flow

of current in a circuit?

4) Activity 5: Check for Understanding (5 mins)

For items (a), (b), and (c), show the complete solution. Box final answers.
a. Determine the dc resistance levels for the diode of figure 5a at (9 pts)
a.1 ID = 2 mA a.2 ID = 20 mA a.3 VD = 10 V at reverse bias

b. Determine the ac or dynamic resistance using figure 5b (3 pts)

b.1 at ID = 2 mA (Note: At ID = 4 mA, VD = 0.76 V, and at ID = 0 mA, ID = 0.65 V)
b.2 at ID = 25 mA (Note: At ID = 30 mA, ID = 0.8 V, and at ID = 20 mA, ID = 0.78 V)

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Figure 5a Figure 5b Figure 5c

c. Calculate the resulting average AC resistance for the changes in ID and VD in Figure 5c. (3 pts)

d. Job-Interview Questions. Briefly answer the following questions in 2-3 sentences. (15 pts)
d.1 How is the electric field across the pn-junction created?
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________

d.2 Because of its barrier potential, can a diode be used as a voltage source? Explain.
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________

d.3 Compare the depletion regions in forward bias and reverse bias.
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________
________________________________________________________________________________________

10

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C. LESSON WRAP-UP

1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

Which strategy worked for you, easily? With difficulty?

FAQs

1. What is the effect of the barrier potential in a forward-biased diode?

When forward bias is applied, the free electrons are provided with enough energy from the bias-voltage source
to overcome the barrier potential and effectively “climb the energy hill” and cross the depletion region. The energy
that the electrons require in order to pass through the depletion region is equal to the barrier potential. In other
words, the electrons give up an amount of energy equivalent to the barrier potential when they cross the depletion
region. This energy loss results in a voltage drop across the pn-junction equal to the barrier potential.

2. How do changes in temperature affect a forward- and reverse-biased diode?

For a forward-biased diode, as temperature is increased, the forward current increases for a given value of
forward voltage. Also, for a given value of for- ward current, the forward voltage decreases. The barrier potential
decreases by 2 mV for each degree increase in temperature. For a reverse-biased diode, as temperature is
increased, the reverse current increases. Keep in mind that the reverse current below breakdown remains
extremely small and can usually be neglected.

KEY TO CORRECTIONS

*Activity 3
a.1 forward bias a.2 forward bias a.3 forward bias a.4 reverse bias a.5 reverse bias
b.1 depletion region b.2 p-type b.3 n-type b.4 extrinsic material b.5 doping
c.1 FALSE c.2 TRUE c.3 FALSE c.4 TRUE c.5 TRUE

**Activity 5
For this summative assessment, answers will be provided by your teacher.

11

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Lesson Title: Materials:

Diode Applications Pencil, paper, and calculator

Load-line Analysis References:

Series, Parallel, and Series-Parallel Diodes 1. Electronic Devices and Circuit
Half-wave Rectifier Theory, 11th Edition by R.
Boylestad & L. Nashelsky (2013),
Lesson Objectives: Pearson;

At the end of this lesson, you should be able to: 2. Electronic Devices:
Conventional Current Version, 9th
● describe the concept of load-line analysis and how it is applied in Edition by Thomas Floyd (2012),
diode networks; Prentice Hall;
● analyze series, parallel, and series-parallel diode networks by
using equivalent diode circuits; 3. Electronic Principles, 8th Edition
● describe the process of rectification to establish a dc level from a by Albert Malvino and David J.
sinusoidal ac input. Bates (2016);

4. Grob’s Basic Electronics, 12th

Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: All great minds were students once. Begin your journey with the end in mind.

A. LESSON PREVIEW/REVIEW
1) Introduction

In the previous module, you have learned that semiconductor is a material that is neither a good conductor nor
a good insulator. In their purest form, semiconductors have few applications in electronics. However, when the
characteristics of a pure semiconductor are altered through a process known as doping, many useful electronic
devices can be developed. The most basic semiconductor device is the diode, a device that allows current to
pass through it in only one direction. This characteristic of a diode has many useful applications in electronics.
One of the most useful applications is converting an AC voltage into a DC voltage. When used for this purpose,
diodes are typically referred to as rectifier diodes.

In this lesson, you will apply the concept on how a diode can be turned on or off by applying the proper polarity
of voltage across the diode terminals. You will also be introduced to half-wave and full-wave rectifiers which
use diodes to convert an alternating-current (AC) voltage into a direct-current (DC) voltage. At the end of this
module, the fundamental behavior pattern of diodes in dc and ac networks should be clearly understood. The
discussion demonstrates an interesting and very useful aspect of the study of a field such as electronic devices
and systems: Once the basic behavior of a device is understood, its function and response in an infinite
variety of configurations can be examined.
1

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In other words, now that we have a basic knowledge of the characteristics of a diode along with its response to
applied voltages and currents, we can use this knowledge to examine a wide variety of networks. There is no
need to reexamine the response of the device for each application. In general: The analysis of electronic
circuits can follow one of two paths: using the actual characteristics or applying an approximate model
for the device.

2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)
1. What is the most basic
function of diode in a circuit?
2. Which diode equivalent
circuit model is widely used in
the analysis of diode circuits?
3. How can an alternating-
current voltage (ACV) be
converted to a usable direct-
current voltage (DCV)?

B. MAIN LESSON
1) Activity 2: Content Notes (13 mins)

LOAD-LINE ANALYSIS
The circuit of Fig. 3.1 is the simplest of diode configurations. It will be used to describe the analysis of a diode
circuit using its actual characteristics. In Fig. 3.2, the diode characteristics are placed on the same set of axes
as a straight line defined by the parameters of the network. The straight line is called a load line because the
intersection on the vertical axis is defined by the applied load R. The analysis to follow is therefore called load-
line analysis. The intersection of the two curves will define the solution for the network and define the current
and voltage levels for the network.

Figure 3.1 Figure 3.2

Series diode configuration: Drawing the load line and
(a) circuit; (b) characteristics. finding the point of operation.

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The point of operation is usually called the quiescent point (abbreviated “Q- point”) to reflect its “still,
unmoving” qualities as defined by a dc network.
The intersections of the load line on the characteristics of Fig. 3.2 can be determined by first applying Kirchhoff’s
voltage law in the clockwise direction, which results in

+E - VD - VR = 0
E = VD + VR
E = VD + IDR Eq. 3.1 Value of E in the load-line

The intersections of the load line on the characteristics can easily be determined if one simply employs the fact
that anywhere on the horizontal axis ID = 0 A and anywhere on the vertical axis VD = 0 V.

E = VD + IDR
E = 0 + I DR
E = I DR
ID = E / R (when VD = 0 V) Eq. 3.2 Value of ID in the load-line

E = VD + IDR
= VD + (0)R
VD = E (when ID = 0 A) Eq. 3.3 Value of VD in the load-line

A straight line drawn between the two points (ID and VD) will define the load line as depicted in Fig. 3.2. Change
the level of R (the load) and the intersection on the vertical axis will change. The result will be a change in the
slope of the load line and a different point of intersection between the load line and the device characteristics.
We now have a load line defined by the network and a characteristic curve defined by the device. The point of
intersection between the two is the point of operation for this circuit. By simply drawing a line down to the
horizontal axis, we can determine the diode voltage VDQ, whereas a horizontal line from the point of intersection
to the vertical axis will provide the level of IDQ. Remember: the load line is determined solely by the applied
network, whereas the characteristics are defined by the chosen device.

SERIES DIODE CONFIGURATIONS

For all the analysis to follow in this module it is assumed that: The forward resistance of the diode is usually so
small compared to the other series elements of the network that it can be ignored. This is a valid approximation
for the vast majority of applications that employ diodes. Using this fact will result in the approximate equivalents
for a silicon diode and an ideal diode that appear in Figure 3.3.

Figure 3.3 Approximate and Ideal Semiconductor Diode Models

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Remember: In general, a diode is in the “on” state if the current established by the applied sources is such that
its direction matches that of the arrow in the diode symbol, and VD = 0.7 V for silicon, VD = 0.3 V for germanium,
and VD = 1.2 V for gallium arsenide.

Figure 3.4 Series diode configuration (forward-biased) and its approximate model.
The state of the diode in Fig. 3.4 is first determined by mentally replacing the diode with a resistive element as
shown. The resulting direction of I is a match with the arrow in the diode symbol, and since E > VK (diode’s knee
voltage, VK = VD), the diode is in the “on” state. The network is then redrawn with the appropriate equivalent
model for the forward-biased silicon diode. Applying Kirchhoff’s Voltage Law (KVL),

VR = E - VK
IR = E - Vk (where I = ID = IR)
ID = IR = VR/R

Figure 3.5 Series diode configuration (reverse-biased) and its approximate model.
The diode in Fig. 3.5 is in the “off” state, resulting in the equivalent open circuit, where the diode current is 0 A
and the voltage across the resistor R is the following: VR = IRR = IDR = (0A)R = 0 V.

In particular, the high voltage across the diode even though it is an “off” state. The current is zero, but the voltage
is significant. For review purposes, keep the following in mind for the analysis to follow:

An open circuit can have any voltage across its terminals, but the current is always 0 A. A short circuit
has a 0-V drop across its terminals, but the current is limited only by the surrounding network.

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The notation of Fig. 3.6 will be employed for the

applied voltage. It is a common industry notation and
one with which you should become very familiar.

Figure 3.6 Source Notation

PARALLEL AND SERIES-PARALLEL CONFIGURATIONS

The methods applied in series diode configuration can be extended to the analysis of parallel and series- parallel
configurations. For each area of application, simply match the sequential series of steps applied to series diode
configurations. The steps are summarized as follows:

Step 1: Mentally replace the diodes with resistive elements and note the resulting current direction as established
by the applied voltages (“pressure”). If the resulting direction is a “match” with the arrow in the diode symbol,
conduction through the diode will occur and the device is in the “on” state. Otherwise, the diode is in the “off”
state or open.
Step 2: The network is then redrawn with the appropriate equivalent model for the forward- or reversed-biased
diode. Note that the polarity of VD or VK is the same as would result if in fact the diode were a resistive element.
Step 3: Write the equation for the network involving ID and VK using KVL. Always keep in mind that under any
circumstances - dc, ac instantaneous values, pulses, and so on - Kirchhoff’s voltage law must be satisfied!

HALF-WAVE RECTIFICATION
Your diode analysis will now be expanded to include
time-varying functions such as the sinusoidal waveform
and the square wave. There is no question that the
degree of difficulty will increase, but once a few
fundamental maneuvers are understood, the analysis
will be fairly direct and follow a common thread. So let’s
get started.
Figure 3.7 Half-wave Rectifier
Over one full cycle, defined by the period T of Fig. 3.7, the average value (the algebraic sum of the areas above
and below the axis) is zero. The circuit of Fig. 3.7, called a half-wave rectifier, will generate a waveform vo that
will have an average value of particular use in the ac-to-dc conversion process. When employed in the
rectification process, a diode is typically referred to as a rectifier (its power and current ratings are typically much
higher than those of diodes employed in other applications).

Figure 3.8a Conduction Region

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Figure 3.8b Non-Conduction Region

Figures 3.8a and 3.8b depicts how conduction and non-conduction of the diode changes the input waveform as it
passes through it resulting in a rectified output voltage waveform shown in Figure 3.9.

The process of removing one-half the input signal to establish a

dc level is called half-wave rectification.

The output signal vo now has a net positive area above the axis
over a full period and an average value determined by

Vdc = Vm/p = 0.318 Vm Eq. 3.4 DC value of

half-wave rectified voltage

Note: Maximum voltage, Vm is being used interchangeably with

peak voltage, Vp.

What if you consider the effect of using a silicon diode with VK =

0.7 V for the forward-bias region? If that is the case, the applied
signal must now be at least 0.7 V before the diode can turn “on.”
For levels of vi less than 0.7 V, the diode is still in an open-circuit
state and vo = 0 V. Consider Figure 3.10 below.
Figure 3.9 Half-wave Rectified Signal

Figure 3.10 Effect of VK on half-wave rectified signal

When conducting, the difference between vo and vi is a fixed level of VK = 0.7 V and vo = vi - VK, as shown in the
figure above. The net effect is a reduction in area above the axis, which reduces the resulting dc voltage level.
For situations where Vm >> VK, Eq. 3.5 can be applied to determine the average value with a relatively high level
of accuracy.
Vdc = (Vm - VK)/ p = 0.318 (Vm - VK) Eq. 3.5 DC value of half-wave rectified voltage with VK
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2) Activity 3: Skill-building Activities

Load-line Analysis
a.1 For the series diode configuration employing the diode characteristics given, determine: V D, ID, VDQ, IDQ, VR.
Draw the load-line and plot the Q-point. Using the Q-point values, calculate the dc resistance RD.

a.2 Repeat a.1 using the approximate model of a silicon diode. Note: You will use the characteristic curve of
the approximate model of a diode and plot the same load-line.

Diode Configuration

b.1 For the series diode configuration, determine: VD, ID, and VR.
Use the approximate model of the silicon diode.

b.2 Determine Vo, ID, and IR. Draw the equivalent circuit using
approximate models of the diodes.

Note: A diode which emits

light when forward-biased is
known as light-emitting
diodes (LED). LEDs have
different colors and each
color has equivalent knee
voltage.

Table 3.1Typical Light-Emitting Diodes, Construction and Forward Voltage

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b.3 Determine I, V1, V2, and Vo b.4 Determine the currents I1, I2, and ID2
for the series dc configuration of the network.

Rectifier
c.1 Sketch the output waveform, vo. Also,
determine the dc level of the output for the
network if the diode is ideal.

c.2 Replace the ideal diode in c.1 with Silicon.

Sketch and calculate the dc level of the output.

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is the most basic

function of diode in a circuit?

2. Which diode equivalent

circuit model is widely used in
the analysis of diode circuits?

3. How can an alternating-

current voltage (ACV) be
converted to a usable direct-
current voltage (DCV)?

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4) Activity 5: Check for Understanding

This is a self-assessment. Key answers will be provided by your

teacher.

a.1 Determine the value of IR1, IR2 and the combined voltage VC
of the Silicon diode and the blue LED.

a.2 Calculate the current, I, through the resistors and the output voltage VO.

a.3 Determine the labeled output voltages VO, VO1, and VO2 in the circuits provided. Also, find the current
passing through the 4.7-kW resistors in each.

a.4 Determine the labeled output voltages

VO, VO1, and VO2 in the circuits provided.

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C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

What motivated you to finish the lessons today?

Did you progress in the content smoothly?

FAQs

1. When is the practical model of a diode useful in diode circuit analysis? The complete model?

The practical model is useful when you are troubleshooting in lower-voltage circuits. In these cases, the 0.7 V
drop across the diode may be significant and should be taken into account. The practical model is also useful
when you are designing basic diode circuits.

For troubleshooting work, it is unnecessary to use the complete model, as it involves complicated calculations.
This model is generally suited to design problems using a computer for simulation.

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2. Generally, what are some ways to determine if diode is still ‘good’ (still useful) or already ‘bad’
(should be replaced)?

The condition of a semiconductor diode can be determined quickly using (1) a

digital display meter (DDM), or digital multimeter (DMM), with a diode
checking function, (2) the ohmmeter section of a multimeter.

Diode Checking Function

A digital display meter with a diode checking capability appears in figure on the
left. Note the small diode symbol at the top right of the rotating dial. When set
in this position and hooked up as shown, the diode should be in the “on” state
and the display will provide an indication of the forward-bias voltage such as
0.67 V (for Si). The meter has an internal constant-current source (about 2 mA)
that will define the voltage level as indicated below.

An OL indication with the hookup reveals an open (defective) diode. If the leads are reversed, an OL indication
should result due to the expected open-circuit equivalence for the diode. In general, therefore, an OL indication
in both directions is an indication of an open or defective diode.

Ohmmeter Testing
You already found that the forward-bias resistance of a semiconductor
diode is quite low compared to the reverse-bias level. Therefore, if we
measure the resistance of a diode using the connections indicated in the
right figure, you can expect a relatively low level. The resulting ohmmeter
indication will be a function of the current established through the diode
by the internal battery (often 1.5 V) of the ohmmeter circuit. The higher
the current, the lower is the resistance level. For the reverse-bias situation
the reading should be quite high, requiring a high resistance scale on the
meter.

A high resistance reading in both directions indicates an open

(defective-device) condition, whereas a very low resistance reading
in both directions will probably indicate a shorted device.

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3. When diodes are being used as rectifiers, what is the most important consideration in the design?

The peak inverse voltage (PIV) [or PRV (peak reverse voltage)]
rating of the diode is of primary importance in the design of
rectification systems. The peak inverse voltage (PIV) equals the peak
or maximum value of the input voltage, and the diode must be capable
of withstanding this amount of repetitive reverse voltage. For a simple
rectifier diode, the maximum value of reverse voltage, designated as
PIV, occurs at the peak of each negative alternation of the input
voltage when the diode is reverse-biased.

A diode should be rated at least 20% higher than the PIV.

KEY TO CORRECTIONS

Activity 3

a.1 ID = 20 mA; VD = 10 V
VDQ = 0.78 V ; IDQ = 18.5 mA ; VR = 9.22 V;
RD = 42.16 W

a.2 ID = 20 mA; VD = 10 V
VDQ = 0.7 V ; IDQ = 18.5 mA ; VR = 9.3 V;
RD = 37.84 W

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Lesson Title: Materials:

Diode Applications - Part 2 Pencil, paper, calculator

References:
Full-wave Rectifiers 1. Electronic Devices and Circuit
Bridge-type Theory, 11th Edition by R.
Center-tapped Boylestad & L. Nashelsky (2013),
Pearson;
Wave-Shaping Circuits
Clippers or Diode Limiters 2. Electronic Devices:
Clampers Conventional Current Version, 9th
Edition by Thomas Floyd (2012),
Prentice Hall;
Lesson Objectives:
3. Electronic Principles, 8th Edition
At the end of this lesson, you should be able to: by Albert Malvino and David J.
● explain and analyze the operation of full-wave rectifiers, namely Bates (2016);
bridge-type and center-tapped;
● explain and analyze the operation of clippers and clampers as 4. Grob’s Basic Electronics, 12th
wave-shaping circuits. Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: Your brain is a muscle. It needs exercise so you can stay sharp.
And don’t forget to take regular breaks. Rest if you must.

A. LESSON PREVIEW/REVIEW
1) Introduction

Welcome back!

In the previous modules, you were introduce with some basic functions and applications of a diode - as
switch that either closed or open depending on the applied bias, and a rectifier that converts ac into pulsating
dc. Although half-wave rectifiers have some applications, the full-wave rectifier is the most commonly used
type in dc power supplies. In this module, you will use what you learned about half-wave rectification and
expand it to full-wave rectifiers. You will learn about two types of full-wave rectifiers: center-tapped and bridge.

The previous module on rectification gives clear evidence that diodes can be used to change the appearance
of an applied waveform. In addition, the lesson of this module on clippers and clampers will expand on the wave-
shaping abilities of diodes.

Let’s get started!

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2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)
1. How should two diodes be
connected in the input terminals in
order to expand half-wave into full-
wave rectification?
2. What is a clipper?

3. What is a clamper?

B. MAIN LESSON
1) Activity 2: Content Notes (13 mins)

FULL-WAVE RECTIFICATION
A full-wave rectifier allows unidirectional (one-way) current through the load during the entire 360° of the input
cycle, whereas a half-wave rectifier allows current through the load only during one-half of the cycle. The result
of full-wave rectification is an output voltage with a frequency twice the input frequency and that pulsates every
half-cycle of the input, as shown in Fig. 4.1.

Figure 4.1 Full-wave rectification

The number of positive alternations that make up the full-wave rectified voltage is twice that of the half-wave
voltage for the same time interval. The average or dc value, which is the value measured on a dc voltmeter, for a
full-wave rectified sinusoidal voltage is twice that of the half-wave, as shown in the following formula:

Vdc = 2Vm/p = 0.637 Vm Eq. 4.1 Ideal DC or average value of a full-wave rectified voltage.
Bridge-type Rectifier. The most familiar network for performing full-rectification appears in Fig. 4.2 with its
four diodes in a bridge configuration.

Figure 4.2 Operation of a bridge rectifier

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When the input cycle is positive as in Figure 4.2a, diodes D 1 and D2 are forward-biased and conduct current in
the direction shown. A voltage is developed across R L that looks like the positive half of the input cycle. During
this time, diodes D3 and D4 are reverse-biased. When the input cycle is negative as in Figure 4.2b, diodes D 3
and D4 are forward- biased and conduct current in the same direction through R L as during the positive half-
cycle. During the negative half-cycle, D1 and
D2 are reverse-biased. A full-wave rectified
output voltage appears across R L as a result
of this action.

Bridge Output Voltage. If silicon rather than

ideal diodes are employed as shown in Fig.
4.3, the application of Kirchhoff’s voltage law
around the conduction path results in

vi - VK - vo - VK = 0
vo = vi - 2VK Figure 4.3 Maximum Output Voltage for Bridge-type Rectifier

Therefore, for the maximum output voltage and its dc value of a bridge network using practical diodes is given
by the following equations:

Vp(out) = Vm(out) = Vm - 2VK Eq. 4.2 Peak value of a full-wave rectified

voltage using practical diode

Vdc(out) = 2 (Vm - 2VK)/p = 0.637(Vm - 2VK) Eq. 4.3 DC value of a full-wave rectified
Vdc(out) = 2 Vp(out)/p = 0.637 Vp(out) voltage using practical diode

PIV of Bridge Configuration. The required PIV of each diode can be

determined from Fig. 4.4 obtained at the peak of the positive region of
the input signal. For the indicated loop the maximum voltage across R
is Vm and the PIV rating is defined by

PIV > Vm Eq. 4.4a PIV of each ideal diode in the

bridge configuration

PIV > Vm + VK Eq. 4.4b PIV of each practical diode in the

bridge configuration
Figure 4.4 PIV for Bridge Configuration

Center-tapped Rectifier. A second popular full-wave rectifier appears in Fig. 4.5 with only two diodes but
requiring a center-tapped (CT) transformer to establish the input signal across each section of the secondary of
the transformer. For a positive half-cycle of the input voltage, the polarities of the secondary voltages are as
shown in Figure 4.5a. This condition forward-biases diode D1 and reverse-biases diode D2. The current path is
through D1 and the load resistor RL, as indicated. For a negative half-cycle of the input voltage, the voltage
polarities on the secondary are as shown in Figure 4.5b. This condition reverse-biases D1 and forward-biases
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D2. The current path is through D2 and RL, as indicated. Because the output current during both the positive and
negative portions of the input cycle is in the same direction through the load, the output voltage developed across
the load resistor is a full-wave rectified dc voltage, as shown.

Figure 4.5 Operation of a center-tapped rectifier

Center-tapped Output Voltage.

Using an ideal diode, the output voltage for center-

tapped configuration is given by:

Vo = Vp(sec) / 2

no matter what the transformer’s turns ratio (n). And

since n = Vsec / Vpri = Vp(sec) / Vp(pri) then,

Vo = n Vp(pri) / 2
Figure 4.6 Center-tapped Configuration Output voltage

Vo = Vp(pri) / 2
Vo = Vi / 2 = Vm / 2 Eq. 4.5a Peak value of a full-wave rectified voltage
using ideal diode with n = 1
Vo = Vp(pri)
Vo = Vi = Vm Eq. 4.5b Peak value of a full-wave rectified voltage
using ideal diode with n = 2

Note: For center-tapped configuration, an output voltage with a peak equal to the input peak (less the diode
drop) is obtained using a step-up transformer with a turns ratio of n = 2.

Vp(out) = Vm(out) = Vm - VK Eq. 4.6 Peak value of a full-wave rectified

voltage using practical diode

Vdc(out) = 2 (Vm - 2VK)/p = 0.637(Vm - 2VK) Eq. 4.7 DC value of a full-wave rectified
Vdc(out) = 2 Vp(out)/p = 0.637 Vp(out) voltage using practical diode

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PIV of Center-tapped. The network of Fig. 4.7 will help us determine the net
PIV for each diode for this full-wave rectifier. Inserting the maximum voltage
for the secondary voltage and Vm as established by the adjoining loop results
in

PIV = Vp(sec) + VR = Vm + Vm
PIV = 2Vm Eq. 4.8a PIV of each ideal diode in the
center-tapped configuration

PIV > 2Vm + VK Eq. 4.8b PIV of each practical diode in the
center-tapped configuration

Figure 4.7 PIV for Center-tapped

WAVE-SHAPING CIRCUITS
Diode circuits, called limiters or clippers, are sometimes used to clip off portions of signal voltages above or
below certain levels. Another type of diode circuit, called a clamper, is used to add or restore a dc level to an
electrical signal.

Clippers or Diode Limiters. Clippers are networks that employ diodes to “clip” away a portion of an input signal
without distorting the remaining part of the applied waveform. The half-wave rectifier is an example of the
simplest form of diode clipper— one resistor and a diode. Depending on the orientation of the diode, the positive
or negative region of the applied signal is “clipped” off. There are two general categories of clippers: series and
parallel.

Series Clipper. The series configuration is defined as one where the diode is in series with the load. Consider
the following figures.

Figure 4.8 Unbiased Series Clipper

with Given Inputs and Ideal Output Waveforms

Note: The analysis of diode clippers may involve either

an ideal or practical diode. When practical diodes are
considered, output waveforms must reflect the
corresponding diode drop, VK.

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Parallel Clipper. The parallel configuration is defined as one where the diode is in parallel with the load.

Figure 4.9 Unbiased Parallel Clipper

with Given Inputs and Ideal Output Waveforms

Consider Figures 4.10 and 4.11 for various simple

clipping circuits, both series and parallel, some with
bias voltages.

Figure 4.10 Clipping Circuits (Series)

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Figure 4.11 Clipping Circuits (Parallel)

Clampers or DC Restorers. A clamper is a network constructed of a diode, a resistor, and a capacitor that shifts
a waveform to a different dc level without changing the appearance of the applied signal. Clamping networks
have a capacitor connected directly from input to output with a resistive element in parallel with the output signal.
The diode is also in parallel with the output signal, as shown in Fig. 4.12, but may or may not have a series dc
supply as an added element.

The chosen resistor and capacitor of the network must be chosen such that the
time constant (t = RC) is sufficiently large to ensure that the voltage across the
capacitor does not discharge significantly during the interval the diode is
nonconducting. Throughout the analysis we assume that for all practical
purposes the capacitor fully charges or discharges in five time constants (5t).
Consider Fig. 4.13 for a variety of clamping circuits.
Figure 4.12 Simple Clamper
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Figure 4.13 Clamping Circuits with Ideal Diodes

2) Activity 3: Skill-building Activities (with answer key) (18 mins + 2 mins checking)

a. Full-wave Bridge-type Rectifier.

Consider the following circuit on the right.

a.1 Determine the peak and dc output voltage for

the bridge rectifier.
a.2 Assuming the practical model, what PIV rating
is required for the diodes? The transformer is
specified to have a 12 V rms secondary voltage for
the standard 120 V across the primary.

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b. Full-wave Center-tapped Rectifier.

Consider the following circuit on the right.

b.1 Show the voltage waveforms across each half

of the secondary winding and across RL when a
100 V peak sine wave is applied to the primary
winding;
b.2 What minimum PIV rating must the diodes
have?

c. Clipper.
Show the output waveform of the clipping circuit with
input given using ideal diode.

d. Clamper. Show the output

waveform of the clamping circuit with
input given using ideal diode.

3) Activity 4: What I Know Chart, part 2 (2 mins)

What I Know Questions: What I Learned (Activity 4)

1. How should two diodes be
connected in the input terminals in
order to expand half-wave into full-
wave rectification?
2. What is a clipper?

3. What is a clamper?

4) Activity 5: Check for Understanding (5 mins)

This is a summative assessment. Answers will be provided by your teacher.
Show complete solution to get the maximum points possible for each problem.
a. Using KVL, complete the working equations for the clipping circuits shown in Fig. 4.11 for both positive and
negative half-cycles of the input.
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C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

What part of your learning experience did you find satisfactory today?
What strategy worked for you to achieve the satisfaction?

FAQs

1. What is a transformer and what are the advantages of using it in a basic power supply?
A transformer is often used to couple the ac input voltage from the source to the rectifier. Transformer coupling
provides two advantages. First, it allows the source voltage to be stepped down as needed. Second, the ac
source is electrically isolated from the rectifier, thus preventing a shock hazard in the secondary circuit. The
amount that the voltage is stepped down is determined by the
turns ratio, or “the number of turns in the secondary (Nsec)
divided by the number of turns in the primary (Npri)”, of the
transformer. Thus, a transformer with a turns ratio less than 1 is
a step-down type and one with a turns ratio greater than 1 is a
step- up type. To show the turns ratio on a schematic, it is
common practice to show the numerical ratio directly above the
windings. However, transformer datasheets rarely show the turns
ratio. A transformer is generally specified based on the secondary
voltage rather than the turns ratio.

2. Since a clipper limits the level of maximum voltage in its output, how could it be used in networks
other than being a rectifier?
Many circuits have certain restrictions on the input level to avoid damaging the circuit. For example, almost all
digital circuits should not have an input level that exceeds the power supply voltage. An input of a few volts more
than this could dam- age the circuit. To prevent the input from exceeding a specific level, you may see a diode
limiter across the input signal path in many digital circuits. Consider the clippers below that uses a voltage-divider
network in order to function as protection circuits.

10

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 ECE 028: Electronic Devices and Circuits
Student Activity Sheet #5

Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Lesson Title: Materials:

Diode Applications - Part 3 Pencil and paper

References:
Voltage Multipliers 1. Electronic Devices and Circuit
Zener Diodes as Voltage Regulators Theory, 11th Edition by R.
Boylestad & L. Nashelsky (2013),
Pearson;

Lesson Objectives: 2. Electronic Devices:

Conventional Current Version, 9th
At the end of this lesson, you should be able to: Edition by Thomas Floyd (2012),
● explain and analyze the operation of voltage multipliers; Prentice Hall;
● define the characteristics of a Zener diode and analyze its operation
3. Electronic Principles, 8th Edition
by Albert Malvino and David J.
Bates (2016);

4. Grob’s Basic Electronics, 12th

Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: Mastery requires constant practice.

Just do it!

A. LESSON PREVIEW/REVIEW
1) Introduction

You are now on the third part of diode application! The range of practical applications for diodes is so broad
that it would be virtually impossible to consider all the options in one section. However, to develop some sense
for the use of the device in everyday networks, a number of common areas of application were already introduced
- rectification and wave-shaping. In this module, you will learn about voltage multiplication and regulation

Voltage multipliers use clamping action to increase peak rectified voltages without the necessity of increasing
the transformer’s voltage rating. Multiplication factors of two, three, and four are common. Voltage multipliers are
used in high-voltage, low-current applications such as cathode-ray tubes (CRTs) and particle accelerators.

The use of the Zener diode as a regulator is so common that three conditions surrounding the analysis of the
basic Zener regulator are considered. The analysis provides an excellent opportunity to become better
acquainted with the response of the Zener diode to different operating conditions. The analysis is first for fixed
quantities, followed by a fixed supply voltage and a variable load, and finally a fixed load and a variable supply.

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2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)
1. How are diodes and capacitors
critical in the operation of voltage
multipliers?
2. What is voltage regulation and
its importance in power supplies?

B. MAIN LESSON
1) Activity 2: Content Notes (13 mins)

VOLTAGE MULTIPLIERS
Half-wave Voltage Doubler. A voltage doubler is a voltage multiplier with a multiplication factor of two. A half-
wave voltage doubler is shown in Fig. 5.1.

Figure 5.1 Half-wave voltage doubler operation.

During the positive half-cycle of the secondary voltage, diode D1 is forward-biased and D2 is reverse-biased.
Capacitor C1 is charged to the peak of the secondary voltage (Vp) less the diode drop with the polarity shown
in part (a). During the negative half-cycle, diode D2 is forward-biased and D1 is reverse-biased, as shown in part
(b). Since C1 can’t discharge, the peak voltage on C1 adds to the secondary voltage to charge C2 to
approximately 2Vp. Applying Kirchhoff’s law around the loop as shown in part (b), the voltage across C2 is

VC1 -VC2 +Vp =0

VC2 =Vp +VC1

Neglecting the diode drop of D2, VC1 = Vp. Therefore, VC2 = Vp +Vp = 2Vp

Under a no-load condition, C2 remains charged to approximately 2Vp. If a load resistance is connected across
the output, C2 discharges slightly through the load on the next positive half-cycle and is again recharged to 2Vp
on the following negative half-cycle. The resulting output is a half-wave, capacitor-filtered voltage. The peak
inverse voltage across each diode is 2Vp. If the diode were reversed, the output voltage across C2 would have
the opposite polarity.

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Full-Wave Voltage Doubler. A full-wave doubler is shown in Fig. 5.2. When the secondary voltage is positive,
D1 is forward-biased and C1 charges to approximately Vp, as shown in part (a). During the negative half-cycle,
D2 is forward-biased and C2 charges to approximately Vp, as shown in part (b). The output voltage, 2Vp, is
taken across the two capacitors in series.

Figure 5.2 Full-wave voltage doubler operation.

Voltage Tripler. The addition of another diode-

capacitor section to the half-wave voltage doubler
creates a voltage tripler, as shown in Fig. 5.3. The
operation is as follows: On the positive half-cycle of
the secondary voltage, C1 charges to Vp through
D1. During the negative half-cycle, C2 charges to
2Vp through D2, as described for the doubler.
During the next positive half-cycle, C3 charges to
2Vp through D3. The tripler output is taken across
C1 and C3, as shown in the figure on the right.
Figure 5.3 Voltage tripler.

Voltage Quadrupler. The addition of still

another diode-capacitor section, as shown
in Figure 5.4, produces an output four times
the peak secondary voltage. C4 charges to
2Vp through D4 on a negative half-cycle.
The 4Vp output is taken across C2 and C4,
as shown.

Figure 5.4 Voltage quadrupler

Note: In both the tripler and quadrupler circuits, the PIV of each diode is 2Vp.
3

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ZENER DIODE
A zener diode (see symbol in the figure) is a silicon pn junction device that is designed
for operation in the reverse-breakdown region. The breakdown voltage of a zener diode
is set by carefully controlling the doping level during manufacture. Recall, from the
discussion of the diode characteristic curve in the previous modules, that when a diode
reaches reverse breakdown (Figure 5.6), its voltage remains almost constant even
though the current changes drastically, and this is the key to zener diode operation. The
analysis of networks employing Zener diodes is quite similar to the analysis of
semiconductor diodes in previous sections. First the state of the diode must be
determined, followed by a substitution of the appropriate model and a determination of
the other unknown quantities of the network.
Figure 5.5 Zener Diode

Figure 5.6 General Zener diode Figure 5.7 Approximate equivalent circuits for the
V-I characteristic Zener diode in regions of application.

Figure 5.8 reviews the approximate equivalent circuits for each region of a Zener diode assuming the straight-
line approximations at each break point. Note that the forward-bias region is included because occasionally an
application will skip into this region also.

Zener Breakdown. Zener diodes are designed to operate in reverse breakdown. Two types of reverse
breakdown in a zener diode are avalanche and zener. Zener breakdown occurs in a zener diode at low reverse
voltages. A zener diode is heavily doped to reduce the breakdown voltage. This causes a very thin depletion
region. As a result, an intense electric field exists within the depletion region. Near the zener breakdown voltage
(VZ), the field is in- tense enough to pull electrons from their valence bands and create current. Zener diodes
with breakdown voltages of less than approximately 5 V operate predominately in zener breakdown. Those with
breakdown voltages greater than approximately 5 V operate predominately in avalanche breakdown. Both types,
however, are called zener diodes. Zeners are commercially available with breakdown voltages from less than 1
V to more than 250 V with specified tolerances from 1% to 20%.

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Figure 5.9 Example of Zener Diodes for Reference Voltage Setting (left)

Zener Diodes for Reference Voltage. Consider Figure 5.9. Note that the silicon diode
was used to create a reference voltage of 4 V because

Vo1 = VZ2 + VK = 3.3 V + 0.7 V = 4.0 V

Combining the voltage of the 6-V Zener diode with the 4 V results in

Vo2 = Vo1 + VZ1 = 4 V + 6 V = 10.0 V

Calculating for the resistor current,

VS - VR - VLED(white) - Vo2 = 0
VS - IRR - VLED(white) - Vo2 = 0
IR = [VS - VLED(white) - Vo2 ] / R = [40 V - 4.0 V - 10.0 V] / 1.3 kW IR
= 20 mA

Similarly, the current for the LED is ILED = 20 mA due to series connection.

Zener Regulation. The ability to keep the reverse voltage across its terminals essentially constant is the key
feature of the zener diode. A zener diode operating in breakdown acts as a voltage regulator because it maintains
a nearly constant voltage across its terminals over a specified range of reverse-current values.

Figure 6.0 Basic Zener Regulator (left)

A. Vi and R Fixed. The simplest of Zener diode regulator networks

appears in Fig. 5.10. The applied dc voltage is fixed, as is the load
resistor. The analysis can fundamentally be broken down into two
steps.

1. Determine the state of the Zener diode by removing it from the

network and calculating the voltage across the resulting open circuit.

Eq. 5.1 Determining the state of

Zener Diode

If V ³ VZ, the Zener diode is on, and the appropriate equivalent model
can be substituted. If V < VZ, the diode is off, and the open-circuit
equivalence is substituted.

Note: VZ is the Zener breakdown voltage defined in its datasheet.

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2. Substitute the appropriate equivalent circuit and solve for the desired unknowns.

For the “on” state,

VL = VZ Eq. 5.2 Load Voltage
and,

Figure 6.1 Zener equivalent for the “on” situation PZ = VZIZ Eq. 5.3 Zener Power

Note: Before continuing, it is particularly important to realize that the first step was employed only to determine
the state of the Zener diode. If the Zener diode is in the “on” state, the voltage across the diode is not V volts.
When the system is turned on, the Zener diode will turn on as soon as the voltage across the Zener diode
is VZ volts. It will then “lock in” at this level and never reach the higher level of V volts.

B. Fixed Vi and Variable RL. Due to the offset voltage VZ, there is a specific range
of resistor values (and therefore load current) that will ensure that the Zener is in the
“on” state. Too small a load resistance RL will result in a voltage VL across the load
resistor less than VZ, and the Zener device will be in the “off” state. To determine the
minimum load resistance of Fig. 6.0 that will turn the Zener diode on, simply calculate
the value of RL that will result in a load voltage VL = VZ.
Eq. 5.4 Minimum Load

The condition defined by Eq. 5.4 establishes the minimum RL,

but in turn specifies the maximum IL as

Once the diode is in the “on” state, the voltage across R remains fixed at
VR = Vi - VZ
and IR remains fixed at IR = VR / R
The Zener current: IZ = IR - IL
resulting in a minimum IZ when IL is a maximum and a maximum IZ when IL is a minimum value, since IR is
constant. Since IZ is limited to IZM as provided on the data sheet, it does affect the range of RL and therefore
IL. Substituting IZM for IZ establishes the minimum IL as
ILmin = IR - IL

and the maximum load resistance as

6

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C. Fixed RL and Variable Vi. For fixed values of RL in Fig. 6.0, the voltage Vi must be sufficiently large to turn
the Zener diode on. The minimum turn-on voltage Vi = Vimin is determined by

The maximum value of Vi is limited by the

maximum Zener current IZM.
Since IZM = IR - IL,

Since IL is fixed at VZ / RL and IZM is the

maximum value of IZ, the maximum Vi is

2) Activity 3: Skill-building Activities (with answer key) (18 mins + 2 mins checking)

a.1 For the Zener diode network shown in the figure to the right,
determine VL, VR, IZ, and PZ.

a.2. Repeat part (a.1) with RL = 3 kW.

b.1 For the network shown in the figure to the right,

determine the range of RL and IL that will result in VRL
being maintained at 10 V.

b.2 Determine the maximum wattage rating of the diode.

c.1 Determine the range of values of Vi that will maintain the

Zener diode in the “on” state. Refer to the figure in the right.

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3) Activity 4: What I Know Chart, part 2 (2 mins)

What I Know Questions: What I Learned (Activity 4)

1. How are diodes and capacitors critical
in the operation of voltage multipliers?
2. What is voltage regulation and its
importance in power supplies?

4) Activity 5: Check for Understanding (5 mins)

This is a self-assessment. Answers will be provided by your teacher.

a.1 Determine the voltage available from the voltage doubler

of figure shown on the right if the secondary voltage of the
transformer is 120 V(rms).

a.2 Determine the required PIV ratings of the diodes of figure

shown on the right in terms of the peak secondary voltage
Vm.

b.1 Determine VL, IL, IZ, and IR for the network of network
shown on the right if RL = 180 W.

b.2 Repeat part (b.1) if RL = 470 W.

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

Which strategy worked for you, easily? With difficulty?

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Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Lesson Title: Materials:

DC Power Supply and Voltage Regulators Pencil, paper, and calculator

References:
1. Electronic Devices and Circuit
Capacitor Filters Theory, 11th Edition by R.
Integrated Circuit (IC) Regulators Boylestad & L. Nashelsky (2013);
Troubleshooting a Power Supply
2. Electronic Devices:
Conventional Current Version, 9th
Edition by Thomas Floyd (2012);
Lesson Objectives:
3. Electronic Principles, 8th Edition
At the end of this lesson, you should be able to: by Albert Malvino and David J.
● explain and analyze power supply circuits and regulators; Bates (2016);
● calculate the output voltage of filtered and regulated full-wave
power supply; 4. Grob’s Basic Electronics, 12th
● differentiate line regulation and load regulation. Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: Every day is an opportunity to be better! Seek meaning and be in better path, each day.

A. LESSON PREVIEW/REVIEW
1) Introduction

This module introduces the operation of power supply circuits built using filters, rectifiers, and then voltage
regulators. The previous modules has an the initial description of diode rectifier circuits. A power supply filter
ideally eliminates the fluctuations in the output voltage of a half-wave or full-wave rectifier and produces a
constant-level dc voltage. The regulation is usually obtained from an integrated circuit (IC) voltage regulator unit,
which takes a dc voltage and provides a somewhat lower dc voltage, which remains the same even if the input
dc voltage varies or the output load connected to the dc voltage changes.

Starting with an ac voltage, we obtain a steady dc voltage by rectifying the ac voltage, then filtering to a dc
level, and, finally, regulating to obtain a desired fixed dc voltage. Filtering is necessary because electronic circuits
require a constant source of dc voltage and current to provide power and biasing for proper operation. You will
see in this module that filters are implemented with capacitors and voltage regulation in power supplies is usually
done with integrated circuit voltage regulators. At the end of this module, you will also be guided with the basic
working concept and systematic approach of troubleshooting: analysis, planning, and measuring.

Let’s get on with it.

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2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)
1. What are the basic functional blocks
of a power supply?
2. What are the important
considerations in building a power
supply?
3. How do you troubleshoot a power
supply?

B. MAIN LESSON
1) Activity 2: Content Notes (13 mins)

DC POWER SUPPLY. A block diagram containing the parts of a typical power supply and the voltage at
various points in the unit is shown in Fig. 6.1.

Figure 6.1 Block diagram showing parts of a power supply.

The ac voltage, typically 120 V rms (abroad) or 220 V rms (Philippines), is connected to a transformer,
which steps that ac voltage down to the level for the desired dc output. A diode rectifier then provides a full-
wave rectified voltage, which is initially filtered by a basic capacitor filter to produce a dc voltage. This resulting
dc voltage usually has some ripple or ac voltage variation. A regulator circuit can use this dc input to provide a
dc voltage that not only has much less ripple voltage, but also remains at the same dc value even if the input dc
voltage varies somewhat or the load connected to the output dc voltage changes. This voltage regulation is
usually obtained using one of a number of popular voltage regulator IC units.

GENERAL FILTER CONSIDERATIONS

A rectifier circuit is necessary to convert a
signal having zero average value into one that
has a nonzero average. The output resulting
from a rectifier is a pulsating dc voltage and not
yet suitable as a battery replacement. Such a
voltage could be used in, say, a battery
charger, where the average dc voltage is large
enough to provide a charging current for the
battery.

Figure 6.2 Power Supply Filtering (right)

2

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For dc supply voltages, such as those used in a radio, stereo system, computer, and so on, the pulsating dc
voltage from a rectifier is not good enough. A filter circuit is necessary to provide a steadier dc voltage. Figure
6.2 illustrates the filtering concept showing a nearly smooth dc output voltage from the filter. The small amount
of fluctuation in the filter output voltage is called ripple.

Filter Voltage Regulation and Ripple Voltage.

The filtered output of Fig. 6.3 has a dc value and
some ac variation (ripple). Although a battery has
essentially a constant or dc output voltage, the dc
voltage derived from an ac source signal by
rectifying and filtering will have some ac variation
(ripple). The smaller the ac variation with respect to
the dc level, the better is the filter circuit’s
operation.

Figure 6.3 Filter voltage waveform

showing dc and ripple voltages (right)

Consider measuring the output voltage of a filter circuit using a dc voltmeter and an ac (rms) voltmeter. The dc
voltmeter will read only the average or dc level of the output voltage. The ac (rms) meter will read only the rms
value of the ac component of the output voltage (assuming the ac signal is coupled through a capacitor to block
out the dc level). Ripple is defined as:
Eq. 6.0 Ripple

Voltage Regulation. Another factor of importance in a power supply is the amount the dc output voltage changes
over a range of circuit operation. The voltage provided at the output under no-load condition (no current drawn
from the supply) is reduced when load current is drawn from the supply (under load). The amount the dc voltage
changes between the no-load and load conditions is described by a factor called voltage regulation.

If the value of full-load voltage is the same as the

no-load voltage, the voltage regulation calculated
is 0%, which is the best expected. This means
that the supply is a perfect voltage source for
which the output voltage is independent of the
current drawn from the supply. The smaller the
voltage regulation, the better is the operation of
the voltage supply circuit.

Eq. 6.1 Voltage Regulation

Ripple Factor of Rectified Signal. Although the rectified voltage is not a filtered voltage, it nevertheless contains a
dc component and a ripple component. We will see that the full- wave rectified signal has a larger dc component
and less ripple than the half-wave rectified voltage.
Half-wave: For a half-wave rectified signal, the output dc voltage is Vdc = 0.318 Vm
The rms value of the ac component of the output signal can be calculated to be Vr(rms) = 0.385 Vm
3

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Full-wave: For a full-wave rectified voltage the dc value is Vdc = 0.636 Vm

The rms value of the ac component of the output signal can be calculated to be Vr(rms) = 0.308 Vm
So, what’s the percentage ripple for both half- and full-wave rectified signal based on dc and rms values?
In summary, a full-wave rectified signal has less ripple than a half-wave rectified signal and is thus
better to apply to a filter.

CAPACITOR FILTER. A very popular

filter circuit is the capacitor-filter circuit
shown in Fig. 6.4. A capacitor is
connected at the rectifier output, and a
dc voltage is obtained across the
capacitor.

Figure 6.4 Basic capacitor filter

Figure 6.5a shows the output voltage of a full-wave rectifier before the signal is filtered, whereas Fig. 6.5b shows
the resulting waveform after the filter capacitor is connected at the rectifier output. Notice that the filtered
waveform is essentially a dc voltage with some ripple (or ac variation).

Figure 6.5 Capacitor filter operation: (a) full-wave rectifier voltage; (b) filtered output voltage.

Ripple Voltage, Vr(rms). The filtered voltage, as shown in Fig. 6.6,

shows the output waveform to have a dc level Vdc and a ripple
voltage Vr(rms) as the capacitor charges and discharges. The ripple
voltage can be calculated from:

Eq. 6.2 Ripple

Voltage for a
Capacitor Filter

where
Idc is in mA
C is in uF, and RL is in kW. Figure 6.6 Output of capacitor filter circuit
4

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DC Voltage, Vdc. We can express the dc value of the waveform across the filter capacitor as,

Eq. 6.3 DC Voltage across

a filter capacitor

where Vm is the peak rectifier voltage, Idc is the load current (mA), and C is the filter capacitor (uF).

Filter Capacitor Ripple. Using the definition of ripple (Eq. 6.0), with Vdc approximately equal to Vm, we can
obtain the expression for the output waveform ripple of a full-wave rectifier and filter- capacitor circuit:
Eq. 6.4 Filter Capacitor Ripple

where Idc is in mA, C is in uF, Vdc is in

V, and RL is in kW.

Other Formula. For a full-wave rectifier with a capacitor-input filter,

approximations for the peak-to-peak ripple voltage, Vr(pp), and the dc value of
the filter output voltage, VDC, are given in the following equations. The variable
Vp(rect) is the unfiltered peak rectified voltage. Notice that if RL or C increases,
the ripple voltage decreases and the dc voltage increases.
Eq. 6.5 Vr(pp) and VDC
Note: For a half-wave rectifier, the output frequency f is the same as the input frequency.
For a full-wave rectifier, the output frequency f is double the input frequency.

INTEGRATED CIRCUIT (IC) VOLTAGE REGULATORS

Most regulators are integrated circuits

and have three terminals—an input terminal, an
output terminal, and a reference (or adjust)
terminal. The input to the regulator is first filtered
with a capacitor to reduce the ripple to <10%.
The regulator reduces the ripple to a negligible
amount. In addition, most regulators have an
internal voltage reference, short-circuit
protection, and thermal shutdown circuitry. They
are available in a variety of voltages, including
positive and negative outputs, and can be
designed for variable outputs with a minimum of
external components.
Figure 6.7 Three-terminal voltage regulator

Three-terminal regulators designed for fixed output voltages require only external capacitors to complete
the regulation portion of the power supply. Filtering is accomplished by a large-value capacitor between the input

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voltage and ground. An output capacitor (typically 0.1 mF to 1.0 mF) is connected from the output to ground to
improve the transient response.

Figure 6.8 A basic power

supply with +5.0 V IC
regulator (right)

Table 6.0 Positive-Voltage Regulators in the 7800 Series

Safety Note: When working with low-voltage power

supplies, be careful not to come in contact with the 220 V
ac line. Severe shock or worse could result. To verify input
voltage to a rectifier, it is always better to check at the
transformer secondary instead of trying to measure the line
voltage directly. If it becomes necessary to measure the
line voltage, use a multimeter and be careful.

TROUBLESHOOTING A POWER SUPPLY. A defective circuit or system is one with a known good input but
with no output or an incorrect output. For example, in Figure 6.9 (a), a properly functioning dc power supply is
represented by a single block with a known input voltage and a correct output voltage. A defective dc power
supply is represented in part (b) as a block with an input voltage and an incorrect output voltage.

Figure 6.9 Block representations of functioning and nonfunctioning power supplies.

The first thing you should do in analyzing the problem is to try to eliminate any obvious causes. In general, you
should start by making sure the power cord is plugged into an active outlet and that the fuse is not blown. In the

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case of a battery-powered system, make sure the battery is good. Something as simple as this is sometimes the
cause of a problem. However, in this case, there must be power because there is an output voltage.

Beyond the power check, use your senses to detect obvious defects, such as a burned resistor, broken
wire, loose connection, or an open fuse. Since some failures are temperature dependent, you can sometimes
find an overheated component by touch. However, be very cautious in a live circuit to avoid possible burn or
shock. For intermittent failures, the circuit may work properly for a while and then fail due to heat buildup. As a
rule, you should always do a sensory check as part of the analysis phase before proceeding.

Planning. In this phase, you must consider how you will attack the problem. There are three possible approaches
to troubleshooting most circuits or systems.
1. Start at the input (the transformer secondary in the case of a dc power supply) where there is
a known input voltage and work toward the output until you get an incorrect measurement. When you
find no voltage or an incorrect voltage, you have narrowed the problem to the part of the circuit between the last
test point where the voltage was good and the present test point. In all troubleshooting approaches, you must
know what the voltage is supposed to be at each point in order to recognize an incorrect measurement when
you see it.
2. Start at the output of a circuit and work toward the input. Check for voltage at each test point until
you get a correct measurement. At this point, you have isolated the problem to the part of the circuit between
the last test point and the current test point where the voltage is correct.
3. Use the half-splitting method and start in the middle of the circuit. If this measurement shows a
correct voltage, you know that the circuit is working properly from the input to that test point. This means that the
fault is between the current test point and the output point, so begin tracing the voltage from that po int toward
the output. If the measurement in the middle of the circuit shows no voltage or an incorrect voltage, you know
that the fault is between the input and that test point. Therefore, begin tracing the voltage from the test point
toward the input.

Figure 6.10 Example of the half-splitting approach. An open filter capacitor is indicated.

Measurement. The half-splitting method is illustrated in Figure 6.10 with the measurements indicating a
particular fault (open filter capacitor in this case). At test point 2 (TP2) you observe a full-wave rectified voltage
that indicates that the transformer and rectifier are working properly. This measurement also indicates that the
filter capacitor is open, which is verified by the full-wave voltage at TP3. If the filter were working properly, you
would measure a dc voltage at both TP2 and TP3. If the filter capacitor were shorted, you would observe no
voltage at all of the test points because the fuse would most likely be blown. A short anywhere in the system is
7

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very difficult to isolate because, if the system is properly fused, the fuse will blow immediately when a short to
ground develops.
For the case illustrated in Fig. 6.10, the half-splitting method took two measurements to isolate the fault to
the open filter capacitor. If you had started from the transformer output, it would have taken three measurements;
and if you had started at the final output, it would have also taken three measurements, as illustrated in Fig. 6.11.

Figure 6.11 Two other approaches with more oscilloscope measurements than the half-splitting approach

Fault Analysis. In some cases, after isolating a fault to a particular circuit, it may be necessary to isolate the
problem to a single component in the circuit. In this event, you have to apply logical thinking and your
knowledge of the symptoms caused by certain component failures.

2) Activity 3: Skill-building Activities (Refer to the Keys to Correction for the answers)

a.1 Using a dc and ac voltmeter to measure the output signal from a filter circuit, we obtain readings of 25 V dc
and 1.5 V rms. Calculate the ripple of the filter output voltage.
a.2 A dc voltage supply provides 60 V when the output is unloaded. When connected to a load, the output drops

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to 56 V. Calculate the value of voltage regulation.

b.1 Calculate the percentage ripple of a half-wave rectified signal.
b.2 Calculate the ripple voltage of a full-wave rectifier with a 100-mF filter capacitor connected to a load drawing
50 mA.
b.3 Calculate the filter dc voltage of a full-wave rectifier with a 100-mF filter capacitor connected to a load
drawing 50 mA if the peak rectified voltage for a simple filter circuit is 30 V.

c.1 Determine the ripple factor for the filtered

bridge rectifier with a load as indicated in the
figure below.

3) Activity 4: What I Know Chart, part 2 (2 mins)

What I Know Questions: What I Learned (Activity 4)

1. What are the basic functional
blocks of a power supply?
2. What are the important
considerations in building a
power supply?
3. How do you troubleshoot a
power supply?

4) Activity 5: Check for Understanding (Answers will be provided by your teacher.)

a. Determine the peak-to-peak ripple voltage if the filter capacitor in Activity 3 (c.1) is increased to 2200 uF and
the load resistance changes to 2.20 kW.

b. Calculate the percentage ripple of a full-wave rectified signal.

c. Calculate the ripple of a capacitor filter for a peak rectified voltage of 30 V, capacitor C = 50 mF, and a load
current of 50 mA.

d. Draw a voltage supply using a full-wave bridge rectifier, capacitor filter, and IC regulator to provide a IC-
regulated output with the following components:
Input: 120 Vrms
Rectifier Diodes: 1N4001
IC Regulator Output: +12 VDC
IC Regulator Input Capacitor: 250 uF
IC Regulator Output Capacitor: 0.01 uF

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C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

What motivated you to finish the lessons today?

Did you progress in the content smoothly?

FAQs

1. What is line regulation?

The line regulation specifies how much change occurs in the output
voltage for a given change in the input voltage. It is typically defined as
a ratio of a change in output voltage for a corresponding change in the
input voltage expressed as a percentage.

2. What are some typical component failures in a basic power supply and the symptoms?

Open Diode in a Half-Wave Rectifier. The resulting symptom is zero output voltage as indicated. This is obvious
because the open diode breaks the current path from the transformer secondary winding to the filter and load
resistor and there is no load current. Other faults that will cause the same symptom in this circuit ar e an open
transformer winding, an open fuse, or no input voltage.

Open Diode in a Full-Wave Rectifier. If either of the two diodes is open, the output voltage will have twice the
normal ripple voltage, say at 60 Hz, rather than at 120 Hz. Another fault that will cause the same symptom is an
open in the transformer secondary winding.

Faulty Filter Capacitor. There are three types of defects of a filter capacitor:
- Open. If the filter capacitor for a full-wave rectifier opens, the output is a full-wave rectified voltage.
- Shorted. If the filter capacitor shorts, the output is 0 V. A shorted capacitor should cause the fuse to blow open.
If not properly fused, a shorted capacitor may cause some or all of the diodes in the rectifier to burn open due to
excessive current. In any event, the output is 0 V.
- Leaky. A leaky filter capacitor is equivalent to a capacitor with a parallel leakage resistance. The effect of the
leakage resistance is to reduce the time constant and allow the capacitor to discharge more rapidly than normal.
This results in an increase in the ripple voltage on the output. This fault is rare.

Faulty Transformer. An open primary or secondary winding of a power supply transformer results in an output
of 0 V.

10

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Lesson Title: Materials:

Bipolar Junction Transistor (BJT) Fundamentals Pencil and paper

References:
Construction 1. Electronic Devices and Circuit
Basic Operation Theory, 11th Edition by R.
Transistor Configurations Boylestad & L. Nashelsky (2013);
Limits of Operation
2. Electronic Devices:
Conventional Current Version, 9th
Lesson Objectives: Edition by Thomas Floyd (2012);

At the end of this lesson, you should be able to: 3. Electronic Principles, 8th Edition
● describe the basic structure and operation of the BJT; by Albert Malvino and David J.
● discuss basic BJT parameters and characteristics and analyze Bates (2016);
transistor circuits.
4. Grob’s Basic Electronics, 12th
Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: The longer you wait to do something you should do now,
the greater the odds that you will never actually do it. So, start doing that something. Now.

A. LESSON PREVIEW/REVIEW
1) Introduction

Congratulations for finishing the first period of the course! You are now on the second part. Keep it coming!

For the first part of this period, you will be introduced with the invention of the transistor, the beginning of a
technological revolution that is still continuing. All of the complex electronic devices and systems today are an
outgrowth of early developments in semiconductor transistors. One of the two basic types of transistors is the
bipolar junction transistor (BJT). The BJT is used in two broad areas—as a linear amplifier to boost or amplify
an electrical signal and as an electronic switch.

The advantages of three-terminal solid-state device over the vacuum tube were immediately obvious: It
was smaller and lightweight; it had no heater requirement or heater loss; it had a rugged construction; it was
more efficient since less power was absorbed by the device itself; it was instantly available for use, requiring no
warm-up period; and lower operating voltages were possible.

This module contains the first discussion of devices with three or more terminals. You will find that all
amplifiers (devices that increase the voltage, current, or power level) have at least three terminals, with one
controlling the flow or potential between the other two.
1

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2) Activity 1: What I Know Chart, part 1

What I Know Questions: What I Learned (Activity 4)

1. What do you know about the
three-terminal devices like
transistors?
2. What is meant by “bipolar” in
electronics?
3. Could you identify important
characteristics of a transistor?

B. MAIN LESSON
1) Activity 2: Content Notes

TRANSISTOR CONSTRUCTION
The transistor is a three-layer semiconductor device consisting
of either two n- and one p-type layers of material or two p- and
one n-type layers of material. The former is called an npn
transistor, and the latter is called a pnp transistor. Refer to
Figure 7.1 for the epitaxial planar structure.

Figure 7.1 Basic epitaxial planar structure of a transistor (left)

The proper dc biasing of an npn and pnp transistor are shown in Figure 7.2 . You should take note that dc
biasing is necessary to establish the proper region of operation for ac amplification.

The three regions of a transistor are called emitter,

base, and collector. The emitter layer is heavily
doped, with the base and collector only lightly doped.
The outer layers have widths much greater than the
sandwiched p- or n-type material. The ratio of the total
width to that of the center layer is 0.150/0.001 = 150:1.
The doping of the sandwiched layer is also
considerably less than that of the outer layers
(typically, 1:10 or less). This lower doping level
decreases the conductivity (increases the resistance)
of this material by limiting the number of “free” carriers.

Figure 7.2 Types of transistors: (a) pnp; (b) npn. (left)

For the biasing shown in Fig. 7.2 the terminals have been indicated by the capital letters E for emitter, C for
collector, and B for base. The abbreviation BJT, from bipolar junction transistor, is often applied to this three-
terminal device. The term bipolar reflects the fact that holes and electrons participate in the injection process
into the oppositely polarized material. If only one carrier is employed (electron or hole), it is considered a
unipolar device (e.g. Schottky diode).
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BASIC OPERATION
The basic operation of the transistor will now be described using the pnp transistor of Fig. 7.2a. The operation
of the npn transistor is exactly the same if the roles played by the electron and hole are interchanged. In Fig.
7.3a the pnp transistor has been redrawn without the base-to-collector bias. Note the similarities between this
situation and that of the forward-biased diode. The depletion region has been reduced in width due to the
applied bias, resulting in a heavy flow of majority carriers from the p- to the n-type material.

Figure 7.3 Biasing a transistor: (a) forward-bias; (b) reverse-bias.

Let us now remove the base-to-emitter bias of the pnp

transistor of Fig. 7.2a as shown in Fig. 7.3b. Consider the
similarities between this situation and that of the reverse-
biased diode. Recall that the flow of majority carriers is zero,
resulting in only a minority-carrier flow, as indicated in Fig.
7.3b. In summary, therefore:

One p–n junction of a transistor is reverse-biased, whereas

the other is forward-biased.

Figure 7.4 Majority and minority carrier flow

of a pnp transistor (left)

In Fig. 7.4 both biasing potentials have been applied to a pnp transistor, with the resulting majority- and minority-
carrier flows indicated. Note the widths of the depletion regions, indicating clearly which junction is forward-biased
and which is reverse-biased. As indicated, a large number of majority carriers will diffuse across the forward- biased
p–n junction into the n-type material. The question then is whether these carriers will contribute directly to the base
current IB or pass directly into the p-type material. Since the sandwiched n-type material is very thin and has a low
conductivity, a very small number of these carriers will take this path of high resistance to the base terminal. The
magnitude of the base current is typically on the order of microamperes, as compared to milliamperes for the emitter
and collector currents. The larger number of these majority carriers will diffuse across the reverse-biased junction
into the p-type material connected to the collector terminal. The reason for the relative ease with which the majority
carriers can cross the reverse-biased junction is easily understood if we consider that for the reverse-biased diode
the injected majority carriers will appear as minority carriers in the n-type material. In other words, there has been an
injection of minority carriers into the n-type base region
3

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material. Combining this with the fact that all the minority carriers in the depletion region will cross the reverse-
biased junction of a diode accounts for the flow indicated in Fig. 7.4.

Applying Kirchhoff’s current law to the transistor of Fig. 7.4 as if it were a single node, we obtain

Eq. 7.0 Transistor Currents

and find that the emitter current is the sum of the collector and base currents. The collector current, however,
comprises two components—the majority and the minority carriers. The minority-current component is
called the leakage current ICO (IC current with emitter terminal Open). The collector current, therefore, is
determined in total by
Eq. 7.1 Collector Current

For general-purpose transistors, IC is measured in milliamperes and ICO is measured in microamperes or

nanoamperes. ICO, like Is for a reverse -biased diode, is temperature sensitive and must be examined carefully
when applications of wide temperature ranges are considered. It can severely affect the stability of a system at
high temperature if not considered properly. Improvements in construction techniques have resulted in
significantly lower levels of ICO, to the point where its effect can often be ignored.

COMMON-BASE CONFIGURATION
The common-base terminology is derived from the fact that the base is common to both the input and output
sides of the configuration. In addition, the base is usually the terminal closest to, or at, ground potential. See
figure below.
Note: Throughout the discussion, all current directions
will refer to conventional (hole) flow rather than electron
flow. The result is that the arrows in all electronic
symbols have a direction defined by this convention.
Recall that the arrow in the diode symbol defined the
direction of conduction for conventional current. For the
transistor: The arrow in the graphic symbol defines the
direction of emitter current (conventional flow) through
the device.

Figure 7.5 Notation and symbols used with

the common-base configuration:
(a) pnp transistor; (b) npn transistor.

All the current directions appearing in Fig. 7.5 are the

actual directions as defined by the choice of
conventional flow. Note in each case that IE = IC + IB.
Note also that the applied biasing (voltage sources) are such as to establish current in the direction indicated
for each branch. That is, compare the direction of IE to the polarity of VEE for each configuration and the
direction of IC to the polarity of VCC.

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To fully describe the behavior of a three-terminal device such as the common-base amplifiers requires two sets
of characteristics—one for the driving point or input parameters and the other for the output side. The input set
for the common-base amplifier as shown in Fig. 7.6 relates an input current (IE) to an input voltage (VBE) for
various levels of output voltage (VCB).

Figure 7.6 Input or driving point characteristics Figure 7.7 Output or collector characteristics
for a common-base silicon transistor amplifier. for a common-base transistor amplifier.

The output set relates an output current (IC) to an output voltage (VCB) for various levels of input current (IE)
as shown in Fig. 3.8. The output or collector set of characteristics has three basic regions of interest, as
indicated in Fig. 7.7: the active, cutoff, and saturation regions. The active region is the region normally
employed for linear (undistorted) amplifiers. In particular: In the active region the base–emitter junction is
forward-biased, whereas the collector– base junction is reverse-biased. As inferred by its name, the cutoff
region is defined as that region where the collector current is 0 A. In addition: In the cutoff region the base–
emitter and collector–base junctions of a transistor are both reverse-biased. The saturation region is
defined as that region of the characteristics to the left of VCB = 0 V. The horizontal scale in this region was
expanded to clearly show the dramatic change in characteristics in this region. Note the exponential increase in
collector current as the voltage VCB increases toward 0 V. In the saturation region the base–emitter and
collector–base junctions are forward-biased.
Note: Once a transistor is in the “on” state, the base-to-emitter voltage will be assumed to be the following:
VBE = 0.7 V.
Alpha (a). In the dc mode the levels of IC and IE due to the majority carriers are related by a quantity called
alpha and defined by the following equation:
Eq. 7.2 DC alpha

where IC and IE are the levels of current at the point of operation. Even though the characteristics
of Fig. 3.8 would suggest that a = 1, for practical devices alpha typically extends
5

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from 0.90 to 0.998, with most values approaching the high end of the range. Since alpha is defined solely for
the majority carriers, Eq. 7.1 becomes
Eq. 7.3 Collector current
For ac situations where the point of operation
moves on the characteristic curve, an ac alpha is
defined by Eq. 7.4 AC alpha

The ac alpha is formally called the common-base, short-circuit, amplification factor.

COMMON-EMITTER CONFIGURATION
The most frequently encountered
transistor configuration appears in Fig.
7.8 for the pnp and npn transistors. It is
called the common-emitter configuration
because the emitter is common to both
the input and output terminals (in this
case common to both the base and
collector terminals).

Figure 7.8 Notation and symbols used

with the common-emitter configuration:
(a) npn transistor; (b) pnp transistor.

Two sets of characteristics are again

necessary to describe fully the behavior of
the common-emitter configuration: one for
the input or base–emitter circuit and one
for the output or collector–emitter circuit.
Both are shown in Fig. 7.9.

The emitter, collector, and base currents are shown in their actual conventional current direction. Even though
the transistor configuration has changed, the current relations developed for the common-base configuration
are still applicable. That is, IE = IC + IB and IC = a IE.
For the common-emitter configuration the output characteristics are a plot of the output current (IC) versus output
voltage (VCE) for a range of values of input current (IB). The input characteristics are a plot of the input current (IB)
versus the input voltage (VBE) for a range of values of output voltage (VCE). The active region for the common-
emitter configuration is that portion of the upper-right quadrant that has the greatest linearity, that is, that region in
which the curves for IB are nearly straight and equally spaced. In Fig. 7.9a, this region exists to the right of the

vertical dashed line at VCEsat and above the curve for IB equal to zero. The region to the left of VCEsat is called
the saturation region. In the active region of a common-emitter amplifier, the base– emitter junction is
forward-biased, whereas the collector–base junction is reverse-biased. You will recall that these were the
same conditions that existed in the active region of the common-base configuration. The
6

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active region of the common-emitter configuration can be employed for voltage, current, or power amplification.
The cutoff region for the common-emitter configuration is not as well defined as for the common-base
configuration. Note on the collector characteristics of Fig. 7.9 that IC is not equal to zero when IB is zero. For
the common-base configuration, when the input current IE was equal to zero, the collector current was equal
only to the reverse saturation current ICO, so that the curve IE = 0 and the voltage axis were, for all practical
purposes, one. The collector current defined by the condition IB = 0 mA will be assigned the notation indicated
by the following equation:
Eq. 7.5 Collector Current
for IB = 0 mA

For linear (least distortion) amplification purposes, cutoff for the common-emitter configuration will be
defined by IC = ICEO.

Figure 7.9 Characteristics of a silicon transistor in the common-emitter configuration:

(a) collector characteristics; (b) base characteristics.
Beta (b). In the dc mode the levels of IC and IB are related by a quantity called beta and defined by
the following equation:

Eq. 7.6 DC beta

where IC and IB are determined at a particular operating point on the characteristics. For
practical devices the level of b typically ranges from about 50 to over 400, with most in the
midrange.

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On specification sheets bdc is usually included as hFE with the italic letter h derived from an ac hybrid
equivalent circuit.. The subscript FE is derived from forward-current amplification and common-emitter
configuration, respectively.

For ac situations an ac beta is defined as follows: Eq. 7.7 AC beta

The formal name for bac is common-emitter, forward-current, amplification factor. Since the collector
current is usually the output current for a common-emitter configuration and the base current is the input
current, the term amplification is included.

Derivations: A relationship can be developed between b and a using the basic relationships introduced thus
far. Using b = IC / IB, we have IB = IC / b, and from a = IC / IE we have IE = IC / a.

Eq. 7.8
Alpha and Beta

COMMON-COLLECTOR CONFIGURATION
The third and final transistor configuration is
the common-collector configuration, shown in
Fig. 7.10 with the proper current directions
and voltage notation. The common-collector
configuration is used primarily for
impedance-matching purposes since it has
a high input impedance and low output
impedance, opposite to that of the common-
base and common-emitter configurations.

Figure 7.10 Notation and symbols used with

the common-collector configuration:
(a) pnp transistor; (b) npn transistor.

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A common-collector circuit configuration is provided in Fig. 3.21 with the load

resistor connected from emitter to ground. Note that the collector is tied to
ground even though the transistor is connected in a manner similar to the
common-emitter configuration. For all practical purposes, the output
characteristics of the common-collector configuration are the same as for the
common-emitter configuration. For the common-collector configuration the
output characteristics are a plot of IE versus VCE for a range of values of IB.
The input current, therefore, is the same for both the common- emitter and
common-collector characteristics. The horizontal voltage axis for the
common-collector configuration is obtained by simply changing the sign of
the collector-to-emitter voltage of the common-emitter characteristics.
Figure 7.11 Common-collector
used for impedance-matching.

LIMITS OF OPERATION. For each transistor there is a region of operation on the characteristics that will
ensure that the maximum ratings are not being exceeded and the output signal exhibits minimum distortion.

The maximum dissipation level is defined by:

If the characteristic curves are unavailable or do not Eq. 7.9

appear on the specification sheet (as is often the case), Limits and
one must simply be sure that IC, VCE, and their product Range of
VCEIC fall into the following range: Operation

For the common-base characteristics the maximum

power curve is defined by the product of output quantities:

2) Activity 3: Skill-building Activities (Answers can be found in Keys to Correction)

a.1 Determine bDC and the emitter current IE for a transistor where IB = 50 mA and IC = 3.65 mA.
a.2 The maximum dissipation level is equal to 300 mW. If we choose IC to be the maximum value of 50 mA,
what is the voltage across collector-emitter?

b.1 Given an aDC of 0.998, determine IC if IE = 4 mA.

b.2 Determine aDC if IE = 2.8 mA, IC = 2.75 mA and ICBO = 0.1 mA.

c.1 Given that aDC = 0.980, determine the corresponding value of bDC.
c.2 Given bDC = 120, determine the corresponding value of a.
c.3 Given that bDC = 120 and IC = 2.0 mA, find IE and IB.

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3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What do you know about the three-
terminal devices like transistors?
2. What is meant by “bipolar” in
electronics?
3. Could you identify important
characteristics of a transistor?

4) Activity 5: Check for Understanding (This is an assessment.)

Job-Interview Questions: Answer the following items briefly. Label all required diagrams completely.

a.1 What names are applied to the two types of BJT transistors? Sketch the basic construction of each and
label the various minority and majority carriers in each. Draw the graphic symbol next to each.

a.2 What is the major difference between a bipolar and a unipolar device?

b.1 How must the two transistor junctions be biased for proper transistor amplifier operation?
b.2 What is the source of the leakage current in a transistor?
b.3 Which of the transistor currents is always the largest? Which is always the smallest? Which two currents
are relatively close in magnitude?

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

Which strategy worked for you, easily? With difficulty?

FAQs

1. How do we test transistors?

As with diodes, there are three routes one can take to check a transistor: use of a curve tracer, a digital meter,
and an ohmmeter.

2. What is Moore’s Law?

Moore’s law predicts that the transistor count of an integrated circuit will double every 2 years. First presented
in a paper by Gordon E. Moore in 1965, the prediction has had an amazing accuracy level.

10

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Name: ___________________________________________________________ Class number: ________

Section: ____________ Schedule: _____________________________________ Date: _______________

Lesson Title: Materials:

BJT Biasing and Direct Current Analysis – Part 1 Pencil, paper, and calculator

Transistor Operating Points References:

Common-Emitter Configuration 1. Electronic Devices and Circuit
Fixed Bias Theory, 11th Edition by R.
Emitter Bias Boylestad & L. Nashelsky (2013);
Voltage-Divider Bias
Collector-Feedback 2. Electronic Devices:
Conventional Current Version, 9th
Lesson Objectives: Edition by Thomas Floyd (2012);
At the end of this lesson, you should be able to:
● determine the dc levels for the BJT common-emitter configuration; 3. Electronic Principles, 8th
● measure the important voltage levels of a BJT common-emitter Edition by Albert Malvino and
configuration and use them to determine whether the network is David J. Bates (2016);
operating properly;
● determine saturation and cutoff conditions of a BJT network and 4. Grob’s Basic Electronics, 12th
the expected voltage and current levels established by each Edition by Mitchel E. Schultz,
condition. (2016).

Productivity Tip: Life is like riding a bicycle. Only by keeping balance can we move forward.
Live a balanced life!

A. LESSON PREVIEW/REVIEW
1) Introduction

Welcome back! Today, you will learn the basic analysis of the transistor amplifier circuits! The analysis
or design of a transistor amplifier requires a knowledge of both the dc and the ac response of the system. Too
often it is assumed that the transistor is a magical device that can raise the level of the applied ac input without
the assistance of an external energy source.

In actuality, any increase in ac voltage, current, or power is the result of a transfer of energy from the
applied dc supplies. The analysis or design of any electronic amplifier therefore has two components: a dc and
an ac portion.

Fortunately, the superposition theorem is applicable, and the investigation of the dc conditions can be
totally separated from the ac response. However, you must keep in mind that during the design or synthesis
stage the choice of parameters for the required dc levels will affect the ac response, and vice versa. The dc
level of operation of a transistor is controlled by a number of factors, including the range of possible operating
points on the device characteristics. In the previous module, we specified the range for the bipolar junction
transistor (BJT) amplifier. Once the desired dc current and voltage levels have been defined, a network must
be constructed that will establish the desired operating point.
1

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2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)

1. What is meant by the term “biasing”?
2. What are the regions of operation of
the transistor and the necessary
conditions to operate in these regions?
3. How does a transistor work as
an amplifier?

B. MAIN LESSON
1) Activity 2: Content Notes

TRANSISTOR OPERATING POINTS

The term biasing is an all-inclusive
term for the application of dc voltages
to establish a fixed level of current
and voltage. For transistor amplifiers
the resulting dc current and voltage
establish an operating point on the
characteristics that define the region
that will be employed for amplification
of the applied signal. Because the
operating point is a fixed point on the
characteristics, it is also called the
quiescent point (Q-point). By
definition, quiescent means quiet, still,
inactive.

Figure 8.1 Various operating points

within the limits of operation of a
transistor

The biasing circuit can be designed to set the device operation at any of these points or others within the active
region. The maximum ratings are indicated on the characteristics of Fig. 8.1 by a horizontal line for the maximum
collector current ICmax and a vertical line at the maximum collector-to-emitter voltage VCEmax. The maximum
power constraint is defined by the curve PCmax in the same figure. At the lower end of the scales are the cutoff

region, defined by IB £ 0 mA, and the saturation region, defined by VCE £ VCEsat. The BJT device could be biased
to operate outside these maximum limits, but the result of such operation would be either a considerable shortening
of the lifetime of the device or destruction of the device. Confining ourselves to the active region, we can select
many different operating areas or points. The chosen Q-point often depends on the intended use of

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the circuit. Still, we can consider some differences among the various points shown in Fig. 8.1 to present some
basic ideas about the operating point and, thereby, the bias circuit.

For the BJT to be biased in its linear or active operating region the following must be true:
1. The base–emitter junction must be forward-biased (p-region voltage more positive), with a resulting forward-
bias voltage of about 0.6 V to 0.7 V.
2. The base–collector junction must be reverse-biased (n-region more positive), with the reverse-bias voltage
being any value within the maximum limits of the device.

Note that for forward bias the voltage across the p–n junction is p-positive, whereas for reverse bias it is
opposite (reverse) with n-positive.

Operation in the cutoff, saturation, and linear regions of the BJT characteristic are provided as follows:
1. Linear-region operation: Base–emitter junction forward-biased Base–collector junction reverse-biased
2. Cutoff-region operation: Base–emitter junction reverse-biased Base–collector junction reverse-biased
3. Saturation-region operation: Base–emitter junction forward-biased Base–collector junction forward-biased

COMMON-EMITTER CONFIGURATION
Fixed Bias Configuration. The fixed-bias circuit of Fig. 8.2 is the simplest transistor dc bias configuration.
Even though the network employs an npn transistor, the equations and calculations apply equally well to a pnp
transistor configuration merely by changing all current directions and voltage polarities. The current directions
of Fig. 8.2 are the actual current directions, and the volt- ages are defined by the standard double-subscript
notation. For the dc analysis the network can be isolated from the indicated ac levels by replacing the
capacitors with an open-circuit equivalent because the reactance of a capacitor is a function of the applied
frequency. For dc, f = 0 Hz, and XC = 1 / [2*pi*f*C] = 1 / [2*pi*0*C] = ¥ W. In addition, the dc supply VCC can
be separated into two supplies (for analysis purposes only) as shown in Fig. 8.3 to permit a separation of input
and output circuits. It also reduces the linkage between the two to the base current IB. The separation is
certainly valid, as we note in Fig. 8.3 that VCC is connected directly to RB and RC just as in Fig. 8.2.

Figure 8.2 Figure 8.3

Fixed-bias circuit DC equivalent of fixed-bias circuit.
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Base-emitter loop:
Eq. 8.1 Base current
for fixed bias

The base current is the current through RB and by Ohm’s law that current is
the voltage across RB divided by the resistance RB. The voltage across RB is
the applied voltage VCC at one end less the drop across the base-to-emitter
junction (VBE). In addition, because the supply voltage VCC and the base–
emitter voltage VBE are constants, the selection of a base resistor RB sets
the level of base current for the operating point.

Collector-emitter loop:
Eq. 8.2 Collector
current for fixed bias

It is interesting to note that because the base current is controlled by the level
of RB and IC is related to IB by a constant b, the magnitude of IC is not a
function of the resistance RC. Changing RC to any level will not affect the level
of IB or IC as long as we remain in the active region of the device. However,
as we shall see, the level of RC will determine the magnitude of VCE, which is
an important parameter.

Eq. 8.3 Various

voltages for fixed bias

Keep in mind that voltage levels such as VCE are determined by placing the
positive lead (normally red) of the voltmeter at the collector terminal with the
negative lead (normally black) at the emitter terminal as shown in Fig. 8.4. VC
is the voltage from collector to ground and is measured as shown in the same
figure. In this case the two readings are identical, but in the networks to follow
the two can be quite different. Clearly understanding the differ - ence between
the two measurements can prove to be quite important in the troubleshooting
of transistor networks.

Figure 8.4 Measuring VCE and VC.

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Transistor Saturation. The term saturation is applied to any system where

levels have reached their maximum values. For a transistor operating in the
saturation region, the current is a maximum value for the particular design.
Change the design and the corresponding saturation level may rise or drop.
Of course, the highest saturation level is defined by the maximum collector
current as provided by the specification sheet. Saturation conditions are
normally avoided because the base–collector junction is no longer reverse-
biased and the output amplified signal will be distorted.

Figure 8.5 Determining ICsat Eq. 8.4 Collector Current

for the fixed-bias. Saturation for fixed bias

Load-Line Analysis. In load-line analysis, the load (network resistors) of the network defines the slope of the
straight line connecting the points defined by the network parameters. The characteristics of the BJT are
superimposed on a plot of the network equation defined by the same axis parameters. The load resistor RC for
the fixed-bias configuration will define the slope of the network equation and the resulting intersection between
the two plots. The smaller the load resistance, the steeper the slope of the network load line.

Figure 8.6 Fixed-bias load line. Figure 8.7 Movement of the Q-point
with increasing level of IB.

By joining the two points defined by VCE = VCC - ICRC ( VCE = VCC when IC = 0, and IC = VCC / RC when
VCE = 0), you can draw the straight line. The resulting line on the graph of Fig. 8.6 is called the load line
because it is defined by the load resistor RC. By solving for the resulting level of IB, we can establish the actual
Q-point as shown in same figure.

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Figure 8.8 Effect of an increasing level of RC Figure 8.9 Effect of lower values of VCC
on the load line and the Q-point. on the load line and the Q-point.

If the level of IB is changed by varying the value of RB, the Q-point moves up or down the load line as shown in
Fig. 8.7 for increasing values of IB. If VCC is held fixed and RC increased, the load line will shift as shown in
Fig. 8.8. If IB is held fixed, the Q-point will move as shown in the same figure. If RC is fixed and VCC
decreased, the load line shifts as shown in Fig. 8.9.

Emitter Bias. The dc bias network

of Fig. 8.10 contains an emitter
resistor to improve the stability
level over that of the fixed-bias
configuration. The more stable a
configuration, the less its response
will change due to undesirable
changes in temperature and
parameter variations. The
improved stability will be
demonstrated through a numerical
example later in the section. The
analysis will be performed by first
examining the base–emitter loop
and then using the results to
investigate the collector–emitter
loop. Figure 8.10 BJT bias circuit Figure 8.11 DC Equivalent
with emitter resistor of emitter bias
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Base-emitter loop:

Eq. 8.5 Base current

for emitter bias

Collector-emitter loop:

Eq. 8.6 Various voltages in emitter bias

Improved Bias Stability. The addition of the emitter resistor to the dc bias of the
BJT provides improved stability, that is, the dc bias currents and voltages
remain closer to where they were set by the circuit when outside conditions,
such as temperature and transistor beta, change.

Saturation Level. The collector saturation level or maximum collector current for
an emitter-bias design can be determined using the same approach applied to
the fixed-bias configuration: Apply a short circuit between the collector–emitter
terminals as shown in Fig. 8.9 and calculate the resulting collector current.

Figure 8.9 Determining ICsat Eq. 8.7 Collector Current

for the emitter-stabilized bias circuit.

The addition of the emitter resistor reduces the collector saturation level below
that obtained with a fixed-bias configuration using the same collector resistor.

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Load-Line Analysis. The load-line analysis of the emitter-bias

network is only slightly different from that encountered for the
fixed-bias configuration. The level of IB as determined by Eq.
8.5 defines the level of IB on the characteristics of Fig. 8.10
(denoted IBQ).

Different levels of IBQ will, of course, move the Q-point up or

down the load line.

Figure 8.10 Load line for the emitter-bias configuration.

(right)
Voltage-Divider Bias. The voltage-divider bias configuration of
Fig. 8.11 is a network with a bias circuit that is less dependent
on, or in fact is independent of, the transistor beta. If analyzed
on an exact basis, the sensitivity to changes in
beta is quite small. If the circuit parameters are properly chosen,
the resulting levels of ICQ and VCEQ can be almost totally independent of beta.

Figure 8.11 Voltage-divider bias configuration Figure 8.12 Q-point for the voltage-divider bias

There are two methods that can be applied to analyze the voltage-divider configuration. The first to be
demonstrated is the exact method, which can be applied to any voltage-divider configuration. The second is
referred to as the approximate method and can be applied only if specific conditions are satisfied. The
approximate approach permits a more direct analysis with a savings in time and energy.

Exact Analysis. For the dc analysis the network of Fig. 8.11 can be redrawn as shown in Fig. 8.13. The input
side of the network can then be redrawn as shown in Fig. 8.14 for the dc analysis. The Thévenin equivalent
network for the network to the left of the base terminal can then be found:
8

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Eq. 8.8
RTh

Figure 8.13 DC components Figure 8.14 Determining RTh.

of the voltage-divider.

Eq. 8.9 ETh

Figure 8.15 ETh and

Thévenin equivalent
circuit. Eq. 9.10 Base current
for voltage-divider

Approximate Analysis. The input section of the voltage-

divider configuration can be represented by the network of
Fig. 4.36. The resistance Ri is the equivalent resistance
between base and ground for the transistor with an emitter
resistor RE. The reflected resistance between base and
emitter is defined by Ri = (b + 1)RE. If Ri is much larger
than the resistance R2, the current IB will be much smaller
than I2 (current always seeks the path of least resistance)
and I2 will be approximately equal to I1.

Figure 8.16 Calculating the approximate base voltage

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If we accept the approximation that IB is essentially 0 A compared to I1 or I2, then I1 = I2, and R1 and R2 can
be considered series elements. The voltage across R2, which is actually the base voltage, can be determined
using the voltage-divider rule (hence the name for the configuration).

If this condition is satisfied, then:

Eq. 9.11 Approximate values for

voltage-divider configuration\

Transistor Saturation. The output collector–emitter circuit for the voltage-divider configuration has the same
appearance as the emitter-biased circuit. The resulting equation for the saturation current (when VCE is set to
0 V on the schematic) is therefore the same as obtained for the emitter-biased configuration.

Load-Line Analysis. The similarities with the output circuit of the emitter-biased configuration result in the same
intersections for the load line of the voltage-divider configuration.

Collector-Feedback. An improved level of stability

can also be obtained by introducing a feedback path
from collector to base as shown in Fig. 8.17.
Although the Q-point is not totally independent of
beta (even under approximate conditions), the
sensitivity to changes in beta or temperature
variations is normally less than encountered for the
fixed-bias or emitter-biased configurations.

Figure 8.17 DC bias circuit with voltage feedback.

Base-emitter
loop:

Eq. 9.12 Base current

of collector-feedback

10

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Collector-emitter loop:

Eq. 9.13 Collector-emitter

voltage for collector-feedback

* exactly as obtained for the emitter-bias and voltage-divider bias configurations.

Saturation Conditions. Using the approximation IC’ = IC, we find that the equation for the saturation current is
the same as obtained for the voltage-divider and emitter-bias configurations.
Load-Line Analysis. Continuing with the approximation IC’ = IC results in the same load line defined for the voltage-
divider and emitter-biased configurations. The level of IBQ is defined by the chosen bias configuration.

2) Activity 3: Skill-building Activities (Answers can be found on Keys to Correction)

Solve completely the following networks. Indicate the loop and the corresponding equations before substitution
of values. Box your final answers.

a. Determine the following values for the fixed-bias

configuration in the figure to the right.

IBQ and ICQ,

VCEQ, VB, and VC

VBC

11

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b. For the emitter-bias network in the figure to the

left, determine:

IBQ and ICQ,

VCEQ, VC, VB, VE

VBC

c.1 Determine the dc bias voltage VCE and the current

IC for the voltage-divider configuration on the right using
exact analysis.

c.2 Determine the dc bias voltage VCE and the current

IC for the voltage-divider configuration on the right using
approximate analysis.

d. Determine the dc bias voltage VCE and the current IC for the
collector-feedback network on the left.

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3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is meant by the term “biasing”?
2. What are the regions of operation of
the transistor and the necessary
conditions to operate in these regions?
3. How does a transistor work as an
amplifier?

4) Activity 5: Check for Understanding

This part is an assessment. Solve completely the following networks. Indicate the loop and the corresponding
equations before substitution of values. Box your final
answers.

a. Given the network on the right,

find ICQ and VCEQ if beta is equal to 248.

b. Given the network on the right,

find VCEQ and IEQ.

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

What portion/s of the lesson you found easy? Difficult?
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FAQs

1. What is a transistor switch? How does it work?

The figure below illustrates the basic operation of a BJT as a switching device. In part (a), the transistor is in the
cutoff region because the base-emitter junction is not forward-biased. In this condition, there is, ideally, an open
between collector and emitter, as indicated by the switch equivalent. In part (b), the transistor is in the saturation
region because the base- emitter junction and the base-collector junction are forward-biased and the base current is
made large enough to cause the collector current to reach its saturation value. In this condition, there is, ideally, a
short between collector and emitter, as indicated by the switch equivalent. Actually, a small voltage drop across the
transistor of up to a few tenths of a volt normally occurs, which is the saturation voltage, VCE(sat).

Conditions in Cutoff As mentioned before, a transistor is in the cutoff region when the base-emitter junction is
not forward-biased. Neglecting leakage current, all of the currents are zero, and VCE at cutoff is equal to VCC.
Conditions in Saturation As you have learned, when the base-emitter junction is forward-biased and there is
enough base current to produce a maximum collector current, the transistor is saturated.

Since VCE(sat) is very small compared to VCC, it can usually be neglected. The minimum value of base
current needed to produce saturation is

Normally, IB should be significantly greater than IB(min) to ensure that the transistor is saturated.

2. What is a phototransistor?
In a phototransistor the base current is produced when light strikes the photosensitive semiconductor base
region. The collector-base pn junction is exposed to incident light through a lens opening in the transistor
package. When there is no incident light, there is only a small thermally generated collector-to-emitter leakage
current, ICEO; this dark current is typically in the nA range. When light strikes the collector-base pn junction, a
base current, Il, is produced that is directly proportional to the light intensity. This action pro- duces a collector
current that increases with Il. Except for the way base current is generated, the phototransistor behaves as a
conventional BJT. In many cases, there is no electrical connection to the base.

14

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Lesson Title: Materials:

BJT Biasing and Direct Current Analysis – Part 2 Pencil, paper, and calculator

References:
Common-Base Configuration 1. Electronic Devices and Circuit
Miscellaneous Configuration Theory, 11th Edition by R.
Multiple BJT Networks Boylestad & L. Nashelsky (2013);

2. Electronic Devices:
Lesson Objectives: Conventional Current Version, 9th
Edition by Thomas Floyd (2012);
At the end of this lesson, you should be able to:
● determine the dc levels for the BJT common-base and 3. Electronic Principles, 8th
miscellaneous configurations; Edition by Albert Malvino and
● measure the important voltage levels of a BJT common-base and David J. Bates (2016);
miscellaneous configurations and use them to determine whether the
network is operating properly; 4. Grob’s Basic Electronics, 12th
● determine the dc levels for multiple BJT networks. Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: Stress, when properly regulated, is beneficial to the physiological development.
Regulate stress by practicing mindfulness and self-compassion. Breathe!

A. LESSON PREVIEW/REVIEW
1) Introduction

Congratulations on making it to the second part of the discussion on BJT biasing! As you already know, a
transistor must be properly biased with a dc voltage in order to operate as a linear amplifier. A dc operating
point must be set so that signal variations at the input terminal are amplified and accurately reproduced at the
output terminal. As you learned in the previous modules, when you bias a transistor, you establish the dc
voltage and current values. This means, for example, that at the dc operating point, IC and VCE have specified
values. The dc operating point is often referred to as the Q-point (quiescent point).

Bias establishes the dc operating point (Q-point) for proper linear operation of an amplifier. If an amplifier is
not biased with correct dc voltages on the input and output, it can go into saturation or cutoff when an input
signal is applied. Figure 9.1 shows the effects of proper and improper dc biasing of an inverting amplifier. In
part (a), the output signal is an amplified replica of the input signal except that it is inverted, which means that it
is 180° out of phase with the input. The output signal swings equally above and below the dc bias level of the
output, VDC(out).

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Figure 9.1 Linear and nonlinear operation of an amplifier

Improper biasing can cause distortion in the output signal, as illustrated in parts (b) and (c). Part (b)
illustrates limiting of the positive portion of the out- put voltage as a result of a Q-point (dc operating point)
being too close to cutoff. Part (c) shows limiting of the negative portion of the output voltage as a result of a dc
operating point being too close to saturation.

Let us now continue our discussion for the remaining transistor configurations!

2) Activity 1: What I Know Chart, part 1

What I Know Questions: What I Learned (Activity 4)

1. What is the most stable transistor
bias circuit for an amplifier?
2. How do the dc analysis npn
and pnp BJT networks differ?
3. What are multiple BJT networks?

B. MAIN LESSON
1) Activity 2: Content Notes

COMMON-BASE CONFIGURATION
The common-base configuration is unique in that the applied signal is connected to the emitter terminal and the
base is at, or just above, ground potential. It is a fairly popular configuration because in the ac domain it has a
very low input impedance, high output impedance, and good gain. A typical common-base configuration
appears in Fig. 9.2. Note that two supplies are used in this configuration and the base is the common terminal
between the input emitter terminal and output collector terminal.

Eq. 9.1 Emitter Current

for Common-base
Figure 9.2 Common-base configuration. Figure 9.3 Input dc equivalent
2

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Applying Kirchhoff’s voltage law to the entire outside perimeter:

Eq. 9.2 Various voltages for common-base configuration

MISCELLANEOUS CONFIGURATION
There are a number of BJT bias configurations that do not match the basic mold of those analyzed in
the previous sections. In fact, there are variations in design that would require many more pages than is
possible in a single publication. However, the primary purpose here is to emphasize those characteristics of the
device that permit a dc analysis of the configuration and to establish a general procedure toward the desired
solution. For each configuration discussed thus far, the first step has been the derivation of an expression for
the base current. Once the base current is known, the collector current and voltage levels of the output circuit
can be determined quite directly. This is not to imply that all solutions will take this path, but it does suggest a
possible route to follow if a new configuration is encountered.
The first example is simply one where the emitter resistor has been
dropped from the voltage-feedback configuration of Fig. 9.4. The
analysis is quite similar, but does require dropping RE from the
applied equation.

Figure 9.4 Voltage-feedback

without emitter resistor

Figure 9.5 Miscellaneous configuration

3

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Table 9.1 Review of

the most common
single-stage
BJT configurations

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MULTIPLE BJT NETWORKS

This part of the module will cover some of the most popular networks using multiple transistors. It will demonstrate
how the methods introduced thus far in this chapter can be applied to networks with any number of components.
The R–C coupling of Fig. 9.6 is probably the most common. The collector output of one stage is fed directly into the
base of the next stage using a coupling capacitor CC. The capacitor is chosen to ensure that it will block dc between
the stages and act like a short circuit to any ac signal. The network of Fig. 9.6 has two voltage-divider stages, but
the same coupling can be used between any combination of networks such as the fixed-bias or emitter-follower
configurations. Substituting an open-circuit equivalent for CC and the other capacitors of the network will result in
the two bias arrangements shown in Fig. 9.7. The methods of analysis introduced in this chapter can then be applied
to each stage separately since one stage will not affect the other.

Figure 9.6 R–C coupled BJT amplifiers.

Figure 9.7 DC equivalent of the R–C coupled BJT amplifiers

Darlington Configuration. The Darlington configuration of Fig. 9.8 feeds the output of one stage directly into
the input of the succeeding stage. Since the output is taken directly off the emitter terminal, the ac gain is very
close to 1 but the input impedance is very high, making it attractive for use in amplifiers operating off sources

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that have a relatively high internal resistance. If a load resistor were added to the collector leg and the output
taken off the collector terminal, the configuration would provide a very high gain.

Figure 9.8 Darlington amplifier. Figure 9.8 DC equivalent of Darlington.

Eq. 9.3 Darlington beta or super-beta

Eq. 9.4 Base current of Q1

Eq. 9.4 Various voltages for Q2

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Cascode Configuration. The cascode configuration of Fig. 9.9 ties the collector of one transistor to the emitter
of the other. In essence it is a voltage-divider network with a common-base configuration at the collector. The
result is a network with a high gain and a reduced Miller capacitance .

Figure 9.9 Cascode configuration and its DC equivalent

Eq. 9.5 Currents and voltages

for cascode configuration
7

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Feedback Pair. The feedback pair shown in Fig. 9.10 employs both an npn and pnp transistor. The result is a
configuration that provides high gain with increased stability.

Figure 9.10 Feedback pair amplifier and its DC equivalent

Eq. 9.6 Currents and voltages

for feedback-pair amplifier

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Direct Coupled Amplifier. The last multistage configuration is the direct coupled amplifier such as appearing
in Figure 9.11. Note the absence of a coupling capacitor to isolate the dc levels of each stage. The dc levels in
one stage will directly affect the dc levels in succeeding stages. The benefit is that the coupling capacitor
typically limits the low-frequency response of the amplifier. Without coupling capacitors, the amplifier can
amplify signals of very low frequency—in fact down to dc. The disadvantage is that any variation in dc levels
due to a variety of reasons in one stage can affect the dc levels in the succeeding stages of the amplifier.

Figure 9.11 Direct coupled amplifier and its DC equivalent

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2) Activity 3: Skill-building Activities (Answers found in Keys to Correction)

a. Determine the currents IE and IB

and the voltages VCE and VCB
for the common-base configuration on the right.

b. Determine VC and VB
for the voltage-divider network on the left.

c. Given VB = 4 V for the network on the right,

determine IB and beta.

d. For the network on the left,

determine VCE.

3) Activity 4: What I Know Chart, part 2 (2 mins)

What I Know Questions: What I Learned (Activity 4)
1. What is the most stable transistor
bias circuit for an amplifier?
2. How do the dc analysis npn and
pnp BJT networks differ?
3. What are multiple BJT networks?

10

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4) Activity 5: Check for Understanding

This is an assessment. Show complete solutions to the following items. Begin with redrawing the dc network
before writing the pertinent equations and making substitutions. Box your final answers.

a. For the network below, b. For the Darlington amplifier,

determine IB, IC, VE and VCE. determine the voltages VC1, VC2, VE1, and VE2.

c. For the cascode amplifier,

determine VB1, VB2, VE1, VC1, VE2, and VC2.

d. For the feedback amplifier,

determine the base, emitter, and collector
voltages of each transistor.

11

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C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

Which strategy worked for you, easily? With difficulty?

FAQs

1. Are current mirrors amplifiers?

No. The current mirror is a dc network in which the current through a load is controlled by a current at another
point in the network. That is, if the controlling current is raised or lowered the current through the load will
change to the same level. The discussion to follow will demonstrate that the effectiveness of the design is
dependent on the fact that the two transistors employed have identical characteristics.

2. Do networks with pnp transistors differ in analysis from networks with npn transistors?
The analysis of pnp transistors follows the same pattern established for npn transistors. The level of I B is first
determined, followed by the application of the appropriate transistor relationships to determine the list of
unknown quantities. In fact, the only difference between the resulting equations for a network in which an npn
transistor has been replaced by a pnp transistor is the sign associated with particular quantities.

KEY TO CORRECTIONS

Activity 3 a. IE = 2.75 mA; IB = 45.08 mA; VCE = 4.10 V; VCB = 3.51 V.

b. VC = 8.53 V; VB = - 11.59 V.
c. IB = 24.09 uA; beta = 114.16 d. VCE = 4.72 V
12

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Lesson Title: Materials:

BJT Small-Signal, Alternating Current (AC) Analysis – Part 1 Pencil, paper, and calculator

References:
1. Electronic Devices and Circuit
Amplification in the AC Domain Theory, 11th Edition by R.
BJT Transistor Modeling Boylestad & L. Nashelsky (2013);
The re model of BJT Configurations
2. Electronic Devices:
Conventional Current Version, 9th
Edition by Thomas Floyd (2012);
Lesson Objectives:
3. Electronic Principles, 8th
At the end of this lesson, you should be able to: Edition by Albert Malvino and
● use the equivalent model to find the important ac parameters for David J. Bates (2016);
an amplifier;
● calculate general ac characteristics of a variety of important BJT 4. Grob’s Basic Electronics, 12th
configurations. Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: There are too many people praying for mountains of difficulty to be
removed, when what they really need is the courage to climb them!

A. LESSON PREVIEW/REVIEW
1) Introduction

The things you learned about biasing a transistor in previous module are now applied in this one where
bipolar junction transistor (BJT) circuits are used as small-signal amplifiers. You will now begin to examine the
ac response of the BJT amplifier by reviewing the models most frequently used to represent the transistor in
the sinusoidal ac domain. Additionally, you will learn how to reduce an amplifier to an equivalent ac circuit for
easier analysis, and you will learn about multistage amplifiers.

One of our first concerns in the sinusoidal ac analysis of transistor networks is the magnitude of the input
signal. It will determine whether small-signal or large-signal techniques should be applied. The term small-
signal refers to the use of signals that take up a relatively small percentage of an amplifier’s operational range.

There are three models commonly used in the small-signal ac analysis of transistor networks: the re model,
the hybrid p model, and the hybrid equivalent model. This module emphasizes the re model.

Be tough and let’s get going!

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2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)

1. What is an amplifier and
how does it work?
2. How is ac analysis
different from the analysis
in dc domain?
3. What are the most
important ac parameters of
an amplifier?

B. MAIN LESSON
1) Activity 2: Content Notes

AMPLIFICATION IN THE AC DOMAIN

The transistor can be employed as an amplifying device. That is, the output sinusoidal signal is
greater than the input sinusoidal signal, or, stated another way, the output ac power is greater than the input ac
power. The question then arises as to how the ac power output can be greater than the input ac power.

Figure 10.1 Effect of a control element on the steady-state flow of an electrical system

Conservation of energy dictates that over time the total power output, Po, of a system cannot be greater
than its power input, Pi, and that the efficiency defined by h = Po / Pi cannot be greater than 1. The factor that
permits an ac power output to be greater than the input ac power is the applied dc power. It is the principal
contributor to the total output power even though part of it is dissipated by the device and resistive elements. In
other words, there is an “exchange” of dc power to the ac domain that permits establishing a higher output ac
power. In fact, a conversion efficiency is defined by h = Po(ac) / Pi(dc), where Po(ac) is the ac power to the
load and Pi(dc) is the dc power supplied. This is demonstrated in Fig. 10.1.

The peak value of the oscillation in the output circuit is controlled by the established dc level. Any attempt to
exceed the limit set by the dc level will result in a “clipping” (flattening) of the peak region at the high and low end of
the output signal. In general, therefore, proper amplification design requires that the dc and ac components be
sensitive to each other’s requirements and limitations. In other words, one can make a complete

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dc analysis of a system before considering the ac response. Once the dc analysis is complete, the ac response
can be determined using a completely ac analysis.

BJT TRANSISTOR MODELING

The key to transistor small-signal analysis is the use of the equivalent circuits (models). A model is a
combination of circuit elements, properly chosen, that best approximates the actual behavior of a
semiconductor device under specific operating conditions. Once the ac equivalent circuit is determined, the
schematic symbol for the device can be replaced by this equivalent circuit and the basic methods of circuit
analysis applied to determine the desired quantities of the network.
In the formative years of transistor network analysis the hybrid equivalent network was employed the
most frequently. The drawback to using this equivalent circuit, however, is that it is defined for a set of
operating conditions that might not match the actual operating conditions. In most cases, this is not a serious
flaw because the actual operating conditions are relatively close to the chosen operating conditions on the data
sheets. In addition, there is always a variation in actual resistor values and given transistor beta values, so as
an approximate approach it was quite reliable.
In time the use of the re model became the more desirable approach because an important parameter
of the equivalent circuit was determined by the actual operating conditions rather than using a data sheet value
that in some cases could be quite different. The re model is really a reduced version of the hybrid p model used
almost exclusively for high-frequency analysis. This model also includes a connection between output and
input to include the feedback effect of the output voltage and the input quantities.

Figure 10.2 Defining the important parameters of any system.

Even though the network appearance may change, you want to be sure the quantities you find in the
reduced network are the same as defined by the original network. In Fig. 10.2, the input impedance (Zi) is
defined from base to ground, the input current (Ii) as the base current of the transistor, the output voltage (Vo)
as the voltage from collector to ground, and the output current (Io) as the current through the load resistor RC.
The input current Ii and output current Io are, by definition, defined to enter the system. If the output current
is leaving the system rather than entering the system as shown in Fig. 10.2, a minus sign must be applied. The
defined polarities for the input and output voltages are also as appearing in Fig. 10.2. If Vo has the opposite polarity,
the minus sign must be applied. Note that Zi is the impedance “looking into” the system, whereas Zo is the
impedance “looking back into” the system from the output side. By choosing the defined directions for the currents
and voltages as appearing in Fig. 10.2, both the input impedance and output impedance are defined as having
positive values. The input and output impedances for a particular system are both resistive. For the direction of Ii
and Io the resulting voltage across the resistive elements will have the same polarity as Vi and Vo, respectively. If Io
had been defined as the opposite direction, a minus sign would have to be applied. For each

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case Zi = Vi / Ii and Zo = Vo / Io with positive results if they all have the defined directions and polarity of Fig.
10.2. If the output current of an actual system has a direction opposite, a minus sign must be applied to the
result.
Because we know that the transistor is an amplifying device, we would expect some indication of how
the output voltage Vo is related to the input voltage Vi — the voltage gain (Av = Vo / Vi). Note that the current
gain is defined by Ai = Io / Ii.

In summary, therefore, the ac equivalent of a transistor network is obtained by:

1. Setting all dc sources to zero and replacing them by a short-circuit equivalent;
2. Replacing all capacitors by a short-circuit equivalent;
3. Removing all elements bypassed by the short-circuit equivalents introduced by steps 1 and 2; and
4. Redrawing the network in a more convenient and logical form.

The aforementioned steps are demonstrated in Figures 10.3, 10.4, and 10.5.

Figure 10.3 CE, voltage-divider amplifier Figure 10.4 Equivalent circuit after steps 1-3

Figure 10.5 Equivalent circuit after step 4

4
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THE re MODEL OF BJT CONFIGURATIONS

The re model for the CE, CB, and CC BJT transistor configurations will now be introduced with a short
description of why each is a good approximation to the actual behavior of a BJT transistor.

Common-Emitter Configuration. The equivalent circuit for the common-emitter configuration will be
constructed using the device characteristics and a number of approximations. Starting with the input side, we
find the applied voltage Vi is equal to the voltage Vbe with the input current being the base current Ib as shown
in Fig. 10.6.

Figure 10.6 The input circuit of a BJT, its equivalent circuit, and defined level of Zi

For the equivalent circuit, therefore, the input side is simply a single diode with a current Ie. We must
now add a component to the network that will establish the current Ie using the output characteristics. It can be
improved by first replacing the diode by its equivalent resistance as determined by the level of IE. Recall that
the diode resistance is determined by rD = 26 mV / ID. Using the subscript e because the determining current
is the emitter current will result in re = 26 mV / IE.

Eq. 10.1
Input impedance
for BJT
Figure 10.7 CE re model of BJT

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Early Voltage. In reality the characteristics do not have the ideal appearance of Fig. 10.8. Rather, they have a
slope as shown In Fig. 10.9 that defines the output impedance of the device. The steeper the slope, the less
the output impedance and the less ideal the transistor.

In general, it is desirable to have large output impedances to avoid loading down the next stage of a
design.

Figure 10.8 Constant b characteristics Figure 10.9 Early voltage and the output impedance of a transistor

If the slope of the curves is extended until they reach the horizontal axis, it is interesting to note in Fig. 10.9 that
they will all intersect at a voltage called the Early voltage (VA). This intersection was first discovered by James
M. Early in 1952. As the base current increases the slope of the line increases, resulting in an increase in
output impedance with increase in base and collector current. For a particular collector and base current, the
output impedance can be found using the following equation:
Eq. 10.2 Output
Impedance

Typically, however, the Early voltage is sufficiently Eq. 10.3 Approximate

large compared with the applied collector-to-emitter Output Impedance
voltage to permit the following approximation:

Clearly, since VA is a fixed voltage, the larger the collector current,

the less the output impedance. For situations where the Early voltage is not available the output impedance
can be found from the characteristics at any base or collector current using the following equation:

Eq. 10.4 Output

Impedance using
slope

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Common-Base Configuration. The common-base equivalent circuit will be developed in much the same
manner as applied to the common-emitter configuration. The general characteristics of the input and output
circuit will generate an equivalent circuit that will approximate the actual behavior of the device. Recall for the
common-emitter configuration the use of a diode to represent the connection from base to emitter.

Figure 10.10 Common-base BJT transistor and its equivalent circuit

In Figure 10.10 The collector current is related to the emitter current by alpha a . In this case, however, the
controlled source defining the collector current as inserted is opposite in direction to that of the controlled
source of the common-emitter configuration. The direction of the collector current in the output circuit is now
opposite that of the defined output current. For the ac response, the diode can be replaced by its equivalent ac
resistance determined by re = 26 mV / IE.
In general, common-base configurations have very
low input impedance because it is essentially simply re.
Typical values extend from a few ohms to perhaps
50 W. The output impedance ro will typically extend
into the megohm range. Because the output current is
opposite to the defined Io direction, you will find that
there is no phase shift between the input and
output voltages. For the common-emitter
configuration there is a 180° phase shift.
Figure 10.11 CB re model of BJT

Common-Collector Configuration. For the common-collector configuration, the model defined for the common-
emitter configuration is normally applied rather than defining a model for the common-collector configuration.

npn versus pnp. The dc analysis of npn and pnp configurations is quite different in the sense that the currents
will have opposite directions and the voltages opposite polarities. However, for an ac analysis where the signal
will progress between positive and negative values, the ac equivalent circuit will be the same.

COMMON-EMITTER (CE) FIXED-BIAS CONFIGURATION. The first configuration to be analyzed in

detail is the common-emitter fixed-bias network of Fig. 10.12. Note that the input signal Vi is applied to the
base of the transistor, whereas the output Vo is off the collector. In addition, recognize that the input current Ii
is not the base current, but the source current, and the output current Io is the collector current. The small-
signal ac analysis begins by removing the dc effects of VCC and replacing the dc blocking capacitors C1 and
C2 by short-circuit equivalents, resulting in the network shown.
7

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Figure 10.12 Common-emitter fixed-bias configuration and its equivalent network

Figure 10.13 Common-emitter fixed-bias configuration re model

Eq. 10.5 Input and output impedances,

and voltage gain for common-emitter
fixed-bias configuration

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Phase Relationship. The negative sign in the resulting

equation for Av reveals that a 180° phase shift occurs
between the input and output signals, as shown in Fig.
10.14. The is a result of the fact that b Ib establishes a
current through RC that will result in a voltage across RC,
the opposite of that defined by Vo.

Figure 10.14 180° phase shift between input and output

waveforms of CE, fixed-bias configuration (right)

CE VOLTAGE-DIVIDER BIAS. The next configuration to be analyzed is the voltage-divider bias network of
Fig. 10.15. Recall that the name of the configuration is a result of the voltage-divider bias at the input side to
determine the dc level of VB. Note the absence of RE due to the low-impedance shorting effect of the bypass
capacitor, CE. That is, at the frequency (or frequencies) of operation, the reactance of the capacitor is so small
compared to RE that it is treated as a short circuit across RE. When VCC is set to zero, it places one end of R1
and RC at ground potential. In addition, note that R1 and R2 remain part of the input circuit, whereas RC is part
of the output circuit.

Figure 10.15 Common-emitter voltage-divider bias

configuration and its re model

Eq. 10.6 Input and output

impedances, and voltage gain for
common-emitter voltage-divider bias
configuration

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Phase Relationship. The negative sign in the resulting equation for Av reveals that a 180° phase shift occurs
between the input and output signals.

CE EMITTER-BIAS CONFIGURATION (Unbypassed). The most fundamental of unbypassed configurations

appears in Fig. 10.16. The re equivalent model is substituted but note the absence of the resistance ro. The
effect of ro is to make the analysis a great deal more complicated, and considering the fact that in most
situations its effect can be ignored, it will not be included in the present analysis.

Figure 10.15 Common-emitter emitter-bias configuration and its re model

Eq. 10.7 Input and output impedances, and voltage gain for common-emitter emitter bias configuration

10

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Phase Relationship. The negative sign in the resulting equation for Av reveals that a 180° phase shift occurs
between the input and output signals.
Bypassed. If RE is bypassed by an emitter capacitor CE, the complete re equivalent model can be substituted,
resulting in the same equivalent network. Approximate equations in Eq. 10.7 are therefore applicable.

EMITTER-FOLLOWER CONFIGURATION. When the output is taken from the emitter terminal of the transistor
as shown in Fig. 10.16, the network is referred to as an emitter-follower. The output voltage is always slightly
less than the input signal due to the drop from base to emitter, but the approximation Av @ 1 is usually a good
one. Unlike the collector voltage, the emitter voltage is in phase with the signal Vi. That is, both Vo and Vi
attain their positive and negative peak values at the same time. The fact that Vo “follows” the magnitude of Vi
with an in-phase relationship accounts for the terminology emitter-follower. In fact, because the collector is
grounded for ac analysis, it is actually a common-collector configuration. The emitter-follower configuration
is frequently used for impedance-matching purposes. It presents a high impedance at the input and a low
impedance at the output, which is the direct opposite of the standard fixed-bias configuration. The resulting
effect is much the same as that obtained with a transformer, where a load is matched to the source impedance
for maximum power transfer through the system.

Figure 10.16 Emitter-follower configuration and its re model

Eq. 10.8 Input and output impedances, and voltage gain for emitter-follower configuration
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Activity 3: Skill-building Activities (Answers in Keys to Correction)

a. For the fixed-bias network shown below, b. For the voltage-divider bias network shown below,
calculate Zi , Zo, and Av. calculate Zi , Zo, and Av.

c. For the emitter bias network shown below, d. For the emitter bias network shown below,
calculate Zi , Zo, and Av. calculate Zi , Zo, and Av.

12

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2) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is an amplifier and
how does it work?
2. How is ac analysis
different from the analysis
in dc domain?
3. What are the most
important ac parameters of
an amplifier?

3) Activity 5: Check for Understanding

This is an assessment. Solve completely.

a. What is the conversion efficiency of an amplifier in which the effective value of the current through a 2.2-kW
load is 5 mA and the drain on the 18-V dc supply is 3.8 mA?

b. What is the reactance of a 10-mF capacitor at a frequency of 1kHz? For networks in which the resistor levels
are typically in the kilohm range, is it a good assumption to use the short-circuit equivalence for the conditions
just described? How about at 100 kHz?

c. Given an Early voltage of VA = 100 V, determine ro if VCEQ = 8 V and ICQ = 4 mA.

d. For the common-base configuration, an ac signal of 10 mV is applied, resulting in an ac emitter current of

0.5 mA. If alpha is 0.980 and RL = 1.2 kW, determine Zi, Vo, and Av.

e. Determine Zi and Av for a common-emitter amplifier if beta is 80, IE(dc) = 2mA, ro = 40 kW, and RL = 1.2 kW.

f. For the network on the left,

what value of RC will cut the
voltage gain to half the value
obtained from the original
values in the circuit? Ignore ro
in your calculation.

g. For the network on the right,

calculate Zi, Zo, and Av.

13

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C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning (5 mins)

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

Which strategy worked for you, easily? With difficulty?

FAQs

1. What affects the stability of the voltage gain in common-emitter amplifiers?

Stability is a measure of how well an amplifier maintains its design values over changes in temperature or for
a transistor with a different beta. Although bypassing RE does produce the maximum voltage gain, there is a
stability problem because the ac voltage gain is dependent on re since Av = - RC/re. Also, re depends on IE
and on temperature. This causes the gain to be unstable over changes in temperature because when re
increases, the gain decreases and vice versa.

2. What is the role of a swamping resistor?

Swamping is a method used to minimize the effect of re without
reducing the voltage gain to its minimum value. This method
“swamps” out the effect of re on the voltage gain. Swamping is, in
effect, a compromise between having a bypass capacitor across RE
and having no bypass capacitor at all. In a swamped amplifier, RE is
partially bypassed so that a reasonable gain can be achieved, and the
effect of re on the gain is greatly reduced or eliminated. The total
external emitter resistance, RE, is formed with two separate emitter
resistors, RE1 and RE2. One of the resistors, RE2, is bypassed and
the other is not. Both resistors (RE1 + RE2) affect the dc bias while
only RE1 affects the ac voltage gain.

KEY TO CORRECTIONS

Activity 3
a. Zi = 1.07 kW; Zo = 2.83 kW; and Av = -264.24 c. Zi = 59.34 kW; Zo = 2.20 kW; and Av = -3.89 d.
b. Zi = 1.35 kW; Zo = 5.98 kW; and Av = -324.30 Zi = 132.72 kW; Zo = 12.56 W; and Av = 0.996

14

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Lesson Title: Materials:

BJT Small-Signal, Alternating Current (AC) Analysis – Part 2 Pencil, paper, and calculator

References:
The re model of BJT Configurations 1. Electronic Devices and Circuit
Effect of RL and RS Theory, 11th Edition by R.
Two-Port System Approach Boylestad & L. Nashelsky (2013);

2. Electronic Devices:
Lesson Objectives: Conventional Current Version, 9th
Edition by Thomas Floyd (2012);
At the end of this lesson, you should be able to:
● calculate general ac characteristics of a variety of important BJT 3. Electronic Principles, 8th
configurations; Edition by Albert Malvino and
● analyze the effects of a source resistance and load resistor on David J. Bates (2016);
the overall gain and characteristics of an amplifier; and
● analyze the advantages associated with the two-port systems 4. Grob’s Basic Electronics, 12th
approach to single- and multi-stage amplifiers. Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: Never give up. Never give in.

Many had done it. Anyone can do it. Believe!

A. LESSON PREVIEW/REVIEW
1) Introduction

In the previous module, you were introduced with the re model as a means for small-signal analysis of BJT
common-emitter configurations. You shall continue the analysis of other bias network of this configuration and
that of common-base.
Also, this module will tackle the effect of the source and load resistances of the network to its important ac
parameters. Crucial to this discussion is the introduction of the two-port system approach which shall be heavily
employed in the conversion of any complex network to that one with two terminals only – the input and output.

2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)

1. Which transistor configuration
has the greatest gain?
2. What is loading in a network and how
does it affect the the parameters?
3. What are the elements in a two-
port system?
1

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B. MAIN LESSON
1) Activity 2: Content Notes

THE RE MODEL OF BJT CONFIGURATIONS (cont’d)

Common-Base Configuration. The common-base configuration is characterized as having a relatively low
input and a high output impedance and a current gain less than 1. The voltage gain, however, can be quite
large. The standard configuration with the common-base re equivalent model appears in in Fig. 11.1.

Figure 11.1 Common-base configuration and its re equivalent model

Eq. 11.1 Input and output impedances,

and voltage and current gain
for common-base configuration

Phase Relationship. The fact that Av is a positive number shows that Vo and Vi are in phase for the common-
base configuration.

COLLECTOR FEEDBACK CONFIGURATION. The collector feedback

network of Fig. 11.2 employs a feedback path from collector to base to
increase the stability of the system.

Figure 11.2 Collector-feedback configuration and its re equivalent model

2

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Eq. 11.2 Input and output impedances,

and voltage gain for collector-feedback configuration

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Phase Relationship. The negative sign of the voltage gain indicates a 180° phase shift between Vo and Vi.

COLLECTOR DC FEEDBACK CONFIGURATION. The network of Fig. 11.3 has a dc feedback resistor for
increased stability, yet the capacitor C3 will shift portions of the feedback resistance to the input and output
sections of the net- work in the ac domain. The portion of RF shifted to the input or output side will be deter-
mined by the desired ac input and output resistance levels. At the frequency or frequencies of operation, the
capacitor will assume a short-circuit equivalent to ground due to its low impedance level compared to the other
elements of the network.

Figure 11.2 Collector DC feedback configuration and its re equivalent model

Eq. 11.2 Input and output impedances, and voltage gain for collector DC feedback configuration

Phase Relationship. The negative sign of the voltage gain indicates a 180° phase shift between Vo and Vi.
EFFECT OF RL AND RS
All the parameters determined in the last few sections have been for an unloaded amplifier with the input
voltage connected directly to a terminal of the transistor. In this section the effect of applying a load to the
output terminal and the effect of using a source with an internal resistance will be investigated. The network of
Fig. 11.3a is typical of those investigated in the previous section. Because a resistive load was not attached to
the output terminal, the gain is commonly referred to as the no-load gain and given the following notation:
AVNL = Vo / Vi. Eq. 11.3 No-load voltage gain
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In Fig. 11.3b a load has been added in the form of a resistor RL, which will change the overall gain of the system.
This loaded gain is typically given the following notation:
AVL = Vo / Vi (with RL) Eq. 11.4 Loaded voltage gain

In Fig. 11.3c both a load and a source resistance have been introduced, which will have an additional effect on
the gain of the system. The resulting gain is typically given the fol-lowing notation:
AVs = Vo / Vi (with RL and Rs) Eq. 11.4 Loaded voltage gain
with respect to source

Figure 11.3 Amplifier configurations: (a) unloaded; (b) loaded; (c) loaded with a source resistance.

IMPORTANT
1. The loaded voltage gain of an amplifier is always less than the no-load gain.
2. The gain obtained with a source resistance in place will always be less than that obtained under loaded or
unloaded conditions due to the drop in applied voltage across the source resistance.
3. For the same configuration AvNL > AvL > Avs.
4. For a particular design, the larger the level of RL, the greater is the level of ac gain.
5. For a particular amplifier, the smaller the internal resistance of the signal source, the greater is the overall
gain.
6. For any network that have coupling capacitors, the source and load resistance do not affect the dc biasing
levels.

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Table 11.1a BJT Transistor Amplifiers Including the Effect of Rs and RL

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Table 11.1b BJT Transistor Amplifiers Including the Effect of Rs and RL (cont’d)

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TWO-PORT SYSTEM APPROACH

In the design process, it is often necessary to work with the terminal characteristics of a device rather then the
individual components of the system. In other words, the designer is handed a packaged product with a list of
data regarding its characteristics but has no access to the internal construction. This section will relate the
important parameters determined for a number of configurations in the previous sections to the important
parameters of this packaged system. The result will be an understanding of how each parameter of the
packaged system relates to the actual amplifier or network. The system of Fig. 11.4 is called a two-port
system because there are two sets of terminals—one at the input and the other at the output.

Figure 11.4 Two-port system

Under no-load:

Figure 11.4 Two-port system under no-load condition

Figure 11.5 Two-port system under loaded condition

Ideally, all the parameters of the model are unaffected by changing loads and levels of source resistance.
However, for some transistor configurations the applied load can affect the input resistance, whereas for others
the output resistance can be affected by the source resistance. In all cases, however, by simple definition, the
no-load gain is unaffected by the application of any load.
8

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In Fig. 11.6, a source with an internal resistance Rs and a load RL have been applied to a two-port system for
which the parameters Zi, AvNL, and Zo have been specified.

Figure 11.6 Effects of Rs and RL on the gain of an amplifier.

Eq. 11.3 Voltage and current gains with the effects of of Rs and RL

2) Activity 3: Skill-building Activities (Answers found in Keys to Correction)

a. For the network below, determine Zi , Zo, Av, and Ai. c. For the network below,
determine Zi , Zo, and Vo if Vi = 2 mV

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b. For the network below, determine Zi , Zo, and Av. d. Given the packaged amplifier below,
determine the gain AvL and AvS with RL = 1.2 kW.

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. Which transistor configuration
has the greatest gain?
2. What is loading in a network and how
does it affect the the parameters?
3. What are the elements in a two-
port system?

4) Activity 5: Check for Understanding

This is an assessment. Solve completely the following items.

a. Given re = 10 W , beta is 200, Av = -160, and Ai = b. Given RC = 2.2 kW, RF = 120 kW, RE = 1.2 kW,
19 for the network below, determine RC, RF, and VCC. beta = 90, and VCC = 10 V, find Av, Zi, and Zo.

10

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c.1 For the network given below, determine AvNL, Zi, and Zo.

c.2 For the network given below, calculate AvL and Avs using two-system approach.

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning
You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

Which strategy worked for you, easily? With difficulty?

KEY TO CORRECTIONS

Activity 3

a. Zi = 19.61 W; Zo = 5 kW; Av = 250; Ai = - 0.98

b. Zi = 566.16 W; Zo = 2.66 kW; Av = - 240.86
c. Zi = 1.37 kW; Zo = 2.87 kW; Vo = (-) 579 mV
d. AvL = - 180 ; AvS = - 171.36

11

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Lesson Title: Materials:

BJT Small-Signal, Alternating Current (AC) Analysis – Part 3 Pencil, paper, and calculator

References:
1. Electronic Devices and Circuit
Multi-stage Amplifiers: Cascode and Cascade Theory, 11th Edition by R.
Multiple BJT Networks: Darlington and Feedback Pairs Boylestad & L. Nashelsky (2013);

2. Electronic Devices:
Conventional Current Version, 9th
Lesson Objectives: Edition by Thomas Floyd (2012);

At the end of this lesson, you should be able to: 3. Electronic Principles, 8th Edition
● use the equivalent model to find the important ac parameters for by Albert Malvino and David J.
multi-stage BJT amplifier; Bates (2016);
● calculate general ac characteristics of a variety of important multiple 4. Grob’s Basic Electronics, 12th
BJT networks. Edition by Mitchel E. Schultz,
(2016).

Productivity Tip: No sacrifice, no victory.

A. LESSON PREVIEW/REVIEW
1) Introduction

In the previous module, it is important to realized that when using the two-port equations in some
configurations the input impedance is sensitive to the applied load (such as the emitter-follower and collector
feedback) and in some the output impedance is sensitive to the applied source resistance (such as the emitter-
follower). In such cases the no-load parameters for Zi and Zo have to first be calculated before substituting into
the two-port equations. For most packaged systems such as op-amps this sensitivity of the input and output
parameters to the applied load or source resistance is minimized to eliminate the need to be concerned about
changes from the no-load levels when using the two-port equations.
In this module, you will learn that no matter how perfect the system design, the application of a succeeding
stage or load to a two-port system will affect the voltage gain. Therefore, there is no possibility of a situation
where Av1, Av2, and so on are simply the no-load values. The no-load parameters can be used to determine
the loaded gains of each stage.

You will also be introduced with multiple BJT networks and their ac response in this module.

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2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)

1. What is a cascaded
system?
2. How do the preceding
and succeeding stages in a
cascaded system affect the
ac parameters of a certain
stage?
3. What are expected
values of the ac parameters
for multiple BJT amplifiers?

B. MAIN LESSON
1) Activity 2: Content Notes (13 mins)

CASCADED SYSTEMS

Figure 12.1 Cascaded System

The two-port systems approach is particularly useful for cascaded systems such as that appearing in Fig. 11.7,
where Av1, Av2, Av3, and so on, are the voltage gains of each stage under loaded conditions. That is, Av1 is
determined with the input impedance to Av2 acting as the load on Av1. For Av2, Av1 will determine the signal
strength and source impedance at the input to Av2. The total gain of the system is then determined by the
product of the individual gains as follows:

Eq. 12.1 Total voltage and current

gains for cascaded system

RC-Coupled BJT Amplifiers

One popular connection of amplifier stages is the RC -coupled variety shown in Fig. 12.2. The name is derived
from the capacitive coupling capacitor Cc and the fact that the load on the first stage is an RC combination.
The coupling capacitor isolates the two stages from a dc viewpoint but acts as a short-circuit equivalent for the
ac response. The input impedance of the second stage acts as a load on the first stage, permitting the same
approach to the analysis as described in the last two sections.
2

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Figure 12.2 RC-coupled BJT amplifier

Cascode Connection
The cascode configuration has one of two configurations.
In each case the collector of the leading transistor is
connected to the emitter of the following transistor.
Possible arrangement appears in Fig. 12.3.

Figure 12.3 Practical cascode circuits

DARLINGTON CONNECTION
A very popular connection of two bipolar junction transistors for operation as one “super- beta” transistor is the
Darlington connection shown in Fig. 12.4. The main feature of the Darlington connection is that the composite
transistor acts as a single unit with a current gain that is the product of the current gains of the individual
transistors. If the connection is made using two separate transistors having current gains of b1 and b2, the
Darlington connection provides a current gain of bD = b1 b2.
3

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Figure 12.4 A Darlington amplifier used in an emitter-follower configuration

AC Input Impedance. The ac input impedance can be determined using the ac equivalent network below.

Eq. 12.2 Darlington’s input impedance

AC Current Gain. The current gain can be determined from the equivalent network below. The output
impedance of each transistor is ignored and the parameters for each transistor are employed.

Eq. 12.3 Darlington’s current gain

4

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AC Voltage Gain. The voltage gain can be determined using following derivation:

Eq. 12.4 Emitter-follower,

Darlington’s Voltage gain

AC Output Impedance. The output impedance will be determined by setting Vi to zero volts as shown in the
figure below. The resistor RB is “shorted out”.

Eq. 12.5 Emitter-follower,

Darlington’s output impedance

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FEEDBACK PAIR
The feedback pair connection is a two-transistor circuit
that operates like the Darlington circuit. Notice that the
feedback pair uses a pnp transistor driving an npn
transistor, the two devices acting effectively much like one
pnp transistor. (See Figure 12.5) As with a Darlington
connection, the feedback pair provides very high current
gain (the product of the transistor current gains), high
input impedance, low output impedance, and a voltage
gain slightly less than one. Initially, it may appear that it
would have a high voltage gain because the output is
taken off the collector with a resistor RC in place.
However, the pnp–npn combination results in terminal
characteristics very similar to that of the emitter–follower
configuration.

Figure 12.5 A feedback pair amplifier and its operation

AC Operation. Consider the equivalent circuit that follows.

Input Impedance, Zi
The ac input impedance seen looking into the base of transistor
Q1 is determined as:

Eq. 12.6 Feedback pair input impedance

6

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Current Gain Voltage Gain

Eq. 12.7 Feedback pair current and voltage gains

Output Impedance

Eq. 12.8 Feedback pair output impedance

2) Activity 3: Skill-building Activities (Answers in Keys to Correction)

a. For the configuration below, determine the loaded gain for each stage; the total gain for the system, Av and
Avs; and the total current gain for the system.

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b. For the network below, calculate the input and c. For the network below, calculate Zi, Zo, Av.
output impedances, and the voltage and current gains.

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is a cascaded system?

2. How do the preceding and

succeeding stages in a
cascaded system affect the ac
parameters of a certain stage?
3. What are expected values of
the ac parameters for multiple
BJT amplifiers?

4) Activity 5: Check for Understanding

This is an assessment. Solve the following problems completely. Box your final answers.

a. For the configuration below, determine the loaded gain for each stage; the total gain for the system, Av and
Avs; and the total current gain for the system.

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b. For the cascode amplifier circuit, c. For the network below, calculate Zi, Zo, Av.
calculate the voltage gain Av and output voltage Vo.

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

FAQs

1. What is a Sziklai pair?

The Sziklai pair is similar to the Darlington pair except that it consists of two types
of transistors, an npn and a pnp. This configuration is sometimes known as a
complementary Darlington or a compound transistor. The current gain is about the
same as in the Darlington pair, as illustrated. The difference is that the Q2 base
current is the Q1 collector current instead of emitter current, as in the Darlington
arrangement.

An advantage of the Sziklai pair, compared to the Darlington, is that it takes less
voltage to turn it on because only one barrier potential has to be overcome. A
Sziklai pair is sometimes used in conjunction with a Darlington pair as the output
stage of power amplifiers. In this case, the output power transistors are both the
same type (two npn or two pnp transistors). This makes it easier to obtain exact
matches of the output transistors, resulting in improved thermal stability and better
sound quality in audio applications.

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2. What is a differential amplifier?

A differential amplifier is an amplifier that produces outputs
that are a function of the difference between two input
voltages. The differential amplifier has two basic modes of
operation: differential (in which the two inputs are different)
and common mode (in which the two inputs are the same).
The differential amplifier is important in operational
amplifiers.

KEY TO CORRECTIONS

Activity 3

a. Av1 = 0.684; Av2 = 147.87; Avt = 101.20; Avs = 92; Ait = - 123.41.
b. Zi = 1.38 MW; Zo = 3.30 W; Ai = 3140; Av = 1
c. Zi = 42.97 kW; Zo = 1.20 kW; Ai = 8630.7; Av = - 241.04

10

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Lesson Title: Materials:

Field-Effect Transistor (FET) Fundamentals Pen, paper, and calculator

Differences of FET and BJT References:

FET Construction and Operating Characteristics 1. Electronic Devices and Circuit
Transfer Characteristics Theory, 11th Edition by R.
Boylestad & L. Nashelsky (2013);
Lesson Objectives:
2. Electronic Devices:
At the end of this lesson, you should be able to: Conventional Current Version, 9th
● compare and contrast BJT and FET; Edition by Thomas Floyd (2012);
● familiarize and discuss the construction and operating
characteristics of Junction Field Effect (JFET); and 3. Electronic Principles, 8th Edition
● sketch the transfer characteristics from the drain characteristics of by Albert Malvino and David J.
a JFET. Bates (2016);

Productivity Tip: Encourage oneself and think about how electronics impacts your life.

A. LESSON PREVIEW/REVIEW
1) Introduction
The previous modules presented bipolar-junction transistor (BJT) and its application as amplifier. In this module,
you will be introduced with the field-effect transistor (FET), a three-terminal device used for a variety of
applications that match, to a large extent, those of the BJT. Although there are important differences between
the two types of devices, there are also many similarities.

As an overview, there are three types of FETs that will be introduced: the junction field-effect transistor (JFET),
the metal–oxide–semiconductor field-effect transistor (MOSFET), and the metal–semiconductor field-effect
transistor (MESFET).

To gain a deeper understanding of these FETs, let’s start digging in first on the primary differences of a FET and
a BJT. Both transistors are remarkable but the other is just way better in many ways. Let’s find out.

2) Activity 1: What I Know Chart, part 1

What I Know Questions: What I Learned (Activity 4)
1. What is a “junction” and its role in a
transistor?
2. How are “bipolar” and “unipolar”
devices differ?
3. What are the independent and
dependent variables in the governing
current equation for BJT? for FET?

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B. MAIN LESSON
1) Activity 2: Content Notes
For maximum retention, students are encourage to highlight and underline important terms and concepts.

DIFFERENCES OF FET AND BJT

The primary difference between the two types of transistors is the fact that: The BJT transistor is a current-
controlled device whereas the JFET transistor is a voltage-controlled device, as depicted in Fig. 13.1.

Figure 13.1 (a) Current-controlled and (b) voltage-controlled amplifiers.

In other words, the current IC in BJT is a direct function of the level of IB. For the FET, the current ID will be a
function of the voltage VGS applied to the input circuit. In each case the current of the output circuit is controlled
by a parameter of the input circuit—in one case a current level and in the other an applied voltage.

Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel field-effect transistors.
However, it is important to keep in mind that the BJT transistor is a bipolar device—the prefix bi indicates that
the conduction level is a function of two charge carriers, electrons and holes. The FET is a unipolar device
depending solely on either electron (n- channel) or hole (p-channel) conduction.

The term field effect in the name deserves some explanation. You are all familiar with the ability of a permanent
magnet to draw metal filings to itself without the need for actual contact. The magnetic field of the permanent
magnet envelopes the filings and attracts them to the magnet along the shortest path provided by the magnetic
flux lines. For the FET an electric field is established by the charges present, which controls the conduction path
of the output circuit without the need for direct contact between the controlling and controlled quantities.

One of the most important characteristics of the FET is its high input impedance. It far exceeds the typical input
resistance levels of the BJT transistor configurations—a very important characteristic in the design of linear ac
amplifier systems. On the other hand, the BJT transistor has a much higher sensitivity to changes in the applied
signal. In other words, the variation in output current is typically a great deal more for BJTs than for FETs for the
same change in the applied voltage. For this reason: Typical ac voltage gains for BJT amplifiers are a great deal
more than for FETs. However, FETs are more temperature stable than BJTs, and FETs are usually smaller than
BJTs, making them particularly useful in integrated-circuit (IC) chips. The construction characteristics of some
FETs, however, can make them more sensitive to handling than BJTs.

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FET CONSTRUCTION
Junction field-effect transistor (JFET) is a three-terminal device with one terminal capable of controlling the
current between the other two (the n-channel device will be the prominent device).

The basic construction of the n-channel JFET is shown in

Fig. 13.2. Note that the major part of the structure is the
n-type material, which forms the channel between the
embedded layers of p-type material. The top of the n-type
channel is connected through an ohmic contact to a
terminal referred to as the drain (D), whereas the lower
end of the same material is connected through an ohmic
contact to a terminal referred to as the source (S). The two
p-type materials are connected together and to the gate
(G) terminal. In essence, therefore, the drain and the
source are connected to the ends of the n-type channel
and the gate to the two layers of p-type material. In the
absence of any applied potentials the JFET has two p–n
junctions under no-bias conditions. The result is a
depletion region at each junction, as shown in Fig. 13.2,
that resembles the same region of a diode under no-bias
conditions. Recall also that a depletion region is void of
free carriers and is therefore unable to support
conduction.
Figure 13.2 Junction field-effect transistor.

The water analogy of Fig. 13.3 does provide a sense for the JFET control at the
gate terminal and the appropriateness of the terminology applied to the
terminals of the device. The source of water pressure can be likened to the
applied voltage from drain to source, which establishes a flow of water
(electrons) from the spigot (source). The “gate,” through an applied signal
(potential), controls the flow of water (charge) to the “drain.” The drain and
source terminals are at opposite ends of the n-channel as introduced in Fig. 13.3
because the terminology is defined for electron flow.

Figure 13.3 Junction field-effect transistor

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OPERATION
VGS = 0 V, VDS Some Positive Value. In Fig. 13.4, a positive voltage
VDS is applied across the channel and the gate is connected directly
to the source to establish the condition VGS = 0 V. The result is a gate
and a source terminal at the same potential and a depletion region in
the low end of each p-material similar to the distribution of the no-bias
conditions of Fig. 13.2. The instant the voltage VDD (=VDS) is applied,
the electrons are drawn to the drain terminal, establishing the
conventional current ID with the defined direction of Fig. 13.4. The path
of charge flow clearly reveals that the drain and source currents are
equivalent (ID = IS). Under the conditions in Fig. 13.4, the flow of
charge is relatively uninhibited and is limited solely by the resistance
of the n-channel between drain and source.

Figure 13.4 (top-right)

JFET at VGS = 0 V, VDS > 0 V

It is important to note that the depletion region is wider near the top of
both p-type materials. Assuming a uniform resistance in the n-channel,
we can break down the resistance of the channel into the divisions
appearing in Fig. 13.5. The current ID will establish the voltage levels
through the channel as indicated on the same figure. The result is that
the upper region of the p-type material will be reverse-biased by about
1.5 V, with the lower region only reverse-biased by 0.5 V. Recall from the
discussion of the diode operation that the greater the applied reverse
bias, the wider is the depletion region—hence the distribution of the
depletion region as shown in Fig. 13.5.

Figure 13.5 Varying reverse-bias potentials across the p–n junction of an n-channel JFET.

The fact that the p–n junction is reverse-biased for the length of the channel results in a gate current of zero
amperes, as shown in the same figure. The fact that IG = 0 A is an important characteristic of the JFET.

As the voltage VDS is increased from 0 V to a few volts, the

current will increase as determined by Ohm’s law and the plot
of ID versus VDS will appear as shown in Fig. 13.6. The relative
straightness of the plot reveals that for the region of low
values of VDS, the resistance is essentially constant. As VDS
increases and approaches a level referred to as VP in Fig.
13.6, the depletion regions of Fig. 13.4 will widen, causing a
noticeable reduction in the channel width. The reduced path
of conduction causes the resistance to increase and the curve
in the graph of Fig. 13.6 to occur. The more horizontal the
curve, the higher the resistance, suggesting that the
resistance is approaching “infinite” ohms in the horizontal
region.
Figure 13.6 ID vs VDS at VGS = 0 V
4

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If VDS is increased to a level where it appears that the two depletion

regions would “touch” as shown in Fig. 13.7, a condition referred to as
pinch-off will result. The level of VDS that establishes this condition is
referred to as the pinch-off voltage and is denoted by VP, as shown in
Fig. 13.6. In actuality, the term pinch-off is a “misnomer” in that it
suggests the current ID is pinched off and drops to 0 A. However, this
is hardly the case — ID maintains a saturation level defined as IDSS in
Fig. 13.6. In reality a very small channel still exists, with a current of
very high density. The fact that ID does not drop off at pinch-off and
maintains the saturation level is verified by the following fact: The
absence of a drain current would remove the possibility of different
potential levels through the n-channel material to establish the varying
levels of reverse bias along the p–n junction. The result would be a loss
of the depletion region distribution that caused pinch-off in the first
place.

Figure 13.7 (left) Pinch-off (VGS = 0 V, VDS = VP).

As VDS is increased beyond VP, the region of close encounter between the two
depletion regions increases in length along the channel, but the level of ID
remains essentially the same. In essence, therefore, once VDS > VP the JFET
has the characteristics of a current source. As shown in Fig. 13.8, the current
is fixed at ID = IDSS, but the voltage VDS (for levels 7 VP) is determined by the
applied load.

Figure 13.8 Current source equivalent for VGS = 0 V, VDS > VP

The choice of notation IDSS is derived from the fact that it is the drain-to-source current with a short-circuit
connection from gate to source. As we continue to investigate the characteristics of the device we will find that:
IDSS is the maximum drain current for a JFET and is defined by the conditions VGS = 0 V and VDS > |VP |. Note in
Fig. 13.6 that VGS = 0 V for the entire length of the curve.

VGS < 0 V. The voltage from gate to source, denoted VGS, is the controlling voltage of the JFET. For the n-channel
device the controlling voltage VGS is made more and more negative from its VGS = 0 V level. In other words, the
gate terminal will be set at lower and lower potential levels as compared to the source.

In Fig. 13.9 on the succeeding page, a negative voltage of -1 V is applied between the gate and source terminals
for a low level of VDS. The effect of the applied negative-bias VGS is to establish depletion regions similar to those
obtained with VGS = 0 V, but at lower levels of VDS. Therefore, the result of applying a negative bias to the gate
is to reach the saturation level at a lower level of VDS, as shown in Fig. 13.11 for VGS = -1 V. The resulting
saturation level for ID has been reduced and in fact will continue to decrease as VGS is made more and more
negative. Note also in Fig. 13.10 on the next page how the pinch-off voltage continues to drop in a parabolic
manner as VGS becomes more and more negative. Eventually, VGS when VGS = -VP will be sufficiently negative
to establish a saturation level that is essentially 0 mA, and for all practical purposes the device has been “turned
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off.”
In summary: The level of VGS that results in ID = 0 mA is defined by VGS = VP, with VP being a negative voltage
for n-channel devices and a positive voltage for p-channel JFETs.

Figure 13.9 Application of a negative voltage Figure 13.10 n-Channel JFET characteristics
to the gate of a JFET. with IDSS = 8 mA and VP = -4 V.

On most specification sheets, the pinch-off voltage is specified as VGS(off) rather than VP. The region to the right
of the pinch-off locus of Fig. 13.10 is the region typically employed in linear amplifiers (amplifiers with minimum
distortion of the applied signal) and is commonly referred to as the constant-current, saturation, or linear
amplification region.

Voltage-Controlled Resistor. The region to the left of the pinch-off locus of Fig. 13.10 is referred to as the
ohmic or voltage-controlled resistance region. In this region, the JFET can actually be employed as a variable
resistor (possibly for an automatic gain control system) whose resistance is controlled by the applied gate-to-
source voltage. Note in Fig. 13.10 that the slope of each curve and therefore the resistance of the device between
drain and source for VDS < VP are a function of the applied voltage VGS. As VGS becomes more and more negative,
the slope of each curve becomes more and more horizontal, corresponding to an increasing resistance level.
The following equation provides a good first approximation to the resistance level in terms of the applied voltage
VGS:
Eq. 13.1 FET resistance at a particular level of VGS

where ro is the resistance with VGS = 0 V and rd is the resistance at a particular level of VGS. For an n-channel
JFET with ro = 10 kohms (VGS = 0 V, VP = -6 V), Eq. (7.1) results in 40 kohms at VGS = -3 V.
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p-Channel Devices. The p-channel JFET is constructed in exactly

the same manner as the n-channel device of Fig. 13.2 but with a
reversal of the p- and n-type materials as shown in Fig. 13.11. The
defined current directions are reversed, as are the actual polarities
for the voltages VGS and VDS. For the p-channel device, the channel
will be constricted by increasing positive voltages from gate to
source and the double-subscript notation for VDS will result in
negative voltages for VDS on the characteristics of Fig. 13.12, which
has an IDSS of 6 mA and a pinch-off voltage of VGS = +6 V. Do not
let the minus signs for VDS confuse you. They simply indicate that
the source is at a higher potential than the drain.

Figure 13.11 (right)

p-Channel Devices
FET

Note at high levels of VDS that the curves suddenly rise to levels
that seem unbounded. The vertical rise is an indication that
breakdown has occurred and the current through the channel (in
the same direction as normally encountered) is now limited
solely by the external circuit. Although not appearing in Fig.
13.10 for the n-channel device, they do occur for the n-channel
device if sufficient voltage is applied. This region can be avoided
if the level of VDSmax is noted on the specification sheet and the
design is such that the actual level of VDS is less than this value
for all values of VGS.
Figure 13.12 p-Channel JFET characteristics
with IDSS = 6 mA and VP = +6 V.

Symbols. The graphic symbols for the n-channel and p-channel JFETs
are provided in Fig. 13.13. Note that the arrow is pointing in for the n-
channel device of Fig. 13.13a to represent the direction in which IG would
flow if the p–n junction were forward-biased. For the p-channel device
(Fig. 13.13b) the only difference in the symbol is the direction of the arrow
in the symbol.
Figure 13.13 (right) JFET symbols:
Important Parameters and Relationships (for n-channel JFET): (a) n-channel; (b) p-channel.

1. The maximum current is defined as IDSS and occurs when VGS = 0 V and VDS  |VP |. (See Fig. 13.14a)
2. For gate-to-source voltages VGS is less than (more negative than) the VP level, the drain current is 0 A
(ID = 0 A). (See Fig. 13.14b)
3. For all levels of VGS between 0 V and the pinch-off level, the current ID will range between IDSS and 0 A,
respectively. (See Fig. 13.14c)
Note: A similar list can be developed for p-channel JFETs.
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Figure 13.14 (a) VGS = 0 V, ID = IDSS; (b) cutoff (ID) VGS is less than VP level;
(c) ID is between 0 A and IDSS for VGS  0 V and greater than the pinch-off level.

TRANSFER CHARACTERISTICS

The relationship between ID and VGS is:

Equation 13.2
Shockley’s Equation

The squared term in the equation results in a nonlinear relationship between ID and VGS, producing a curve that
grows exponentially with decreasing magnitude of VGS.

The transfer characteristics defined by Shockley’s equation are unaffected by the network in which the device is
employed.

Figure 13.15 Obtaining the transfer curve from the drain characteristics.

The transfer curve can be obtained using Shockley’s equation or from the output characteristics of Fig. 13.10. In
Fig. 13.15 two graphs are provided, with the vertical scaling in milliamperes for each graph. One is a plot of ID
versus VDS, whereas the other is ID versus VGS. Using the drain characteristics on the right of the “y” axis, we can
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draw a horizontal line from the saturation region of the curve denoted VGS = 0 V to the ID axis. The resulting
current level for both graphs is IDSS. The point of intersection on the ID versus VGS curve will be as shown since
the vertical axis is defined as VGS = 0 V.

In review, when VGS = 0V, ID = IDSS and when VGS = VP, ID = 0 mA

Before continuing, it is important to realize that the drain characteristics relate one output (or drain) quantity to
another output (or drain) quantity—both axes are defined by variables in the same region of the device
characteristics. The transfer characteristics are a plot of an output (or drain) current versus an input-controlling
quantity. There is therefore a direct “transfer” from input to output variables when employing the curve to the left
of Fig. 13.15.

Applying Shockley’s Equation. The transfer curve of Fig. 13.15 can also be obtained directly from Shockley’s
equation (13.2) given simply the values of IDSS and VP. The levels of IDSS and VP define the limits of the curve on
both axes and leave only the necessity of finding a few intermediate plot points. The validity of Eq. (13.2) as a
source of the transfer curve of Fig. 13.15 is best demonstrated by examining a few specific levels of one variable
and finding the resulting level of the other as follows:

Substituting VGS = 0 V gives For the drain characteristics of Fig. 13.15,

if we substitute VGS = -1 V,

Substituting VGS = VP yields

It should be obvious from the above that given IDSS and VP (as is normally provided on specification sheets), the
level of ID can be found for any level of VGS. Conversely, by using basic algebra we can obtain [from Eq. (13.2)]
an equation for the resulting level of VGS for a given level of ID. The derivation is quite straightforward and results
in
When ID = 4.5 mA,

Equation 13.3. VGS given ID

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Activity 3: Skill-building Activities (Answers in Keys to Correction)

a. Fill-in the blanks. Identify the best term or phrase in each item.

a.1 A device is one in which a current defines the operating conditions of the device,
whereas a device is one in which a particular voltage defines the operating conditions.
a.2. The JFET can actually be used as a because of a unique sensitivity of the drain-
to-source impedance to the gate-to-source voltage.
a.3. The current for any JFET is labeled IDSS and occurs when VGS = 0 V.
a.4. The current for a JFET occurs at pinch-off defined by VGS = VP.
a.5. The relationship between the drain current and the gate-to-source voltage of a JFET is
as defined by Shockley’s equation. As the current level approaches IDSS, the sensitivity
of ID to changes in VGS increases significantly.
a.6. The characteristics (ID versus VGS) are characteristics of the device itself and are
not sensitive to the network in which the JFET is employed.

b. Complete the following table of values (VGS vs. ID) using Shockley’s Equation given a fixed value of IDSS to
complete the a shorthand of this equation.

VGS ID
0V
0.3 VP
0.5 VP
VP

c. Using the shorthand method provided by your answer in item (b),

sketch the transfer curve (ID in x-axis, VGS in y-axis) defined by IDSS = 12 mA and VP = - 6 V.

2) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is a “junction” and its role in a
transistor?
2. How are “bipolar” and “unipolar”
devices differ?
3. What are the independent and
dependent variables in the governing
current equation for BJT? for FET?

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3) Activity 5: Check for Understanding

This is an assessment. Solve the following problems completely. Box your final answers.

a. List at least 5 notable differences between a BJT and a FET.

b. Using the shorthand method, sketch the transfer curve for a p-channel device (ID in x-axis, VGS in y-axis)
with IDSS = 4 mA and VP = 3V.

C. LESSON WRAP-UP

1) Activity 6: Thinking about Learning

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning objectives? How did you do it?

Which strategy worked for you, easily? With difficulty?

FAQs

1. When is a FET being used as a replacement for a BJT amplifier?

Because of FETs nonlinear characteristics, they are generally not as widely used in amplifiers as BJTs except
where very high input impedances are required.

2. Which between FET and BJT is more preferred in switching applications?

FETs are the preferred device in low-voltage switching applications because they are generally faster than
BJTs when turned on and off. The insulated-gate bipolar transistor (IGBT) is generally used in high-voltage
switching applications.

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Lesson Title: Materials:

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Pencil, paper, and calculator

Depletion-type MOSFET References:

Enhancement-type MOSFET 1. Electronic Devices and Circuit
Power MOSFET, CMOS, MESFET Theory, 11th Edition by R.
Boylestad & L. Nashelsky (2013);
Lesson Objectives:
2. Electronic Devices:
At the end of this lesson, you should be able to: Conventional Current Version, 9th
● compare and contrast the construction and operation of the two Edition by Thomas Floyd (2012);
types of MOSFET: depletion type and enhancement type;
3. Electronic Principles, 8th Edition
● plot the transfer characteristic curve of MOSFET. by Albert Malvino and David J.
Bates (2016);

Productivity Tip: Keep your mind wide open and wonder! Gnaw and digest the fundamentals
and always get back to basics whenever you need to find your way back.

A. LESSON PREVIEW/REVIEW
1) Introduction

As noted in the previous module, there are three types of FETs: JFETs, MOSFETs, and MESFETs. MOSFETs
are further broken down into depletion type and enhancement type.

The terms depletion and enhancement define their basic mode of operation; the name MOSFET stands for
metal–oxide–semiconductor field-effect transistor. Since there are differences in the characteristics and
operation of different types of MOSFET, you will start to examine the depletion-type MOSFET, which has
characteristics similar to those of a JFET between cutoff and saturation at IDSS, and also has the added feature
of characteristics that extend into the region of opposite polarity for VGS. After these, you will proceed with
operation and characteristics of the enhancement-type MOSFET.

The MOSFET transistor has become one of the most important devices used in the design and construction of
integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely
popular in computer circuit design. However, as a discrete element in a typical top-hat container, it must be
handled with care. The MESFET is a more recent development and takes full advantage of the high-speed
characteristics of GaAs as the base semiconductor material. Although currently the more expensive option, the
cost issue is often outweighed by the need for higher speeds in radio frequency (RF) and computer designs.

So, how are MOSFETs constructed?

How do each type differ in operation?

Let’s move on and find the answers to these questions in the succeeding parts of this module.
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2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)

1. What is the most
important characteristic of a
FET?
2. What is the role of the
oxide layer in the gate
terminal of a FET?
3. What are other variations
of a MOSFET which are
designed to be utilized in
special applications?

B. MAIN LESSON
1) Activity 2: Content Notes

DEPLETION-TYPE MOSFET
Basic Construction. The basic construction of the n-
channel depletion-type MOSFET is provided in Fig. 14.1.
A slab of p-type material is formed from a silicon base and
is referred to as the substrate. It is the foundation on
which the device is constructed. In some cases the
substrate is internally connected to the source terminal.
However, many discrete devices provide an additional
terminal labeled SS, resulting in a four-terminal device,
such as that in Fig. 14.1. The source and drain terminals
are connected through metallic contacts to n-doped
regions linked by an n-channel as shown in the figure. The
gate is also connected to a metal contact surface but
remains insulated from the n-channel by a very thin silicon
dioxide (SiO2) layer. SiO2 is a type of insulator referred
to as a dielectric, which sets up opposing (as indicated by
the prefix di-) electric fields within the dielectric when
exposed to an externally applied field. The fact that the
SiO2 layer is an insulating layer means that: Figure 14.1
There is no direct electrical connection between the gate n-Channel depletion-type MOSFET
terminal and the channel of a MOSFET.

In addition: It is the insulating layer of SiO2 in the MOSFET construction that accounts for the very desirable high
input impedance of the device.

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In fact, the input resistance of a MOSFET is usually more than that of a typical JFET, even though the input
impedance of most JFETs is sufficiently high for most applications. Because of the very high input impedance,
the gate current IG is essentially 0 A for dc- biased configurations.

The reason for the label metal–oxide–semiconductor FET is now fairly obvious: metal for the drain, source, and
gate connections; oxide for the silicon dioxide insulating layer; and semiconductor for the basic structure on
which the n- and p-type regions are diffused. The insulating layer between the gate and the channel has resulted
in another name for the device: insulated-gate FET, or IGFET, although this label is used less and less in the
literature.

Basic Operation and Characteristics. In Fig. 14.2 the

gate-to-source voltage is set to 0 V by the direct
connection from one terminal to the other, and a voltage
VDD is applied across the drain-to-source terminals. The
result is an attraction of the free electrons of the n-channel
for the positive voltage at the drain. The result is a current
similar to that flowing in the channel of the JFET. In fact,
the resulting current with VGS = 0 V continues to be labeled
IDSS, as shown in Fig. 14.3.

Figure 14.2 (left) n-Channel depletion-type MOSFET with

VGS = 0 V and applied voltage VDD.

Figure 14.3 Drain and transfer characteristics for an n-channel depletion-type MOSFET.

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In Fig. 14.4, VGS is set at a negative voltage such as -1 V.

The negative potential at the gate will tend to pressure
electrons toward the p-type substrate (like charges repel)
and attract holes from the p-type substrate (opposite
charges attract) as shown in Fig. 14.4. Depending on the
magnitude of the negative bias established by VGS, a level
of recombination between electrons and holes will occur that
will reduce the number of free electrons in the n-channel
available for conduction. The more negative the bias, the
higher is the rate of recombination. The resulting level of
drain current is therefore reduced with increasing negative
bias for VGS, as shown in Fig. 14.3 for VGS = -1 V, -2 V, and
soon, to the pinch-off level of -6 V. The resulting levels of
drain current and the plotting of the transfer curve proceed
exactly as described for the JFET.

Figure 14.4 (left) Reduction in free carriers in a channel

due to a negative potential at the gate terminal.

For positive values of VGS, the positive gate will draw additional electrons (free carriers) from the p-type
substrate due to the reverse leakage current and establish new carriers through the collisions resulting between
accelerating particles. As the gate-to-source voltage continues to increase in the positive direction, Fig. 14.3
reveals that the drain current will increase at a rapid rate for the reasons listed above. The vertical spacing
between the VGS = 0 V and VGS = +1 V curves of Fig. 14.3 is a clear indication of how much the current has
increased for the 1-V change in VGS. Due to the rapid rise, the user must be aware of the maximum drain current
rating since it could be exceeded with a positive gate voltage. That is, for the device of Fig. 14.3, the application
of a voltage VGS = +4 V would result in a drain current of 22.2 mA, which could possibly exceed the maximum
rating (current or power) for the device.

As revealed above, the application of a positive gate-to-source voltage has “enhanced” the level of free carriers
in the channel compared to that encountered with VGS = 0 V. For this reason the region of positive gate voltages
on the drain or transfer characteristics is often referred to as the enhancement region, with the region between
cutoff and the saturation level of IDSS referred to as the depletion region.

It is particularly interesting and helpful that Shockley’s equation will continue to be applicable for the depletion-
type MOSFET characteristics in both the depletion and enhancement regions. For both regions, it is simply
necessary that the proper sign be included with VGS in the equation and the sign be carefully monitored in the
mathematical operations.

Using the shorthand method for Shockley’s equation, how do we plot the transfer characteristic curve of a
depletion-type MOSFET? An example is provided in the next page.
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Transfer Characteristics. Sketch the transfer characteristics for an n-channel depletion-type MOSFET with IDSS
= 10mA and VP = -4V.

Recall: The resulting graph:

p-Channel Depletion-Type MOSFET. The construction of a p-channel depletion-type MOSFET is exactly the
reverse of that appearing in Fig. 14.1. That is, there is now an n-type substrate and a p-type channel, as shown
in Fig. 14.5a. The terminals remain as identified, but all the voltage polarities and the current directions are
reversed, as shown in the same figure.

Figure 14.5 p-Channel depletion-type MOSFET with IDSS = 6 mA and VP = +6 V.

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The drain characteristics would appear exactly as in Fig. 14.3, but with VDS having negative values, ID having
positive values as indicated (since the defined direction is now reversed), and VGS having the opposite polarities
as shown in Fig. 14.5c. The reversal in VGS will result in a mirror image (about the ID axis) for the transfer
characteristics as shown in Fig. 14.5b. In other words, he drain current will increase from cutoff at VGS = VP in
the positive VGS region to IDSS and then continue to increase for increasingly negative values of VGS. Shockley’s
equation is still applicable and requires simply placing the correct sign for both VGS and VP in the equation.

Symbols for Depletion-Type MOSFETs. The graphic symbols for

an n- and p-channel depletion-type MOSFET are provided in Fig.
14.6. Note how the symbols chosen try to reflect the actual
construction of the device. The lack of a direct connection (due to the
gate insulation) between the gate and the channel is represented by
a space between the gate and the other terminals of the symbol. The
vertical line representing the channel is connected between the drain
and the source and is “supported” by the substrate. Two symbols are
provided for each type of channel to reflect the fact that in some
cases the substrate is externally available, whereas in others it is not.

Figure 14.6 (left) Graphic symbols for: (a) n-channel depletion-type

MOSFETs and (b) p-channel depletion-type MOSFETs.

ENHANCEMENT-TYPE MOSFET
Although there are some similarities in construction
and mode of operation between depletion-type and
enhancement-type MOSFETs, the characteristics of
the enhancement-type MOSFET are quite different
from anything obtained thus far. The transfer curve
is not defined by Shockley’s equation, and the drain
current is now cut off until the gate-to- source
voltage reaches a specific magnitude. In particular,
current control in an n-channel device is now
effected by a positive gate-to-source voltage rather
than the range of negative voltages encountered for
n-channel JFETs and n-channel depletion-type
MOSFETs.

Basic Construction. The basic construction of the

n-channel enhancement-type MOSFET is provided
in the right figure.

Fig. 14.7 n-Channel enhancement-type MOSFET.

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A slab of p-type material is formed from a silicon base and is again referred to as the substrate. As with the
depletion-type MOSFET, the substrate is sometimes internally connected to the source terminal, whereas in
other cases a fourth lead (labeled SS) is made available for external control of its potential level. The source and
drain terminals are again connected through metallic contacts to n-doped regions, but note in Fig. 14.7 the
absence of a channel between the two n-doped regions. This is the primary difference between the construction
of depletion-type and enhancement-type MOSFETs—the absence of a channel as a constructed component of
the device. The SiO2 layer is still present to isolate the gate metallic platform from the region between the drain
and source, but now it is simply separated from a section of the p-type material. In summary, therefore, the
construction of an enhancement-type MOSFET is quite similar to that of the depletion-type MOSFET, except for
the absence of a channel between the drain and source terminals.

Basic Operation and Characteristics. If VGS is set at 0 V and a voltage applied between the drain and the
source of the device of Fig. 14.7, the absence of an n-channel (with its generous number of free carriers) will
result in a current of effectively 0 A — quite different from the depletion-type MOSFET and JFET, where ID = IDSS.
It is not sufficient to have a large accumulation of carriers (electrons) at the drain and the source (due to the n-
doped regions) if a path fails to exist between the two. With VDS some positive voltage, VGS at 0 V, and terminal
SS directly connected to the source, there are in fact two reverse-biased p–n junctions between the n-doped
regions and the p-substrate to oppose any significant flow between drain and source.

In Fig. 14.8, both VDS and VGS have been set at some positive
voltage greater than 0 V, establishing the drain and the gate at
a positive potential with respect to the source. The positive
potential at the gate will pressure the holes (since like charges
repel) in the p-substrate along the edge of the SiO2 layer to
leave the area and enter deeper regions of the p-substrate, as
shown in the figure. The result is a depletion region near the
SiO2 insulating layer void of holes. However, the electrons in
the p-substrate (the minority carriers of the material) will be
attracted to the positive gate and accumulate in the region near
the surface of the SiO2 layer. The SiO2 layer and its insulating
qualities will prevent the negative carriers from being absorbed
at the gate terminal. As VGS increases in magnitude, the
concentration of electrons near the SiO2 surface increases
until eventually the induced n-type region can support a
measurable flow between drain and source. The level of VGS
that results in the significant increase in drain current is called
the threshold voltage and is given the symbol VT. On
specification sheets it is referred to as VGS(Th), although VT is
less unwieldy and will be used in the analysis to follow.

Figure 14.8 Channel formation in the

n-channel enhancement-type MOSFET.
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Since the channel is nonexistent with VGS = 0 V and “enhanced” by the application of a positive gate-to-source
voltage, this type of MOSFET is called an enhancement-type MOSFET. Both depletion- and enhancement-type
MOSFETs have enhancement-type regions, but the label was applied to the latter since it is its only mode of
operation.

As VGS is increased beyond the threshold level, the density of

free carriers in the induced channel will increase, resulting in
an increased level of drain current. However, if we hold VGS
constant and increase the level of VDS, the drain current will
eventually reach a saturation level as occurred for the JFET
and depletion-type MOSFET. The leveling off of ID is due to a
pinching-off process depicted by the narrower channel at the
drain end of the induced channel as shown in Fig. 14.9.
Applying Kirchhoff’s voltage law to the terminal voltages of the
MOSFET of Fig. 14.9, we find that

Equation 14.1
Drain-to-gate voltage (VDG)

Figure 14.9 (left) Change in channel and depletion region

with increasing level of VDS for a fixed value of VGS.

If VGS is held fixed at some value such as 8V

and VDS is increased from 2V to 5V, the voltage
VDG [by Eq. (14.1)] will increase from -6 V to -3 V
and the gate will become less and less positive
with respect to the drain. This reduction in gate-
to-drain voltage will in turn reduce the attractive
forces for free carriers (electrons) in this region of
the induced channel, causing a reduction in the
effective channel width. Eventually, the channel
will be reduced to the point of pinch-off and a
saturation condition will be established as
described earlier for the JFET and depletion-type
MOSFET. In other words, any further increase in
VDS at the fixed value of VGS will not affect the
saturation level of ID until breakdown conditions
are encountered.

Figure 14.10 (left) Drain characteristics of an n-

channel enhancement-type MOSFET

The drain characteristics of Fig. 14.10 reveal that for the device of Fig. 14.9 with VGS = 8 V, saturation occurs at
a level of VDS = 6 V. In fact, the saturation level for VDS is related to the level of applied VGS by

Equation 14.2 Drain-to-source saturation current

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For the characteristics of Fig. 14.9, the level of VT is 2 V, as revealed by the fact that the drain current has
dropped to 0 mA. In general, therefore: For values of VGS less than the threshold level, the drain current of an
enhancement-type MOSFET is 0 mA.

Figure 14.10 clearly reveals that as the level of VGS increases from VT to 8 V, the resulting saturation level for ID
also increases from a level of 0 mA to 10 mA. In addition, it is quite noticeable that the spacing between the
levels of VGS increases as the magnitude of VGS increases, resulting in ever-increasing increments in drain
current. For levels of VGS > VT, the drain current is related to the applied gate-to-source voltage by the following
nonlinear relationship:

Eq. 14.3 Drain current for enhancement-type MOSFET

Again, it is the squared term that results in the nonlinear (curved) relationship between ID and VGS. The k term is
a constant that is a function of the construction of the device. The value of k can be determined from the following
equation [derived from Eq. (6.15)], where ID (on) and VGS (on) are the values for each at a particular point on the
characteristics of the device.

Equation 14.4 Value of the constant k

Substituting ID (on) = 10 mA when VGS (on) = 8 V from the characteristics of Fig. 14.10 yields

Figure 14.11 Sketching the transfer characteristics for an n-channel enhancement-type MOSFET
from the drain characteristics.
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p-C hannel Enhancement-Type MOSFETs. The construction of a p-channel enhancement-type MOSFET is

exactly the reverse of that appearing in Fig. 14.1, as shown in Fig. 14.12a. That is, there is now an n-type
substrate and p-doped regions under the drain and source connections. The terminals remain as identified, but
all the voltage polarities and the current directions are reversed. The drain characteristics will appear as shown
in Fig. 14.12c, with increasing levels of current resulting from increasingly negative values of VGS. The transfer
characteristics of Fig.14.12b will be the mirror image (about the ID axis) of the transfer curve of Fig. 14.11, with
ID increasing with increasingly negative values of VGS beyond VT, as shown in Fig. 14.12c. Equations (14.1)
through (14.4) are equally applicable to p-channel devices.

Figure 14.12 p-Channel enhancement-type MOSFET with VT = 2 V and k = 0.5 x 10-3 A/V2

Symbols. The graphic symbols for the n- and p-channel enhancement-

type MOSFETs are provided as Fig. 14.13. Again note how the symbols
try to reflect the actual construction of the device. The dashed line
between drain and source is chosen to reflect the fact that a channel does
not exist between the two under no-bias conditions. It is, in fact, the only
difference between the symbols for the depletion-type and enhancement-
type MOSFETs.

Figure 14.13 Symbols for:

(a) n-channel enhancement-type MOSFETs and
(b) p-channel enhancement-type MOSFETs.

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2) Activity 3: Skill-building Activities (Answers in Keys to Correction)

a. True or False. Mark each item as TRUE when the statement is correct. Otherwise, mark it FALSE.

a.1. MOSFETs are available in one of two types: depletion and enhancement.
a.2 The depletion-type MOSFET has the same transfer characteristics as a JFET for drain currents up to the IDSS
level. At this point the characteristics of a depletion-type MOSFET continue to levels above IDSS, whereas those
of the JFET will end.
a.3 The arrow in the symbol of n-channel JFETs or MOSFETs will always point into the center of the symbol,
whereas those of a p-channel device will always point out of the center of the symbol.
a.4 The transfer characteristics of an enhancement-type MOSFET are not defined by Shockley’s equation but
rather by a nonlinear equation controlled by the gate-to-source voltage, the threshold voltage, and a constant k
defined by the device employed. The resulting plot of ID versus VGS rises exponentially with increasing values of
VGS.
a.5 Always handle MOSFETs with additional care due to the static electricity that exists in places we might least
suspect. Do not remove any shorting mechanism between the leads of the device until it is installed.
a.6. A CMOS (complementary MOSFET) device employs a unique combination of a p- channel and an n-channel
MOSFET with a single set of external leads. It has the advantages of a very high input impedance, fast switching
speeds, and low operating power levels, all of which make it very useful in logic circuits.
a.7. A depletion-type MESFET includes a metal–semiconductor junction, resulting in characteristics that match
those of an n-channel depletion-type JFET. Enhancement- type MESFETs have the same characteristics as
enhancement-type MOSFETs. The result of this similarity is that the same type of dc and ac analysis techniques
can be applied to MESFETs as was applied to JFETs.

b. Using ID (on) = 10 V, VGS (on) = 7 V, and an average threshold voltage of VGS(Th) = 3 V, determine the resulting
value of k for the MOSFET and the transfer characteristics.

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is the most important
characteristic of a FET?
2. What is the role of the oxide
layer in the gate terminal of a FET?
3. What are other variations of a
MOSFET which are designed to be
utilized in special applications?

4) Activity 5: Check for Understanding

This is an assessment. Solve the following problems completely. Box your final answers.

a. Sketch the transfer and drain characteristics of an n-channel depletion-type MOSFET with IDSS = 12 mA and
VP = -8 V for a range of VGS = -VP to VGS = 1 V.
b. Given ID = 14 mA and VGS = 1 V, determine VP if IDSS = 9.5 mA for a depletion-type MOSFET.
c. Given ID = 4 mA at VGS = -2 V, determine IDSS if VP = -5 V.
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d. The maximum drain current for the 2N4351 n-channel enhancement-type MOSFET is 30 mA.
Determine VGS at this current level if k = 0.06 x 10-3 A/V2 and VT is the maximum value.

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning objectives? How did you do it?

Which strategy worked for you, easily? With difficulty?

KEY TO CORRECTIONS

Activity 3

a.1 TRUE a.2 TRUE a.3 TRUE a.4 TRUE

a.5 TRUE a.6 TRUE a.7 TRUE

b. Transfer curve:

For VGS = 8, 10, 12, and 14 V, ID will be 1.525, 3 (as defined), 4.94, and 7.38 mA, respectively.

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Lesson Title: Materials:

FET Biasing Pencil, paper, and calculator

JFET Networks References:

Fixed-Bias, Self-Bias, Voltage-Divider Bias 1. Electronic Devices and Circuit
Common Gate Configuration Theory, 11th Edition by R.
Special Case Boylestad & L. Nashelsky (2013);
Depletion-type MOSFET
Enhancement-type MOSFET 2. Electronic Devices:
Conventional Current Version, 9th
Lesson Objectives: Edition by Thomas Floyd (2012);
At the end of this lesson, you should be able to:
3. Electronic Principles, 8th Edition
● perform a dc analysis of JFET and MOSFET networks; by Albert Malvino and David J.
● use load-line analysis to examine FET networks. Bates (2016).

Productivity Tip: No sacrifice, no victory.

A. LESSON PREVIEW/REVIEW
1) Introduction

For the field-effect transistor, the relationship between input and output quantities is nonlinear due to the squared
term in Shockley’s equation. Linear relationships result in straight lines when plotted on a graph of one variable
versus the other, whereas nonlinear functions result in curves as obtained for the transfer characteristics of a
JFET. The nonlinear relationship between ID and VGS can complicate the mathematical approach to the dc
analysis of FET configurations. A graphical approach may limit solutions to tenths-place accuracy, but it is a
quicker method for most FET amplifiers. Since the graphical approach is in general the most popular, the analysis
of module will have graphical solutions rather than mathematical solutions.

The general relationships that can be applied to the dc analysis of all FET amplifiers are

Equation 15.1 Gate current Equation 15.2 Drain, source current

For JFETs and depletion-type MOSFETs and MESFETs, Shockley’s equation is applied to relate the input and
output quantities:

Equation 15.3 Drain current for depletion-type MOSFET

For enhancement-type MOSFETs, the following equation is applicable:

Equation 15.4 Drain current for enhancement-type MOSFET

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It is particularly important to realize that equations 15.1 to 15.4 are for the field-effect transistor only! They do not
change with each network configuration so long as the device is in the active region. The network simply defines
the level of current and voltage associated with the operating point through its own set of equations. In reality,
the dc solution of FET networks is the solution of simultaneous equations established by the device and the
network. The solution can be determined using a mathematical or graphical approach. However, as noted earlier,
the graphical approach is the most popular for FET networks.

2) Activity 1: What I Know Chart, part 1

What I Know Questions: What I Learned (Activity 4)

1. How do we define a load-line
in a network?
2. What does the word “bias” mean
when a network is taken into
consideration?
3. What are the expected dc
parameters for FET networks?

B. MAIN LESSON
1) Activity 2: Content Notes

FIXED-BIAS CONFIGURATION
The simplest of biasing arrangements for the n-channel
JFET appears in Fig. 15.1. Referred to as the fixed-bias
configuration, it is one of the few FET configurations that
can be solved just as directly using either a mathematical or
a graphical approach. Both methods are included in this
section to demonstrate the difference between the two
methods and also to establish the fact that the same
solution can be obtained using either approach.

Figure 15.1 Fixed-bias configuration.

The configuration of Fig. 15.1 includes the ac levels Vi and Vo and the coupling capacitors (C1 and C2). Recall
that the coupling capacitors are “open circuits” for the dc analysis and low impedances (essentially short circuits)
for the ac analysis. The resistor RG is present to ensure that Vi appears at the input to the FET amplifier for the
ac analysis. For the dc analysis,

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The zero-volt drop across RG permits replacing RG by a short-circuit

equivalent, as appearing in the network of Fig. 15.2, specifically redrawn
for the dc analysis. The fact that the negative terminal of the battery is
connected directly to the defined positive potential of VGS clearly reveals
that the polarity of VGS is directly opposite to that of VGG. Applying
Kirchhoff’s voltage law in the clockwise direction of the indicated loop of
Fig. 15.2 results in

Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude,

resulting in the designation “fixed-bias configuration.” The resulting level of
drain current is now controlled by Shockley’s equation (Eq. 15.3)

Figure 15.2 Fixed-bias for dc analysis

Since VGS is a fixed quantity for this configuration, its magnitude and sign can simply be substituted into
Shockley’s equation and the resulting level of ID calculated. This is one of the few instances in which a
mathematical solution to a FET configuration is quite direct. A graphical analysis would require a plot of
Shockley’s equation as shown in Fig. 15.3. Recall that choosing VGS = VP/2 will result in a drain current of
IDSS/4 when plotting the equation. For the analysis of this chapter, the three points defined by IDSS, VP, and
the intersection just described will be sufficient for plotting the curve.

Figure 15.3 Plotting Shockley’s equation. Figure 15.4 Finding the solution for the fixed-bias
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In Fig. 15.4, the fixed level of VGS has been superimposed as a vertical
line at VGS = -VGG. At any point on the vertical line, the level of VGS
is -VGG—the level of ID must simply be determined on this vertical line.
The point where the two curves intersect is the common solution to the
configuration—commonly referred to as the quiescent or operating
point. The subscript Q will be applied to the drain current and gate-to-
source voltage to identify their levels at the Q-point.

Note in Fig. 15.4 that the quiescent level of ID is determined by drawing

a horizontal line from the Q-point to the vertical ID axis. It is important
to realize that once the network of Fig. 15.1 is constructed and
operating, the dc levels of ID and VGS that will be measured by the
meters of Fig. 15.5 are the quiescent values defined by Fig. 15.4.

Figure 15.5 Measuring the quiescent values of ID and VGS.

Following these measurements, the following equations hold:

The fact that VD = VDS and VG = VGS is fairly obvious from the fact that VS = 0 V, but the derivations above
were included to emphasize the relationship that exists between double-subscript and single-subscript notation.
Since the configuration requires two dc supplies, its use is limited and will not be included in the forthcoming list
of the most common FET configurations.

SELF-BIAS CONFIGURATION
The self-bias configuration eliminates the need for two dc supplies. The controlling gate-to-source voltage is now
determined by the voltage across a resistor RS introduced in the source leg of the configuration as shown in Fig.
15.6.

For the dc analysis, the capacitors can again be replaced by “open circuits” and the resistor RG replaced by a
short-circuit equivalent since IG = 0 A. The result is the network of Fig. 15.7 for the important dc analysis. The
current through RS is the source current IS, but

IS = ID VR = IDRS Equation 15.5

VGS for
For the indicated closed loop of Fig. 15.7, we find that Self-Bias

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Figure 15.6 Figure 15.7

JFET self-bias configuration DC analysis of the self-bias configuration.

Note in this case that VGS is a function of the output current ID and not fixed in magnitude as occurred for the
fixed-bias configuration.

The formula for VGS is defined by the network configuration, and Shockley’s equation relates the input and
output quantities of the device. Both equations relate the same two variables, ID and VGS, permitting either a
mathematical or a graphical solution. A mathematical solution could be obtained simply by substituting the
expression for VGS into Shockley’s equation as follows:

By performing the squaring process indicated and rearranging terms, we obtain an equation of the following
form:

The quadratic equation can then be solved for the appropriate solution for ID.

The graphical approach requires that we first establish the device transfer characteristics as shown in Fig. 15.8.
Since expression for VGS defines a straight line on the same graph, let us now identify two points on the graph
that are on the line and simply draw a straight line between the two points. The most obvious condition to apply
is ID = 0 A since it results in VGS = -IDRS = (0 A)(RS) = 0 V. The expression for VGS, therefore, one point on
the straight line is defined by ID = 0 A and VGS = 0 V, as appearing on Fig. 15.8.

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Figure 15.8 Defining a point on the self-bias line. Figure 15.9 Sketching the self-bias line.

The second point for VGS = -IDRS requires that a level of VGS or ID be chosen and the corresponding level of
the other quantity be determined using VGS = -IDRS. The resulting levels of ID and VGS will then define another
point on the straight line and permit the drawing of the straight line. Suppose, for example, that we choose a
level of ID equal to one-half the saturation level. That is,

The result is a second point for the straight-line plot as shown in Fig. 15.9. The straight line as defined by VGS
= -IDRS is then drawn and the quiescent point obtained at the intersection of the straight-line plot and the device
characteristic curve. The quiescent values of ID and VGS can then be determined and used to find the other
quantities of interest.

The level of VDS can be determined by applying Kirchhoff’s voltage law to the output circuit, with the result that

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VOLTAGE-DIVIDER BIAS
The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to FET amplifiers as
demonstrated by Fig. 15.10. The basic construction is exactly the same, but the dc analysis of each is quite
different. IG = 0 A for FET amplifiers, but the magnitude of IB for common-emitter BJT amplifiers can affect the
dc levels of current and volt- age in both the input and output circuits. Recall that IB provides the link between
input and output circuits for the BJT voltage-divider configuration, whereas VGS does the same for the FET
configuration.

Figure 15.10 Figure 15.11

Voltage-divider bias arrangement. Redrawn network of Fig. 15.10 for dc analysis.

The network of Fig. 15.10 is redrawn as shown in Fig. 15.11 for the dc analysis. Note that all the capacitors,
including the bypass capacitor CS, have been replaced by an “open-circuit” equivalent in Fig. 15.11b. In addition,
the source VDD was separated into two equivalent sources to permit a further separation of the input and output
regions of the network. Since IG = 0 A, Kirchhoff’s current law requires that IR = IR , and the series equivalent
circuit appearing to the left of the figure can be used to find the level of VG. The voltage VG, equal to the voltage
across R2, can be found using the voltage-divider rule and Fig. 15.11a as follows:

Applying Kirchhoff’s voltage law in the clockwise direction to the indicated loop:

Equation 15.6 VGS for Voltage-Divider

The result is an equation that continues to include the same two variables appearing in Shockley’s equation:
VGS and ID. The quantities VG and RS are fixed by the network construction. Equation (15.6) is still the equation
for a straight line, but the origin is no longer a point in the plotting of the line. The procedure for plotting Eq. (15.6)
is not a difficult one and will proceed as follows. Since any straight line requires two points to be defined, let us
first use the fact that anywhere on the horizontal axis of Fig. 15.12 the current ID = 0 mA. If we therefore select

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ID to be 0 mA, we are in essence stating that we are somewhere on the horizontal axis. The exact location can
be determined simply by substituting ID = 0 mA into Eq. (15.6) and finding the resulting value of VGS as follows:

The result specifies that whenever we plot Eq. (15.6), if we choose ID = 0 mA, the value of VGS for the plot will
be VG volts. The point just determined appears in Fig. 15.12.

Figure 15.12 Figure 15.13

Sketching the network equation Effect of RS on the resulting Q-point.
for the voltage-divider configuration.

For the other point, let us now employ the fact that at any point on the vertical axis VGS = 0V and solve for the
resulting value of ID:

The result specifies that whenever we plot Eq. (15.6), if VGS = 0 V, the level of ID is determined by the equation
for ID. This intersection also appears on Fig. 15.12. The two points defined above permit the drawing of a straight
line to represent Eq. (15.6). The intersection of the straight line with the transfer curve in the region to the left of
the vertical axis will define the operating point and the corresponding levels of ID and VGS.

Since the intersection on the vertical axis is determined by ID = VG/RS and VG is fixed by the input network,
increasing values of RS will reduce the level of the ID intersection as shown in Fig. 15.13. It is fairly obvious from
Fig. 15.13 that: Increasing values of RS result in lower quiescent values of ID and declining values of VGS.

Once the quiescent values of IDQ and VGSQ are determined,

the remaining network analysis can be performed in the usual manner. That is,

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COMMON-GATE CONFIGURATION
The next configuration is one in which the gate terminal is grounded and the input signal typically applied to the
source terminal and the output signal obtained at the drain terminal as shown in Fig. 15.14a. The network can
also be drawn as shown in Fig. 15.14b.

Figure 15.14 Two versions of the common-gate configuration

Applying Kirchhoff’s voltage law in the direction shown in Fig. 15.15 will result in:

Applying the condition ID = 0 mA:

Applying the condition VGS = 0 V:

The resulting load-line appears in Fig. 15.16 intersecting the transfer curve for the
Figure 9.15 Determining JFET as shown in the figure. The resulting intersection defines the operating
the network equation current IDQ and voltage VDQ for the network as also indicated in the network.

Applying Kirchhoff’s voltage law around the loop containing the two sources, the JFET and the resistors RD
and RS in Fig. 15.14a and Fig. 15.14b will result in +VDD - IDRD - VDS - ISRS + VSS = 0

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Substituting IS = ID we have +VDD + VSS - VDS - ID(RD +RS) = 0

Thus,

Figure 15.16 (left)

Determining the Q-point for the network

SPECIAL CASE: VGSQ = 0

A network of recurring practical value because of its relative simplicity is the configuration of Fig. 15.17. Note
that direct connection of the gate and source terminals to ground resulting in VGS = 0 V. It specifies that for any
dc condition the gate to source voltage must be zero volts. This will result in a vertical load line at VGS = 0 V as
shown in Fig. 15.18.

Figure 15.17 Figure 15.18

Special case VGSQ = 0 configuration. Finding the Q-point for the network

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Since the transfer curve of a JFET will cross the vertical axis at IDSS the drain current for the network is set at
that level. Therefore,

Applying Kirchhoff’s voltage law: VDD - IDRD -VDS = 0

Thus,

DEPLETION-TYPE MOSFET
The similarities in appearance between the transfer curves of JFETs and depletion-type MOSFETs permit a
similar analysis of each in the dc domain. The primary difference between the two is the fact that depletion-type
MOSFETs permit operating points with positive values of VGS and levels of ID that exceed IDSS. In fact, for all
the configurations dis- cussed thus far, the analysis is the same if the JFET is replaced by a depletion-type
MOSFET.

The only undefined part of the analysis is how to plot Shockley’s equation for positive values of VGS. How far
into the region of positive values of VGS and values of ID greater than IDSS does the transfer curve have to
extend? For most situations, this required range will be fairly well defined by the MOSFET parameters and the
resulting bias line of the network. A few examples will reveal the effect of the change in device on the resulting
analysis.

Example A: For the n-channel depletion-type

MOSFET of Fig. 15.19, determine: IDQ , VGSQ ,
and VDS.

For the transfer characteristics, a plot point is

defined by ID = IDSS/4 = 6 mA/4 = 1.50 mA and
VGS = VP/2 = -3 V/2 = -1.50 V. Considering the
level of VP and the fact that Shockley’s equation
defines a curve that rises more rapidly as VGS
becomes more positive, a plot point will be defined
at VGS = +1 V. Substituting into Shockley’s
equation yields

Figure 15.19 Depletion-type MOSFET network

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The resulting transfer curve appears in Fig. 15.20.

Proceeding as described for JFETs, we have

Setting ID = 0 mA results in VGS = VG = 1.5 V

Setting VGS = 0 V yields

The plot points and resulting bias line appear in Fig.

9.20. The resulting operating point is given by

Figure 15.20 Load Line of the Example A

Example B. Repeat Example A with RS = 150 .

The plot points are the same for the transfer curve as
shown in Fig. 15.21. For the bias line,
VGS = VG - IDRS = 1.50 V - ID(150 .)
Setting ID = 0 mA results in
VGS = 1.50 V
Setting VGS = 0 V yields

The bias line is included on Fig. 15.21. Note in this case

that the quiescent point results in a drain current that
exceeds IDSS, with a positive value for VGS. The result
is

Figure 15.21 Load Line of Example B

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ENHANCEMET-TYPE MOSFET
The transfer characteristics of the enhancement-type MOSFET are quite different from those encountered for
the JFET and depletion-type MOSFETs, resulting in a graphical solution quite different from those of the
preceding sections. First and foremost, recall that for the n-channel enhancement-type MOSFET, the drain
current is zero for levels of gate-to-source voltage less than the threshold level VGS(Th), as shown in Fig. 15.22.
For levels of VGS greater than VGS(Th), the drain current is defined by

Equation 15.7 Drain current for enhancement-type MOSFET

Since specification sheets typically provide the threshold voltage and a level of drain current (ID(on)) and its
corresponding level of VGS(on), two points are defined immediately as shown in Fig. 15.22. To complete the
curve, the constant k must be determined from the specification sheet data by substituting into Eq. (15.7) and
solving for k as follows:

Equation 15.8 Constant k

Once k is defined, other levels of ID can be

determined for chosen values of VGS.
Typically, a point between VGS(Th) and
VGS(on) and one just greater than VGS(on)
will provide a sufficient number of points to plot
Eq. (15.7) (note ID1 and ID2 on Fig. 15.22).

Figure 15.22 Transfer characteristics

of an n-channel enhancement-type MOSFET.

Feedback Biasing Arrangement. A popular biasing arrangement for enhancement-type MOSFETs is provided
in Fig. 15.23. The resistor RG brings a suitably large voltage to the gate to drive the MOSFET “on.” Since IG =
0 mA, VRG = 0 V and the dc equivalent network appears as shown in Fig. 15.24.

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Figure 15.23 Figure 15.24

Feedback biasing arrangement DC equivalent of the network

A direct connection now exists between drain and gate, resulting in VD = VG

For the output circuit, VDS = VDD - IDRD which becomes the following after substitution:

Equation 15.8 Gate-to-source voltage

The result is an equation that relates ID to VGS, permitting the plot of both on the same set of axes.
Since VGS = VDD - IDRD is that of a straight line, the same procedure described earlier can be employed to
determine the two points that will define the plot on the graph. Substituting ID = 0 mA into VGS = VDD - IDRD
gives

Substituting VGS = 0 V into Eq.

(15.36), we have

The plots defined by Eqs. (15.7) and

(15.8) appear in Fig. 15.25 with the
resulting operating point.

Fig. 15.25 (left) Q-point for Fig. 15.23

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Example C. Determine IDQ and VDSQ for the

enhancement-type MOSFET in the given network.

Plotting the Transfer Curve

Solving for k, we obtain

For VGS = 6 V (between 3 and 8 V):

ID = 0.24 x 10-3 (6V – 3V)2 = 0.24 x 10-3 (9)
ID = 2.16 mA
For VGS = 10 V (slightly greater than VGS(Th)),
ID = 0.24 x 10-3(10 V – 3 V)2 = 0.24 x 10-3 (49) = 11.76 mA

The four points are sufficient to plot the full curve for the range of interest as shown in Fig. 15.26.

For the Network Bias Line

VGS = VDD – IDRD = 12V - ID(2 k)

The resulting bias line appears in Fig. 15.27

Figure 15.26 Figure 15.27

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Voltage-Divider Biasing Arrangement. A second popular biasing

arrangement for the enhancement-type MOSFET appears in Fig. 15.28. The
fact that IG = 0 mA results in the following equation for VGG as derived from an
application of the voltage-divider rule:

Applying Kirchhoff’s voltage law around the indicated loop of Fig. 15.28 results
in

Once IDQ and VGSQ are known, all the remaining quantities of the network
such as VDS, VD, and VS can be determined.
Figure 15.28 Voltage-divider

Example D. Determine IDQ, VGSQ, and VDS for the network and plot the load line.

16

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Table 15.1 Summary of FET Bias Configurations

17

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2) Activity 3: Skill-building Activities (Answers in Keys to Correction)

3.1 For the fixed-bias network, determine: 3.2 For the self-bias network, determine:
a. VGSQ; b. IDQ; c. VDS; d. VD; e. VG; f. VS. a. VGSQ; b. IDQ; c. VDS; d. VS; e. VG; f. VD.

3.3 For the voltage-divider network, determine: 3.4 For the common-gate configuration, determine:
a. IDQ and VGSQ; b. VD; c. VS; d. VDS; e. VDG. a. VGSQ; b. IDQ; c. VD; d. VG; e. VS; f. VDS.

18

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3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)
1. How do we define a load-line
in a network?
2. What does the word “bias” mean
when a network is taken into
consideration?
3. What are the expected dc
parameters for FET networks?

4) Activity 5: Check for Understanding

This is an assessment. Solve the following problems completely. Box your final answers.

5.1 Given VDS = 4 V for the network, 5.2 Determine VD and VGS.
determine: a. ID; c. VD and VD ; c. VGS.

5.3 For the network 5.4 For the voltage-divider configuration

a. IDQ and VGSQ. a. IDQ and VGSQ.
b. VDS and VS. b. VDS and VS.

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C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

Which strategy worked for you, easily? With difficulty?

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Lesson Title: Materials:

Operational Amplifiers – Part 1 Pencil, paper, and calculator

Introduction to Operational Amplifiers References:

Op-Amp Input Modes and Parameters 1. Electronic Devices and Circuit
Op-Amps with Negative Feedback Theory, 11th Edition by R.
Bias Current and Offset Voltage Boylestad & L. Nashelsky (2013);
Open-Loop Frequency and Phase Responses
Closed-Loop Frequency Response 2. Electronic Devices:
Conventional Current Version, 9th
Lesson Objectives: Edition by Thomas Floyd (2012);

At the end of this lesson, you should be able to: 3. Electronic Principles, 8th Edition
● Describe the basic operational amplifier and its characteristics; by Albert Malvino and David J.
● Discuss op-amp modes and several parameters; Bates (2016);
● Explain and analyze op-amps with negative feedback;
● Discuss bias current and offset voltage;
● Analyze the open-loop frequency response of an op-amp;
● Analyze the closed-loop frequency response of an op-amp.

Productivity Tip: Focus on “why” you’re doing something. The “how” will follow suit.

A. LESSON PREVIEW/REVIEW
1) Introduction

Now you will begin the study of linear integrated circuits (ICs), where many transistors, diodes, resistors, and
capacitors are fabricated on a single tiny chip of semiconductive material and packaged in a single case to form
a functional circuit. An integrated circuit, such as an operational amplifier (op-amp), is treated as a single device.
This means that you will be concerned with what the circuit does more from an external viewpoint than from an
internal, component-level viewpoint.
In this module, you will learn the basics of op-amps, which are the most versatile and widely used of all linear
integrated circuits. You will also learn about open-loop and closed-loop frequency responses, bandwidth, phase
shift, and other frequency-related parameters. The effects of negative feedback will be examined.

2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)
1. What is an operational
amplifier?
2. What is negative
feedback?
3. What are the benefits of
negative feedback?

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B. MAIN LESSON
1) Activity 2: Content Notes (13 mins)

INTRODUCTION TO OPERATIONAL AMPLIFIERS

Early operational amplifiers (op-amps) were used primarily to perform mathematical operations such as
addition, subtraction, integration, and differentiation—thus the term operational. These early devices were
constructed with vacuum tubes and worked with high voltages. Today’s op-amps are linear integrated circuits
(ICs) that use relatively low dc supply voltages and are reliable and inexpensive.

The standard operational

amplifier (op-amp) symbol is shown in
Figure 16a.1(a). It has two input
terminals, the inverting (-) input and the
noninverting (+) input, and one output
terminal. Most op-amps operate with
two dc supply voltages, one positive and
the other negative, as shown in Figure
16a.1(b), although some have a single
dc supply. Usually these dc voltage
terminals are left off the schematic
symbol for simplicity but are understood
to be there. Some typical op-amp IC
packages are shown in Figure 16a.1(c).

Figure 16a.1 Op-amp symbols

and packages.

The Ideal Op-Amp. To illustrate what

an op-amp is, let’s consider its ideal
characteristics. A practical op-amp, of course, falls short of these ideal standards, but it is much easier to
understand and analyze the device from an ideal point of view.

Figure 16a.2 Basic op-amp representations.

First, the ideal op-amp has infinite voltage gain and infinite bandwidth. Also, it has an infinite input impedance
(open) so that it does not load the driving source. Finally, it has a zero output impedance. Op-amp characteristics

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are illustrated in Figure 16a.2(a). The input voltage, Vin, appears between the two input terminals, and the output
voltage is AvVin, as indicated by the internal voltage source symbol. The concept of infinite input impedance is a
particularly valuable analysis tool for the various op-amp configurations.

The Practical Op-Amp . Although integrated circuit (IC) op-amps approach parameter values that can be treated
as ideal in many cases, the ideal device can never be made. Any device has limitations, and the IC op-amp is
no exception. Op-amps have both voltage and current limitations. Peak- to-peak output voltage, for example, is
usually limited to slightly less than the two supply voltages. Output current is also limited by internal restrictions
such as power dissipation and component ratings.
Characteristics of a practical op-amp are very high voltage gain, very high input impedance, and very low
output impedance. These are labelled in Figure 16a.2(b). Another practical consideration is that there is always
noise generated within the op-amp. Noise is an undesired signal that affects the quality of a desired signal.
Today, circuit designers are using smaller voltages that require high accuracy, so low-noise components are in
greater demand. All circuits generate noise; op-amps are no exception, but the amount can be minimized.

Internal Block Diagram of an Op-Amp. A typical op-amp is made up of three types of amplifier circuits: a
differential amplifier, a voltage amplifier, and a push-pull amplifier, as shown in Figure 16a.3. The differential
amplifier is the input stage for the op-amp. It pro- vides amplification of the difference voltage between the two
inputs. The second stage is usually a class A amplifier that provides additional gain. Some op-amps may have
more than one voltage amplifier stage. A push-pull class B amplifier is typically used for the output stage.

Figure 16a.3 Basic internal arrangement of an op-amp.

The term differential comes from the amplifier’s ability to amplify the difference of two input signals applied to its
inputs. Only the difference in the two signals is amplified; if there is no difference, the output is zero. The
differential amplifier exhibits two modes of operation based on the type of input signals. These modes are
differential and commo. Since the differential amplifier is the input stage of the op-amp, the op-amp exhibits the
same modes.
OP-AMP INPUT MODES AND PARAMETERS
In this part, important op-amp input modes and several parameters are defined. Also several common IC op-
amps are compared in terms of these parameters.

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Input Signal Modes. Recall that the input signal modes are determined by the differential amplifier input stage
of the op-amp.
Differential Mode. In the differential mode, either one signal is applied to an input with the other input
grounded or two opposite-polarity signals are applied to the inputs. When an op-amp is operated in the single-
ended differential mode, one input is grounded and a signal voltage is applied to the other input, as shown in
Figure 16a.4. In the case where the signal voltage is applied to the inverting input as in part (a), an inverted,
amplified signal voltage appears at the output. In the case where the signal is applied to the non- inverting input
with the inverting input grounded, as in Figure 16a.4(b), a noninverted, amplified signal voltage appears at the
output.

Figure 16a.4 Single-ended differential mode

In the double-ended differential mode, two opposite-polarity (out-of-phase) signals are applied to the inputs,
as shown in Figure 16a.5(a). The amplified difference between the two inputs appears on the output.
Equivalently, the double-ended differential mode can be represented by a single source connected between the
two inputs, as shown in Figure 16a.5(b).

Figure 16a.5 Double-ended differential mode

Common Mode. In the common mode, two signal voltages of the same phase, frequency, and amplitude
are applied to the two inputs, as shown in Figure 16a.6. When equal input signals are applied to both inputs,
they tend to cancel, resulting in a zero output voltage.

Figure 16a.6 Common mode operation

This action is called common-mode rejection. Its importance lies in the situation where an unwanted signal
appears commonly on both op-amp inputs. Common-mode rejection means that this unwanted signal will not

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appear on the output and distort the desired signal. Common-mode signals (noise) generally are the result of
the pick-up of radiated energy on the input lines, from adjacent lines, the 60 Hz power line, or other sources.
Op-Amp Parameters
Common-Mode Rejection Ratio. Desired signals can appear on only one input or with opposite polarities on
both input lines. These desired signals are amplified and appear on the output as previously discussed.
Unwanted signals (noise) appearing with the same polarity on both input lines are essentially cancelled by the
op-amp and do not appear on the output. The measure of an amplifier’s ability to reject common-mode signals
is a parameter called the CMRR (common-mode rejection ratio).
Ideally, an op-amp provides a very high gain for differential-mode signals and zero gain for common-mode
signals. Practical op-amps, however, do exhibit a very small common-mode gain (usually much less than 1),
while providing a high open-loop differential voltage gain (usually several thousand). The higher the open-loop
gain with respect to the common-mode gain, the better the performance of the op-amp in terms of rejection of
common-mode signals. This suggests that a good measure of the op-amp’s performance in rejecting unwanted
common-mode signals is the ratio of the open-loop differential voltage gain, Aol, to the common-mode gain, Acm.
This ratio is the common-mode rejection ratio, CMRR.

The higher the CMRR, the better. A very high value of CMRR means that the open-loop gain, Aol, is high and
the common-mode gain, Acm, is low. The CMRR is often expressed in decibels (dB) as

The open-loop voltage gain, Aol, of an op-amp is the internal voltage gain of the device and represents the ratio
of output voltage to input voltage when there are no external components. The open-loop voltage gain is set
entirely by the internal design. Open-loop voltage gain can range up to 200,000 (106 dB) and is not a well-
controlled parameter. Datasheets often refer to the open-loop voltage gain as the large-signal voltage gain.

A CMRR of 100,000, for example, means that the desired input signal (differential) is amplified 100,000 times
more than the unwanted noise (common-mode). If the amplitudes of the differential input signal and the common-
mode noise are equal, the desired signal will appear on the output 100,000 times greater in amplitude than the
noise. Thus, the noise or interference has been essentially eliminated.

Maximum Output Voltage Swing (VO(p-p)). With no input signal, the output of an op- amp is ideally 0 V. This is
called the quiescent output voltage. When an input signal is applied, the ideal limits of the peak-to-peak output
signal are  VCC. In practice, however, this ideal can be approached but never reached. VO(p-p) varies with the
load connected to the op-amp and increases directly with load resistance.

Some op-amps do not use both positive and negative supply voltages. One example is when a single dc voltage
source is used to power an op-amp that drives an analog-to-digital converter. In this case, the op-amp output is
designed to operate between ground and a full scale output that is near (or at) the positive supply voltage. Op-
amps that operate on a single supply use the terminology VOH and VOL to specify the maximum and minimum
output voltage. (Note that these are not the same as the digital definitions of VOL and VOH.)
Input Offset Voltage. The ideal op-amp produces zero volts out for zero volts in. In a practical op-amp, however,
a small dc voltage, VOUT(error), appears at the output when no differential input voltage is applied. Its primary cause
is a slight mismatch of the base- emitter voltages of the differential amplifier input stage of an op-amp.

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As specified on an op-amp datasheet, the input offset voltage, VOS, is the differential dc voltage required between
the inputs to force the output to zero volts. Typical values of input offset voltage are in the range of 2 mV or less.
In the ideal case, it is 0 V.

The input offset voltage drift is a parameter related to VOS that specifies how much change occurs in the input
offset voltage for each degree change in temperature. Typical values range anywhere from about 5 mV per
degree Celsius to about 50 mV per degree Celsius. Usually, an op-amp with a higher nominal value of input
offset voltage exhibits a higher drift.

Input Bias Current. You have seen that the input terminals of a
bipolar differential amplifier are the transistor bases and, therefore,
the input currents are the base currents. The input bias current is
the dc current required by the inputs of the amplifier to properly
operate the first stage. By definition, the input bias current is the
average of both input currents.
Figure 16a.7 Input bias current

Input Impedance. Two basic ways of specifying the input impedance of an op-amp are the differential and the
common mode. The differential input impedance is the total resistance between the inverting and the
noninverting inputs, as illustrated in Figure 16a.8(a). Differential impedance is measured by determining the
change in bias current for a given change in differential input voltage. The common-mode input impedance is
the resistance between each input and ground and is measured by determining the change in bias current for a
given change in common-mode input voltage. It is depicted in Figure 16a.8(b).

Figure 16a.8 Op-amp input impedance.

Input Offset Current. Ideally, the two input bias currents are equal, and thus their difference is zero. In a practical
op-amp, however, the bias currents are not exactly equal. The input offset current, I OS, is the difference of the
input bias currents, expressed as an absolute value.

Actual magnitudes of offset current are usually at least an order of magnitude (ten times) less than the bias
current. In many applications, the offset current can be neglected. However, high-gain, high-input impedance
amplifiers should have as little IOS as possible because the difference in currents through large input resistances
develops a substantial offset voltage, as shown in Figure 16a.9.

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Figure 11.9 Effect of input offset current.

The offset voltage developed by the input offset current is

The error created by IOS is amplified by the gain Av of the op-amp and appears in the output as

A change in offset current with temperature affects the error

voltage. Values of temperature coefficient for the offset current
in the range of 0.5 nA per degree Celsius are common.

Output Impedance. The output impedance is the resistance

viewed from the output terminal of the op-amp, as indicated in
Figure 16a.10.

Figure 16a.10 Op-amp output impedance.

Slew Rate. The maximum

rate of change of the output
voltage in response to a step
input voltage is the slew rate
of an op-amp. The slew rate
is dependent upon the high-
frequency response of the
amplifier stages within the
op-amp.

Figure 16a.11
Slew rate measurement

Slew rate is measured with an op-amp connected as shown in Figure 16a.1(a). This particular op-amp connection
is a unity-gain, noninverting configuration. It gives a worst-case (slowest) slew rate. Recall that the high-
frequency components of a voltage step are contained in the rising edge and that the upper critical frequency of
an amplifier limits its response to a step input. For a step input, the slope on the output is inversely proportional
to the upper critical frequency. Slope increases as upper critical frequency decreases.

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A pulse is applied to the input and the resulting ideal output voltage is indicated in Figure 16a.11(b). The width
of the input pulse must be sufficient to allow the output to “slew” from its lower limit to its upper limit. A certain
time interval, t, is required for the output voltage to go from its lower limit -Vmax to its upper limit +Vmax, once the
input step is applied. The slew rate is expressed as

where Vout = +Vmax - (-Vmax). The unit of slew rate is volts per microsecond (V/s).

Frequency Response. The internal amplifier stages that make up an op-amp have voltage gains limited by
junction capacitances. Although the differential amplifiers used in op-amps are somewhat different from the basic
amplifiers discussed earlier, the same principles apply. An op-amp has no internal coupling capacitors, however;
therefore, the low-frequency response extends down to dc (0 Hz).

Noise Specification. Noise has become a more important issue in new circuit designs because of the
requirement to run at lower voltages and with greater accuracy than in the past. As little as two or three microvolts
can create errors in analog-to-digital con- version. Many sensors produce only tiny voltages that can be masked
by noise. As a result, unwanted noise from op-amps and components can degrade the performance of circuits.
Noise is defined as an unwanted signal that affects the quality of a desired signal. While interference from an
external source (such as a nearby power line) qualifies as noise, for the purpose of op-amp specifications,
interference is not included. Only noise generated within the op-amp is considered in the noise specification.
When the op-amp is added to a circuit, additional noise contributions are added from other circuit elements, such
as the feedback resistors or any sensors. For example, all resistors generate thermal noise—even one sitting in
the parts bin. The circuit designer must consider all sources within the circuit, but the concern here is the op-
amp specification for noise, which only considers the op-amp.

There are two basic forms of noise. At low

frequencies, noise is inversely proportional to the
frequency; this is called 1/f noise or “pink noise”.
Above a critical noise frequency, the noise
becomes flat and is spread out equally across the
frequency spectrum; this is called “white noise”.
The power distribution of noise is measured in
watts per hertz (W/Hz). Power is proportional to
the square of the voltage, so noise voltage
(density) is found by taking the square root of the
noise power density, resulting in units of volts per
square root hertz (V/Hz). For operational
amplifiers, noise level is normally shown with units
of nVHz and is specified to the input at a specific
frequency above the critical frequency. At low
frequencies, the noise level is higher than this due
to the 1/f noise contribution as you can see from
the graph.

Figure 16a.12 Noise as a function of

frequency for a typical op-amp.

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NEGATIVE FEEDBACK
Negative feedback is one of the most useful concepts in
electronics, particularly in op-amp applications. Negative
feedback is the process whereby a portion of the output
voltage of an amplifier is returned to the input with a phase
angle that opposes (or subtracts from) the input signal.

Negative feedback is illustrated in Figure 16a.13. The

inverting (-) input effectively makes the feedback signal 180°
out of phase with the input signal.

Figure 16a.13 (right) Illustration of negative

feedback.

Why Use Negative Feedback? The inherent open-loop voltage gain of a typical op-amp is very high (usually
greater than 100,000). Therefore, an extremely small input voltage drives the op-amp into its saturated output
states. In fact, even the input offset voltage of the op-amp can drive it into saturation. For example, assume VIN
= 1 mV and Aol = 100,000. Then, VIN Aol = (1 mV)(100,000) = 100 V.

Since the output level of an op-amp can never reach 100 V, it is driven deep into saturation and the output is
limited to its maximum output levels, as illustrated in Figure 16a.14 for both a positive and a negative input
voltage of 1 mV.

The usefulness of an op-amp operated without negative feedback is generally limited to comparator applications.
With negative feedback, the closed-loop voltage gain (Acl) can be reduced and controlled so that the op-amp can
function as a linear amplifier. In addition to providing a controlled, stable voltage gain, negative feedback also
provides for control of the input and output impedances and amplifier bandwidth. Table 16a.1 summarizes the
general effects of negative feedback on op-amp performance.

Table 16a.1 General effects of negative feedback on op-amp performance

OP-AMPS WITH NEGATIVE FEEDBACK

An op-amp can be connected using negative feedback to stabilize the gain and increase frequency response.
Negative feedback takes a portion of the output and applies it back out of phase with the input, creating an

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effective reduction in gain. This closed-loop gain is usually much less than the open-loop gain and independent
of it.
Closed-Loop Voltage Gain, Acl
The closed-loop voltage gain is the voltage gain of an op-amp with external feedback. The amplifier
configuration consists of the op-amp and an external negative feedback circuit that connects the output to the
inverting input. The closed-loop voltage gain is determined by the external component values and can be
precisely controlled by them.

Noninverting Amplifier
An op-amp connected in a closed-loop configuration as a
noninverting amplifier with a controlled amount of voltage
gain is shown in Figure 16a.15. The input signal is applied to
the noninverting (+) input. The output is applied back to the
inverting (-) input through the feedback circuit (closed loop)
formed by the input resistor Ri and the feedback resistor Rf.
This creates negative feedback as follows. Resistors Ri and
Rf form a voltage-divider circuit, which reduces Vout and
connects the reduced voltage Vf to the inverting input. The
feedback voltage is expressed as

Figure 16a.15 Noninverting amplifier.

The difference of the input voltage, Vin, and the feedback voltage, Vf, is the differential input to the op-amp, as
shown in Figure 16a.16. This differential voltage is amplified by the open-loop voltage gain of the op-amp (Aol)
and produces an output voltage expressed as

The attenuation, B, of the feedback circuit is

Substituting BVout for Vf in the Vout equation,

Then applying basic algebra,

Since the overall voltage gain of the amplifier in Figure 16a.15 is Vout/Vin,

The product AolB is typically much greater than 1, so the equation simplifies to

The closed-loop gain of the noninverting (NI) amplifier is the reciprocal of the attenuation (B) of the feedback
circuit (voltage-divider).

Therefore,
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Notice that the closed-loop voltage gain is not at all dependent on the op-amp’s open-loop voltage gain under
the condition AolB >> 1. The closed-loop gain can be set by selecting values of Ri and Rf.

Voltage-Follower
The voltage-follower configuration is a special case of the noninverting
amplifier where all of the output voltage is fed back to the inverting (-) input
by a straight connection, as shown in Figure 16a.16. As you can see, the
straight feedback connection has a voltage gain of 1 (which means there
is no gain). The closed-loop voltage gain of a noninverting amplifier is 1/B
as previously derived. Since B = 1 for a voltage-follower, the closed-loop
voltage gain of the voltage-follower is

Figure 16a.16 Op-amp voltage-follower

The most important features of the voltage-follower configuration

are its very high input impedance and its very low output
impedance. These features make it a nearly ideal buffer amplifier
for interfacing high-impedance sources and low-impedance loads.

Inverting Amplifier
An op-amp connected as an inverting amplifier with a controlled
amount of voltage gain is shown in Figure 16a.17. The input signal
is applied through a series input resistor Ri to the inverting (-) input.
Also, the output is fed back through Rf to the same input. The non-
inverting (+) input is grounded.
Figure 16a.17 Inverting amplifier

At this point, the ideal op-amp parameters mentioned earlier are useful in simplifying the analysis of this circuit.
In particular, the concept of infinite input impedance is of great value. An infinite input impedance implies zero
current at the inverting input. If there is zero current through the input impedance, then there must be no voltage
drop between the inverting and noninverting inputs. This means that the voltage at the inverting (-) input is zero
because the noninverting (+) input is grounded. This zero voltage at the inverting input terminal is referred to as
virtual ground. This condition
is illustrated in Figure
16a.18(a). Since there is no
current at the inverting input,
the current through Ri and the
current through Rf are equal
(Iin = If), as shown in Figure
16a.18(b).

Figure 16a.18
Virtual ground concept

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The voltage across Ri equals Vin because the resistor is connected to virtual ground at the inverting input of the
op-amp. Therefore,

Also, the voltage across Rf equals -Vout because of virtual ground, and therefore,

Since If = Iin,

Rearranging the terms,

Of course, Vout /Vin is the overall gain of the inverting (I) amplifier.

The equation shows that the closed-loop voltage gain of the inverting amplifier (Acl(I)) is the ratio of the feedback
resistance (Rf) to the input resistance (Ri). The closed- loop gain is independent of the op-amp’s internal open-
loop gain. Thus, the negative feed- back stabilizes the voltage gain. The negative sign indicates inversion.

EFFECTS OF NEGATIVE FEEDBACK ON OP-AMP IMPEDANCES

Impedances of the Noninverting Amplifier

Input Impedance. The input impedance of a noninverting
amplifier can be developed with the aid of Figure 16a.19. For this
analysis, assume a small differential voltage, Vd, exists between
the two inputs, as indicated. This means that you cannot assume
the op-amp’s input impedance to be infinite or the input current to
be zero.

Express the input voltage as

Vin =Vd +Vf
Substituting BVout for the feedback voltage, Vf, yields Figure 16a.19
Vin = Vd + BVout
Remember, B is the attenuation of the negative feedback circuit and is equal to Ri/(Ri + Rf).
Since Vout = AolVd (Aol is the open-loop gain of the op-amp),
Vin = Vd + AolBVd = (1 + AolB)Vd
Now substituting Iin Zin for Vd,
Vin = (1 + AolB)IinZin
where Zin is the open-loop input impedance of the op-amp (without feedback connections).
Vin / Iin = (1 + AolB)Zin
Vin/Iin is the overall input impedance of a closed-loop noninverting amplifier configuration.

Zin(NI) = (1 + AolB)Zin

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This equation shows that the input impedance of the noninverting amplifier configuration with negative feedback
is much greater than the internal input impedance of the op-amp itself (without feedback).
Output Impedance. An expression for output
impedance of a noninverting amplifier can be
developed with the aid of Figure 16a.20.

By applying Kirchhoff’s voltage law to the output

circuit,
Vout = Aol Vd – Zout Iout
The differential input voltage is Vd = Vin - Vf;
therefore, by assuming that AolVd >> ZoutIout, you
can express the output voltage as
Vout = Aol (Vin - Vf)
Substituting BVout for Vf,
Vout = Aol (Vin – B Vout)
Expanding and factoring yields Figure 16a.20
Vout = Aol Vin – Aol BVout
Aol Vin = Vout + Aol BVout = (1 + Aol B)Vout
Since the output impedance of the noninverting amplifier configuration is Zout(NI) = Vout/Iout, you can
substitute Iout Zout(NI) for Vout; therefore,
Aol Vin = (1 + Aol B) Iout Zout(NI)
Dividing both sides of the previous expression by Iout,
Aol Vin / Iout = (1 + Aol B) Zout(NI)
The term on the left is the internal output impedance of the op-amp (Zout) because, without feedback,
Aol Vin = Vout.
Therefore,
Zout = (1 + AolB)Zout(NI)
Thus,

This equation shows that the output impedance of the noninverting amplifier configuration with negative feedback
is much less than the internal output impedance, Zout, of the op-amp itself (without feedback) because Zout is
divided by the factor 1 + AolB.

Voltage-Follower Impedances. Since a voltage-follower is a special case of the noninverting amplifier

configuration, the same impedance formulas are used but with B = 1.

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As you can see, the voltage-follower input impedance is greater for a given Aol and Zin than for the noninverting
amplifier configuration with the voltage-divider feedback circuit. Also, its output impedance is much smaller.
Impedances of the Inverting Amplifier
The input and output impedances of an inverting op-amp configuration are developed with the aid of Figure
16a.21. Both the input signal and the negative feedback are applied, through resistors, to the inverting (-) terminal
as shown.

Input Impedance The input impedance for an inverting

amplifier is
Zin(I) = Ri

This is because the inverting input of the op-amp is at virtual

ground (0 V), and the input source simply sees Ri to ground.

Output Impedance As with a noninverting amplifier, the

output impedance of an inverting amplifier is decreased by
the negative feedback. In fact, the expression is the same as
for the noninverting case.

Figure 16a.21

The output impedance of both the noninverting and the inverting amplifier configurations is very low; in fact, it is
almost zero in practical cases. Because of this near zero output impedance, any load impedance within limits
can be connected to the op-amp output and not change the output voltage. The limits for the load impedance
are determined by the maximum peak-to-peak swing of the output (VO(p-p)) and the current limit of the op-amp.

BIAS CURRENT AND OFFSET VOLTAGE

Certain deviations from the ideal op-amp must be recognized because of their effects on its operation.
Transistors within the op-amp must be biased so that they have the correct values of base and collector currents
and collector-to-emitter voltages. The ideal op-amp has no input current at its terminals; but in fact, the practical
op-amp has small input bias currents typically in the nA range. Also, small internal imbalances in the transistors
effectively produce a small offset voltage between the inputs.

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Figure 16a.22 Effects of bias currents

Effect of Input Bias Current. Figure 16a.22(a) is an inverting amplifier with zero input voltage. Ideally, the
current through Ri is zero because the input voltage is zero and the voltage at the inverting (-) terminal is zero.
The small input bias current, I1, is through Rf from the output terminal. I1 creates a voltage drop across Rf, as
indicated. The positive side of Rf is the output terminal, and therefore, the output error voltage is I 1Rf when it
should be zero.

Figure 16a.22(b) is a voltage-follower with zero input voltage and a source resistance, Rs. In this case, an input
bias current, I1, produces a drop across Rs and creates an output voltage error as shown. The voltage at the
inverting input terminal decreases to -I1Rs because the negative feedback tends to maintain a differential voltage
of zero, as indicated. Since the inverting terminal is connected directly
to the output terminal, the output error voltage is -I1Rs.

Figure 16a.23 is a noninverting amplifier with zero input voltage.

Ideally, the voltage at the inverting terminal is also zero, as indicated.
The input bias current, I1, produces a voltage drop across Rf and thus
creates an output error voltage of I1Rf, just as with the inverting
amplifier.

Figure 16a.23 Input bias current creates output

error voltage in a noninverting amplifier.

Bias Current Compensation

Voltage-Follower. The output error voltage due to bias
currents in a voltage-follower can be sufficiently reduced
by adding a resistor, Rf, equal to the source resistance,
Rs, in the feedback path, as shown in Figure 16a.24. The
voltage drop created by I1 across the added resistor
subtracts from the -I2Rs output error voltage.

Figure 16a.24
Bias current compensation in a voltage-follower.

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If I1 = I2, then the output voltage is zero. Usually I1 does not quite equal I2; but even in this case, the output
error voltage is reduced as follows because IOS is less than I2.
VOUT(error) = |I1 - I2|Rs = IOSRs
where IOS is the input offset current.

Noninverting and Inverting Amplifiers To compensate for the effect of bias current in the noninverting
amplifier, a resistor Rc is added, as shown in Figure 16a.25(a). The compensating resistor value equals the
parallel combination of Ri and Rf . The input current creates a voltage drop across Rc that offsets the voltage
across the combination of Ri and Rf, thus sufficiently reducing the output error voltage. The inverting amplifier is
similarly compensated, as shown in Figure 16a.25(b).

Figure 16a.25 Bias current compensation in the noninverting and inverting amplifier configurations.

Effect of Input Offset Voltage

The output voltage of an op-amp should be zero when the differential
input is zero. However, there is always a small output error voltage
present whose value typically ranges from microvolts to millivolts.
This is due to unavoidable imbalances within the internal op- amp
transistors aside from the bias currents previously discussed. In a
negative feedback configuration, the input offset voltage VIO can be
visualized as an equivalent small dc volt- age source, as illustrated in
Figure 16a.26 for a voltage-follower. Generally, the output error
voltage due to the input offset voltage is
VOUT(error) = AclVIO

For the case of the voltage-follower, Acl = 1, so

VOUT(error) = VIO Figure 16a.26 Input offset voltage equivalent.

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Input Offset Voltage Compensation

Most integrated circuit op-amps provide a means of compensating for offset voltage. This is usually done by
connecting an external potentiometer to designated pins on the IC package, as illustrated in Figure 16a.27(a)
and (b) for a 741 op-amp. The two terminals are labelled offset null. With no input, the potentiometer is simply
adjusted until the output voltage reads 0, as shown in Figure 16a.27(c).

Figure 16a.27
Input offset voltage compensation
for a 741 op-amp.

OPEN-LOOP FREQUENCY AND PHASE RESPONSES

In this section, the open-loop frequency response and the open-loop phase response of an op-amp are covered.
Open-loop responses relate to an op-amp with no external feedback. The frequency response indicates how the
voltage gain changes with frequency, and the phase response indicates how the phase shift between the input
and output signal changes with frequency. The open-loop gain, like the beta of a transistor, varies greatly from
one device to the next of the same type and cannot be depended upon to have a constant value.

Review of Op-Amp Voltage Gains. Figure 16a.28 illustrates the open-loop and closed-loop amplifier
configurations. As shown in part (a), the open-loop voltage gain, Aol, of an op-amp is the internal voltage gain of
the device and represents the ratio of output voltage to input voltage. Notice that there are no external
components, so the open-loop voltage gain is set entirely by the internal design. In the closed-loop op-amp
configuration shown in part (b), the closed-loop voltage gain, Acl, is the voltage gain of an op-amp with external
feedback. The closed-loop voltage gain is determined by the external component values for an inverting amplifier
configuration and is always less than the open-loop gain. The closed-loop voltage gain can be precisely con-
trolled by external component values.

Figure 16a.28 Open-loop and closed-loop op-amp configurations

Bandwidth Limitations. In the previous discussions, all of the voltage gain expressions were based on the
midrange gain and were considered independent of the frequency. The midrange open-loop gain of an op-amp
extends from zero frequency (dc) up to a critical frequency at which the gain is 3 dB less than the midrange
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value. Op-amps are dc amplifiers (no capacitive coupling between stages), and therefore, there is no lower
critical frequency. This means that the midrange gain extends down to zero frequency (dc), and dc voltages are
amplified the same as midrange signal frequencies.

An open-loop response curve (Bode plot) for a certain op-amp is shown. Most op-amp datasheets show this type
of curve or specify the midrange open-loop gain. Notice that the curve rolls off (decreases) at - 20 dB per decade
( - 6 dB per octave). The midrange gain is 200,000, which is 106 dB, and the critical (cutoff) frequency is ap-
proximately 10 Hz.
3 dB Open-Loop Bandwidth Recall from Chapter 10 that the bandwidth of an ac am- plifier is the frequency
range between the points where the gain is 3 dB less than the midrange gain. In general, the bandwidth equals
the upper critical frequency ( fcu) minus the lower critical frequency ( fcl).
BW = fcu – fcl
Since fcl for an op-amp is zero, the bandwidth is simply equal to the upper critical frequency.
BW = fc = fcu

Figure 16a.28 Ideal plot of open-loop

voltage gain versus frequency for a typical
op-amp. The frequency scale is logarithmic.

Unity-Gain Bandwidth. Notice in Figure

16a.28 that the gain steadily decreases to a
point where it is equal to unity (1 or 0 dB).
The value of the frequency at which this unity
gain occurs is the unity-gain frequency
designated fT. fT is also called the unity-gain
bandwidth.

Gain-Versus-Frequency Analysis

The RC lag (low-pass) circuits within an op-amp are responsible for the
roll-off in gain as the frequency increases. From basic ac circuit theory,
the attenuation of an RC lag circuit, such as in Figure 16a.29, is
expressed as
Figure 16a.29
RC lag circuit.

Dividing both the numerator and denominator to the right of the equals
sign by XC,

The critical frequency of an RC circuit is

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Dividing both sides by f gives

Since XC = 1 / (2pfC), the previous expression can be written as

Substituting this result in the previous equation for Vout/Vin produces the following expression for the attenuation
of an RC lag circuit in terms of frequency:

If an op-amp is represented by a voltage gain element with

a gain of Aol(mid ) plus a single RC lag circuit, as shown
in Figure 16a.30, it is known as a compensated op-amp.
The total open-loop gain of the op-amp is the product of
the midrange open-loop gain, Aol(mid ), and the
attenuation of the RC circuit.

Figure 16a.30 Op-amp represented by a gain

element and an internal RC circuit.

As you can see from the equation, the open-loop gain equals the midrange gain
when the signal frequency f is much less than the critical frequency fc and drops
off as the frequency increases. Since fc is part of the open-loop response of an op-
amp, we will refer to it as fc(ol).

Example. Determine Aol for the following values of f. Assume

fc(ol) = 100 Hz and Aol(mid ) = 100,000.

(a) f = 0 Hz (b) f = 10 Hz (c) f = 100 Hz (d) f = 1000 Hz

This example demonstrates how the open-loop gain decreases

as the frequency increases above fc(ol).

Phase Shift
An RC circuit causes a propagation delay from input to output,
thus creating a phase shift between the input signal and the output signal. An RC lag circuit such as found in
an op-amp stage causes the output signal voltage to lag the input, as shown in Figure 16a.31. From basic ac
circuit theory, the phase shift, , is

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Since R / XC = f / fc,

The negative sign indicates that the output lags the input. This equation shows that the phase shift increases
with frequency and approaches -90° as f becomes much greater than fc.

Figure 16a.31 Output voltage

lags input voltage

Overall Frequency Response

Previously, an op-amp was defined to have a constant roll-off of - 20 dB/decade above its critical frequency. For
most op-amps this is the case; for some, however, the situation is more complex. The more complex IC
operational amplifier may consist of two or more cascaded amplifier stages. The gain of each stage is frequency
dependent and rolls off at - 20 dB/decade above its critical frequency. Therefore, the total response of an op-
amp is a composite of the individual responses of the internal stages. As an example, a three-stage op-amp is
represented in Figure 16a.32(a), and the frequency response of each stage is shown in Figure 16a.32(b). As
you know, dB gains are added so that the total op-amp frequency response is as shown in Figure 16a.32(c).
Since the roll-off rates are additive, the total roll-off rate increases by - 20 dB/decade ( - 6 dB/decade) as each
critical frequency is reached.

Figure 16a.32 Op-amp open-loop frequency response.

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Overall Phase Response

In a multistage amplifier, each stage contributes to the total phase lag. As you have seen, each RC lag circuit
can produce up to a -90° phase shift. Since each stage in an op-amp includes an RC lag circuit, a three-stage
op-amp, for example, can have a maximum phase lag of -270°. Also, the phase lag of each stage is less than -
45° when the frequency is below the critical frequency, equal to -45° at the critical frequency, and greater than -
45° when the frequency is above the critical frequency. The phase lags of the stages of an op-amp are added to
produce a total phase lag, according to the following formula for three stages:

CLOSED-LOOP FREQUENCY RESPONSE

Op-amps are normally used in a closed-loop configuration with negative feedback in order to achieve precise
control of the gain and bandwidth. Recall that midrange gain of an op-amp is reduced by negative feedback, as
indicated by the following closed-loop gain expressions for the three amplifier configurations previously covered,
where B is the feedback attenuation.

For a noninverting amplifier,

For an inverting amplifier,

For a voltage-follower,

Effect of Negative Feedback on Bandwidth.

You know how negative feedback affects the gain; now you will learn how it affects the amplifier’s bandwidth.
The closed-loop critical frequency of an op-amp is

This expression shows that the closed-loop critical frequency, fc(cl), is higher than the open- loop critical
frequency fc(ol) by the factor 1 + BAol(mid). Since fc(cl) equals the bandwidth for the closed-loop amplifier, the
closed-loop band- width (BWcl) is also increased by the same factor.

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Figure 16a.33 graphically illustrates the concept

of closed-loop response. When the open-loop
gain of an op-amp is reduced by negative
feedback, the bandwidth is increased.

The closed-loop gain is independent of the open-

loop gain up to the point of intersection of the two
gain curves. This point of intersection is the critical
frequency, fc(cl), for the closed- loop response.
Notice that the closed-loop gain has the same roll-
off rate as the open-loop gain, beyond the closed-
loop critical frequency.

Figure 16a.33 Closed-loop gain

compared to open-loop gain.

Gain-Bandwidth Product
An increase in closed-loop gain causes a decrease in the bandwidth and vice versa, such that the product of
gain and bandwidth is a constant. This is true as long as the roll-off rate is fixed, as in the case of a compensated
op-amp. If you let Acl represent the gain of any of the closed-loop configurations and fc(cl) represent the closed-
loop critical frequency (same as the bandwidth), then Acl fc(cl) = Aol fc(ol).

The gain-bandwidth product is always equal to the frequency at which the op-amp’s
open-loop gain is unity or 0 dB (unity-gain bandwidth, fT).

2) Activity 3: Skill-building Activities (Answers in Keys to Correction)

1. A certain op-amp has an open-loop differential voltage gain of 100,000 and a common-mode gain of 0.2.
Determine the CMRR and express it in decibels.

2. The output voltage of a certain op-amp appears as shown (right

figure) in response to a step input. Determine the slew rate.

3. Determine the closed-loop voltage gain of the amplifier.

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4. Find the values of the input and output impedances in the figure. Also, determine the closed-loop voltage gain.
The op-amp has the following parameters: Aol = 50,000; Zin = 4
MOhms; and Zout = 50 ohms.

5. A certain amplifier has an open-loop midrange gain of 150,000

and an open-loop 3 dB bandwidth of 200 Hz. The attenuation (B)
of the feedback loop is 0.002. What is the closed-loop bandwidth?

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is an operational
amplifier?
2. What is negative
feedback?
3. What are the benefits of
negative feedback?
4) Activity 5: Check for Understanding
This is an assessment. Solve the following problems completely. Box your final answers.

1. Given the op-amp configuration, determine the value of Rf

required to produce a closed-loop voltage gain of -100.

2. Determine the input and output impedances of the amplifier.

The op-amp datasheet gives Zin = 2 MOhms, Zout = 75 ohms,
and Aol = 200,000. Also, find the closed-loop voltage gain.

3. Calculate the phase shift for an RC lag circuit for each of the
following frequencies. Assume fc = 100 Hz.
(a) f = 1 Hz (b) f = 10 Hz (c) f = 100 Hz
(d) f = 1000 Hz (e) f = 10, 000 Hz

4. A certain op-amp has three internal amplifier stages with the

following gains and critical frequencies:
Stage 1: Av1 = 40 dB, fc1 = 2 kHz
Stage 2: Av2 = 32 dB, fc2 = 40 kHz
Stage 3: Av3 = 20 dB, fc3 = 150 kHz
Determine the open-loop midrange gain in decibels and the total phase lag when f = fc1.

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5. Determine the bandwidth of each of the amplifiers. Both op-amps have an open-loop gain of 100 dB and a
unity-gain bandwidth (fT) of 3 MHz.

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

KEY TO CORRECTIONS

Activity 3

1.

2.

3. This is a noninverting op-amp configuration.

Therefore, the closed-loop voltage gain is

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Lesson Title: Materials:

Operational Amplifiers – Part 2 Pencil, paper, and calculator

Comparators References:
Summing Amplifiers 1. Electronic Devices and Circuit
Integrators Theory, 11th Edition by R.
Differentiators Boylestad & L. Nashelsky (2013);

Lesson Objectives: 2. Electronic Devices:

Conventional Current Version, 9th
At the end of this lesson, you should be able to: Edition by Thomas Floyd (2012);
● describe and analyze the operation of several types of comparator
circuits; 3. Electronic Principles, 8th Edition
● describe and analyze the operation of several types of summing by Albert Malvino and David J.
amplifiers; Bates (2016).
● describe and analyze the operation of integrators and differentiators

Productivity Tip: Understand how your brain works and when you are most productive.

A. LESSON PREVIEW/REVIEW
1) Introduction
In the previous module, you learned about the principles, operation, and characteristics of the operational
amplifier. Op-amps are used in such a wide variety of circuits and applications that it is impossible to cover all of
them at once. Therefore, in this module, four fundamentally important circuits are covered to give you a
foundation in op-amp circuits.

2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)
1. What is a comparator?

2. What is a summing amplifier?

3. What is the difference

between an integrator and a
differentiator?

B. MAIN LESSON
1) Activity 2: Content Notes (13 mins)

COMPARATORS. Operational amplifiers are often used as comparators to compare the amplitude of one
voltage with another. In this application, the op-amp is used in the open-loop configuration, with the input
voltage on one input and a reference voltage on the other.
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A comparator is a specialized op-amp circuit that compares two input voltages and pro- duces an output that is
always at either one of two states, indicating the greater or less than relationship between the inputs.
Comparators provide very fast switching times, and many have additional capabilities (such as fast propagation
delay or internal reference voltages) to optimize the comparison function. For example, some ultra-high-speed
comparators can have propagation delays of as little as 500 ps. Because the output is always in one of two
states, comparators are often used to interface between an analog and digital circuit.

For less critical applications, an op-amp running without negative feedback (open-loop) is often used as a
comparator. Although op-amps are much slower and lack other special features, they have very high open-loop
gain, which enables them to detect very tiny differences in the inputs. In general, comparators cannot be used
as op-amps, but op-amps can be used as comparators in noncritical applications. Because an op-amp without
negative feedback is essentially a comparator, we will look at the comparison function using a typical op-amp.

Zero-Level Detection. One application of an op-amp used as a comparator is to determine when an input
voltage exceeds a certain level. Figure 16b.1(a) shows a zero-level detector. Notice that the inverting (-) input is
grounded to produce a zero level and that the input signal voltage is applied to the noninverting (+) input.
Because of the high open-loop voltage gain, a very small difference voltage between the two inputs drives the
amplifier into saturation, causing the output voltage to go to its limit. For example, consider an op-amp having
Aol = 100,000. A voltage difference of only 0.25 mV between the inputs could produce an output voltage of (0.25
mV)(100,000) = 25 V if the op-amp were capable. However, since most op-amps have maximum output voltage
limitations near the value of their dc supply volt- ages, the device would be driven into saturation.

Figure 16b.1 The op-amp as a zero-level detector.

Figure 16b.1(b) shows the result of a sinusoidal input voltage applied to the noninverting (+) input of the zero-
level detector. When the sine wave is positive, the output is at its maximum positive level. When the sine wave
crosses 0, the amplifier is driven to its opposite state and the output goes to its maximum negative level, as
shown. As you can see, the zero- level detector can be used as a squaring circuit to produce a square wave
from a sine wave.

Nonzero-Level Detection. The zero-level detector in Figure 12.1 can be modified to detect positive and negative
volt- ages by connecting a fixed reference voltage source to the inverting (-) input, as shown in Figure 16b.2(a).
A more practical arrangement is shown in Figure 12.2(b) using a voltage divider to set the reference voltage,
VREF, as follows:

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where +V is the positive op-amp dc supply voltage. The circuit in Figure 16b.2(c) uses a Zener diode to set the
reference voltage (VREF = VZ). As long as Vin is less than VREF, the output remains at the maximum negative level.
When the input voltage exceeds the reference voltage, the output goes to its maximum positive voltage, as
shown in Figure 16b.2(d) with a sinusoidal input voltage.

Figure 16b.2 Nonzero-level detectors.

Effects of Input Noise on Comparator Operation. In many practical

situations, noise (unwanted voltage fluctuations) appears on the input
line. This noise voltage becomes superimposed on the input voltage,
as shown in Figure 16b.3 for the case of a sine wave, and can cause a
comparator to erratically switch output states.

Figure 16b.3 Sine wave with superimposed noise.

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In order to understand the potential effects of noise

voltage, consider a low-frequency sinusoidal
voltage applied to the noninverting (+) input of an
op-amp comparator used as a zero-level detector,
as shown in Figure 16b.4(a).

Part (b) of the figure shows the input sine wave plus
noise and the resulting output. When the sine wave
approaches 0, the fluctuations due to noise may
cause the total input to vary above and below 0
several times, thus producing an erratic output
voltage.

Figure 16b.4 (right) Effects of noise on

comparator circuit.

Reducing the Effects of Noise with Hysteresis.

An erratic output voltage caused by noise on the input occurs because the op-amp comparator switches from its
negative output state to its positive output state at the same input voltage level that causes it to switch in the
opposite direction, from positive to negative. This unstable condition occurs when the input voltage hovers
around the reference voltage, and any small noise fluctuations cause the comparator to switch first one way and
then the other.

In order to make the comparator less sensitive to noise, a technique incorporating positive feedback, called
hysteresis, can be used. Basically, hysteresis means that there is a higher reference level when the input voltage
goes from a lower to higher value than when it goes from a higher to a lower value. A good example of hysteresis
is a common household thermostat that turns the furnace on at one temperature and off at another.

The two reference levels are referred to as the upper trigger point (UTP) and
the lower trigger point (LTP). This two-level hysteresis is established with a
positive feedback arrangement, as shown in Figure 12.5. Notice that the
noninverting (+) input is connected to a resistive voltage divider such that a
portion of the output voltage is fed back to the input. The input signal is applied
to the inverting (-) input in this case.

Figure 16b.5 (right) Comparator with positive feedback for hysteresis.

The basic operation of the comparator with hysteresis is illustrated in Figure

16b.6. Assume that the output voltage is at its positive maximum, +Vout(max).
The voltage fed back to the noninverting input is VUTP and is expressed as

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Figure 16b.6 Operation of a comparator with hysteresis.

When Vin exceeds VUTP, the output voltage drops to its negative maximum, -Vout(max), as shown in part (a). Now
the voltage fed back to the noninverting input is VLTP and is expressed as

The input voltage must now fall below VLTP, as shown in part (b), before the device will switch from the maximum
negative voltage back to the maximum positive voltage. This means that a small amount of noise voltage has no
effect on the output, as illustrated by Figure 16b.6(c).

A comparator with built-in hysteresis is sometimes known as a Schmitt trigger. The amount of hysteresis is
defined by the difference of the two trigger levels.

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Output Bounding. In some applications, it is necessary to limit the

output voltage levels of a comparator to a value less than that provided
by the saturated op-amp. A single Zener diode can be used, as shown in
Figure 16b.7, to limit the output voltage to the Zener voltage in one
direction and to the forward diode voltage drop in the other. This process
of limiting the output range is called bounding.

Figure 16b.7 (right) Operation Comparator with output bounding.

The operation is as follows. Since the anode of the Zener

is connected to the inverting (-) input, it is at virtual
ground (approximately 0 V). Therefore, when the output
voltage reaches a positive value equal to the Zener
voltage, it limits at that value, as illustrated in Figure
12.8(a). When the output switches negative, the Zener
acts as a regular diode and be- comes forward-biased at
0.7 V, limiting the negative output voltage to this value,
as shown in part (b). Turning the Zener around limits the
output voltage in the opposite direction.

Figure 16b.8 (left) Operation of

a bounded comparator.

Two Zener diodes arranged as in Figure 16b.9 limit the output voltage to the Zener voltage plus the forward
voltage drop (0.7 V) of the forward-biased Zener, both positively and negatively, as shown.

Figure 16b.9 Double-bounded comparator.

SUMMING AMPLIFIERS
The summing amplifier is an application of the inverting op-amp configuration. The averaging amplifier and the
scaling amplifier are variations of the basic summing amplifier.

Summing Amplifier with Unity Gain. A summing amplifier has two or more inputs, and its output voltage is
proportional to the negative of the algebraic sum of its input voltages. A two-input summing amplifier is shown in
Figure 16b.10, but any number of inputs can be used.

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Figure 16b.10 Two-input inverting summing amplifier.

The operation of the circuit and derivation of the output expression are as follows. Two voltages, VIN1 and VIN2,
are applied to the inputs and produce currents I1 and I2, as shown. Using the concepts of infinite input impedance
and virtual ground, you can determine that the inverting (-) input of the op-amp is approximately 0 V and has no
current through it. This means that both input cur- rents I1 and I2 combine at a summing point, A, and form the
total current (IT), which goes through Rf, as indicated in Figure 16b.10.

Since V = - ITR , the following steps apply:

If all three of the resistors are equal (R1 = R2 = Rf = R), then

The previous equation shows that the output voltage has the same magnitude as the sum of the two input
voltages but with a negative sign, indicating inversion.

A general expression is given below for a unity-gain summing amplifier

with n inputs, as shown in Figure 16b.11 where all resistors are equal in
value.

Figure 16b.11 (right) Summing amplifier with n inputs.

Summing Amplifier with Gain Greater Than Unity. When Rf is larger than the input resistors, the amplifier
has a gain of Rf /R, where R is the value of each equal-value input resistor. The general expression for the
output is

As you can see, the output voltage has the same magnitude as the sum of all the input voltages multiplied by a
constant determined by the ratio - (Rf /R).

Averaging Amplifier. A summing amplifier can be made to produce the mathematical average of
the input voltages. This is done by setting the ratio Rf /R equal to the reciprocal of the number of
inputs (n). You obtain the average of several numbers by first adding the numbers and then dividing
by the quantity of numbers you have.
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Scaling Adder. A different weight can be assigned to each input of a summing amplifier by simply adjusting the
values of the input resistors. As you have seen, the output voltage can be expressed as

The weight of a particular input is set by the ratio of Rf to the resistance, Rx, for that input (Rx = R1, R2, . . . Rn).
For example, if an input voltage is to have a weight of 1, then Rx = Rf. Or, if a weight of 0.5 is required, Rx = 2Rf.
The smaller the value of input resistance Rx, the greater the weight, and vice versa.

INTEGRATORS AND DIFFERENTIATORS

An op-amp integrator simulates mathematical integration, which is basically a summing process that determines
the total area under the curve of a function. An op-amp differentiator simulates mathematical differentiation,
which is a process of determining the instantaneous rate of change of a function. It is not necessary for you to
understand mathematical integration or differentiation, at this point, in
order to learn how an integrator and differentiator work. Ideal integrators
and differentiators are used to show basic principles. Practical integrators
often have an additional resistor in parallel with the feedback capacitor to
prevent saturation. Practical differentiators may include a resistor in
series with the comparator to reduce high frequency noise.

The Op-Amp Integrator

The Ideal Integrator. An ideal integrator is shown in Figure 16b.12.
Notice that the feedback element is a capacitor that forms an RC circuit
with the input resistor.
Figure 16b.12 An op-amp integrator

To understand how an integrator works, it is important to review how a capacitor charges. Recall that the charge
Q on a capacitor is proportional to the charging current (IC) and the time (t).

Also, in terms of the voltage, the charge on a capacitor is

From these two relationships, the capacitor voltage can be expressed as

This expression has the form of an equation for a straight line that begins at zero with a constant slope of I C /C.
Remember from algebra that the general formula for a straight line is y = mx + b. In this case, y = V C, m = IC/C,
x = t, and b = 0.

Recall that the capacitor voltage in a simple RC circuit is not linear but is
exponential. This is because the charging current continuously decreases
as the capacitor charges and causes the rate of change of the voltage to
continuously decrease. The key thing about using an op-amp with an RC
circuit to form an integrator is that the capacitor’s charging current is made
constant, thus producing a straight-line (linear) voltage rather than an
exponential voltage. Now let’s see why this is true.

Figure 16b.13 Current in an integrator

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In Figure 16b.13, the inverting input of the op-amp is at virtual ground (0 V), so the voltage across Ri equals Vin.
Therefore, the input current is

If Vin is a constant voltage, then Iin is also a constant because the inverting input always remains at 0 V, keeping
a constant voltage across Ri. Because of the very high input impedance of the op-amp, there is negligible current
at the inverting input. This makes all of the input current go through the capacitor, as indicated in Figure 16b.13,
so IC = Iin

The Capacitor Voltage. Since Iin is constant, so is IC.

The constant IC charges the capacitor linearly and
produces a linear voltage across C. The positive side of
the capacitor is held at 0 V by the virtual ground of the
op-amp. The voltage on the negative side of the
capacitor, which is the op-amp output voltage,
decreases linearly from zero as the capacitor charges,
as shown in Figure 16b.14. This voltage, VC, is called a
negative ramp and is the consequence of a constant
positive input.

Figure 16b.14 (above) A linear ramp voltage is produced across the capacitor by the constant charging current.

The Output Voltage. Vout is the same as the voltage on

the negative side of the capacitor. When a constant
positive input voltage in the form of a step or pulse (a
pulse has a constant amplitude when high) is applied, the
output ramp decreases negatively until the op-amp
saturates at its maximum negative level. This is indicated
in Figure 16b.15.

Figure 16b.15 (left) A constant input voltage produces a

ramp on the output of the integrator.

Rate of Change of the Output Voltage. The rate at which the capacitor charges, and
therefore the slope of the output ramp, is set by the ratio IC /C, as you have seen. Since
IC = Vin/Ri, the rate of change or slope of the integrator’s output voltage is Vout /t.
Integrators are especially useful in triangular-wave oscillators.

The Practical Integrator. The ideal integrator uses a capacitor in the feedback path, which is open to dc. This
implies that the gain at dc is the open-loop gain of the op-amp. In a practical integrator, any dc error voltage due
to offset error will cause the output to produce a ramp that moves toward either positive or negative saturation
(depending on the offset), even when no signal is present.

Practical integrators must have some means of overcoming the effects of offset and bias current. Various
solutions are available, such as chopper stabilized amplifiers; however, the simplest solution is to use a resistor

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in parallel with the capacitor in the feedback path, as shown in Figure

16b.16. The feedback resistor, Rf, should be large compared to the
input resistor Rin, in order to have a negligible effect on the output
waveform. In addition, a compensating resistor, Rc, may be added to
the noninverting input to balance the effects of bias current.

Figure 16b.16 (right)

The Op-Amp Differentiator

The Ideal Differentiator. An ideal differentiator is shown in Figure

16b.17. Notice how the placement of the capacitor and resistor differ
from the integrator. The capacitor is now the input element, and the
resistor is the feedback element. A differentiator produces an output
that is proportional to the rate of change of the input voltage.

Figure 16b.17 An op-amp differentiator

To see how the differentiator works, apply a positive-going ramp

voltage to the input as indicated in Figure 16b.18. In this case, IC = Iin
and the voltage across the capacitor is equal to Vin at all times (VC =
Vin) because of virtual ground on the inverting input.

From the basic formula, V = (IC/C)t, the capacitor

current is

Figure 116b 2.18 A differentiator with a ramp input

Since the current at the inverting input is negligible, IR

= IC. Both currents are constant because the slope of
the capacitor voltage (VC/t) is constant. The output
voltage is also constant and equal to the voltage
across Rf because one side of the feedback resistor
is always 0 V (virtual ground).

The output is negative when the input is a positive-going ramp and positive when
the input is a negative-going ramp, as illustrated in Figure 16b.19. During the
positive slope of the input, the capacitor is charging from the input source and the
constant current through the feedback resistor is in the direction shown. During the
negative slope of the input, the current is in the opposite direction because the
capacitor is discharging.
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Figure 16b.19 Output of a differentiator with a series of positive & negative ramps (triangle wave) on the input.

Notice that the term VC/t is the slope of the input. If the slope increases, Vout increases. If the slope decreases,
Vout decreases. The output voltage is proportional to the slope (rate of change) of the input. The constant of
proportionality is the time constant, RfC.

The Practical Differentiator. The ideal differentiator uses a capacitor in series with the inverting input. Because
a capacitor has very low impedance at high frequencies, the combination of Rf and C form a very high gain
amplifier at high frequencies. This means that a differentiator circuit tends to be noisy because electrical noise
mainly consists of high frequencies. The solution to this problem is simply to add a resistor, Rin, in series with
the capacitor to act as a low-pass filter and reduce the gain at high frequencies. The resistor should be small
compared to the feedback resistor in order to have a negligible effect on the desired signal. Figure 16b.20 shows
a practical differentiator. A bias compensating resistor may also be used on the noninverting input.

Figure 16b.20 The Practical Differentiator

2) Activity 3: Skill-building Activities (Answers in Keys to Correction)

Solve the following items completely.

1. The input signal in figure is applied to the

comparator. Draw the output showing its
proper relationship to the input signal. Assume
the maximum output levels of the comparator
are  14 V.

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2. Determine the upper and lower trigger points for the comparator circuit.

3. Determine the output voltage.

4. Determine the rate of change of the output

voltage in response to the input square wave, as
shown for the ideal integrator. The output voltage
is initially zero. The pulse width is 100 ms. Then
describe the output and draw the waveform.

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is a comparator?

2. What is a summing
amplifier?
3. What is the difference
between an integrator and a
differentiator?

4) Activity 5: Check for Understanding

This is an assessment. Solve the following problems completely. Box your final answers.

1. Determine the output voltage for the summing amplifier.

12

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2. Show that the amplifier produces an output whose

magnitude is the mathematical average of the input voltages.

3. Determine the weight of each input voltage for the scaling

adder find the output voltage.

4. Determine the output voltage of the ideal op-amp

differentiator for the triangular-wave input shown.

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning

You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

FAQ

1. How are comparators used in analog-to-digital (A/D) conversion?

A/D conversion is a common interfacing process often used when a linear analog system must provide
inputs to a digital system. Many methods for A/D conversion are available. However, in this discussion, only one
type is used to demonstrate the concept.
The simultaneous, or flash, method of A/D conversion uses parallel comparators to com- pare the linear
input signal with various reference voltages developed by a voltage divider. When the input voltage exceeds the
reference voltage for a given comparator, a high level is produced on that comparator’s output. The figure shows
an analog-to-digital converter (ADC) that produces three-digit binary numbers on its output, which represent the
values of the analog input voltage as it changes. This converter requires seven comparators. In general, 2 n - 1
comparators are required for conversion to an n-digit binary number. The large number of comparators
necessary for a reasonably sized binary number is one of the drawbacks of the simultaneous ADC, but IC
technology has reduced the problem somewhat by combining multiple comparators and associated circuits on a
single IC chip. For example, 6- or 8-bit flash converters are readily available. These ADCs are useful in
applications that require the fastest possible conversion times, such as video processing.
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In the figure, the reference voltage for each comparator is

set by the resistive voltage- divider circuit and VREF. The
output of each comparator is connected to an input of the
priority encoder. The priority encoder is a digital device that
produces a binary number on its output representing the
highest value input.

The encoder samples its input when a pulse occurs on the

enable line (sampling pulse), and a three-digit binary number
proportional to the value of the analog input signal appears
on the encoder’s outputs.

The sampling rate determines the accuracy with which the

sequence of binary numbers represents the changing input
signal. The more samples taken in a given unit of time, the
more accurately the analog signal is represented in digital
form.

Figure: A simplified simultaneous (flash) analog-to-digital

converter (ADC) using op-amps as comparators.

2. What is D/A conversion?

D/A conversion is an important interface process for converting digital signals to analog (linear) signals.
An example is a voice signal that is digitized for storage, processing, or transmission and must be changed back
into an approximation of the original audio signal in order to drive a speaker.
One method of D/A conversion uses a scaling adder with input resistor values that represent the binary
weights of the digital input code. Although this is not the most widely used method, it serves to illustrate how a
scaling adder can be applied. A more common method for D/A conversion is known as the R/2R ladder method.
The R/2R ladder is introduced here for comparison although it does not use a scaling adder.

The figure shows a four-digit digital-to-analog converter

(DAC) of this type (called a binary-weighted resistor DAC). The
switch symbols represent transistor switches for ap- plying each
of the four binary digits to the inputs. The inverting (-) input is at
virtual ground, and so the output voltage is proportional to the
current through the feedback resistor Rf (sum of input currents).
The lowest-value resistor R corresponds to the highest weighted
binary input (23). All of the other resistors are multiples of R and
correspond to the binary weights 22, 21, and 20.

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Lesson Title: Materials:

Integrated Circuit Pencil, paper

Basic Idea of Integrated Circuits

Types of IC’s References:
Levels of Integration 1. Electronic Devices and Circuit
Theory, 11th Edition by R.
Boylestad & L. Nashelsky (2013);
Lesson Objectives:
2. Electronic Principles, 8th Edition
At the end of this lesson, you should be able to: by Albert Malvino and David J.
● describe how integrated circuits are manufactured. Bates (2016);

Productivity Tip: Do the hardest thing first. ‘Eat the frog’ means tackling the most challenging, or least
favorite task, first thing in the day.

A. LESSON PREVIEW/REVIEW
1) Introduction

The first integrated circuit (IC) was developed by Jack Kilby while working at Texas Instruments in 1958.
The invention of the integrated circuit was a major breakthrough because the components are no longer discrete;
they are integrated. This means that they are produced and connected during the manufacturing process on a
single chip, a small piece of semiconductor material. Because the components are microscopically small, a
manufacturer can place thousands of these integrated components in the space occupied by a single discrete
transistor.
In this module, what follows is a brief description of how an IC is made. Current manufacturing processes
are much more complicated, but the simplified discussion will give you the basic idea behind the making of a
bipolar IC.

2) Activity 1: What I Know Chart, part 1 (3 mins)

What I Know Questions: What I Learned (Activity 4)

1. What is an integrated
circuit (IC)?

2. How are integrated circuits

manufactured?

3. What are the types of and

levels of integration in an IC?
1

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B. MAIN LESSON
1) Activity 2: Content Notes

BASIC IDEA
First, the manufacturer produces a p crystal several inches long (Fig. 17.1a). This is sliced into many thin
wafers, as in Fig. 17.1b. One side of the wafer is lapped and polished to get rid of surface imperfections. This
wafer is called the p substrate. It will be used as a chassis for the integrated components. Next, the wafers are
put into a furnace. A gas mixture of silicon atoms and pentavalent atoms passes over the wafers. This forms a
thin layer of n-type semiconductor on the heated surface of the substrate (see Fig. 17.1c). We call this thin layer
an epitaxial layer. As shown in Fig. 17.1c, the epitaxial layer is about 0.1 to 1 mil thick.

Figure 17.1 (a) P crystal; (b) wafer; (c) epitaxial layer; (d ) insulating layer.

To prevent contamination of the epitaxial layer, pure oxygen is blown over the
surface. The oxygen atoms combine with the silicon atoms to form a layer of
silicon dioxide (SiO2) on the surface, as shown in Fig. 17.1d. This glass-like
layer of SiO2 seals off the surface and prevents further chemical reactions.
Sealing off the surface like this is known as passivation.

The wafer is then cut into the rectangular areas shown in Fig. 17.2. Each of
these areas will be a separate chip after the wafer is cut. But before the wafer
is cut, the manufacturer produces hundreds of circuits on the wafer, one on
each chip area of Fig. 17.2. This simultaneous mass production is the reason
for the low cost of IC’s.
Figure 17.2
Cutting wafer into chips

Here is how an integrated transistor is formed: Part of the SiO 2 is etched off, exposing the epitaxial layer (see
Fig. 17.3a). The wafer is then put into a furnace, and trivalent atoms are diffused into the epitaxial layer. The
concentration of trivalent atoms is enough to change the exposed epitaxial layer from n material to p material.
Therefore, we get an island of n material under the SiO 2 layer (Fig. 17.3b). Oxygen is again blown over the
surface to form the complete SiO2 layer shown in Fig. 17.3c.

A hole is now etched in the center of the SiO2 layer. This exposes the n epitaxial layer (Fig. 17.3d ). The hole in
the SiO2 layer is called a window. We are now looking down at what will be the collector of the transistor.
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Figure 17.3 Steps in making a transistor.

To get the base, we pass trivalent atoms through this window; these impurities diffuse into the epitaxial layer
and form an island of p-type material (Fig. 17.3e). Then, the SiO2 layer is re-formed by passing oxygen over
the wafer (Fig. 17.3f ). To form the emitter, we etch a window in the SiO 2 layer and expose the p island (Fig.
17.3g). By diffusing pentavalent atoms into the p island, we can form the small n island shown in Fig. 17.3h.

We then passivate the structure by blowing oxygen over the wafer (Fig. 17.3i). By etching windows in the SiO 2
layer, we can deposit metal to make electrical contact with the emitter, base, and collector. This gives us the
integrated transistor of Fig. 17.4a.

Figure 17.4 Integrated components: (a) Transistor; (b) diode; (c) resistor.
3

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To get a diode, we follow the same steps up to the point at which the p island has been formed and sealed off
(Fig. 17.3f ). Then, we etch windows to expose the p and n islands. By depositing metal through these windows,
we make electrical contact with the cathode and anode of the integrated diode (Fig. 17.4b). By etching two
windows above the p island of Fig. 17.3f, we can make metallic contact with this p island; this gives us an
integrated resistor (Fig. 17.4c).

Figure 17.5 Simple IC.

Transistors, diodes, and resistors are easy to fabricate on a chip. For this reason, almost all IC’s use these
components. It is not practical to integrate inductors and large capacitors on the surface of a chip.

A Simple Example. To give you an idea of how a circuit is produced, look at the simple three-component circuit
of Fig. 17.5a. To fabricate this circuit, we would simultaneously produce hundreds of circuits like this on a wafer.
Each chip area would resemble Fig. 17.5b. The diode and resistor would be formed at the point mentioned
earlier. At a later step, the emitter of the transistor would be formed. Then we would etch windows and deposit
metal to connect the diode, transistor, and resistor, as shown in Fig. 17.5b.

Regardless of how complicated a circuit may be, producing it is mainly a process of etching windows, forming p
and n islands, and connecting the integrated components. The p substrate isolates the integrated components
from each other. In Fig. 17.5b, there are depletion layers between the p substrate and the three n islands that
touch it. Because the depletion layers have essentially no current carriers, the integrated components are
insulated from one another. This kind of insulation is known as depletion-layer isolation.

TYPES OF IC’S
The integrated circuits we have described are called monolithic IC’s. The word monolithic is from the Greek and
means “one stone.” The word is appropriate because the components are part of one chip. Monolithic IC’s are
the most common type of IC. Since their invention, manufacturers have been producing monolithic IC’s to carry
out all kinds of functions.

Commercially available types can be used as amplifiers, voltage regulators, crowbars, AM receivers, television
4

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circuits, and computer circuits. But the monolithic IC has power limitations. Since most monolithic IC’s are about
the size of a discrete small-signal transistor, they are used in low-power applications.

When higher power is needed, thin-film and thick-film IC’s may be used. These devices are larger than monolithic
IC’s but smaller than discrete circuits. With a thin- or thick-film IC, the passive components like resistors and
capacitors are integrated, but the transistors and diodes are connected as discrete components to form a
complete circuit. Therefore, commercially available thin- and thick-film circuits are combinations of integrated
and discrete components.

Another IC used in high-power applications is the hybrid IC. Hybrid ICs combine two or more monolithic IC’s in
one package, or they combine monolithic ICs with thin- or thick-film circuits. Hybrid IC’s are widely used for high-
power audio-amplifier applications from 5 to more than 50 W.

LEVELS OF INTEGRATION
Figure 17.5b is an example of small-scale integration (SSI); only a few components have been integrated to form
a complete circuit. SSI refers to IC’s with fewer than 12 integrated components. Most SSI chips use integrated
resistors, diodes, and bipolar transistors.

Medium-scale integration (MSI) refers to IC’s that have from 12 to 100 integrated components per chip. Either
bipolar transistors or MOS transistors (enhancement-mode MOSFETS) can be used as the integrated transistors
of an IC. Again, most MSI chips use bipolar components.

Large-scale integration (LSI) refers to IC’s with more than a hundred components. Since it takes fewer steps to
make an integrated MOS transistor, a manufacturer can produce more components on a chip than is possible
with bipolar transistors.

Very large-scale integration (VLSI) refers to placing thousands (or hundreds of thousands) of components on a
single chip. Nearly all modern chips employ VLSI.

Finally, there is ultra large-scale integration (ULSI), which refers to placing more than 1 million components on
a single chip. Various versions of microprocessors have been developed containing over 1 billion internal
components. The exponential growth, often referred to as Moore’s law, is being challenged. However, new
technologies, such as nanotechnology, and refined manufacturing processes should allow the continued growth
to occur.

2) Activity 3: Skill-building Activities (Answers in Keys to Correction)

Supply the best term(s).

1. This means that components are produced and connected during the manufacturing process on a single
chip, a small piece of semiconductor material.
2. In the wafer, the will be used as a chassis for the integrated components.
3. When wafers are put into a furnace, a gas mixture of silicon atoms and pentavalent atoms passes over. This
forms a thin layer, called , of n-type semiconductor on the heated surface of the substrate.
4. The glass-like layer of SiO2 seals off the surface of a wafer and prevents further chemical reactions. Sealing
off the surface like this is known as .
5-7. Give three components that are easy to fabricate on a chip.
5

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8. This term describes that components are part of one chip.

9. When higher power is needed, these IC’s may be used.
10. It refers to placing more than 1 million components on a single chip.

3) Activity 4: What I Know Chart, part 2

What I Know Questions: What I Learned (Activity 4)

1. What is an integrated circuit
(IC)?

2. How are integrated circuits

manufactured?

3. What are the types of an IC?

4) Activity 5: Check for Understanding

Job-interview questions. Briefly answer the following questions.

1. Cite the important steps in the production of integrated circuits.

2. Why is Moore’s Law being challenged?
3. Discuss the levels of integration for integrated circuits.

C. LESSON WRAP-UP
1) Activity 6: Thinking about Learning
You are done with the session! Let’s track your progress.
Period 1 Period 2 Period 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Were you able to meet all the learning targets?

Which strategy worked for you, easily? With difficulty?

KEY TO CORRECTIONS
Activity 3

1. integrated
2. p substrate
3. epitaxial layer
4. passivation
5-7. (in any order) transistors, diodes, and resistors
8. monolithic
9. thin-film and thick-film
10. ultra large-scale integration (ULSI)

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