Jan M.

Rabaey
Anantha Chandrakasan
Borivoje Nikolic

Introduction
July 30, 2002

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 Why is designing
digital ICs different
today than it was
before?
Will it change in
future?

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 Primo esempio di
sistema computazionale
meccanico

The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470

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 !"#

L=24m
H=2.6m

18000
Valvole

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 $

First transistor
Bell Labs, 1948

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 Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966

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 !%%!&

1971
1000 transistors
1 MHz operation

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 '#

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 & ( )*
“La densità di componenti è raddoppiata
ogni anno. Sicuramente, a breve termine
ci si può attendere che questo ritmo
continui, o addirittura acceleri. Nel lungo
periodo, la velocità è meno prevedibile,
sebbene non vi sia alcuna ragione per
credere che questo ritmo non debba
rimanere circa costante per almeno dieci
anni. Ciò significa che nel 1975, il numero
di componenti per circuito integrato sarà
65.000”
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 & ( )*
In 1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months

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EE141
&
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1959
1960
( )*

1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
 +,

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 1 Billion
K
Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected

EE141 Courtesy, Intel

 & ( * &
1000

100 2X growth in 1.96 years!

Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
Transistors
Transistors
0.01 on
on Lead
Lead Microprocessors
Microprocessors double
double every
every 22 years
years
8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

EE141 Courtesy, Intel

 -. / *
100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year

Die
Die size
size grows
grows by
by 14%
14% to
to satisfy
satisfy Moore’s
Moore’s Law
Law

EE141 Courtesy, Intel

 0 ,
10000
Doubles every
1000 2 years
Frequency (Mhz)

100 P6
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead
Lead Microprocessors
Microprocessors frequency
frequency doubles
doubles every
every 22 years
years

EE141 Courtesy, Intel

 *
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead
Lead Microprocessors
Microprocessors power
power continues
continues to
to increase
increase

EE141 Courtesy, Intel

 * * 1 2 1
100000
18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power
Power delivery
delivery and
and dissipation
dissipation will
will be
be prohibitive
prohibitive

EE141 Courtesy, Intel

 * ,
10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
8080 286 486
1
1970 1980 1990 2000 2010
Year

Power
Power density
density too
too high
high to
to keep
keep junctions
junctions at
at low
low temp
temp

EE141 Courtesy, Intel

 3 ,&
Cell
Phone

Small Power
Signal RF RF

Digital Cellular Market

(Phones Shipped) Power
Management

1996 1997 1998 1999 2000

Analog
Units 48M 86M 162M 260M 435M Baseband

Digital Baseband
(DSP + MCU)

(data from Texas Instruments)

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 1 )
SYSTEM

MODULE

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

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 &

How to evaluate performance of a

digital circuit (gate, block, …)?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function

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 NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area

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 $

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 Single die

Wafer

! "# $

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 cost:
¢-per-
per-transistor
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

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 4
No. of good chips per wafer
Y= ×100%
Total number of chips per wafer
Wafer cost
Die cost =
Dies per wafer × Die yield
π × (wafer diameter/2)2 π × wafer diameter
Dies per wafer = −
die area 2 × die area

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 −α
defects per unit area × die area
die yield = 1 +
α
α % & '(

die cost = f (die area)4

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- + !#
Chip Metal Line Wafer Def./ Area Dies/ Yield Die
layers width cost cm2 mm2 wafer cost
386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 4 0.80 $1700 1.3 121 115 28% $53

601
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

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 $ 1 ,5

v(t) V DD
i(t)

Inductive coupling Capacitive coupling Power and ground

noise

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'
V(y)

VOH = f(VOL)
V f
OH
V(y)=V(x)
VOL = f(VOH)
VM = f(VM)

VM Switching Threshold

V OL

V OL V V(x)
OH

Nominal Voltage Levels

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 & 1 *

V
V
out
“ 1” OH
V Slope = -1
V OH
IH

Undefined
Region

V
IL
Slope = -1

V
“ 0” V OL
OL
V V V
IL IH in

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 &

"1"
V
OH
NM H Noise margin high
V
IH
Undefined
Region
NM L V
V
OL
IL Noise margin low

"0"

Gate Output Gate Input

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 $ , Vin1 Vout1

Vin2 Vout2
out out
Vout1 v 3 v3
Vin2 f (v) fin v(v)

v1 v1

v3
fin v(v) f (v)

v2 v0 in v0 v2 in
Vin1
Regenerative Vout2
Non-Regenerative

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 $ ,

v0 v1 v2 v3 v4 v5 v6

A chain of inverters

v0
V (Volt)

1 v1
v2

21
Simulated response 0 2 4 6 8 10
t (nsec)

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 . 6
Variazioni sui livelli di tensione in ingresso non
devono influenzare i livelli di tensione in
uscita

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Aumentare il fan-out comporta una
La complessità (# transistori) è
variazione del valore logico di tensione
proporzionale al fan-in
e deteriora il comportamento dinamico
della porta

Fan-in M

Fan-out N
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 /
V out

Ri = ∞
Ro = 0
Fanout = ∞
g=∞
NMH = NML = VDD/2

V in

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 3
5.0

4.0 NM L

3.0
( V)

o u t

2.0
VM
V

NM H
1.0

0.0 1.0 2.0 3.0 4.0 5.0

V in (V)

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 .
#operazioni/sec (Architettura)
Frequenza di clock (Circuito)
Tempi di propagazione (Porta)

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 , tp = (tpLH + tpHL)/2
V in

50%

tpHL tpLH
V out
90%

50%

10% t
tf tr

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 $ 3

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2 × tp × N

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 3 $ * 7

R
vout

vin C

tp = ln (2) τ = 0.69 RC
tr = ln (9) t = 2.2 RC
) '* '% ' ( + ,' '
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 *
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)

Peak power:
Ppeak = Vsupplyipeak

Average power:
1 t +T Vsupply t +T
Pave = p (t )dt = isupply (t )dt
T t T t

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 , , ,
- ' ./' (- ! #-/-$0
10 1 ' ( ' ' 0 ×

1 ' (./' (- ! #1/-$0

2! ( ' + '0 ×

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 3 $ * 7
R
vout

vin CL

T T Vdd
E0 = P ( t ) dt = V dd i sup ply( t ) dt = Vdd CL dV out = C L • V dd 2
→1
0 0 0

T T Vdd
1 2
E ca p = P cap ( t ) dt = V out i ca p( t ) dt = C L Vout dVout = --- C • V dd
2 L
0 0 0

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 - ,
Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
Some interesting challenges ahead
Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
Understanding the design metrics that govern
digital design is crucial
Cost, reliability, speed, power and energy
dissipation

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