19ECE349-RISC Processor

Design using HDL

 Learning and Course Objectives
• Learning Objectives:

• LO1: To understand principles of processor architectures

• LO2: To familiarize with RISC design principles
• LO3: To design a pipelined processor using Verilog HDL
• Course Outcomes:

• CO1: Able to understand the concepts of pipelined computer architecture

• CO2: Able to design circuits using Verilog and understand concept of timing analysis

• CO3: Able to understand and design a MIPS based processor

• CO4: Able to implement a pipelined architecture of MIPS

• CO5: Able to understand memory hierarchy and design of cache memories

 Syllabus
• Unit I:

• Fundamental techniques of computer design – RISC and CISC architectures - computer arithmetic, - comparison of
RISC and CISC architectures - Introduction to superscalar and super pipelined architectures - Verilog Introduction
and review of basic designs using Verilog - Static timing analysis – Introduction - setup and hold time constraints -
processor timing issues - design examples.

• Unit II:

• MIPS Processor- Introduction to MIPS features and MIPS instruction set, logical design of MIPS datapath - control
unit and instruction decode - Design of single cycle - multi-cycle and pipelined architectures of MIPS - Hazards-
data and control hazards - Verilog designs of single cycle and multi-cycle MIPS processor.

• Unit III:

• Verilog design of pipelined MIPS processor - Introduction to memory hierarchy cache memory fundamentals -
memory systems for superscalar processors.
Textbook(s) and References:
Textbook(s):

• 1.Patterson, David A., and John L. Hennessy, “Computer Organization and Design: The Hardware Software
Interface”, Morgan kaufmann, First edition 2005.
• 2. Sarah L Harris, David Money Harris “, Digital Design and Computer Architecture RISC-V Edition
• 2. Palnitkar, Samir. “Verilog HDL: a guide to digital design and synthesis”, Edition 1, Prentice Hall
Professional, 2003.
Reference(s)
• 1.Hamacher, V. Carl, et al. “Computer organization”, Fifth edition. New York et al. McGraw-Hill, 1984.

• 2.Dandamudi, Sivarama P, “Guide to RISC processors: for programmers and engineers”, First edition, Springer
Science & Business Media, 2005.
 Simple RISC Processor?
compute
jump/branch
targets

A
memory register
alu

D
file

B
+4
addr
PC control din dout
inst

M
B
memory
extend Forward
new
imm

unit
Detect
pc hazard

Instruction Instruction Execute Write-

ctrl

ctrl

ctrl
Fetch Decode Memory Back
IF/ID ID/EX EX/MEM MEM/WB
5
Fundamental Techniques of Computer Design
• Computer Architecture Basics
• Von Neumann vs. Harvard Architecture
• Microarchitecture vs. Architecture
• Performance Metrics: Throughput, Latency, CPI, MIPS, FLOPS
• Instruction Set Architecture (ISA)
• Types of Instructions: Data movement, Arithmetic, Logical, Control, etc.
• RISC vs. CISC: Characteristics and differences
• Addressing Modes
• Instruction Formats
Fundamental Techniques of Computer Design
• Pipeline Design
• Pipeline Stages: Fetch, Decode, Execute, Memory, Write-back
• Memory Hierarchy
• Cache Memory: Cache organization, mapping techniques, replacement
policies
• Main Memory: DRAM, SRAM, Virtual Memory
• Memory Access Techniques: Direct Memory Access (DMA)
 Simple RISC Processor?
compute
jump/branch
targets

A
memory register
alu

D
file

B
+4
addr
PC control din dout
inst

M
B
memory
extend Forward
new
imm

unit
Detect
pc hazard

Instruction Instruction Execute Write-

ctrl

ctrl

ctrl
Fetch Decode Memory Back
IF/ID ID/EX EX/MEM MEM/WB
8
Memory Hierarchy
Computer Architecture Basics - Von Neumann
• Single memory
• Instructions
• Data
 Computer Architecture Basics - Harvard Architecture

• Two memories
• One for Instructions
• One for Data
Computer Architecture Basics - Harvard Architecture
Computer Architecture Basics - Von Neumann
Basis for Comparison Von Neumann Architecture Harvard Architecture

Basic Data and instructions reside within a single Data and instruction are provided 2
memory unit. different memory units.

Memory system Single Dual

Required space Less Comparatively more

Set of address/ data bus One Two

Development cost Low Comparatively more

Efficiency Less More

Execution speed Slow Comparatively fast

Operation Simple Complex

Performance offered Low Comparatively high

Clock cycle Single instruction is executed in minimum two Single instruction is executed in one clock
clock cycles. cycle.
Computer Architecture:
 Computer Architecture:
• Definition: Refers to a computer system's abstract,
high-level design. It defines a computer's capabilities
and programming model but does not specify how
these are implemented.

• Key Aspects : Instruction Set Architecture (ISA): The

set of instructions that the processor can execute. This
includes instruction formats, addressing modes, and
the execution model.
• Functional Units: High-level description of the
components like ALU, FPU, registers, and their
interconnections.
• Memory Management: Virtual memory layout,
memory hierarchy.
• I/O Systems: General structure of input/output
subsystems.
 Computer Micro-Architecture
• Definition:
• Microarchitecture, also known as computer organization, refers to the structure
and design of a computer's central processing unit (CPU) or other hardware
components. It encompasses the internal organization, data paths, memory
hierarchy, and control units of a computer system.
• Refers to the detailed, lower-level design of the computer's hardware. It is the
implementation of the architecture's specifications in actual circuitry.

• Key Aspects:
• Pipeline Design: Specific stages and handling of data hazards, control hazards,
and structural hazards.
• Cache Organization: Details on cache size, levels, associativity, and replacement
policies.
• Branch Prediction: Techniques used to guess the outcome of branches and
improve pipeline efficiency.
• Execution Units: The detailed design of units like ALUs, FPUs, load/store units,
and how they execute instructions.
• Control Unit: How the processor manages and sequences operations, whether
using a hardwired approach or microprogramming.
A micro-architecture organized around a single bus processor
Microarchitecture Vs. Architecture
• In electronics, computer science and computer
engineering, microarchitecture, also called computer
organization and sometimes abbreviated as μarch or uarch, is
the way a given instruction set architecture (ISA) is
implemented in a particular processor.
• A given ISA may be implemented with different
microarchitectures; implementations may vary due to different
goals of a given design or due to shifts in technology.

• Computer architecture is the combination of microarchitecture

and instruction set architecture.
Performance Metrics
1. Throughput
• Definition: The number of tasks or transactions a system can handle in a given
amount of time.
• Example: In a processor, throughput can refer to the number of instructions executed
per second.
2. Latency
• Definition: The time taken to complete a single task or transaction from start to
finish.
• Example: In memory systems, latency is the time delay between a memory request
and the moment data is available.
3. Cycles Per Instruction (CPI)
• Definition: The average number of clock cycles each instruction takes to execute.
• Example: A processor with a CPI of 2 means that, on average, each instruction
requires 2 clock cycles to complete.
 Performance Metrics
4. Million Instructions Per Second (MIPS)
• Definition: A measure of a computer's processor speed, representing the
number of million instructions it can process per second.
• Example: A processor with a performance of 100 MIPS can execute 100
million instructions per second.
5. Floating Point Operations Per Second (FLOPS)
• Definition: A measure of a computer's performance, especially in fields of
scientific calculations that make heavy use of floating-point calculations.
• Example: A supercomputer may have a performance rating in teraFLOPS
(trillions of floating-point operations per second).
RISC Processor Features
RISC Processor Features
• RISC stands for reduced (complexity) instruction set computing

• “Reduced complexity instruction” means instructions are simple compare

to the CISC instructions.

• RISC relatively operates at higher frequency and faster than CISC

 Reduced Instruction Set Computer
RISC-V = Reduced Instruction Set Computer (RlSC)
• ≈ 200 instructions, 32 bits each, 4 formats
• all operands in registers
• almost all are 32 bits each
• ≈ 1 addressing mode: Mem[reg + imm]

x86 = Complex Instruction Set Computer (ClSC)

• > 1000 instructions, 1 to 15 bytes each
• operands in dedicated registers, general purpose
registers, memory, on stack, …
• can be 1, 2, 4, 8 bytes, signed or unsigned
• 10s of addressing modes
• e.g. Mem[segment + reg + reg*scale + offset]
23
Reduced Instruction Set Computer

RISC-V
x86

RISC-V X86
Reduced Instruction Set Computer Complex Instruction Set Computer
(RlSC) (ClSC)
• ≈ 200 instructions, • > 1000 instructions,
• 1 to 15 bytes each
• 32 bits each, 4 formats
• operands in dedicated registers,
• all operands in registers general purpose registers, memory,
• almost all are 32 bits each on stack, …
• can be 1, 2, 4, 8 bytes, signed or
unsigned
• ≈ 1 addressing mode: Mem[reg + • 10s of addressing modes
imm] • e.g. Mem[segment + reg + reg*scale +
offset]

24
Comparison of RISC and CISC (x86)
Parameter RISC CISC
Instruction Set Size ≈ 200 instructions > 1000 instructions
Instruction Length 32 bits each 1 to 15 bytes each
Instruction Formats 4 formats N/A (variable-length instructions)
Operands in dedicated registers,
Operand Location All operands in registers general purpose registers, memory,
on stack, etc.
Can be 1, 2, 4, 8 bytes, signed or
Operand Size Almost all are 32 bits each
unsigned
10s of addressing modes (e.g.,
≈ 1 addressing mode (Mem[reg +
Addressing Modes Mem[segment + reg + reg*scale +
imm])
offset])
Example Comparison of RISC and CISC instructions
Example of RISC: ADD R1, R2, R3 Example of CISC: ADD A, [M]
• Opcode Rd, Rs1, Rs2 • Opcode Rd/Rs1, [m]
• Read source 1 operand from • Read source 1 operand from
register Rs1, register Rs1,
• Read source 2 operand from • Read source 2 operand from
register Rs2, Memory location M, which has
• Perform Arithmetic operation on many sub-operations
source 1 and source 2 data • Perform Arithmetic operation on
• Write arithmetic result into register source 1 and source 2 data
Rd • Write arithmetic result into register
• No, memory read operation Rd
• only arithmetic operation • Both, memory read operation and
arithmetic operation
Example Comparison of RISC and CISC instructions
Example of RISC: ADD R1, R2, R3 Example of CISC: ADD A, [M]
• Opcode Rd, Rs1, Rs2 • Opcode Rd/Rs1, [m]
• Read source 1 operand from • Read source 1 operand from
register Rs1, register Rs1,
• Read source 2 operand from • Read source 2 operand from
register Rs2, Memory location M, which has
• Perform Arithmetic operation on many sub-operations
source 1 and source 2 data • Perform Arithmetic operation on
• Write arithmetic result into register source 1 and source 2 data
Rd • Write arithmetic result into register
• No, memory read operation Rd
• only arithmetic operation • Both, memory read operation and
arithmetic operation
Example Comparison of RISC and CISC instructions
Example of RISC: ADD R1, R2, R3 Example of SISC: ADD A, [M]
• Opcode Rd, Rs1, Rs2 • Opcode Rd/Rs1, [m]
• Read source 1 operand from • Read source 1 operand from
register Rs1, register Rs1,
• Read source 2 operand from • Read source 2 operand from
register Rs2, Memory location M, which has
• Perform Arithmetic operation on many sub-operations
source 1 and source 2 data • Perform Arithmetic operation on
• Write arithmetic result into register source 1 and source 2 data
Rd • Write arithmetic result into register
• No, memory read operation Rd
• only arithmetic operation • Both, memory read operation and
arithmetic operation
Example Comparison of RISC and CISC instructions
Example of RISC: ADD R1, R2, R3 Example of SISC: ADD A, [M]
• Opcode Rd, Rs1, Rs2 • Opcode Rd/Rs1, [m]
• Read source 1 operand from • Read source 1 operand from
register Rs1, register Rs1,
• Read source 2 operand from • Read source 2 operand from
register Rs2, Memory location M, which has
• Perform Arithmetic operation on many sub-operations
source 1 and source 2 data • Perform Arithmetic operation on
• Write arithmetic result into register source 1 and source 2 data
Rd • Write arithmetic result into register
• No, memory read operation Rd
• only arithmetic operation • Both, memory read operation and
arithmetic operation
Example Comparison of RISC and CISC instructions
Example of RISC: ADD R1, R2, R3 Example of SISC: ADD A, [M]
• Opcode Rd, Rs1, Rs2 • Opcode Rd/Rs1, [m]
• Read source 1 operand from • Read source 1 operand from
register Rs1, register Rs1,
• Read source 2 operand from • Read source 2 operand from
register Rs2, Memory location M, which has
• Perform Arithmetic operation on many sub-operations
source 1 and source 2 data • Perform Arithmetic operation on
• Write arithmetic result into register source 1 and source 2 data
Rd • Write arithmetic result into register
• No, memory read operation Rd
• only arithmetic operation • Both, memory read operation and
arithmetic operation
Example Comparison of RISC and CISC instructions
Example of RISC: ADD R1, R2, R3 Example of SISC: ADD A, [M]
• Opcode Rd, Rs1, Rs2 • Opcode Rd/Rs1, [m]
• Read source 1 operand from • Read source 1 operand from
register Rs1, register Rs1,
• Read source 2 operand from • Read source 2 operand from
register Rs2, Memory location M, which has
• Perform Arithmetic operation on many sub-operations
source 1 and source 2 data • Perform Arithmetic operation on
• Write arithmetic result into register source 1 and source 2 data
Rd • Write arithmetic result into register
• No, memory read operation Rd
• only arithmetic operation • Both, memory read operation and
arithmetic operation
RISC Processor Architecture
Single and Multi Cycle
Simple
RISC
Processor
:
 Lecture
Single and Multi-stage Processor
Date: 07-August 2024
Single-Cycle RISC-V Datapath
Big Picture: Building a Processor

memory inst
register
alu
file

+4 +4
addr
=?
PC din dout
offset control cmp
memory
new target
imm
pc extend

A single cycle processor

36
• Understanding the basics of a processor
• We now have the technology to build a CPU!

• Putting it all together:

• Arithmetic Logic Unit (ALU)
• Register File
• Memory
• SRAM: cache
• DRAM: main memory
• RISC-V Instructions & how they are executed

37 37
RISC-V Register File

memory inst
register
alu
file

+4 +4
addr
=?
PC din dout
offset control cmp
memory
new target
imm
pc extend

A single cycle processor

38
RISC-V Register File
• RISC-V register file
• 32 registers, 32-bits each DW QA
32 32
• x0 wired to zero Dual-Read-Port
Single-Write-Port
• Write port indexed via RW 32 x 32 QB 32
• on falling edge when WE=1 Register File
• Read ports indexed via RA, RB
WE RW R A RB
1 5 5 5

39
RISC-V Register File
• RISC-V register file
• 32 registers, 32-bits each 32 W x0 A 32
• x0 wired to zero x1
• Write port indexed via RW … B 32
• on falling edge when WE=1
• Read ports indexed via RA, RB x31
WE RW R A RB
• RISC-V register file 1 5 5 5
• Numbered from 0 to 31
• Can be referred by number: x0, x1, x2, … x31
• Convention, each register also has a name:
• x10 – x17  a0 – a7, x28 – x31  t3 – t6

8
RISC-V Memory

memory inst
register
alu
file

+4 +4
addr
=?
PC din dout
offset control cmp
memory
new target
imm
pc extend

A single cycle processor

41
RISC-V Memory
1 byte address
Din Dout
32
memory 32
0x000fffff
. . .
0x0000000b
32 2 0x05 0x0000000a
addr mc E 0x00000009
• 32-bit address 0x00000008
0x00000007
• 32-bit data (but byte addressed) 0x00000006
• Enable + 2 bit memory control (mc) 0x00000005
0x00000004
0x00000003
00: read word (4 byte aligned) 0x00000002
01: write byte 0x00000001
10: write halfword (2 byte aligned) 0x00000000
11: write word (4 byte aligned)
42
Putting it all together: Basic Processor

memory inst
register
alu
file

+4 +4
addr
=?
PC din dout
offset control cmp
memory
new target
imm
pc extend

A single cycle processor

43
 Takeaway
A processor executes instructions
• Processor has some internal state in storage elements
(registers)
A memory holds instructions and data
• (modified) Harvard architecture: separate insts and data
• von Neumann architecture: combined inst and data
A bus connects the two

We now have enough building blocks to build

machines that can perform non-trivial computational
tasks
44
 Takeaway

A RISC-V processor and ISA (instruction set architecture) is

an example a Reduced Instruction Set Computers (RISC)
where simplicity is key, thus enabling us to build it!!
Five-Stage RISC-V Datapath
Five Stages of RISC-V Datapath
Prog. inst
Reg. ALU
Mem Data
File
Mem
+4
5 5 5
PC
control

Fetch Decode Execute Memory WB

A single cycle processor – this diagram is not 100% spatial

47
Five Stages of RISC-V Datapath
Basic CPU execution loop
1. Instruction Fetch
2. Instruction Decode
3. Execution (ALU)
4. Memory Access
5. Register Writeback

48
Stage 1: Instruction Fetch
inst
Prog.
Reg. ALU
Mem Data
File
Mem
+4
5 5 5
PC
control

Fetch Decode Execute Memory WB

Fetch 32-bit instruction from memory

Increment PC = PC + 4 49
Stage 2: Instruction Decode
Prog. inst
Reg. ALU
Mem Data
File
Mem
+4
5 5 5
PC
control

Fetch Decode Execute Memory WB

Gather data from the instruction

Read opcode; determine instruction type, field lengths
Read in data from register file
(0, 1, or 2 reads for jump, addi, or add, respectively)
50
Stage 3: Execution (ALU)
Prog. inst
Reg. ALU
Mem Data
File
Mem
+4
5 5 5
PC
control

Fetch Decode Execute Memory WB

Useful work done here (+, -, *, /), shift, logic operation,

comparison (slt)
Load/Store? lw x2, x3, 32  Compute address
51
Stage 4: Memory Access
Prog. inst addr
Reg. ALU
Mem Data Data
File
Mem
+4
Data
5 5 5
PC R/W
control

Fetch Decode Execute Memory WB

Used by load and store instructions only

Other instructions will skip this stage
52
Stage 5: Writeback
Prog. inst
Reg. ALU
Mem Data
File
Mem
+4
5 5 5
PC
control

Fetch Decode Execute Memory WB

Write to register file

• For arithmetic ops, logic, shift, etc, load. What about stores?
Update PC
• For branches, jumps
53
Takeaway
• The datapath for a RISC-V processor has five stages:
1. Instruction Fetch
2. Instruction Decode
3. Execution (ALU)
4. Memory Access
5. Register Writeback

• This five stage datapath is used to execute all RISC-V instructions

 Next Goal
How are instructions executed?

What is the general datapath to execute an instruction?

Specific datapaths RISC-V Instructions

MOV R1, #08

Data path activity

Simple RISC Processor: MOV R1, #08
Simple RISC Processor
ADD Rd, Rs1, Rs2

Data path activity

Simple RISC Processor: ADD Rd, Rs1, Rs2
Simple RISC Processor: ADD Rd, Rs1, Rs2
Simple RISC Processor: ADD Rd, Rs1, Rs2
ADD Rd, Rs1, #08

Data path activity

Simple RISC Processor: ADD Rd, Rs1, #08
Simple RISC Processor: ADD Rd, Rs1, #08
Simple RISC Processor: ADD Rd, Rs1, #08
Instruction Set Architecture
(ISA)
Instruction Set Architecture (ISA)
Different CPU architectures specify different instructions

Two classes of ISAs

• Reduced Instruction Set Computers (RISC)
IBM Power PC, Sun Sparc, MIPS, Alpha
• Complex Instruction Set Computers (CISC)
Intel x86, PDP-11, VAX

Another ISA classification: Load/Store Architecture

• Data must be in registers to be operated on
For example: array[x] = array[y] + array[z]
1 add ? OR 2 loads, an add, and a store ?
• Keeps HW simple  many RISC ISAs are load/store
68
RISC Arithmetic Instructions
1.Addition (ADD): 5.Remainder (REM):
•add rd, rs1, rs2 (rd = rs1 + rs2) •rem rd, rs1, rs2 (rd = rs1 % rs2)
2.Subtraction (SUB): 6.Multiplication and Add
•sub rd, rs1, rs2 (rd = rs1 - rs2) (MULH, MULHU, MULHSU):
3.Multiplication (MUL): •mulh rd, rs1, rs2 (rd = (rs1 * rs2) >>
•mul rd, rs1, rs2 (rd = rs1 * rs2) XLEN)
4.Division (DIV): •mulhu rd, rs1, rs2 (rd = (rs1 * rs2) >>
•div rd, rs1, rs2 (rd = rs1 / rs2) XLEN, for RV64)
•mulhsu rd, rs1, rs2 (rd = (rs1 * rs2) >>
XLEN, signed, for RV64)
RISC Logical Instructions
1.Bitwise AND (AND):
•and rd, rs1, rs2 (rd = rs1 & rs2) 5.Shift Left Logical (SLL):
2.Bitwise OR (OR): •sll rd, rs1, rs2 (rd = rs1 << (rs2 %
•or rd, rs1, rs2 (rd = rs1 | rs2) XLEN))
3.Bitwise XOR (XOR): 6.Shift Right Logical (SRL):
•xor rd, rs1, rs2 (rd = rs1 ^ rs2) •srl rd, rs1, rs2 (rd = rs1 >> (rs2 %
4.Bitwise NOT (NOT): XLEN))
•not rd, rs1 (rd = ~rs1) 7.Shift Right Arithmetic (SRA):
•sra rd, rs1, rs2 (rd = rs1 >> (rs2 %
XLEN), sign-extended)
Instruction Processing
Prog
inst
Mem Reg. ALU
File Data
Mem
+4
5 5 5
PC
control
Instructions: A basic processor
stored in memory, encoded in binary • fetches
00100000000000100000000000001010 • decodes
00100000000000010000000000000000
00000000001000100001100000101010 • executes
one instruction at a time
71
Levels of Interpretation: Instructions
for (i = 0; i < 10; i++) High Level Language
printf(“go cucs”); • HDL, C, Java, Python, ADA, …
• Loops, control flow, variables

main: addi x2, x0, 10 Assembly Language

addi x1, x0, 0 • No symbols (except labels)
loop: slt x3, x1, x2 • One operation per statement
... • “human readable machine
language”
10 x2 x0 op=addi
00000000101000010000000000010011 Machine Language
00100000000000010000000000010000 • Binary-encoded assembly
00000000001000100001100000101010 • Labels become addresses
• The language of the CPU
Instruction Set Architecture
Machine Implementation
ALU, Control, Register File, …
(Microarchitecture) 72
 ISA-Architecture
HDL int x = 10;
compiler x = 2 * x + 15; x0 = 0
x5 = x0 + 10
RISC-V addi x5, x0, 10
muli x5, x5, 2 x5 = x5<<1 #x5 = x5 * 2
assembly addi x5, x5, 15 x5 = x15 + 15
assembler 10 r0 r5 op = addi
00000000101000000000001010010011
machine 00000000001000101000001010000000
code 00000000111100101000001010010011
15 r5 r5 op = addi
CPU op = r-type x5 shamt=1 x5 func=sll

Circuits

Gates

Transistors
73
Silicon
Big Picture: Where are we going?
HDL int x = 10;
compiler x = 2 * x + 15; High Level
addi x5, x0, 10 Languages
RISC-V
muli x5, x5, 2
assembly addi x5, x5, 15
assembler
00000000101000000000001010010011
machine 00000000001000101000001010000000
code 00000000111100101000001010010011
Instruction Set
CPU Architecture (ISA)
Circuits

Gates

Transistors
74
Silicon
RISC-V Instruction Types
RISC-V Instruction Types
• Arithmetic/Logical
• R-type: result and two source registers, shift amount in register
• I-type: result and source register, shift amount in 12-bit immediate with sign/zero
extension
• U-type: result register, 20-bit immediate with sign/zero extension
• S-type: result register (5-bit immediate), source register, 12-bit immediate

• Memory Access
• I-type for loads and S-type for stores
• load/store between registers and memory
• word, half-word and byte operations

• Control flow
• U-type: jump-and-link
• I-type: jump-and-link register
• S-type: conditional branches: pc-relative addresses
76
RISC-V instruction formats
All RISC-V instructions are 32 bits long, have 4
formats
• R-type funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

• I-type imm rs1 funct3 rd op

12 bits 5 bits 3 bits 5 bits 7 bits

• S-type imm rs2 rs1 funct3 imm op

7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

• U-type imm rd op
20 bits 5 bits 7 bits 77
R-Type (1): Arithmetic and Logic
00000000011001000100001000110011
funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

op funct3 mnemonic description

0110011 000 ADD rd, rs1, rs2 R[rd] = R[rs1] + R[rs2]
0110011 000 SUB rd, rs1, rs2 R[rd] = R[rs1] – R[rs2]
0110011 110 OR rd, rs1, rs2 R[rd] = R[rs1] | R[rs2]
0110011 100 XOR rd, rs1, rs2 R[rd] = R[rs1]  R[rs2]

78
Arithmetic and Logic

Prog.
Reg. ALU
Mem
File
+4
55 5
PC
control

Fetch Decode Execute Memory WB

skip

79
R-Type (2): Shift Instructions
0000000001100010000101000011011
funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

op funct3 mnemonic description

0110011 001 SLL rd, rs1, rs2 R[rd] = R[rs1] << R[rs2]
0110011 101 SRL rd, rs1, rs2 R[rd] = R[rs1] >>> R[rs2] (zero ext.)
0110011 101 SRA rd, rs1, rs2 R[rd] = R[rt] >>> R[rs2] (sign ext.)

80
Shift

Prog.
Reg. ALU
Mem
File
+4
55 5
PC
control

Fetch Decode Execute Memory WB

skip

81
I-Type (1): Arithmetic immediates
00000000010100101000001010010011
imm rs1 funct3 rd op
12 bits 5 bits 3 bits 5 bits 7 bits

op funct3 mnemonic description

0010011 000 ADDI rd, rs1, imm R[rd] = R[rs1] + imm
0010011 111 ANDI rd, rs1, imm R[rd] = R[rs1] &
zero_extend(imm)
0010011 110 ORI rd, rs1, imm R[rd] = R[rs1] |
zero_extend(imm)

82
Arithmetic w/ immediates

Prog.
Reg. ALU
Mem
File
+4
55 5
PC
control

imm
extend
16 12

shamt

Fetch Decode Execute Memory WB

skip

83
 “ ”
U-Type (1): Load Upper Immediate
00000000000000000101001010110111
imm rd op
20 bits 5 bits 7 bits

op mnemonic description
0110111 LUI rd, imm R[rd] = imm << 16

84
Load Upper Immediate

Prog.
Reg. ALU
Mem
File
0x50000
+4
55 5
PC
control 16

imm
extend
16 12

shamt

Fetch Decode Execute Memory WB

skip

85
Multiplication

86
 RISC-V Instruction Types
• Arithmetic/Logical
• R-type: result and two source registers, shift amount
• I-type: result and source register, shift amount in 16-bit immediate with sign/zero
extension
• U-type: result register, 16-bit immediate with sign/zero extension

• Memory Access
• I-type for loads and S-type for stores
• load/store between registers and memory
• word, half-word and byte operations

• Control flow
• U-type: jump-and-link
• I-type: jump-and-link register
• S-type: conditional branches: pc-relative addresses

87
RISC-V instruction formats
All RISC-V instructions are 32 bits long, have 4
formats
• R-type funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

• I-type imm rs1 funct3 rd op

12 bits 5 bits 3 bits 5 bits 7 bits

• S-type imm rs2 rs1 funct3 imm op

7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

• U-type imm rd op
20 bits 5 bits 7 bits 88
R-Type (1): Arithmetic and Logic
00000000011001000100001000110011
funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

op funct3 mnemonic description

0110011 000 ADD rd, rs1, rs2 R[rd] = R[rs1] + R[rs2]
0110011 000 SUB rd, rs1, rs2 R[rd] = R[rs1] – R[rs2]
0110011 110 OR rd, rs1, rs2 R[rd] = R[rs1] | R[rs2]
0110011 100 XOR rd, rs1, rs2 R[rd] = R[rs1]  R[rs2]

89
R-Type (2): Shift Instructions
0000000001100010000101000011011
funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

op funct3 mnemonic description

0110011 001 SLL rd, rs1, rs2 R[rd] = R[rs1] << R[rs2]
0110011 101 SRL rd, rs1, rs2 R[rd] = R[rs1] >>> R[rs2] (zero ext.)
0110011 101 SRA rd, rs1, rs2 R[rd] = R[rt] >>> R[rs2] (sign ext.)

90
Thank You
Additional Slides
Intel 80826 Micro-architecture
Intel Core 2 Architecture
Example Cell Phone Processor (OMAP 2420) from TI