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Exp - 5

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15 views2 pages

Exp - 5

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tripathianuj931
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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K

Experiment No. 5

Cect: Study of LVDT (Linear Variable Differential


Transformer) experimental set up and us2
output variation VS input variatic n
it as a transducers and take reading of linearity of
A aratus: (1) Instrumentation tutor I.
(2) LVDT Set up.
whicih
inductance transducer is differential transformer,
1 ory: One of most useful variable the displacement of core passing thr ugh
provides an AC voltage output proportional to making use of three coils arranged
the windings. It is a mutual inductance device magnetic form.
generally on single cylindrical, concentric non
AC power source and the two cid
The center coil is energized from an external coils.Outpu
coils,connected in series opposition to each other are used as pick-up
the two pick-up coil and
amplitude and phase depend on the relative coupling between
the power coil. position of the core Ticoretically there should
Relative coupling in them are dependent on the
be the same
in each of the pick-up coil or seco1ry will
be core position for which the voltage induced
magnitude and the resulting output should be zero. for conversion of mechani al displacement into
L.V.D.T is a very widely used transducers
electrical voltage. The displacenment into proportional electrical voitge range extends for
proportional temperature effects.
few microns to few tens of inches if it is free from

C ervation: Input
Input Meter Metei
SI. No. Displacement Displacement Read1ng
Reading -Ve axis
+ Ve axis

(input) verses variatjon cf voitage


R ult: The graph shows the variation of displacemen:
(output).

P caution: (1) Move the


core in a gentle fashion.
lead wire from panel to transducer make paper
(2) While connecting
connections.
source terminals.
(3) Avoid shorting of the excitation
FRONT CONTROL PANEL FOR L.V.D.T.
(DIGITAL)

FUSE

MAX MIN

SECONDARY

L.V.D.T. STRAIN

PRIMARY

PRIMARY

SECONDARY SECONDARY

BLOCK DIAGRAM OF CAPACITIVE TRANSDUCER SETUP

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