STM32U073x8/B/C

Datasheet

Ultra-low-power Arm® Cortex®-M0+ 32-bit MCU, up to 256-Kbyte flash memory,

40-Kbyte SRAM, USB, LCD

Features
Includes ST state-of-the-art patented technology.
LQFP48 UFQFPN32
(7 x 7 mm) (5 x 5 mm)
LQFP64
(10 x 10 mm)
UFQFPN48
(7 x 7 mm)
Ultra-low-power features (ultra-low-power devices)
LQFP80
(12 x 12 mm) • 1.71 V to 3.6 V power supply
FBGA • -40 °C to 85/125 °C temperature range
• VBAT mode: 130 nA (with RTC and 9 x 32-bit backup registers)
UFBGA64 WLCSP42 • Shutdown mode (6 wake-up pins): 16 nA
(5 x 5 mm) (2.82 x 2.93 mm)
UFBGA81 • Standby mode (6 wake-up pins): 160 nA with RTC, 30 nA without RTC
(5 x 5 mm)
• Stop 2 mode: 825 nA with RTC, 695 nA without RTC
• Run mode (LDO mode): 52 μA/MHz
• Batch acquisition mode (BAM)
• 4 μs wake-up from Stop mode
• Brownout reset (BOR)
Product summary
Core
STM32U073K8,
STM32U073H8, • 32-bit Arm® Cortex®-M0+ CPU, frequency up to 56 MHz
STM32U073x8 STM32U073C8,
STM32U073R8, ART Accelerator
STM32U073M8
• 1-Kbyte instruction cache allowing 0-wait-state execution from flash memory
STM32U073KB,
STM32U073HB,
STM32U073xB STM32U073CB, Benchmarks
STM32U073RB,
STM32U073MB
• 1.13 DMIPS/MHz (Drystone 2.1)
• 134 CoreMark® (2.4 CoreMark/MHz at 56 MHz)
STM32U073KC,
STM32U073HC, • 407 ULPMark™-CP
STM32U073xC STM32U073CC,
STM32U073RC,
• 143 ULPMark™-PP
STM32U073MC • 19.7 ULPMark™-CM

Memories
Product label
• Up to 256-Kbyte single bank flash memory, proprietary code readout protection
• 40-Kbyte SRAM with hardware parity check

Rich analog peripherals (independent supply)

• 1x 12-bit ADC (0.4 µs conversion time), up to 16-bit with hardware
oversampling
• 1x 12-bit DAC output channel, low-power sample and hold
• 1x general-purpose operational amplifier with built-in PGA (variable gain up to
16)
• 2x ultra-low-power comparators

LCD driver
• 8×48 or 4×52 segments, with step-up converter

DS14548 - Rev 2 - March 2024 www.st.com

For further information contact your local STMicroelectronics sales office.
 STM32U073x8/B/C

General-purpose inputs/outputs
• Up to 69 fast I/Os, most of them 5 V‑tolerant

20 communication interfaces
• USB 2.0 full-speed crystal-less solution with LPM and BCD
• 7x USARTs/LPUARTs (SPI, ISO 7816, LIN, IrDA, modem)
• 4x I2C interfaces supporting Fast-mode and Fast-mode Plus (up to 1 Mbit/s)
• 3x SPIs, plus 4x USARTs in SPI mode
• IRTIM (Infrared interface)

Security
• Customer code protection
• Robust read out protection (RDP): 3 protection level states and password-based regression (128-bit
PSWD)
• Hardware protection feature (HDP)
• Secure boot
• True random number generation, candidate for NIST SP 800-90B certification
• Candidate for Arm® PSA level 1 and SESIP level 3 certifications
• 5 passive anti-tamper pins
• 96-bit unique ID

Clock management
• 4 to 48 MHz crystal oscillator
• 32 kHz crystal oscillator for RTC (LSE)
• Internal 16 MHz factory-trimmed RC (±1%)
• Internal low-power 32 kHz RC (±5%)
• Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)
• Internal 48 MHz with clock recovery
• PLL for system clock, USB, ADC

10 timers, RTC, and 2 watchdogs

• 1x 16-bit advanced motor-control, 1x 32-bit and 3x 16-bit general purpose, 2x 16-bit basic, 3x low-power
16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer
• RTC with hardware calendar, alarms and calibration

CRC calculation unit

Up to 21 capacitive sensing channels

• Supporting touchkey, linear and rotary touch sensors

12-channel DMA controller

• Flexible mapping (DMAMUX)

Debug
• Development support: serial wire debug (SWD)

All packages are ECOPACK2 compliant.

DS14548 - Rev 2 page 2/146

 STM32U073x8/B/C
Introduction

1 Introduction

This document provides information on STM32U073x8/B/C devices, such as description, functional overview, pin
assignment and definition, electrical characteristics, packaging and ordering information.
It must be read in conjunction with the STM32U073x8/B/C reference manual (RM0503).
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32U073x8/B/C errata sheet (ES0602).
For information on the Arm® Cortex®-M0+ core, refer to the Cortex-M0+ Technical Reference Manual, available
from the www.arm.com website.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS14548 - Rev 2 page 3/146

 STM32U073x8/B/C
Description

2 Description

The STM32U073x8/B/C devices are ultra-low-power microcontrollers based on the high-performance Arm®
Cortex®-M0+ 32-bit RISC core operating at a frequency of up to 56 MHz.
The STM32U073x8/B/C devices embed high-speed memories (up to 256-Kbyte flash memory and 40-Kbyte
SRAM with hardware parity check), and an extensive range of enhanced I/Os and peripherals connected to APB
and AHB buses, and a 32-bit multi-AHB bus matrix.
They also embed protection mechanisms for embedded flash memory and SRAM, such as readout protection and
write protection.
The STM32U073x8/B/C devices offer a 12-bit ADC, a 12-bit DAC, two embedded rail-to-rail analog comparators,
one operational amplifier, a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to
motor control, three general-purpose 16-bit timers, and three 16-bit low-power timers
The devices also embed up to 21 capacitive sensing channels, plus an integrated LCD controller that enables to
drive 8x48 or 4x52 segments with internal step-up converter.
They also feature standard and advanced communication interfaces, namely four I2Cs, three SPIs, four USARTs
and three low-power UARTs, plus one crystal-less USB full-speed device.
The STM32U073x8/B/C operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction)
temperature ranges from a 1.71 to 3.6 V VDD power supply using an internal LDO regulator. A comprehensive set
of power-saving modes makes possible the design of low-power applications.
Independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMP and
comparator, as well as VBAT input allowing the backup of the RTC and backup registers.
The STM32U073x8/B/C offer eight packages from 32 to 81 pins.
Refer to the table below for the list of peripherals available on each part number.

Table 1. Device features and peripheral counts

Peripherals STM32U073Mx STM32U073Rx STM32U073Cx STM32U073Hx STM32U073Kx

Flash memory (Kbytes) 64/128/256

SRAM (Kbytes) 40
Advanced
1 (16 bits)
control

General 3 (16 bits)

purpose 1 (32 bits)
Basic 2 (16 bits)
Timers
Low power 3 (16 bits)
SysTick 1
Watchdog
timers
2
(independent,
window)
SPI 3
I2C 4
Communication
USART 4
interfaces
LPUART 3
USB Yes
RTC Yes
Tamper pins 5 5 4 3 3
LCD Yes Yes Yes Yes Yes
COM x SEG 8x48 or 4x52 8x33 or 4x37 4x24 3x19 3x17
TRNG Yes

DS14548 - Rev 2 page 4/146

 STM32U073x8/B/C
Description

Peripherals STM32U073Mx STM32U073Rx STM32U073Cx STM32U073Hx STM32U073Kx

GPIOs 68/69(1) 53 39 33 27
Wakeup pins 6 6 6 4 3

Capacitive sensing
21 18 12 9 8
Number of channels
12-bit ADC 1 1
Number of channels 16 10
12-bit DAC 1
Internal voltage reference buffer Yes No
Analog comparators 2
Operational amplifier 1
Max. CPU frequency (MHz) 56
Operating voltage (VDD) 1.71 to 3.6 V

Ambient operating temperature:-40 to 85 °C/-40 to 125 °C

Operating temperature
Junction temperature:-40 to 105 °C/-40 to 130 C
LQFP80, LQFP64, LQFP48,
Packages WLCSP42 UFQFPN32
UFBGA81 UFBGA64 UFBGA48

1. LQFP80 and UFBGA81 offer 68 and 69 GPIOs, respectively.

DS14548 - Rev 2 page 5/146

 STM32U073x8/B/C
Description

Figure 1. Block diagram

POWER
SWCLK DMAMUX
SWD Voltage
SWDIO VCORE regulator
DMA1&2
VDDIO1 VDDUSB,
CPU Flash memory VDDA VDD, VDDA,
CORTEX-M0+ I/F Up to 256 KB VSS, VSSA
VDD

Bus matrix
SUPPLY
fmax = 56 MHz SUPERVISION
POR
SRAM1 8 KB POR/BOR
Reset
SRAM2 32 KB Int NRST
NVIC IOPORT Parity T sensor
MSI MSI PVD
HSI48 RC 48 MHz
GPIOs HSI16 RC 16 MHz
PLLPCLK
PAx Port A
PLLQCLK PLL
PLLRCLK XTAL OSC OSC_IN
PBx Port B RNG 4-48 MHz OSC_OUT
LSI RC 32 kHz
Decoder

PCx Port C IWDG

HSE
PDx Port D I/F
RCC LSE VDD VBAT
PEx Port E Reset & clock control Low-voltage
CRC detector

PFx Port F LSE OSC32_IN

AHB

XTAL32 kHz
System and OSC32_OUT
peripheral
clocks RTC, TAMP RTC_OUT
EXTI Backup regs RTC_REFIN
RTC_TS
from peripherals I/F
AHB-to-APB TAMP_IN

VOUT, VINM, VINP OPAMP1

4 channels
TIM1
VREF+ VREFBUF BKIN, BKIN2, ETR

COMP1 4 channels
TIM2 (32-bit)
IN+, IN-, ETR
OUT COMP2 SYSCFG
4 channels
TIM3
ETR
DAC_OUT1 DAC I/F 2 channels
TIM6 TIM15
BKIN

TIM7 TIM16 1 channel

16x IN ADC I/F BKIN

LPTIM1,
LPTIMER2& 3
1/2 ETR, IN, OUT
MOSI
MISO PWRCTRL
SPI1, 2 & 3 IRTIM IR_OUT
SCK
NSS
APB

WWDG
APB

DP
DBGMCU
FIFO

RX, TX
PHY

DM USB USART1 &2

NOE USART1/2 CTS, RTS, CK

USART3 &4 RX, TX

USART3/4 CTS, RTS, CK
CRS_SYNC CRS RX, TX,
LPUART1, 2 & 3 CTS, RTS

I2C1, 2, 3 & 4 SCL, SDA

DT71269V5

Power domain of analog blocks : VBAT VDD VDDA VDDIO1 VDDUSB

DS14548 - Rev 2 page 6/146

 STM32U073x8/B/C
Functional overview

3 Functional overview

3.1 Arm® Cortex®-M0+ core with MPU

The Arm Cortex -M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded
applications. It offers significant benefits to developers, including:
• A simple architecture, easy to learn and program
• ultra-low power, energy-efficient operation
• Excellent code density
• Deterministic, high-performance interrupt handling
• Upward compatibility with Cortex-M processor family
• Platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von
Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful
instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle
multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a
higher code density than other 8-bit and 16-bit microcontrollers.
Owing to embedded Arm core, the STM32U073x8/B/C devices are compatible with Arm tools and software.
The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in
Section 3.14.1: Nested vectored interrupt controller (NVIC).

3.2 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M0+
processors. It balances the inherent performance advantage of the Arm Cortex-M0+ over flash memory
technologies, which normally requires the processor to wait for the flash memory at higher frequencies.
To release the processor near 67 DMIPS performance at 56 MHz, the accelerator implements an instruction
prefetch queue and branch cache, which increases program execution speed from the 64-bit flash memory.
Based on benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state
program execution from flash memory at a CPU frequency up to 56 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to
corrupt accidentally the memory or resources used by any other active task.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the
misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program
accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

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 STM32U073x8/B/C
Functional overview

3.4 Memories

3.4.1 Embedded flash memory

STM32U073x8/B/C devices feature up to 256 Kbytes of embedded flash memory available for storing code and
data.
Flexible protections can be configured thanks to option bytes:
• Robust readout protection (RDP) with password-based regression (128-bit PSWD). Three protections level
states are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the flash memory cannot be read from or written to if either
debug features are connected, boot in RAM or bootloader is selected
– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in RAM and
bootloader selection are disabled. This selection is irreversible.
Refer to Table 2 for the memory area access versus the RDP protection level.
• Write protection (WRP): the protected area is protected against erasing and programming. Two areas per
bank can be selected, with 2-Kbyte granularity.

Table 2. Access status versus readout protection level and execution modes

Debug, boot from RAM or boot from

Protection User execution
Area system memory (loader)
level
Read Write Erase Read Write Erase

1 Yes Yes Yes No No No

User memory
2 Yes Yes Yes N/A N/A N/A

System 1 Yes No No Yes No No

memory 2 Yes No No N/A N/A N/A

Option 1 Yes Yes Yes Yes Yes Yes

memory 2 Yes No No N/A N/A N/A

Backup 1 Yes Yes N/A(1) No No N/A(1)

memory 2 Yes Yes N/A N/A N/A N/A

1. Erased upon RDP change from Level 1 to Level 0.

The whole nonvolatile memory embeds the error correction code (ECC) feature supporting:
• Single error detection and correction
• Double error detection
• Readout of the ECC fail address from the ECC register

Securable area
A part of the flash memory can be hidden from the application once the code it contains is executed. As soon as
the security is enabled on the securable area through the FLASH_HDPCR and FLASH_SECR registers, the
securable memory cannot be accessed until the system resets. The securable area generally contains the secure
boot code to execute only once at boot. This helps to isolate secret code from untrusted application code.

3.4.2 Embedded SRAM

STM32U073x8/B/C devices have 40-Kbyte SRAM with hardware parity check. Hardware parity check allows
memory data errors to be detected, which contributes to increasing functional safety of applications.

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 STM32U073x8/B/C
Functional overview

The embedded SRAM is split between two regions, as follows:

• SRAM1: 32 Kbytes with hardware parity check, mapped at address 0x2000 0000
• SRAM2: 8 Kbytes with hardware parity check, located at address 0x1000 0000
SRAM2 is also mapped at address 0x2000 8000, offering a contiguous address space with SRAM1
(8 Kbytes aliased by bit band).
The content of SRAM2 is retained in Standby mode.
It is write-protected with a 1-Kbyte granularity.
The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:
• Boot from user flash memory
• Boot from system memory
• Boot from embedded SRAM
The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot
loader is located in system memory. It manages the flash memory reprogramming through one of the following
interfaces:
• USART on pins PA9/PA10, PC10/PC11, or PA2/PA3
• I2C-bus on pins PB6/PB7 or PB10/PB11
• SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15
• USB on pins PA11/12

3.6 Power supply management

3.6.1 Power supply schemes

The STM32U073x8/B/C devices require a 1.71 to 3.6 V operating supply voltage (VDD).
Several different power supplies are provided to specific peripherals:
• VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and the system analog
such as reset, power management and internal clocks. It is provided externally through VDD pins.
• VDDA = 1.62 V (ADC/COMP)/1.80 V (DAC/OPAMP)/2.4 V (VREFBUF) to 3.6 V: external analog power
supply for ADC, OPAMP, DAC, and comparator. The VDDA voltage level is independent from the VDD
voltage.
• VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The VDDUSB voltage level
is independent from the VDD voltage.
• VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through
power switch) when VDD is not present. When VBAT pin is not available on the package, VBAT pad is
internally bonded to VDD/VDDA pin.
• VREF+ is the analog peripheral input reference voltage, or the output of the internal voltage reference buffer
(when enabled). When VDDA < 2 V, VREF+ must be equal to VDDA. When VDDA ≥ 2 V, VREF+ must be
between 2 V and VDDA. It can be grounded when the analog peripherals using VREF+ are not active.
The internal voltage reference buffer supports two output voltages, which is configured with VRS bit of the
VREFBUF_CSR register:
– VREF+ around 2.048 V (requiring VDDA equal to or higher than 2.4 V)
– VREF+ around 2.5 V (requiring VDDA equal to or higher than 2.8 V)
VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is internally connected to
VDDA, and the internal voltage reference buffer must be kept disabled (refer to datasheets for package
pinout description).
• VCORE
An embedded linear voltage regulator is used to supply the VCORE internal digital power. VCORE is the
power supply for digital peripherals, SRAM and flash memory. The flash memory is also supplied with VDD.

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 STM32U073x8/B/C
Functional overview

Note: When the functions supplied by VDDA are not used, this supply should preferably be shorted to VDD.
If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant.
VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with VDDIO1 = VDD.

Figure 2. Power supply overview

VDDA domain
A/D converters
VDDA D/A converters
Comparators
VSSA Operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS

VDD domain
VDDIO1
VDD I/O ring
Reset block
Temp. sensor
PLL, MSI, HSI48,
HSI16
VSS Standby circuitry
(Wakeup logic,
IWDG) VCORE domain
VCORE Core
Voltage regulator Memories
Digital peripherals

Low voltage detector

Backup domain
LSE crystal 32 K osc
BKP registers
VBAT RCC BDCR register
RTC
DT71259V2

3.6.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power modes except
Shutdown and ensuring proper operation upon power-on and power-down. It maintains the device in reset when
the supply voltage is below VPOR/PDR threshold, without the need for an external reset circuit. Brownout reset
(BOR) function allows extra flexibility. It can be enabled and configured through option bytes, by selecting one of
four thresholds for rising VDD and other four for falling VDD.
The device also features an embedded programmable voltage detector (PVD) that monitors the VDD power
supply and compares it to VPVD threshold. It allows generating an interrupt when VDD level crosses the VPVD
threshold, selectively while falling, while rising, or while falling and rising. The interrupt service routine can then
generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

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 STM32U073x8/B/C
Functional overview

3.6.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR), and low-power regulator (LPR), supply most of
digital circuitry in the device:
• The MR is used in Run, Sleep and Stop 0 modes.
• The LPR is used in Low-power run, Low-power sleep, Stop 1, and Stop 2 modes. It is also used to supply
the 8-Kbyte SRAM2 in Standby mode, in order to ensure SRAM2 retention.
Both regulators are powered down in Standby and Shutdown modes: the regulator output is in high impedance,
and the kernel circuitry is powered down, thus inducing zero consumption.

3.6.4 VBAT operation

The VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and backup registers.
In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for example, an external
battery or an external supercapacitor. Two anti-tamper detection pins are available.
The RTC domain can also be supplied from VDD/VDDA pin.
By means of a built-in switch, an internal voltage supervisor allows automatic switching of RTC domain powering
between VDD and voltage from VBAT pin to ensure that the supply voltage of the RTC domain (VBAT) remains
within valid operating conditions. If both voltages are valid, the RTC domain is supplied from VDD/VDDA pin.
An internal circuit for charging the battery on VBAT pin can be activated if the VDD voltage is within a valid range.
Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT mode, as in that
mode the VDD is not within a valid range.

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 STM32U073x8/B/C
Functional overview

3.7 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the user to select one of the
low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU
when an interrupt/event occurs.
• Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator operating
current. The code can be executed from SRAM or from flash, and the CPU frequency is limited to 2 MHz.
The peripherals with independent clock can be clocked by HSI16.
• Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped. When the wake-up is
triggered by an event or an interrupt, the system reverts to the Low-power run mode.
• Stop 0, Stop 1, and Stop 2 modes
The Stop modes achieve a lowest power consumption while retaining the content of SRAM and registers.
All the clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal
oscillators are disabled. The LSE and LSI clocks are still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with the wake-up capability can enable the HSI16 RC during Stop mode, to detect their
wake-up condition.
Three Stop modes are available, Stop 0, Stop 1 and Stop2:
– In Stop2 mode, most of the VCORE domain is put in lower-leakage mode.
– Stop 1 offers the largest number of active peripherals and wake-up sources, a smaller wake-up time,
but with a higher consumption than Stop 2 mode.
– In Stop 0 mode, the main regulator remains on, allowing a very fast wake-up time, but with a much
higher consumption.
When exiting from Stop 0, Stop 1 or Stop 2 mode, the system clock can be either the MSI clock (up to
48 MHz) or HSI16, depending on software configuration.
• Standby mode
The Standby mode is used to achieve one of the lowest power consumption, with POR/PDR always active
in this mode. The main regulator is switched off to power down VCORE domain. The low-power regulator is
either switched off or kept active. In the latter case, it only supplies SRAM to ensure data retention. The
PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC
can remain active (Standby mode with RTC, Standby mode without RTC).
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor must be applied to
that I/O during Standby mode.
Upon entering Standby mode, register contents are lost except for registers in the RTC domain and
standby circuitry. The SRAM contents can be retained through register setting.
The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wake-up event
(WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wake-up, timestamp, tamper),
or when a failure is detected on LSE (CSS on LSE).
• Shutdown mode
The Shutdown mode enables to achieve the lowest power consumption. The internal regulator is switched
off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators
are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode,
therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable
rising or falling edge), or an RTC event occurs (alarm, periodic wake-up, timestamp, tamper).
The system clock after wake-up is MSI at 4 MHz.

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 STM32U073x8/B/C
Functional overview

Table 3. Functionalities depending on the mode

Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
Stop 0/1 Stop 2 Standby Shutdown

Wake-up capability

Wake-up capability

Wake-up capability

Wake-up capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -

CPU Y - Y - - - - - - - - - -
Flash memory (up to
O(1) O(1) O(1) O(1) - - - - - - - - -
256 Kbytes)

SRAM1 (32 Kbytes) Y Y(2) Y Y(2) Y - Y - - - - - -

SRAM2 (8 Kbytes) Y Y(2) Y Y(2) Y - Y - O(3) - - - -

Backup registers Y Y Y Y Y - Y - Y - Y - Y
Brownout reset (BOR) Y Y Y Y Y Y Y Y Y Y - - -
Programmable voltage
O O O O O O O O - - - - -
detector (PVD)
Peripheral voltage monitor
O O O O O O O O - - - - -
(PVMx; x = 1, 2, 3)
DMA O O O O - - - - - - - - -

High-speed Internal (HSI16) O O O O (4) - (4) - - - - - -

Oscillator RC48 (HSI48) O O - - - - - - - - - - -

High-speed external (HSE) O O O O - - - - - - - - -
Low-speed internal (LSI) O O O O O - O - O - - - -
Low-speed external (LSE) O O O O O - O - O - O - O
Multi-Speed internal (MSI) O O O O - - - - - - - - -
Clock security system (CSS) O O O O - - - - - - - - -
Clock security system on
O O O O O O O O O O - - -
LSE
RTC / Auto-wakeup O O O O O O O O O O O O O
Number of RTC tamper pins 2 2 2 2 2 O 2 O 2 O 2 O 2

USARTx (x = 1, 2, 3, 4) O O O O O(5) O(5) - - - - - - -

LPUARTx (x = 1 to x = 3) O O O O O(5) O(5) O(5) O(5) - - - - -

I2Cx (x = 2, 4) O O O O O(6) O(6) - - - - - - -

I2Cx (x = 1, 3) O O O O O(6) O(6) O(6) O(6) - - - - -

SPIx (x = 1 to 3) O O O O - - - - - - - - -
ADC1 O O O O - - - - - - - - -
DAC1 O O O O O - - - - - - - -
OPAMP1 O O O O O - - - - - - - -
COMPx (x = 1, 2) O O O O O O O O - - - - -
Temperature sensor O O O O - - - - - - - - -
Timers (TIMx) O O O O - - - - - - - - -

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Stop 0/1 Stop 2 Standby Shutdown

Wake-up capability

Wake-up capability

Wake-up capability

Wake-up capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -

LPTIMx (x = 1 to 3) O O O O O O O O - - - - -
Independent watchdog
O O O O O O O O O O - - -
(IWDG)
Window watchdog (WWDG) O O O O - - - - - - - - -
SysTick timer O O O O - - - - - - - - -
Touch sensing controller
O O O O - - - - - - - - -
(TSC)
LCD O O O O O O O O - - - - -
True random number
O(7) O(7) - - - - - - - - - - -
generator (RNG)
CRC calculation unit O O O O - - - - - - - - -

(8)
5 (10)
5
GPIOs O O O O O O O O -
pins(9) pins(9)

1. The flash memory can be configured in power-down mode. By default, it is not in power-down mode.
2. The SRAM clock can be gated on or off.
3. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
4. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral,
and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.
5. UART and LPUART reception is functional in Stop mode, and generates a wake-up interrupt on Start, address match or received frame
event.
6. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match.
7. Voltage scaling Range 1 only.
8. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
9. The I/Os with wake-up from Standby/Shutdown capability are PA0, PA1, PA2, PB15, PC5, and PC13.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown
mode.

3.8 Peripheral interconnect matrix

Several peripherals have direct connections between them. This allows autonomous communication between
peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections
allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

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Table 4. Interconnect of peripherals

Low-power sleep
Low-power run
Sleep
Interconnect

Stop
Run
Interconnect source Interconnect action
destination

TIMx Timer synchronization or chaining Y Y -

ADCx
Conversion triggers Y Y -
TIMx DACx
DMA Memory-to-memory transfer trigger Y Y -
COMPx Comparator output blanking Y Y -
Timer input channel, trigger, break from analog
TIM1, 2, 3 Y Y -
signals comparison
COMPx
Low-power timer triggered by analog signals
LPTIMx Y Y Y
comparison
ADCx TIM1 Timer triggered by analog watchdog Y Y -
TIM16 Timer input channel from RTC events Y Y -
RTC Low-power timer triggered by RTC alarms or
LPTIMx Y Y Y
tampers
All clock sources (internal and Clock source used as input channel for RC
TIM16 Y Y -
external) measurement and trimming
CSS
RAM (parity error)
Flash memory (ECC error) TIM1, 15, 16 Timer break Y Y -
COMPx
PVD
CPU (HardFault) TIM1 15, 16 Timer break Y - -
TIMx External trigger Y Y -
LPTIMx External trigger Y Y Y
GPIOs
ADCx
Conversion external trigger Y Y -
DACx

3.9 Reset and clock controller (RCC)

3.9.1 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In
addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated.

3.9.2 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also
manages clock gating for low-power modes and ensures clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to
the CPU and peripherals can be adjusted by a programmable prescaler.

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• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration
register.
• Clock management: to reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.
• System clock source: two different sources can deliver SYSCLK system clock:
– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock
to system PLL. The HSE can also be configured in bypass mode for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to
system PLL.
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies form
100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be automatically trimmed by hardware to reach an accuracy better than ± 0.25%. The
MSI can supply a PLL.
– System PLL, which can be fed by HSE, HSI16 or MSI. It provides a system clock up to 56 MHz.
• Auxiliary clock source: three ultra-low-power clock sources for the real-time clock (RTC), and the LCD
controller:
– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes.
The LSE can also be configured in bypass mode for using an external clock.
– 32 kHz low-speed internal RC oscillator (LSI) with ± 5% accuracy, also used to clock an independent
watchdog.
• Peripheral clock sources: several peripherals (RNG, USARTs, I2Cs, LPTIMs, ADC) have their own clock
independent of the system clock.
• Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically
switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected
and generate an interrupt. The CSS feature can be enabled by software.
• Clock output:
– MCO (microcontroller clock output) provides one of the internal clocks for external use by the
application
– LSCO (low speed clock output) provides LSI or LSE in all low-power modes (except in VBAT
operation).
Several prescalers enable the application to configure AHB and APB domain clock frequencies, 56 MHz at
maximum.

3.10 Clock recovery system (CRS)

The STM32U073x8/B/C devices embed a special block, which enables automatic trimming of the internal 48 MHz
oscillator, to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is
based on the external synchronization signal, which could be either derived from USB SOF signalization, from
LSE oscillator, from an external signal on CRS_SYNC pin, or generated by the user software. For faster lock-in
during startup, it is also possible to combine automatic trimming with manual trimming action.

3.11 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without
pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital
or analog functions.
Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious
writing to I/O control registers.

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3.12 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture.
With seven channels, it performs data transfers between memory-mapped peripherals and/or memories, to
offload the CPU.
Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes
an arbiter for handling the priority between DMA requests.
Main features of the DMA controller:
• Single-AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-peripheral data
transfers
• Access, as source and destination, to on-chip memory-mapped devices such as flash memory, SRAM, and
AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a peripheral, or with a
software trigger in memory-to-memory transfers. This configuration is done by software.
– Priority between the requests is programmable by software (four levels per channel: very high, high,
medium, low) and by hardware in case of equality (such as request to channel 1 has priority over
request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word), emulating packing
and unpacking. Source and destination addresses must be aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request originates from any of the three
DMA events: transfer complete, half transfer, or transfer error.

3.13 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA
controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its
DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable
events on its input trigger signals.

3.14 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The
Cortex®-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event
controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events
such as, for example, a division by zero and, core-external events such as logical level changes on physical lines.
Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the
original program flow.
The processor context (contents of program pointer and status registers) is stacked upon program interrupt and
unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt
service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-
multiple and store-multiple operations significantly increases the device’s responsiveness in processing
exceptions.

3.14.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line
events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex®-M0+ exceptions. It
provides flexible priority management.
The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and
start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the
NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base
address and the ISR order number used as offset.

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If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for
being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-
chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary
processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.
Features of the NVIC:
• Low-latency interrupt processing
• Four priority levels
• Handling of a non-maskable interrupt (NMI)
• Handling of 32 maskable interrupt lines
• Handling of 10 Cortex-M0+ exceptions
• Later-arriving higher-priority interrupt processed first
• Tail-chaining
• Interrupt vector retrieval by hardware

3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying
wake-up events at processor wake-up from Stop mode.
The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge
detector capability. Any GPIO and a few peripheral signals can be connected to these channels.
The channels can be independently masked.
The EXTI controller can capture pulses shorter than the internal clock period.
A register in the EXTI controller latches every event even in Stop mode, which enables the software to identify the
origin of the processor wake-up from Stop mode or, to identify the GPIO and the edge event having caused an
interrupt.

3.15 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator
polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the
scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC
calculation unit helps compute a signature of the software during runtime, to be compared with a reference
signature generated at link time and stored at a given memory location.

3.16 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32U073x8/B/C devices. It can be extended to 16-
bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels
(temperature sensor, voltage reference, VBAT monitoring). It performs conversions in single-shot or scan mode. In
scan mode, automatic conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 Msps even
with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the
active conversion phase.
The ADC can be served by the DMA controller. It can operate in the whole VDD supply range.
The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to
AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned
channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers,
to allow the application to synchronize A/D conversions with timers.

3.16.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital
value.

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The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature
measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the
uncalibrated internal temperature sensor is suitable only for relative temperature measurements.
To improve the accuracy of the temperature sensor, each part is individually factory-calibrated by ST. The
resulting calibration data are stored in the part’s engineering bytes, accessible in read-only mode.

Table 5. Temperature sensor calibration values

Calibration value
Description Memory address
name

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

TS_CAL1 0x1FFF 6E68 - 0x1FFF 6E69
VDDA = VREF+ = 3.0 V (± 10 mV)

TS ADC raw data acquired at a

TS_CAL2 temperature of 130 °C (± 5 °C), 0x1FFF 6E8A - 0x1FFF 6E8B
VDDA = VREF+ = 3.0 V (± 10 mV)

3.16.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and
comparators. VREFINT is internally connected to an ADC input. The VREFINT voltage is individually precisely
measured for each part by ST during production test and stored in the part’s engineering bytes. It is accessible in
read-only mode.

Table 6. Internal voltage reference calibration values

Calibration value
Description Memory address
name

Raw data acquired at a temperature of 30 °C (± 5 °C),

VREFINT 0x1FFF 6EA4 - 0x1FFF 6EA5
VDDA = VREF+ = 3.0 V (± 10 mV)

3.16.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage using an internal
ADC input. As the VBAT voltage may be higher than VDDA and thus outside the ADC input range, the VBAT pin is
internally connected to a bridge divider by three. As a consequence, the converted digital value is one third the
VBAT voltage.

3.17 Digital-to-analog converter (DAC)

The single-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel
output. The architecture of either channel is based on integrated resistor string and an inverting amplifier.
Features of the DAC:
• One DAC output channel
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• DMA capability
• Triggering with timer events, synchronized with DMA
• Triggering with external events
• Sample-and-hold low-power mode, with internal or external capacitor

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3.18 Voltage reference buffer (VREFBUF)

When enabled, an embedded buffer provides the internal reference voltage to analog blocks (for example ADC)
and to VREF+ pin for external components.
The internal voltage reference buffer supports two voltages:
• 2.048 V
• 2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer
is disabled.
On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to common VDD/VDDA
pin and so the internal voltage reference buffer cannot be used.

3.19 Comparators (COMP)

STM32U073x8/B/C embed two embedded rail-to-rail analog comparators with programmable reference voltage
(internal or external), hysteresis, speed (low for low-power), and output polarity.
The reference voltage can be one of the following:
• External, from an I/O
• Internal, from DAC
• Internal reference voltage (VREFINT) or its submultiple (1/4, 1/2, 3/4)
The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers
and can be also combined into a window comparator.

3.20 Operational amplifier (OPAMP)

The STM32U073x8/B/C devices embed one operational amplifier with external and internal follower routing and
PGA capability.
Features of the operational amplifier:
• Low input bias current
• Low offset voltage
• Low-power mode
• Rail-to-rail input

3.21 Liquid crystal controller (LCD)

The LCD drives up to eight common terminals and 48 segment terminals to drive up to 352 pixels.
Features of the LCD:
• Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter
can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD
• Supports static, 1/2, 1/3, 1/4 and 1/8 duty
• Supports static, 1/2, 1/3 and 1/4 bias
• Phase inversion to reduce power consumption and EMI
• Up to eight pixels can be programmed to blink
Unneeded segments and common pins can be used as general I/O pins
LCD RAM can be updated at any time owing to a double-buffer
The LCD controller can operate in Stop mode

3.22 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any
application. Capacitive sensing technology is able to detect finger presence near an electrode that is protected
from direct touch by a dielectric (such as glass or plastic). The capacitive variation introduced by the finger (or any
conductive object) is measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware library that is free to use
and allows touch sensing functionality to be implemented reliably in the end application.

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The main features of the touch sensing controller are the following:
• Charge transfer acquisition principle
• Up to 21 capacitive sensing channels
• Up to three capacitive sensing channels can be acquired in parallel offering a very good response time
• Five selectable thresholds (VIH, VREF, 3/4 VREF, 1/2 VREF, 1/4 VREF) using the digital threshold or the ultra-
low-power comparator
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to three capacitive sensing channels to reduce the system components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with the STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O
availability.

3.23 True random-number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit
samples. It is composed of a live entropy source (analog) and an internal conditioning component.

3.24 Timers and watchdogs

The device includes an advanced-control timer, six general-purpose timers, two basic timers, three low-power
timers, two watchdog timers and a SysTick timer. Table 7 compares features of the advanced-control, general-
purpose and basic timers.

Table 7. Timer feature comparison

Maximum DMA Capture/ Compleme

Counter Counter Prescaler
Timer type Timer operating request compare ntary
resolution type factor
frequency generation channels outputs

Advanced- Up, down, Integer from

TIM1 16-bit 56 MHz Yes 4 3
control up/down 1 to 216

Up, down, Integer from

TIM2 32-bit 56 MHz Yes 4 -
up/down 1 to 216

Up, down, Integer from

TIM3 16-bit 56 MHz Yes 4 -
General up/down 1 to 216
-purpose Integer from
TIM15 16-bit Up 56 MHz Yes 2 1
1 to 216
Integer from
TIM16 16-bit Up 56 MHz Yes 1 1
1 to 216

TIM6 and Integer from

Basic 16-bit Up 56 MHz Yes - -
TIM7 1 to 216
LPTIM1,
Lower- 2n where
LPTIM2, 16-bit Up 56 MHz No N/A -
power n = 0 to 7
and LPTIM3

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3.24.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6 channels. It has
complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-
purpose timer. The four independent channels can be used for:
• Input capture
• Output compare
• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off
any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in Section 3.24.2: General-
purpose timers (TIM2, 3, 15, 16)) using the same architecture, so the advanced-control timers can work together
with the TIMx timers via the Timer Link feature for synchronization or event chaining.

3.24.2 General-purpose timers (TIM2, 3, 15, 16)

There are four synchronizable general-purpose timers embedded in the device (refer to Table 7 for comparison).
Each general-purpose timer can be used to generate PWM outputs or act as a simple timebase.
• TIM2, TIM3
These are full-featured general-purpose timers:
– TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler
– TIM3 with 16-bit auto-reload up/downcounter and 16-bit prescaler
They have four independent channels for input capture/output compare, PWM, or onepulse mode output.
They can operate together or in combination with other general-purpose timers via the Timer Link feature
for synchronization or event chaining. They can generate independent DMA request and support
quadrature encoders. Their counters can be frozen in debug mode.
• TIM15, TIM16
These are general-purpose timers featuring:
– 16-bit auto-reload upcounter and 16-bit prescaler
– 2 channels and 1 complementary channel for TIM15
– 1 channel and 1 complementary channel for TIM16
All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers
can operate together via the Timer Link feature for synchronization or event chaining. They can generate
independent DMA request. Their counters can be frozen in debug mode.

3.24.3 Basic timers (TIM6 and TIM7)

These timers are mainly used for triggering DAC conversions. They can also be used as generic 16-bit
timebases.

3.24.4 Low-power timers (LPTIM1, LPTIM2, and LPTIM3)

These timers have an independent clock. When fed with LSE, LSI or external clock, they keep running in Stop
mode and they can wake up the system from it.
Features of LPTIM1, LPTIM2, and LPTIM3:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output (pulse, PWM)
• Continuous/one-shot mode
• Selectable software/hardware input trigger
• Selectable clock source:
– Internal: LSE, LSI, HSI16 or APB clocks
– External: over LPTIM input (working even with no internal clock source running, used by pulse
counter application)
• Programmable digital glitch filter
• Encoder mode

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3.24.5 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh
window. It is clocked from an independent 32 kHz internal RC (LSI).
Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to
reset the device when a problem occurs, or as a free-running timer for application timeout management. It is
hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode.

3.24.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a
watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning
interrupt capability. Its counter can be frozen in debug mode.

3.24.7 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter.
Features of SysTick timer:
• 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source

3.25 Real-time clock (RTC), tamper (TAMP) and backup registers

The device embeds an RTC and nine 32-bit backup registers, located in the RTC domain of the silicon die.
The ways of powering the RTC domain are described in Section 3.6.1: Power supply schemes.
The RTC is an independent BCD timer/counter.
Features of the RTC:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD
(binary-coded decimal) format
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Programmable alarm
• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with a master clock
• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be used to improve the
calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy
• Five anti-tamper detection pins with programmable filter
• Timestamp feature to save a calendar snapshot, triggered by an event on the timestamp pin or a tamper
event, or by switching to VBAT mode
• 17-bit auto-reload wake-up timer (WUT) for periodic events, with programmable resolution and period
• Multiple clock sources and references:
– A 32.768 kHz external crystal (LSE)
– An external resonator or oscillator (LSE)
– The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
– The high-speed external clock (HSE) divided by 32
When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When clocked by LSI, the
RTC does not operate in VBAT mode, but it does in low-power modes except for the Shutdown mode.
All RTC events (alarm, wake-up timer, timestamp or tamper) can generate an interrupt and wake the device up
from the low-power modes.
The backup registers allow keeping 20 bytes of user application data in the event of VDD failure, if a valid backup
supply voltage is provided on VBAT pin. They are not affected by the system reset, power reset, and upon the
device wake-up from Standby or Shutdown modes.

3.26 Inter-integrated circuit interface (I2C)

The device embeds four I2C peripherals. Refer to Table 8 for the features.

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 STM32U073x8/B/C
Functional overview

The I2C-bus interface handles communication between the microcontroller and the serial I2C-bus. It controls all
I2C-bus-specific sequencing, protocol, arbitration and timing.
Features of the I2C peripheral:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Clock stretching
• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be
independent of the PCLK reprogramming
• Wake-up from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 8. I2C implementation

I2C features I2C1 I2C2 I2C3 I2C4

Standard mode (up to

X X X X
100 kbit/s)
Fast mode (up to
X X X X
400 kbit/s)
Fast mode Plus (up to
1 Mbit/s) with extra X X X X
output drive I/Os
Programmable analog
X X X X
and digital noise filters
SMBus/PMBus
- - - -
hardware support
Independent clock X - X -
Wakeup from Stop
mode on address X - X -
match

3.27 Universal synchronous/asynchronous receiver transmitter (USART/UART)

The devices embed universal synchronous/asynchronous receivers/transmitters that communicate at speeds of
up to 8 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication
mode, synchronous SPI master/slave communication and single-wire half-duplex communication mode. Some
can also support smartcard communication (ISO 7816), IrDA SIR ENDEC, LIN master/slave capability and auto
baud rate feature, and have a clock domain independent of the CPU clock, which allows them to wake up the
MCU from Stop mode. The wake-up events from Stop mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
All USART interfaces can be served by the DMA controller.

Table 9. USART implementation

X: supported

DS14548 - Rev 2 page 24/146

 STM32U073x8/B/C
Functional overview

USART1 USART3
USART modes/ features
USART2 USART4

Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous SPI mode (master/slave) X X
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X -
LIN mode X -
Dual clock domain and wake-up from
X -
Stop mode
Receiver timeout interrupt X -
Modbus communication X -
Auto baud rate detection X -
Driver enable X X

3.28 Low-power universal asynchronous receiver transmitter (LPUART)

The devices embed three LPUARTs. The peripherals support asynchronous serial communication with minimum
power consumption, as well as half-duplex single wire communication and modem operations (CTS/RTS). They
allow multiprocessor communication.
The LPUARTs have a clock domain independent of the CPU clock, and can wake up the system from Stop mode
using baud rates up to 220 Kbaud. The Stop mode wake-up events are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in
Stop mode, the LPUARTs can wait for an incoming frame while having an extremely low energy consumption. To
reach higher baud rates, a higher speed clock can be used.
The LPUART interface can be served by the DMA controller.

3.29 Serial peripheral interface (SPI)

The devices contain three SPIs running at up to 32 Mbits/s in master and slave modes. It supports half-duplex,
full-duplex and simplex communications. A 3-bit prescaler gives eight master mode frequencies. The frame size is
configurable from 4 bits to 16 bits. The SPI peripherals support NSS pulse mode, TI mode and hardware CRC
calculation.
The SPI peripherals can be served by the DMA controller.

Table 10. SPI implementation

X: supported
SPI modes/ features SPI1 SPI2 SPI3

Hardware CRC calculation X X X

Rx/Tx FIFO X X X
NSS pulse mode X X X
I2S mode - - -
TI mode X X X

DS14548 - Rev 2 page 25/146

 STM32U073x8/B/C
Functional overview

3.30 Universal serial bus device (USB)

The devices embed a USB controller with full-speed USB device compliant with the USB specification version 2.0.
The internal USB PHY supports USB FS signaling, embedded DP pull-up, and also battery charging detection
according to Battery Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s)
function interface with added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up to 1 Kbyte and suspend/resume support. It requires a precise 48 MHz clock that is
generated from the internal main PLL (the clock source must use an HSE crystal oscillator) or by the internal
48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB
data stream itself (SOF signalization) which enables crystal less operation.

3.31 Debug support

3.31.1 Serial wire debug port (SW-DP)

An Arm® SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

DS14548 - Rev 2 page 26/146

 STM32U073x8/B/C
Pinouts/ballouts, pin description, and alternate functions

4 Pinouts/ballouts, pin description, and alternate functions

4.1 Pinout/ballout schematics

Figure 3. UFQFPN32 pinout

PF3-BOOT0

PA15
VSS

PB7
PB6
PB5
PB4
PB3
32
31
30
29
28
27
26
25
VDD 1 24 PA14
PC14-OSC32_IN 2 23 PA13
PC15-OSC32_OUT 3 22 PA12 [PA10]
PF2-NRST 4 21 PA11 [PA9]
VDDA/VREF+ 5
UFQFPN32 20 PA10
PA0-CK_IN 6 19 PA9
PA1 7 18 PA8
PA2 8 17 VDDUSB
10

12
13
14
15
16
11
9

PB0
PB1
VSS

DT71261V1
PA3
PA4
PA5
PA6
PA7

1. The above figure shows the package top view.

Figure 4. WLCSP42 ballout

1 2 3 4 5 6 7 8 9 10 11 12

A NC VSS NC PA15 NC PB5 NC PB7 NC PB8 NC VSS

B VDDUSB NC PA13 NC PB3 NC PB6 NC VBAT NC VDD NC

C NC PA12 NC PA9 NC PB4 NC PF3 NC PC15 NC PC14

D PA11 NC PA8 NC PA14 NC PC13 NC PF1 NC PF0 NC

E NC PA10 NC PA5 NC PA3 NC PA1 NC VSSA/VREF- NC PF2

F VSS NC PB1 NC PB0 NC PA7 NC PA0 NC VDDA/VREF+ NC

DT71292V1

G NC VDD NC PB10 NC PB2 NC PA6 NC PA4 NC PA2

1. The above figure shows the package top view.

DS14548 - Rev 2 page 27/146

 STM32U073x8/B/C
Pinouts/ballouts, pin description, and alternate functions

Figure 5. LQFP48 pinout

PF3-BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDDUSB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12 [PA10]
PF0-OSC_IN 5 32 PA11 [PA9]
PF1-OSC_OUT 6 31 PA10
PF2-NRST 7
LQFP48 30 PA9
VSSA/VREF- 8 29 PA8
VDDA/VREF+ 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24

DT71263V1
PB0
PB1
PB2

VSS
PB10

VDD
PA3
PA4
PA5
PA6
PA7

PB11

1. The above figure shows the package top view.

Figure 6. UFQFPN48 pinout

PF3-BOOT0

PA15
PA14
VDD
VSS
PB9
PB8

PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37

VBAT 1 36 VDDUSB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12 [PA10]
PF0-OSC_IN 5 32 PA11 [PA9]
PF1-OSC_OUT 6 31 PA10
PF2-NRST 7
UFQFPN48 30 PA9
VSSA/VREF- 8 29 PA8
VDDA/VREF+ 9 28 PB15
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10

VSS
VDD
PA3
PA4
PA5
PA6
PA7

PB11

DT71264V1

1. The above figure shows the package top view.

DS14548 - Rev 2 page 28/146

 STM32U073x8/B/C
Pinouts/ballouts, pin description, and alternate functions

Figure 7. LQFP64 pinout

PF3-BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB9
PB8

PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12 [PA10]
PF0-OSC_IN 5 44 PA11 [PA9]
PF1-OSC_OUT 6 43 PA10
PF2-NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD

PC4
PC5
PB0
PB1
PB2

VSS
PB10

VDD
PA3

PA4
PA5
PA6
PA7

PB11

DT71265V1
1. The above figure shows the package top view.

Figure 8. UFBGA64 ballout

1 2 3 4 5 6 7 8

PC14-
A PC13 PB9 PB4 PB3 PA15 PA14 PA13
OSC32_IN

PC15-
B VBAT PB8 PF3-BOOT0 PD2 PC11 PC10 PA12 [PA10]
OSC32_OUT

C PF0-OSC_IN VSS PB7 PB5 PC12 PA10 PA9 PA11 [PA9]

PF1-
D VDD PB6 VSS VSS VSS PA8 PC9
OSC_OUT

E PF2-NRST PC1 PC0 VDD VDDUSB VDD PC7 PC8

F VSSA/VREF- PC2 PA2 PA5 PB0 PC6 PB15 PB14

G PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13

DT71266V1

H VDDA/VREF+ PA1 PA4 PA7 PC4 PC5 PB11 PB12

1. The above figure shows the package top view.

DS14548 - Rev 2 page 29/146

 STM32U073x8/B/C
Pinouts/ballouts, pin description, and alternate functions

Figure 9. LQFP80 pinout

PF3-BOOT0

PC12

PC10
PC11

PA15
PA14
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VSS 1 60 VDDUSB
VDD 2 59 VSS
VBAT 3 58 PA13
PC13 4 57 PA12 [PA10]
PC14-OSC32_IN 5 56 PA11 [PA9]
PC15-OSC32_OUT 6 55 PA10
PF0-OSC_IN 7 54 PA9
PF1-OSC_OUT 8 53 PA8
PF2-NRST 9 52 PC9
PC0 10 51 PC8
PC1 11
LQFP80 50 PC7
PC2 12 49 PC6
PC3 13 48 PD13
VSSA/VREF- 14 47 PD12
VREF+ 15 46 PD11
VDDA 16 45 PD10
PA0 17 44 PD9
PA1 18 43 PD8
PA2 19 42 PB15
PA3 20 41 PB14
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
VDD

PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PB10

VSS
VDD
PB12
PB13
PA4
PA5
PA6
PA7

PB11

DT71267V2
1. The above figure shows the package top view.

Figure 10. UFBGA81 ballout

1 2 3 4 5 6 7 8 9

A PB8 PF3-BOOT0 PB4 PB5 PD4 PD0 PC12 PC10 PA15

B VBAT PB9 PB7 PB6 PD6 PD1 PC11 PA14 PA13

PC15- PC14-
C PE3 PB3 PD5 PD2 VDDUSB PA12 [PA10] PA11 [PA9]
OSC32_OUT OSC32_IN

PF1-
D PF0-OSC_IN VDD VSS PD3 VSS PA9 PA10 PC9
OSC_OUT

E PC0 PF2-NRST PC13 PA1 PC8 PC7 PA8 PC6 PD13

F PC1 PC2 PA0 VSS PB0 VSS PB15 PD11 PD12

G PC3 VSSA/VREF- VDD PC5 PE7 PE8 VDD PD9 PD10

H VREF+ PA2 PA5 PA7 PB1 PE9 PB11 PB13 PD8

DT71293V1

J VDDA PA3 PA4 PA6 PC4 PB2 PB10 PB12 PB14

1. The above figure shows the package top view.

DS14548 - Rev 2 page 30/146

 4.2 Pin description
DS14548 - Rev 2

Table 11. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type
I/O Input /output pin
FT 5V-tolerant I/O
TT 3.6V-tolerant I/O
Bidirectional reset pin with embedded weak
RST
pull-up resistor
Options for TT and FT I/Os
I/O structure
I/O with analog switch function supplied by
_a
VDDA

_f I2C Fm+ capable I/O

_l I/O with LCD function supplied by VLCD

_u I/O with USB function, supplied by VDDUSB

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
Notes
reset.

Pinouts/ballouts, pin description, and alternate functions

Alternate functions Functions selected through GPIOx_AFR registers
Pin functions
Additional functions Functions directly selected/enabled through peripheral registers

Table 12. STM32U073x8/B/C pin/ball definition

Pin Number

I/O structure
Pin type
UFQFPN32

UFQFPN48
WLCSP42

UFBGA64

UFBGA81

Pin name (function

LQFP48

LQFP64

LQFP80

Note Alternate functions Additional functions

after reset)

STM32U073x8/B/C
- - - - - - - C3 PE3 I/O FT TIM3_CH1, EVENTOUT -

- B9 1 1 1 B2 3 B1 VBAT S - - -

(1)(2) WKUP2, TAMP_IN1,

- D7 2 2 2 A2 4 E3 PC13 I/O FT LPTIM1_CH3, LPTIM3_CH3, EVENTOUT
RTC_TS/RTC_OUT1
page 31/146

2 C12 3 3 3 A1 5 C2 PC14-OSC32_IN I/O FT (1)(2) EVENTOUT OSC32_IN

 DS14548 - Rev 2

Pin Number

I/O structure
Pin type
UFQFPN32

UFQFPN48
WLCSP42

UFBGA64

UFBGA81
Pin name (function

LQFP48

LQFP64

LQFP80
Note Alternate functions Additional functions
after reset)

(1)(2) OSC32_OUT,
3 C10 4 4 4 B1 6 C1 PC15-OSC32_OUT I/O FT OSC32_EN, OSC_EN, EVENTOUT
OSC32_EN

- D11 5 5 5 C1 7 D2 PF0-OSC_IN I/O FT EVENTOUT OSC_IN

- D9 6 6 6 D1 8 D1 PF1-OSC_OUT I/O FT OSC_EN, EVENTOUT OSC_OUT

4 E12 7 7 7 E1 9 E2 PF2-NRST I/O RST MCO NRST

LPTIM1_IN1, I2C4_SCL, I2C3_SCL, LPUART1_RX,

- - - - 8 E3 10 E1 PC0 I/O FT_fla LPUART2_TX, LCD_SEG18, LCD_BIAS1, ADC1_IN0
LPTIM2_IN1, EVENTOUT

LPTIM1_CH1, I2C4_SDA, I2C3_SDA,

- - - - 9 E2 11 F1 PC1 I/O FT_fla LPUART1_TX, LPUART2_RX, LCD_SEG19, ADC1_IN1
LCD_BIAS2, EVENTOUT

MCO2, LPTIM1_IN2, SPI2_MISO, LCD_SEG20,

- - - - 10 F2 12 F2 PC2 I/O FT_la ADC1_IN2
LCD_BIAS3, EVENTOUT

LPTIM1_ETR, LPTIM3_CH1, SPI2_MOSI,

- - - - 11 G1 13 G1 PC3 I/O FT_la USART4_CK, LCD_VLCD, LPTIM2_ETR, ADC1_IN3
EVENTOUT

- E10 8 8 12 F1 14 G2 VSSA/VREF- S - - -

- - - - - - 15 H1 VREF+ S - - VREFBUF_OUT

- - - - - - 16 J1 VDDA S - - -

5 F11 9 9 13 H1 - - VDDA/VREF+ S - - -

Pinouts/ballouts, pin description, and alternate functions

OPAMP1_VINP,
TIM2_CH1, USART2_CTS, USART4_TX,
COMP1_INM3,
- F9 10 10 14 G2 17 F3 PA0 I/O FT_la LCD_SEG42, COMP1_OUT, TIM2_ETR,
ADC1_IN4, WKUP1,
EVENTOUT
TAMP_IN2

OPAMP1_VINP,
TIM2_CH1, USART2_CTS, USART4_TX,
COMP1_INM3,
6 - - - - - - - PA0-CK_IN I/O FT_la LCD_SEG42, COMP1_OUT, TIM2_ETR,
ADC1_IN4, CK_IN,
EVENTOUT
WKUP1, TAMP_IN2

OPAMP1_VINM,
TIM2_CH2, LPTIM1_CH2, SPI1_SCK, SPI2_SCK,
COMP1_INP3,
7 E8 11 11 15 H2 18 E4 PA1 I/O FT_la USART2_RTS/USART2_DE, USART4_RX,
ADC1_IN5, WKUP3,
LCD_SEG0, TIM15_CH1N, EVENTOUT
TAMP_IN5

STM32U073x8/B/C
TIM2_CH3, USART2_TX, LPUART1_TX, COMP2_INM3,
8 G12 12 12 16 F3 19 H2 PA2 I/O FT_la LCD_SEG1, COMP2_OUT, TIM15_CH1, ADC1_IN6, WKUP4/
EVENTOUT LSCO

OPAMP1_VOUT,
TIM2_CH4, USART2_RX, LPUART1_RX,
9 E6 13 13 17 G3 20 J2 PA3 I/O TT_la COMP2_INP3,
LCD_SEG2, TIM15_CH2, EVENTOUT
ADC1_IN7

- - - - 18 C2 21 - VSS S - - -
page 32/146

- - - - 19 D2 22 G3 VDD S - - -
 DS14548 - Rev 2

Pin Number

I/O structure
Pin type
UFQFPN32

UFQFPN48
WLCSP42

UFBGA64

UFBGA81
Pin name (function

LQFP48

LQFP64

LQFP80
Note Alternate functions Additional functions
after reset)

COMP1_INM4,
SPI1_NSS, SPI3_NSS, USART2_CK, LPUART3_TX,
10 G10 14 14 20 H3 23 J3 PA4 I/O TT_la COMP2_INM5,
LCD_SEG43, LPTIM2_CH1, EVENTOUT
ADC1_IN8, DAC1_OUT1

TIM2_CH1, TIM2_ETR, SPI1_SCK, USART3_TX, COMP1_INM4,

11 E4 15 15 21 F4 24 H3 PA5 I/O FT_la LPUART3_RX, LCD_SEG44, LPTIM2_ETR, COMP2_INM5,
EVENTOUT ADC1_IN9

TIM1_BKIN, TIM3_CH1, I2C2_SDA, I2C3_SDA,

SPI1_MISO, COMP1_OUT, USART3_CTS,
12 G8 16 16 22 G4 25 J4 PA6 I/O FT_fla ADC1_IN10
LPUART1_CTS, TSC_G5_IO1, LCD_SEG3,
TIM16_CH1, EVENTOUT

TIM1_CH1N, TIM3_CH2, I2C2_SCL, I2C3_SCL,

13 F7 17 17 23 H4 26 H4 PA7 I/O FT_fla SPI1_MOSI, USART3_RX, LCD_SEG4, ADC1_IN14
COMP2_OUT, LPTIM2_CH2, EVENTOUT

USART3_TX, LPUART3_TX, LCD_SEG22, COMP1_INM1,

- - - - 24 H5 27 J5 PC4 I/O FT_la
EVENTOUT ADC1_IN15

COMP1_INP1,
LPTIM3_CH3, USART3_RX, LPUART3_RX,
- - - - 25 H6 28 G4 PC5 I/O FT_la ADC1_IN16, WKUP5,
LCD_SEG23, EVENTOUT
TAMP_IN4

TIM1_CH2N, TIM3_CH3, LPTIM3_CH1, SPI1_NSS,

14 F5 18 18 26 F5 29 F5 PB0 I/O FT_la USART3_CK, LPUART2_CTS, TSC_G5_IO2, ADC1_IN17
LCD_SEG5, COMP1_OUT, EVENTOUT

TIM1_CH3N, TIM3_CH4, LPTIM3_CH2,

USART3_RTS/USART3_DE, LPUART1_RTS_DE, COMP1_INM2,
15 F3 19 19 27 G5 30 H5 PB1 I/O FT_la

Pinouts/ballouts, pin description, and alternate functions

TSC_SYNC, LPUART2_RTS_DE, LCD_SEG6, ADC1_IN18
LPTIM2_IN1, EVENTOUT

COMP1_INP2,
- G6 20 20 28 G6 31 J6 PB2 I/O FT_la RTC_OUT2, LPTIM1_CH1, LCD_VLCD, EVENTOUT
RTC_OUT2

- - - - - - 32 G5 PE7 I/O FT_l TIM1_ETR, LCD_SEG45, EVENTOUT -

- - - - - - 33 G6 PE8 I/O FT_l TIM1_CH1N, LCD_SEG46, EVENTOUT -

TIM1_CH1, LPTIM1_CH3, LCD_SEG47,

- - - - - - 34 H6 PE9 I/O FT_l -
EVENTOUT

TIM2_CH3, LPTIM3_CH1, I2C4_SCL, I2C2_SCL,

SPI2_SCK, USART3_TX, LPUART1_RX,
- G4 21 21 29 G7 35 J7 PB10 I/O FT_fl -
TSC_G5_IO3, LPUART2_RX, LCD_SEG10,

STM32U073x8/B/C
COMP1_OUT, EVENTOUT

TIM2_CH4, I2C4_SDA, I2C2_SDA, USART3_RX,

- - 22 22 30 H7 36 H7 PB11 I/O FT_fl LPUART1_TX, TSC_G5_IO4, LPUART2_TX, -
LCD_SEG11, COMP2_OUT, EVENTOUT

16 F1 23 23 31 D6 37 D4 VSS S - - -

17 G2 24 24 32 E6 38 D3 VDD S - - -
page 33/146

TIM1_BKIN, SPI2_NSS, USART3_CK,

- - 25 25 33 H8 39 J8 PB12 I/O FT_l LPUART1_RTS_DE, TSC_G1_IO1, LCD_SEG12, -
TIM15_BKIN, EVENTOUT
 DS14548 - Rev 2

Pin Number

I/O structure
Pin type
UFQFPN32

UFQFPN48
WLCSP42

UFBGA64

UFBGA81
Pin name (function

LQFP48

LQFP64

LQFP80
Note Alternate functions Additional functions
after reset)

TIM1_CH1N, LPTIM3_IN1, I2C2_SCL, SPI2_SCK,

- - 26 26 34 G8 40 H8 PB13 I/O FT_fl USART3_CTS, LPUART1_CTS, TSC_G1_IO2, -
LCD_SEG13, TIM15_CH1N, EVENTOUT

TIM1_CH2N, LPTIM3_ETR, I2C2_SDA, SPI2_MISO,

- - 27 27 35 F8 41 J9 PB14 I/O FT_fl USART3_RTS/USART3_DE, TSC_G1_IO3, -
LCD_SEG14, TIM15_CH1, EVENTOUT

RTC_REFIN, TIM1_CH3N, SPI2_MOSI,

- - 28 28 36 F7 42 F7 PB15 I/O FT_l TSC_G1_IO4, LCD_SEG15, TIM15_CH2, WKUP7, TAMP_IN3
EVENTOUT

USART3_TX, LPUART3_TX, LCD_SEG28,

- - - - - - 43 H9 PD8 I/O FT_l -
EVENTOUT

LPTIM3_IN1, USART3_RX, LPUART3_RX,

- - - - - - 44 G8 PD9 I/O FT_l -
LCD_SEG29, EVENTOUT

LPTIM3_ETR, USART3_CK, TSC_G6_IO1,

- - - - - - 45 G9 PD10 I/O FT_la COMP2_INP4
LCD_SEG30, LPTIM2_CH2, EVENTOUT

USART3_CTS, LPUART3_CTS, TSC_G6_IO2,

- - - - - - 46 F8 PD11 I/O FT_l -
LCD_SEG31, LPTIM2_ETR, EVENTOUT

I2C4_SCL, USART3_RTS/USART3_DE,
- - - - - - 47 F9 PD12 I/O FT_fl LPUART3_RTS_DE, TSC_G6_IO3, LCD_SEG32, -
LPTIM2_IN1, EVENTOUT

I2C4_SDA, TSC_G6_IO4, LCD_SEG33,

- - - - - - 48 E9 PD13 I/O FT_fl -
LPTIM2_CH1, EVENTOUT

Pinouts/ballouts, pin description, and alternate functions

TIM3_CH1, LPUART2_TX, TSC_G4_IO1,
- - - - 37 F6 49 E8 PC6 I/O FT_la COMP1_INP5
LCD_SEG24, EVENTOUT

TIM3_CH2, LPTIM3_CH4, LPUART2_RX,

- - - - 38 E7 50 E6 PC7 I/O FT_l TSC_G4_IO2, LCD_SEG25, LPTIM2_CH2, -
EVENTOUT

TIM3_CH3, LPTIM3_CH1, TSC_G4_IO3,

- - - - 39 E8 51 E5 PC8 I/O FT_l -
LCD_SEG26, EVENTOUT

TIM3_CH4, LPTIM3_CH2, TSC_G4_IO4, USB_NOE,

- - - - 40 D8 52 D9 PC9 I/O FT_l -
LCD_SEG27, EVENTOUT

MCO, TIM1_CH1, MCO2, USART1_CK,

18 D3 29 29 41 D7 53 E7 PA8 I/O FT_l TSC_G7_IO1, LCD_COM0, LPTIM2_CH1, -

STM32U073x8/B/C
EVENTOUT

MCO, TIM1_CH2, I2C1_SCL, I2C2_SCL,

19 C4 30 30 42 C7 54 D7 PA9 I/O FT_fla USART1_TX, TSC_G7_IO2, LCD_COM1, COMP1_INP4
TIM15_BKIN, EVENTOUT

TIM1_CH3, MCO2, I2C1_SDA, I2C2_SDA,

20 E2 31 31 43 C6 55 D8 PA10 I/O FT_fl SPI2_NSS, USART1_RX, TSC_G7_IO3, -
CRS_SYNC, LCD_COM2, EVENTOUT
page 34/146

(3) TIM1_CH4, TIM1_BKIN2, SPI1_MISO, SPI2_MISO,

21 D1 32 32 44 C8 56 C9 PA11 [PA9] I/O FT_u USB_DM
USART1_CTS, COMP1_OUT, EVENTOUT
 DS14548 - Rev 2

Pin Number

I/O structure
Pin type
UFQFPN32

UFQFPN48
WLCSP42

UFBGA64

UFBGA81
Pin name (function

LQFP48

LQFP64

LQFP80
Note Alternate functions Additional functions
after reset)

(3) TIM1_ETR, SPI1_MOSI, SPI2_MOSI,

22 C2 33 33 45 B8 57 C8 PA12 [PA10] I/O FT_u USB_DP
USART1_RTS/USART1_DE, EVENTOUT

(4) SWDIO, IR_OUT, TSC_G7_IO4, USB_NOE,

23 B3 34 34 46 A8 58 B9 PA13 (SWDIO) I/O FT_l -
LCD_SEG40, EVENTOUT

- A2 35 35 47 D5 59 D6 VSS S - - -

- B1 36 36 48 E5 60 C7 VDDUSB S - - -

(4) SWCLK, LPTIM1_CH1, TSC_G3_IO4, LCD_SEG41,

24 D5 37 37 49 A7 61 B8 PA14 (SWCLK) I/O FT_l -
EVENTOUT

TIM2_CH1, TIM2_ETR, USART2_RX, LPTIM3_IN2,

SPI1_NSS, SPI3_NSS, USART3_RTS/USART3_DE,
25 A4 38 38 50 A6 62 A9 PA15 I/O FT_l -
USART4_RTS/USART4_DE, TSC_G3_IO1,
LCD_SEG17, LPTIM3_CH3, EVENTOUT

LPTIM3_ETR, SPI3_SCK, USART3_TX,

- - - - 51 B7 63 A8 PC10 I/O FT_l USART4_TX, TSC_G3_IO2, LCD_COM4/ -
LCD_SEG28/LCD_SEG48, EVENTOUT

LPTIM3_IN1, SPI3_MISO, USART3_RX,

- - - - 52 B6 64 B7 PC11 I/O FT_l USART4_RX, TSC_G3_IO3, LCD_COM5/ -
LCD_SEG29/LCD_SEG49, EVENTOUT

LPTIM3_CH3, SPI3_MOSI, USART3_CK,

- - - - 53 C5 65 A7 PC12 I/O FT_l USART4_CK, LCD_COM6/LCD_SEG30/ -
LCD_SEG50, EVENTOUT

- - - - - - 66 A6 PD0 I/O FT_l SPI2_NSS, LCD_SEG34, EVENTOUT -

Pinouts/ballouts, pin description, and alternate functions

- - - - - - 67 B6 PD1 I/O FT_l LPTIM1_CH4, SPI2_SCK, LCD_SEG35, EVENTOUT -

TIM3_ETR, USART3_RTS/USART3_DE,
- - - - 54 B5 68 C6 PD2 I/O FT_l TSC_SYNC, LCD_COM7/LCD_SEG31/LCD_SEG51, -
EVENTOUT

SPI2_MISO, USART2_CTS, LCD_SEG36,

- - - - - - 69 D5 PD3 I/O FT_l -
EVENTOUT

LPTIM1_CH3, SPI2_MOSI, USART2_RTS/

- - - - - - 70 A5 PD4 I/O FT_l -
USART2_DE, LCD_SEG37, EVENTOUT

- - - - - - 71 C5 PD5 I/O FT_l USART2_TX, LCD_SEG38, EVENTOUT -

- - - - - - 72 B5 PD6 I/O FT_l USART2_RX, LCD_SEG39, EVENTOUT -

STM32U073x8/B/C
TIM2_CH2, LPTIM1_CH3, I2C2_SCL, I2C3_SCL,
26 B5 39 39 55 A5 73 C4 PB3 I/O FT_fla SPI1_SCK, SPI3_SCK, USART1_RTS/USART1_DE, COMP2_INM2
LCD_SEG7, EVENTOUT

LPTIM1_CH4, TIM3_CH1, I2C2_SDA, I2C3_SDA,

SPI1_MISO, SPI3_MISO, USART1_CTS,
27 C6 40 40 56 A4 74 A3 PB4 I/O FT_fla COMP2_INP1
LPUART3_RTS_DE, TSC_G2_IO1, LCD_SEG8,
EVENTOUT
page 35/146
 DS14548 - Rev 2

Pin Number

I/O structure
Pin type
UFQFPN32

UFQFPN48
WLCSP42

UFBGA64

UFBGA81
Pin name (function

LQFP48

LQFP64

LQFP80
Note Alternate functions Additional functions
after reset)

LPTIM1_IN1, TIM3_CH2, SPI1_MOSI, SPI3_MOSI,

USART1_CK, LPUART3_CTS, TSC_G2_IO2,
28 A6 41 41 57 C4 75 A4 PB5 I/O FT_l -
LCD_SEG9, COMP2_OUT, TIM16_BKIN,
EVENTOUT

- - - - - - - F4 VSS S - -

LPTIM1_ETR, I2C4_SCL, I2C1_SCL, I2C2_SCL,

29 B7 42 42 58 D3 76 B4 PB6 I/O FT_fa LPUART3_TX, USART1_TX, TSC_G2_IO3, COMP2_INP2
LPUART2_TX, TIM16_CH1N, EVENTOUT

LPTIM1_IN2, I2C4_SDA, I2C1_SDA, I2C2_SDA,

LPUART3_RX, USART1_RX, USART4_CTS,
30 A8 43 43 59 C3 77 B3 PB7 I/O FT_fla COMP2_INM1, PVD_IN
TSC_G2_IO4, LPUART2_RX, LCD_SEG21,
EVENTOUT

PF3-BOOT0
31 C8 44 44 60 B4 78 A2 I/O FT EVENTOUT -
(BOOT0)

LPTIM1_IN2, LPTIM3_IN2, I2C2_SCL, I2C1_SCL,

- A10 45 45 61 B3 79 A1 PB8 I/O FT_fl USART3_TX, LCD_SEG16, TIM16_CH1, -
EVENTOUT

IR_OUT, LPTIM3_CH4, I2C2_SDA, I2C1_SDA,

- - 46 46 62 A3 80 B2 PB9 I/O FT_fl SPI2_NSS, USART3_RX, LCD_COM3, -
LPTIM1_CH4, EVENTOUT

32 A12 47 47 63 D4 1 F6 VSS S - - -

1 B11 48 48 64 E4 2 G7 VDD S - - -

Pinouts/ballouts, pin description, and alternate functions

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is
limited:
• The speed should not exceed 2 MHz with a maximum load of 30 pF
• These GPIOs must not be used as current sources (for example to drive a LED).
2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon
system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0503 reference manual.
3. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.
4. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

4.3 Alternate functions

STM32U073x8/B/C
Table 13. Port A alternate functions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPTIM1/ I2C4/ I2C2/4/ COMP1/ CRS/

I2C1/2/3/4/ LPUART1/2/3/ COMP1/2/LC LPTIM1/2/3/
page 36/146

SYS_AF SYS_AF/ LPTIM1/3/ SYS_AF/ I2C2/SPI1/2 LPUART3/ USART1/2/3 TSC LPUART2/U LCD - EVENTOUT
LPTIM3 USART4 D TIM2/15/16
TIM1/2 TIM1/2/3 USART2 SPI2/3 SB

Port PA0 - TIM2_CH1 - - - - - USART2_CTS USART4_TX - - LCD_SEG42 COMP1_OUT - TIM2_ETR EVENTOUT

A
 DS14548 - Rev 2

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPTIM1/ I2C4/ I2C2/4/ COMP1/ CRS/

I2C1/2/3/4/ LPUART1/2/3/ COMP1/2/LC LPTIM1/2/3/
SYS_AF SYS_AF/ LPTIM1/3/ SYS_AF/ I2C2/SPI1/2 LPUART3/ USART1/2/3 TSC LPUART2/U LCD - EVENTOUT
LPTIM3 USART4 D TIM2/15/16
TIM1/2 TIM1/2/3 USART2 SPI2/3 SB

USART2_RTS/
PA1 - TIM2_CH2 LPTIM1_CH2 - - SPI1_SCK SPI2_SCK USART4_RX - - LCD_SEG0 - - TIM15_CH1N EVENTOUT
USART2_DE

PA2 - TIM2_CH3 - - - - - USART2_TX LPUART1_TX - - LCD_SEG1 COMP2_OUT - TIM15_CH1 EVENTOUT

PA3 - TIM2_CH4 - - - - - USART2_RX LPUART1_RX - - LCD_SEG2 - - TIM15_CH2 EVENTOUT

PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK LPUART3_TX - - LCD_SEG43 - - LPTIM2_CH1 EVENTOUT

PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - USART3_TX LPUART3_RX - - LCD_SEG44 - - LPTIM2_ETR EVENTOUT

PA6 - TIM1_BKIN TIM3_CH1 I2C2_SDA I2C3_SDA SPI1_MISO COMP1_OUT USART3_CTS LPUART1_CTS TSC_G5_IO1 - LCD_SEG3 - - TIM16_CH1 EVENTOUT

PA7 - TIM1_CH1N TIM3_CH2 I2C2_SCL I2C3_SCL SPI1_MOSI - USART3_RX - - - LCD_SEG4 COMP2_OUT - LPTIM2_CH2 EVENTOUT

Port PA8 MCO TIM1_CH1 - MCO2 - - - USART1_CK - TSC_G7_IO1 - LCD_COM0 - - LPTIM2_CH1 EVENTOUT
A
PA9 MCO TIM1_CH2 - - I2C1_SCL I2C2_SCL - USART1_TX - TSC_G7_IO2 - LCD_COM1 - - TIM15_BKIN EVENTOUT

PA10 - TIM1_CH3 - MCO2 I2C1_SDA I2C2_SDA SPI2_NSS USART1_RX - TSC_G7_IO3 CRS_SYNC LCD_COM2 - - - EVENTOUT

PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO SPI2_MISO USART1_CTS - - - - COMP1_OUT - - EVENTOUT

USART1_RTS/
PA12 - TIM1_ETR - - - SPI1_MOSI SPI2_MOSI - - - - - - - EVENTOUT
USART1_DE

PA13 SWDIO IR_OUT - - - - - - - TSC_G7_IO4 USB_NOE LCD_SEG40 - - - EVENTOUT

PA14 SWCLK LPTIM1_CH1 - - - - - - - TSC_G3_IO4 - LCD_SEG41 - - - EVENTOUT

USART3_RTS/ USART4_RTS/
PA15 - TIM2_CH1 TIM2_ETR USART2_RX LPTIM3_IN2 SPI1_NSS SPI3_NSS TSC_G3_IO1 - LCD_SEG17 - - LPTIM3_CH3 EVENTOUT
USART3_DE USART4_DE

Table 14. Port B alternate functions

Pinouts/ballouts, pin description, and alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPTIM1/ I2C4/ I2C2/4/ COMP1/

I2C1/2/3/4/ I2C2/ LPUART1/2/3/ CRS/ COMP1/2/LC LPTIM1/2/3/
SYS_AF SYS_AF/ LPTIM1/3/ SYS_AF/ LPUART3/ USART1/2/3 TSC LCD - EVENTOUT
LPTIM3 SPI1/2 USART4 LPUART2/USB D TIM2/15/16
TIM1/2 TIM1/2/3 USART2 SPI2/3

PB0 - TIM1_CH2N TIM3_CH3 - LPTIM3_CH1 SPI1_NSS - USART3_CK LPUART2_CTS TSC_G5_IO2 - LCD_SEG5 COMP1_OUT - - EVENTOUT

USART3_RTS/
PB1 - TIM1_CH3N TIM3_CH4 - LPTIM3_CH2 - - LPUART1_RTS_DE TSC_SYNC LPUART2_RTS_DE LCD_SEG6 - - LPTIM2_IN1 EVENTOUT
USART3_DE

PB2 RTC_OUT2 LPTIM1_CH1 - - - - - - - - - LCD_VLCD - - - EVENTOUT

USART1_RTS/
PB3 - TIM2_CH2 LPTIM1_CH3 I2C2_SCL I2C3_SCL SPI1_SCK SPI3_SCK - - - LCD_SEG7 - - EVENTOUT
USART1_DE

PB4 - LPTIM1_CH4 TIM3_CH1 I2C2_SDA I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS LPUART3_RTS_DE TSC_G2_IO1 - LCD_SEG8 - - EVENTOUT

STM32U073x8/B/C
Port PB5 - LPTIM1_IN1 TIM3_CH2 - - SPI1_MOSI SPI3_MOSI USART1_CK LPUART3_CTS TSC_G2_IO2 - LCD_SEG9 COMP2_OUT - TIM16_BKIN EVENTOUT
B
PB6 - LPTIM1_ETR - I2C4_SCL I2C1_SCL I2C2_SCL LPUART3_TX USART1_TX - TSC_G2_IO3 LPUART2_TX - - - TIM16_CH1N EVENTOUT

PB7 - LPTIM1_IN2 - I2C4_SDA I2C1_SDA I2C2_SDA LPUART3_RX USART1_RX USART4_CTS TSC_G2_IO4 LPUART2_RX LCD_SEG21 - - - EVENTOUT

PB8 - LPTIM1_IN2 LPTIM3_IN2 I2C2_SCL I2C1_SCL - - USART3_TX - - - LCD_SEG16 - - TIM16_CH1 EVENTOUT

PB9 - IR_OUT LPTIM3_CH4 I2C2_SDA I2C1_SDA SPI2_NSS - USART3_RX - - - LCD_COM3 - - LPTIM1_CH4 EVENTOUT
page 37/146

PB10 - TIM2_CH3 LPTIM3_CH1 I2C4_SCL I2C2_SCL SPI2_SCK - USART3_TX LPUART1_RX TSC_G5_IO3 LPUART2_RX LCD_SEG10 COMP1_OUT - - EVENTOUT

PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA - - USART3_RX LPUART1_TX TSC_G5_IO4 LPUART2_TX LCD_SEG11 COMP2_OUT - - EVENTOUT
 DS14548 - Rev 2

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPTIM1/ I2C4/ I2C2/4/ COMP1/

I2C1/2/3/4/ I2C2/ LPUART1/2/3/ CRS/ COMP1/2/LC LPTIM1/2/3/
SYS_AF SYS_AF/ LPTIM1/3/ SYS_AF/ LPUART3/ USART1/2/3 TSC LCD - EVENTOUT
LPTIM3 SPI1/2 USART4 LPUART2/USB D TIM2/15/16
TIM1/2 TIM1/2/3 USART2 SPI2/3

PB12 - TIM1_BKIN - - - SPI2_NSS - USART3_CK LPUART1_RTS_DE TSC_G1_IO1 - LCD_SEG12 - - TIM15_BKIN EVENTOUT

PB13 - TIM1_CH1N LPTIM3_IN1 - I2C2_SCL SPI2_SCK - USART3_CTS LPUART1_CTS TSC_G1_IO2 - LCD_SEG13 - - TIM15_CH1N EVENTOUT
Port
B USART3_RTS/
PB14 - TIM1_CH2N LPTIM3_ETR - I2C2_SDA SPI2_MISO - - TSC_G1_IO3 - LCD_SEG14 - - TIM15_CH1 EVENTOUT
USART3_DE

PB15 RTC_REFIN TIM1_CH3N - - - SPI2_MOSI - - - TSC_G1_IO4 - LCD_SEG15 - - TIM15_CH2 EVENTOUT

Table 15. Port C alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPTIM1/ I2C4/ I2C2/4/ COMP1/ CRS/

I2C1/2/3/4/ LPUART1/2/3/ COMP1/2/ LPTIM1/2/3/
SYS_AF SYS_AF/ LPTIM1/3/ SYS_AF/ I2C2/SPI1/2 LPUART3/ USART1/2/3 TSC LPUART2/US LCD - EVENTOUT
LPTIM3 USART4 LCD TIM2/15/16
TIM1/2 TIM1/2/3 USART2 SPI2/3 B

PC0 - LPTIM1_IN1 I2C4_SCL - I2C3_SCL - - - LPUART1_RX - LPUART2_TX LCD_SEG18 - - LPTIM2_IN1 EVENTOUT

PC1 - LPTIM1_CH1 I2C4_SDA - I2C3_SDA - - - LPUART1_TX - LPUART2_RX LCD_SEG19 - - - EVENTOUT

PC2 MCO2 LPTIM1_IN2 - - - SPI2_MISO - - - - - LCD_SEG20 - - - EVENTOUT

PC3 - LPTIM1_ETR LPTIM3_CH1 - - SPI2_MOSI - - USART4_CK - - LCD_VLCD - - LPTIM2_ETR EVENTOUT

PC4 - - - - - - - USART3_TX LPUART3_TX - - LCD_SEG22 - - - EVENTOUT

PC5 - - - - LPTIM3_CH3 - - USART3_RX LPUART3_RX - - LCD_SEG23 - - - EVENTOUT

PC6 - - TIM3_CH1 - - - - - LPUART2_TX TSC_G4_IO1 - LCD_SEG24 - - - EVENTOUT

PC7 - - TIM3_CH2 - LPTIM3_CH4 - - - LPUART2_RX TSC_G4_IO2 - LCD_SEG25 - - LPTIM2_CH2 EVENTOUT

PC8 - - TIM3_CH3 - LPTIM3_CH1 - - - - TSC_G4_IO3 - LCD_SEG26 - - - EVENTOUT

Port

Pinouts/ballouts, pin description, and alternate functions

PC9 - - TIM3_CH4 - LPTIM3_CH2 - - - - TSC_G4_IO4 USB_NOE LCD_SEG27 - - - EVENTOUT
C
LCD_COM4/
PC10 - - LPTIM3_ETR - - - SPI3_SCK USART3_TX USART4_TX TSC_G3_IO2 - LCD_SEG28/ - - - EVENTOUT
LCD_SEG48

LCD_COM5/
PC11 - - LPTIM3_IN1 - - - SPI3_MISO USART3_RX USART4_RX TSC_G3_IO3 - LCD_SEG29/ - - - EVENTOUT
LCD_SEG49

LCD_COM6/
PC12 - - - - LPTIM3_CH3 - SPI3_MOSI USART3_CK USART4_CK - - LCD_SEG30/ - - - EVENTOUT
LCD_SEG50

PC13 - - LPTIM1_CH3 - LPTIM3_CH3 - - - - - - - - - - EVENTOUT

PC14 - - - - - - - - - - - - - - - EVENTOUT

STM32U073x8/B/C
PC15 OSC32_EN OSC_EN - - - - - - - - - - - - - EVENTOUT
page 38/146
 Table 16. Port D alternate functions
DS14548 - Rev 2

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPTIM1/ I2C4/ I2C2/4/ COMP1/ CRS/

I2C1/2/3/4/ LPUART1/2/3/ COMP1/2/ LPTIM1/2/3/
SYS_AF SYS_AF/ LPTIM1/3/ SYS_AF/ I2C2/SPI1/2 LPUART3/ USART1/2/3 TSC LPUART2/ LCD - EVENTOUT
LPTIM3 USART4 LCD TIM2/15/16
TIM1/2 TIM1/2/3 USART2 SPI2/3 USB

PD0 - - - - - SPI2_NSS - - - - - LCD_SEG34 - - - EVENTOUT

PD1 - LPTIM1_CH4 - - - SPI2_SCK - - - - - LCD_SEG35 - - - EVENTOUT

LCD_COM7/
USART3_RTS/
PD2 - - TIM3_ETR - - - - - TSC_SYNC - LCD_SEG31/ - - - EVENTOUT
USART3_DE
LCD_SEG51

PD3 - - - - - SPI2_MISO - USART2_CTS - - - LCD_SEG36 - - - EVENTOUT

USART2_RTS/
PD4 - LPTIM1_CH3 - - - SPI2_MOSI - - - - LCD_SEG37 - - - EVENTOUT
USART2_DE

PD5 - - - - - - - USART2_TX - - - LCD_SEG38 - - - EVENTOUT

Port
D
PD6 - - - - - - - USART2_RX - - - LCD_SEG39 - - - EVENTOUT

PD8 - - - - - - - USART3_TX LPUART3_TX - - LCD_SEG28 - - - EVENTOUT

PD9 - - - - LPTIM3_IN1 - - USART3_RX LPUART3_RX - - LCD_SEG29 - - - EVENTOUT

PD10 - - - - LPTIM3_ETR - - USART3_CK - TSC_G6_IO1 - LCD_SEG30 - - LPTIM2_CH2 EVENTOUT

PD11 - - - - - - - USART3_CTS LPUART3_CTS TSC_G6_IO2 - LCD_SEG31 - - LPTIM2_ETR EVENTOUT

USART3_RTS/
PD12 - - - - I2C4_SCL - - LPUART3_RTS_DE TSC_G6_IO3 - LCD_SEG32 - - LPTIM2_IN1 EVENTOUT
USART3_DE

PD13 - - - - I2C4_SDA - - - - TSC_G6_IO4 - LCD_SEG33 - - LPTIM2_CH1 EVENTOUT

Table 17. Port E alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts/ballouts, pin description, and alternate functions

Port I2C2/4/ COMP1/ CRS/
LPTIM1/ I2C4/LPTIM1/3/ I2C1/2/3/4/ I2C2/ LPUART1/2/3/ COMP1/2/LC LPTIM1/2/3/
SYS_AF SYS_AF/ LPUART3/ USART1/2/3 TSC LPUART2/US LCD EVENTOUT
SYS_AF/TIM1/2 TIM1/2/3 LPTIM3 SPI1/2 USART4 D TIM2/15/16
USART2 SPI2/3 B

PE3 - - TIM3_CH1 - - - - - - - - - - - - EVENTOUT

PE7 - TIM1_ETR - - - - - - - - - LCD_SEG45 - - - EVENTOUT

Port E
PE8 - TIM1_CH1N - - - - - - - - - LCD_SEG46 - - - EVENTOUT

PE9 - TIM1_CH1 LPTIM1_CH3 - - - - - - - - LCD_SEG47 - - - EVENTOUT

Table 18. Port F alternate functions

STM32U073x8/B/C
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port LPTIM1/ I2C2/4/ COMP1/

I2C4/LPTIM1/3/ I2C1/2/3/4/ I2C2/ LPUART1/2/3/ CRS/ LPTIM1/2/3/
SYS_AF SYS_AF/ SYS_AF/ LPUART3/ USART1/2/3 TSC LCD COMP1/2/LCD EVENTOUT
TIM1/2/3 LPTIM3 SPI1/2 USART4 LPUART2/USB TIM2/15/16
TIM1/2 USART2 SPI2/3

PF0 - - - - - - - - - - - - - - - EVENTOUT

PF1 OSC_EN - - - - - - - - - - - - - - EVENTOUT

page 39/146

Port F
PF2 MCO - - - - - - - - - - - - - - -

PF3 - - - - - - - - - - - - - - - EVENTOUT
 STM32U073x8/B/C
Memory mapping

5 Memory mapping

Refer to the product line reference manual (RM0503) for details on the memory mapping as well as the boundary
addresses for all peripherals.

DS14548 - Rev 2 page 40/146

 STM32U073x8/B/C
Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction
temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an junction
temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated in the
table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and
represent the mean value plus or minus three times the standard deviation (mean ± 3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD =VDDA = 3 V. They are given only as
design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion
lot over the full temperature range, where 95% of the devices have an error less than or equal to the value
indicated (mean ± 2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

Figure 11. Pin loading conditions Figure 12. Pin input voltage

Device pin
Device pin

VIN
C = 50 pF
DT47493V1

DT47494V1

DS14548 - Rev 2 page 41/146

 STM32U073x8/B/C
Electrical characteristics

6.1.6 Power supply scheme

Figure 13. Power supply scheme

VBAT

Backup circuitry
1.55 – 3.6 V (LSE, RTC,
Backup registers)
Power
switch
VDD VCORE
n x VDD
Regulator

VDDIO1

Level shifter
OUT
Kernel logic
n x 100 nF IO (CPU, Digital
GPIOs logic
+1 x 4.7 µF IN & Memories)

n x VSS

VDDA
VDDA
VREF ADCs/
VREF+
10 nF DAC/
+1 µF OPAMPs/
100 nF+1 µF VREF-
COMPs/
VREFBUF

DT72676V2
VSSA

Caution: Each power supply pair (such as VDD/VSS, VDDA/VSSA) must be decoupled with filtering ceramic capacitors as
shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the
underside of the PCB to ensure the good functionality of the device.

DS14548 - Rev 2 page 42/146

 STM32U073x8/B/C
Electrical characteristics

6.1.7 Current consumption measurement

Figure 14. Current consumption measurement scheme

IDD_USB
VDDUSB

IDD_VBAT
VBAT

IDD
VDD

IDDA
VDDA

DT45729V1
The IDD_ALL parameters given in Table 26. Current consumption in Run and Low-power run modes, code with
data processing running from flash memory, bypass mode, ART enabled (cache ON, prefetch OFF), HSE clock
used as system clock to Table 43. Current consumption in VBAT mode represent the total MCU consumption
including the current supplying VDD, VDDA, VDDUSB, and VBAT.

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 19. Voltage characteristics, Table 20. Current
characteristics and Table 21. Thermal characteristics may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 19. Voltage characteristics

All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
Symbol Ratings Min Max Unit

VDDX - VSS External main supply voltage (including VDD, VDDA, VDDUSB, VBAT, VREF+) -0.3 4.0 V

min (VDD, VDDA, VDDUSB) + 4.0(2)

Input voltage on FT_xxx pins VSS - 0.3
(3)

VIN(1)
V
Input voltage on TT_xx pins VSS - 0.3 4.0

Input voltage on any other pins VSS - 0.3 4.0

|ΔVDDX| Variations between different VDDX power pins of the same domain - 50 mV

|VSSx-VSS| Variations between all the different ground pins(4) - 50 mV

VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V

1. VIN maximum must always be respected. Refer to Table 20. Current characteristics for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. Including VREF- pin.

DS14548 - Rev 2 page 43/146

 STM32U073x8/B/C
Electrical characteristics

Table 20. Current characteristics

Symbol Ratings Max Unit

∑IVDD Total current into sum of all VDD power lines (source)(1) 140

∑IVSS Total current out of sum of all VSS ground lines (sink) 140

IVDD(PIN) Maximum current into each VDD power pin (source) 100

IVSS(PIN) Maximum current out of each VSS ground pin (sink) 100

Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20 mA

Output current sourced by any I/O and control pin 20

Total output current sunk by sum of all I/Os and control pins(2) 100
∑IIO(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 100

IINJ(PIN)(3) Injected current on FT_xxx, TT_xx, RST -5/+0(4)

∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins) 25

1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced
between two consecutive power supply pins.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 19. Voltage characteristics for the
maximum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents
(instantaneous values).

Table 21. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150 °C

TJ Maximum junction temperature 150 °C

6.3 Operating conditions

6.3.1 General operating conditions

Table 22. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 56

MHz
fPCLK Internal APB clock frequency - 0 56

VDD Standard operating voltage - 1.71(1) 3.6

ADC or COMP used 1.62

OPAMP used 1.8
VDDA Analog supply voltage 3.6 V
ADC, OPAMP, COMP not
0
used
VBAT Backup domain supply voltage - 1.55 3.6

VDDUSB USB supply voltage USB used 3.0 3.6 V

DS14548 - Rev 2 page 44/146

 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions Min Max Unit

USB not used 0 3.6 V

TT_xx I/Os -0.3 VDDIOx + 0.3

VIN I/O input voltage Min(Min(VDD, VDDA, V
All I/Os except TT_xx pins -0.3
VDDUSB) + 3.6, 5.5)(2)(3)

Maximum power
85
Ambient temperature for suffix 6 dissipation

Low-power dissipation(4) 105

TA -40
Maximum power
125 °C
Ambient temperature for suffix 3 dissipation

Low-power dissipation(4) 130

Suffix 6 version 105

TJ Junction temperature range -40
Suffix 3 version 130

1. When RESET is released, the functionality is guaranteed down to VBOR0 min.

2. This formula has to be applied only on the power supplies related to the I/O structure described by the pin definition table. The maximum I/O
input voltage is the smallest value between Min (VDD, VDDA, VDDUSB) + 3.6 V and 5.5 V.
3. For operation with voltage higher than Min (VDD, VDDA, VDDUSB) + 0.3 V, the internal pull‑up and pull‑down resistors must be disabled.
4. In low‑power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Section 7.10: Package thermal
characteristics).

6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 23 are derived from tests performed under the ambient temperature condition
summarized in Section 6.3.1: General operating conditions.

Table 23. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate - 0 ∞

µs/V
tVDD ULPEN = 0 10 ∞
VDD fall time rate
ULPEN = 1 100 ∞ ms/V
VDDA rise time rate 0 ∞
tVDDA - µs/V
VDDA fall time rate 10 ∞

VDDUSB rise time rate - 0 ∞

tVDDUSB µs/V
VDDUSB fall time rate - 10 ∞

6.3.3 Embedded reset and power control block characteristics

The parameters given in Table 24. Embedded reset and power control block characteristics are derived from tests
performed under the ambient temperature conditions summarized in Section 6.3.1: General operating conditions.

Table 24. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

tRSTTEMPO (2) VDD rising

Reset temporization after BOR0 is detected - 250 400 μs

Rising edge 1.62 1.66 1.7

VBOR0(2) Brownout reset threshold 0 V
Falling edge 1.6 1.64 1.69
Rising edge 2.06 2.1 2.14
VBOR1 Brownout reset threshold 1 V
Falling edge 1.96 2 2.04

DS14548 - Rev 2 page 45/146

 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

Rising edge 2.26 2.31 2.35

VBOR2 Brownout reset threshold 2 V
Falling edge 2.16 2.20 2.24
Rising edge 2.56 2.61 2.66
VBOR3 Brownout reset threshold 3 V
Falling edge 2.47 2.52 2.57
Rising edge 2.85 2.90 2.95
VBOR4 Brownout reset threshold 4 V
Falling edge 2.76 2.81 2.86
Rising edge 2.1 2.15 2.19
VPVD0 Programmable voltage detector threshold 0 V
Falling edge 2 2.05 2.1
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1 V
Falling edge 2.15 2.20 2.25
Rising edge 2.41 2.46 2.51
VPVD2 PVD threshold 2 V
Falling edge 2.31 2.36 2.41
Rising edge 2.56 2.61 2.66
VPVD3 PVD threshold 3 V
Falling edge 2.47 2.52 2.57
Rising edge 2.69 2.74 2.79
VPVD4 PVD threshold 4 V
Falling edge 2.59 2.64 2.69
Rising edge 2.85 2.91 2.96
VPVD5 PVD threshold 5 V
Falling edge 2.75 2.81 2.86
Rising edge 2.92 2.98 3.04
VPVD6 PVD threshold 6 V
Falling edge 2.84 2.90 2.96
Hysteresis in continuous
- 20 -
Vhyst_BORH0 Hysteresis voltage of BORH0 mode mV
Hysteresis in other mode - 30 -
Hysteresis voltage of BORH (except BORH0)
Vhyst_BOR_PVD - - 100 - mV
and PVD
BOR (except BOR0) and PVD consumption
- - 1.1 1.6 µA
from VDD(3)
IDD (BOR_PVD)(2)
BOR(3) (except BOR0) and PVD average
- - 55 1000 nA
consumption from VDD with ENULP = 1

VPVM1 VDDUSB peripheral voltage monitoring - 1.18 1.22 1.26 V

Rising edge 1.61 1.65 1.69

VPVM3 VDDA peripheral voltage monitoring V
Falling edge 1.6 1.64 1.68
Rising edge 1.78 1.82 1.86
VPVM4 VDDA peripheral voltage monitoring V
Falling edge 1.77 1.81 1.85
Vhyst_PVM3 PVM3 hysteresis - - 10 - mV

Vhyst_PVM4 PVM4 hysteresis - - 10 - mV

IDD (PVM1)(2) PVM1 consumption from VDD - - 0.2 - µA

IDD (PVM3/PVM4)(2) PVM3 and PVM4 consumption from VDD - - 2 - µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
2. Specified by design, not tested in production.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current
characteristics tables.

DS14548 - Rev 2 page 46/146

 STM32U073x8/B/C
Electrical characteristics

6.3.4 Embedded voltage reference

The parameters given in Table 25. Embedded internal voltage reference are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Section 6.3.1: General operating
conditions.

Table 25. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage -40 °C < TA < +130 °C 1.182 1.212 1.232 V

tS_vrefint(1) ADC sampling time when reading the internal reference voltage - 4(2) - - µs

tstart_vrefint Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs

IDD(VREFINTBUF) VREFINT buffer consumption from VDD when converted by ADC - - 12.5 20(2) µA

∆VREFINT Internal reference voltage spread over the temperature range VDD = 3 V - 5 7.5(2) mV

TCoeff Temperature coefficient -40°C < TA < +130°C - 30 50(2) ppm/°C

ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm

VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V

VREFINT_DIV1 1/4 reference voltage 24 25 26

VREFINT_DIV2 1/2 reference voltage - 49 50 51 % VREFINT

VREFINT_DIV3 3/4 reference voltage 74 75 76

1. The shortest sampling time can be determined in the application by multiple iterations.
2. Specified by design, not tested in production.

Figure 15. VREFINT versus temperature

V
1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185
-40 -20 0 20 40 60 80 100 120 °C
DT40169V1

Mean Min Max

DS14548 - Rev 2 page 47/146

 6.3.5 Supply current characteristics
DS14548 - Rev 2

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device
software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 14. Current consumption measurement scheme.

Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of
wait states according to CPU clock (HCLK) frequency” available in the RM0503 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 26 to Table 43 are derived from tests performed under ambient temperature and supply voltage conditions summarized in
Section 6.3.1: General operating conditions.

STM32U073x8/B/C
Electrical characteristics
page 48/146
 Table 26. Current consumption in Run and Low-power run modes, code with data processing running from flash memory, bypass mode, ART enabled
DS14548 - Rev 2

(cache ON, prefetch OFF), HSE clock used as system clock

Conditions Typ Max(1)

Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

48 MHz 3.75 3.75 3.85 3.95 4.10 4.1 4.15 4.3 4.5 4.9
32 MHz 2.55 2.55 2.60 2.70 2.90 2.8 2.85 2.95 3.15 3.5
Range 1
24 MHz 1.95 1.95 2.05 2.10 2.30 2.15 2.2 2.3 2.5 2.85
16 MHz 1.35 1.35 1.40 1.50 1.65 1.45 1.5 1.65 1.8 2.15
16 MHz 1.10 1.15 1.20 1.25 1.40 1.25 1.25 1.35 1.5 1.85
IDD (Run) Supply current in Run mode 8 MHz 0.620 0.630 0.675 0.745 0.895 0.68 0.705 0.795 0.94 1.255
4 MHz 0.365 0.375 0.415 0.480 0.630 0.4 0.425 0.505 0.645 0.955
fHCLK = fHSE, bypass mode,
Range 2 2 MHz 0.235 0.245 0.285 0.350 0.500 0.26 0.28 0.36 0.5 0.805 mA
peripherals disabled
1 MHz 0.170 0.185 0.220 0.285 0.435 0.19 0.21 0.285 0.425 0.73
400 kHz 0.135 0.145 0.180 0.245 0.395 0.145 0.17 0.245 0.38 0.685
100 kHz 0.115 0.125 0.160 0.225 0.375 0.125 0.145 0.22 0.36 0.665
2 MHz 0.165 0.175 0.215 0.285 0.440 - - - - -

Supply current in Low-power Low-power 1 MHz 0.090 0.100 0.140 0.210 0.365 - - - - -
IDD (LPRun)
run mode run 400 kHz 0.045 0.055 0.095 0.165 0.320 - - - - -
100 kHz 0.020 0.030 0.070 0.140 0.300 - - - - -

1. Evaluated by characterization, unless otherwise specified.

STM32U073x8/B/C
Electrical characteristics
page 49/146
 Table 27. Current consumption in Run and Low-power run modes, code with data processing running from flash memory, ART enabled (cache ON,
DS14548 - Rev 2

prefetch OFF), MSI clock used as system clock

TBD stands for "to be defined".
Conditions Typ Max(1)
Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

48 MHz 3.75 3.85 3.95 4.10 4.35 4.15 4.4 4.6 4.8 5.25
32 MHz 2.55 2.65 2.70 2.80 3.00 2.8 2.95 3.1 3.35 3.75
Range 1
24 MHz 1.95 2.00 2.10 2.20 2.35 2.15 2.25 2.4 2.6 3
16 MHz 1.35 1.40 1.45 1.55 1.70 1.5 1.55 1.7 1.9 2.25
16 MHz 1.15 1.15 1.20 1.30 1.45 1.25 1.3 1.45 1.6 1.9
IDD (Run) Supply current in Run mode 8 MHz 0.610 0.630 0.675 0.745 0.900 0.67 0.715 0.805 0.95 1.275
4 MHz 0.365 0.375 0.415 0.485 0.635 0.4 0.43 0.51 0.655 0.965
fHCLK = fMSI,peripherals
Range 2 2 MHz 0.235 0.255 0.290 0.355 0.505 0.26 0.285 0.365 0.505 0.815 mA
disabled
1 MHz 0.175 0.185 0.225 0.290 0.435 0.19 0.215 0.295 0.43 0.74
400 kHz 0.135 0.145 0.180 0.245 0.395 0.145 0.17 0.245 0.38 0.69
100 kHz 0.115 0.125 0.160 0.225 0.375 0.125 0.145 0.225 0.36 0.665
2 MHz 0.160 0.175 0.215 0.285 0.445 TBD TBD TBD TBD TBD

Supply current in Low-power Low-power 1 MHz 0.100 0.100 0.140 0.210 0.375 TBD TBD TBD TBD TBD
IDD (LPRun)
run mode run 400 kHz 0.045 0.055 0.095 0.165 0.320 TBD TBD TBD TBD TBD
100 kHz 0.020 0.030 0.070 0.140 0.300 TBD TBD TBD TBD TBD

1. Evaluated by characterization, unless otherwise specified.

STM32U073x8/B/C
Electrical characteristics
page 50/146
 Table 28. Current consumption in Run and Low-power run modes, code with data processing running from flash memory, bypass mode, ART disabled
DS14548 - Rev 2

(cache ON, prefetch OFF), HSE clock used as system clock

TBD stands for "to be defined".
Conditions Typ Max(1)
Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

48 MHz 4.30 4.35 4.45 4.55 4.75 4.75 4.85 5 5.2 5.6
32 MHz 2.95 3.00 3.05 3.15 3.30 3.25 3.3 3.45 3.6 4
Range 1
24 MHz 2.65 2.65 2.70 2.80 3.00 2.9 2.95 3.1 3.3 3.65
16 MHz 1.80 1.85 2.00 2.00 2.15 2 2.05 2.15 2.35 2.7
16 MHz 1.30 1.30 1.35 1.40 1.55 1.4 1.45 1.55 1.7 2
IDD (Run) Supply current in Run mode 8 MHz 0.805 0.815 0.865 0.930 1.090 0.885 0.91 1 1.145 1.465
4 MHz 0.455 0.470 0.505 0.575 0.725 0.5 0.525 0.605 0.745 1.055
fHCLK = fHSE, bypass mode ,
Range 2 2 MHz 0.280 0.295 0.330 0.395 0.545 0.31 0.335 0.41 0.55 0.86 mA
peripherals disabled
1 MHz 0.195 0.205 0.240 0.310 0.455 0.215 0.235 0.31 0.45 0.76
400 kHz 0.145 0.155 0.200 0.255 0.405 0.155 0.18 0.255 0.39 0.7
100 kHz 0.115 0.125 0.165 0.230 0.375 0.13 0.15 0.225 0.36 0.67
2 MHz 0.220 0.235 0.275 0.340 0.500 TBD TBD TBD TBD TBD

Supply current in Low-power Low-power 1 MHz 0.115 0.125 0.165 0.240 0.395 TBD TBD TBD TBD TBD
IDD (LPRun)
run mode run 400 kHz 0.055 0.065 0.105 0.175 0.335 TBD TBD TBD TBD TBD
100 kHz 0.025 0.035 0.075 0.145 0.305 TBD TBD TBD TBD TBD

1. Evaluated by characterization, unless otherwise specified.

STM32U073x8/B/C
Electrical characteristics
page 51/146
 Table 29. Current consumption in Run and Low-power run modes, code with data processing running from flash memory, bypass mode, ART disabled
DS14548 - Rev 2

(cache ON, prefetch OFF), MSI clock used as system clock

TBD stands for "to be defined".
Conditions Typ Max(1)
Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

48 MHz 4.35 4.45 4.60 4.70 4.95 4.8 5 5.25 5.5 6

32 MHz 2.95 3.05 3.15 3.25 3.45 3.25 3.4 3.6 3.85 4.3
Range 1
24 MHz 2.65 2.70 2.80 2.90 3.10 2.9 3.05 3.25 3.45 3.9
16 MHz 1.80 1.85 1.95 2.05 2.25 2 2.1 2.25 2.45 2.85
16 MHz 1.30 1.30 1.40 1.45 1.60 1.4 1.5 1.6 1.75 2.1
IDD (Run) Supply current in Run mode 8 MHz 0.795 0.815 0.860 0.935 1.100 0.875 0.92 1 1.15 1.5
4 MHz 0.455 0.475 0.510 0.590 0.730 0.5 0.53 0.62 0.76 1.05
fHCLK = fMSI, peripherals
Range 2 2 MHz 0.280 0.295 0.335 0.400 0.550 0.31 0.34 0.42 0.56 0.87 mA
disabled
1 MHz 0.195 0.210 0.245 0.315 0.465 0.215 0.24 0.32 0.46 0.765
400 kHz 0.145 0.155 0.190 0.255 0.405 0.155 0.18 0.25 0.39 0.7
100 kHz 0.115 0.130 0.165 0.235 0.375 0.13 0.15 0.225 0.365 0.67
2 MHz 0.220 0.230 0.275 0.345 0.505 TBD TBD TBD TBD TBD

Supply current in Low-power run 1 MHz 0.115 0.135 0.175 0.240 0.400 TBD TBD TBD TBD TBD
IDD (LPRun) Low-power run
mode 400 kHz 0.055 0.065 0.105 0.175 0.335 TBD TBD TBD TBD TBD
100 kHz 0.025 0.035 0.075 0.145 0.305 TBD TBD TBD TBD TBD

1. Evaluated by characterization, unless otherwise specified.

STM32U073x8/B/C
Electrical characteristics
page 52/146
 Table 30. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, bypass mode, HSE clock used as
DS14548 - Rev 2

system clock
TBD stands for "to be defined".
Conditions Typ Max(1)
Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

48 MHz 3.45 3.45 3.50 3.60 3.80 3.8 3.85 3.95 4.1 4.5
32 MHz 2.35 2.35 2.40 2.50 2.65 2.6 2.6 2.7 2.9 3.25
Range 1
24 MHz 1.80 1.80 1.85 1.95 2.10 1.95 2 2.1 2.25 2.65
16 MHz 1.25 1.25 1.30 1.40 1.55 1.35 1.4 1.5 1.65 2
16 MHz 1.05 1.05 1.10 1.15 1.30 1.15 1.2 1.25 1.4 1.7
IDD (Run) Supply current in Run mode 8 MHz 0.580 0.595 0.630 0.700 0.845 0.64 0.665 0.745 0.88 1.2
4 MHz 0.345 0.355 0.395 0.460 0.610 0.38 0.4 0.48 0.615 0.925
fHCLK = fHSE, bypass mode ,
Range 2 2 MHz 0.225 0.235 0.275 0.340 0.485 0.25 0.27 0.35 0.485 0.79 mA
peripherals disabled
1 MHz 0.165 0.180 0.215 0.290 0.425 0.185 0.205 0.28 0.42 0.725
400 kHz 0.130 0.140 0.180 0.245 0.390 0.145 0.165 0.24 0.38 0.685
100 kHz 0.115 0.125 0.160 0.225 0.375 0.125 0.145 0.225 0.36 0.665
2 MHz 0.070 0.080 0.120 0.190 0.350 TBD TBD TBD TBD TBD

Supply current in Low-power Low-power 1 MHz 0.040 0.050 0.090 0.160 0.315 TBD TBD TBD TBD TBD
IDD (LPRun)
run mode run 400 kHz 0.020 0.030 0.070 0.145 0.295 TBD TBD TBD TBD TBD
100 kHz 0.010 0.020 0.060 0.135 0.290 TBD TBD TBD TBD TBD

1. Evaluated by characterization, unless otherwise specified.

STM32U073x8/B/C
Electrical characteristics
page 53/146
 Table 31. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, MSI clock used as system clock
DS14548 - Rev 2

TBD stands for "to be defined".

Conditions Typ Max(1)
Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

48 MHz 3.50 3.55 3.65 3.75 3.95 3.85 3.95 4.15 4.35 4.8
32 MHz 2.35 2.40 2.50 2.60 2.75 2.6 2.7 2.85 3.05 3.45
Range 1
24 MHz 1.80 1.85 1.90 2.00 2.20 2 2.05 2.2 2.4 2.8
16 MHz 1.25 1.30 1.35 1.40 1.60 1.35 1.45 1.55 1.75 2.1
16 MHz 1.05 1.10 1.15 1.20 1.35 1.15 1.2 1.3 1.5 1.8
IDD (Run) Supply current in Run mode 8 MHz 0.575 0.590 0.630 0.695 0.850 0.63 0.66 0.745 0.89 1.2
4 MHz 0.345 0.355 0.395 0.460 0.610 0.375 0.405 0.485 0.625 0.935
fHCLK = fMSI, peripherals
Range 2 2 MHz 0.225 0.240 0.275 0.345 0.490 0.25 0.275 0.35 0.49 0.8 mA
disabled
1 MHz 0.170 0.180 0.215 0.285 0.430 0.185 0.2 0.285 0.425 0.73
400 kHz 0.130 0.140 0.180 0.245 0.395 0.145 0.165 0.245 0.38 0.69
100 kHz 0.115 0.125 0.160 0.225 0.375 0.125 0.15 0.225 0.36 0.67
2 MHz 0.070 0.080 0.120 0.190 0.355 TBD TBD TBD TBD TBD

Supply current in Low-power run 1 MHz 0.040 0.050 0.090 0.160 0.320 TBD TBD TBD TBD TBD
IDD (LPRun) Low-power run
mode 400 kHz 0.020 0.030 0.070 0.145 0.295 TBD TBD TBD TBD TBD
100 kHz 0.010 0.020 0.060 0.130 0.290 TBD TBD TBD TBD TBD

1. Evaluated by characterization, unless otherwise specified.

Table 32. Typical current consumption in Run and Low-power run modes, with different codes running from flash memory, ART enabled (cache ON,
prefetch OFF)

Conditions Typical consumption Typical consumption Typical consumption

Symbol Parameter
Clock source Range Code 25 °C, 1.8 V 25 °C, 3.0 V 25 °C, 3.6 V

Coremark 3640 76 3760 78 3830 80

STM32U073x8/B/C
Reduced code 3880 81 4060 85 4090 85

Electrical characteristics
Range 1, 48 MHz Dhrystone 2.1 3660 76 3830 80 3870 81
fHCLK = fMSI, all peripherals μA/ μA/ μA/
IDD (Run) Supply current in Run mode Fibonacci 3490 μA 73 3650 μA 76 3690 μA 77
disabled MHz MHz MHz
While(1) 2490 52 2610 54 2640 55
page 54/146

Coremark 1090 68 1130 71 1150 72

Range 2, 16 MHz
Reduced code 1160 73 1210 76 1220 76
 DS14548 - Rev 2

Conditions Typical consumption Typical consumption Typical consumption

Symbol Parameter
Clock source Range Code 25 °C, 1.8 V 25 °C, 3.0 V 25 °C, 3.6 V

Dhrystone 2.1 1100 69 1150 72 1160 73

IDD (Run) Supply current in Run mode Range 2, 16 MHz Fibonacci 1050 66 1080 68 1090 68
While(1) 780 49 810 51 820 51

fHCLK = fMSI, all peripherals Coremark 160 80 μA/ 160 80 μA/ 160 80 μA/
μA μA μA
disabled Reduced code 170 85 MHz 170 85 MHz 170 85 MHz
Supply current in Low-power Low-power run,
IDD (LPRun) Dhrystone 2.1 160 80 160 80 160 80
run mode 2 MHz
Fibonacci 150 75 150 75 150 75
While(1) 110 55 110 55 110 55

Table 33. Typical current consumption in Run and Low-power run modes, with different codes running from flash memory, ART disabled

Conditions Typical consumption Typical consumption Typical consumption

Symbol Parameter
Clock source Range Code 25 °C, 1.8 V 25 °C, 3.0 V 25 °C, 3.6 V

Coremark 4160 87 4370 91 4420 92

Reduced code 4310 90 4540 95 4590 96
Range 1, 48 MHz Dhrystone 2.1 4200 88 4430 92 4480 93
Fibonacci 4190 87 4380 91 4440 93
While(1) 2490 52 2600 54 2620 55
IDD (Run) Supply current in Run mode
Coremark 1240 78 1290 81 1300 81
Reduced code 1280 80 1330 83 1350 84
fHCLK = fMSI, all peripherals μA/ μA/ μA/
Range 2, 16 MHz Dhrystone 2.1 1250 μA 78 1300 μA 81 1320 μA 83
disabled MHz MHz MHz
Fibonacci 1240 78 1300 81 1320 83
While(1) 780 49 810 51 820 51
Coremark 210 105 220 110 220 110
Reduced code 220 110 230 115 230 115

STM32U073x8/B/C
Electrical characteristics
Supply current in Low-power Low-power run,
IDD (LPRun) Dhrystone 2.1 220 110 220 110 220 110
run mode 2 MHz
Fibonacci 230 115 240 120 240 120
While(1) 110 55 110 55 110 55
page 55/146
 Table 34. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1
DS14548 - Rev 2

Conditions Typical consumption Typical consumption Typical consumption

Symbol Parameter
Clock source Range Code 25 °C, 1.8 V 25 °C, 3.0 V 25 °C, 3.6 V

Coremark 3340 70 3480 73 3510 73

Reduced code 3400 71 3540 74 3580 75
Range 1, 48 MHz Dhrystone 2.1 3310 69 3450 72 3490 73
Fibonacci 3490 73 3630 76 3680 77
While(1) 2690 56 2810 59 2840 59
IDD (Run) Supply current in Run mode
Coremark 1020 64 1060 66 1070 67
Reduced code 1030 64 1070 67 1080 68
fHCLK = fMSI, all peripherals μA/ μA/ μA/
Range 2, 16 MHz Dhrystone 2.1 1010 μA 63 1050 μA 66 1060 μA 66
disabled MHz MHz MHz
Fibonacci 1060 66 1100 69 1110 69
While(1) 850 53 880 55 890 56
Coremark 138 69 138 69 138 69
Reduced code 140 70 140 70 140 70
Supply current in Low-power Low-power run,
IDD (LPRun) Dhrystone 2.1 140 70 140 70 140 70
run mode 2 MHz
Fibonacci 140 70 150 75 150 75
While(1) 110 55 110 55 120 60

Table 35. Current consumption in Sleep and Low-power sleep modes, flash memory ON, HSE clock used as system clock

Conditions Typ Max

Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

48 MHz 1.25 1.25 1.30 1.40 1.60 1.4 1.4 1.5 1.7 2.05
32 MHz 0.885 0.900 0.910 1.00 1.20 0.975 1 1.1 1.25 1.6
Range 1
24 MHz 0.695 0.710 0.755 0.835 1.00 0.765 0.795 0.89 1.05 1.4
16 MHz 0.505 0.520 0.565 0.640 0.810 0.555 0.585 0.68 0.84 1.2

STM32U073x8/B/C
Electrical characteristics
fHCLK = fHSE, bypass mode, 16 MHz 0.445 0.455 0.490 0.560 0.710 0.485 0.51 0.59 0.73 1.05
IDD (Sleep) Supply current in Run mode mA
peripherals disabled
8 MHz 0.275 0.285 0.325 0.390 0.540 0.305 0.325 0.405 0.545 0.85

Range 2 4 MHz 0.190 0.205 0.245 0.305 0.455 0.21 0.235 0.31 0.445 0.755
2 MHz 0.155 0.160 0.195 0.265 0.410 0.165 0.185 0.26 0.4 0.705
page 56/146

1 MHz 0.130 0.145 0.175 0.240 0.390 0.14 0.165 0.24 0.375 0.68
 DS14548 - Rev 2

Conditions Typ Max

Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

400 kHz 0.115 0.125 0.165 0.230 0.375 0.13 0.15 0.225 0.36 0.665
IDD (Sleep) Supply current in Run mode Range 2
100 kHz 0.110 0.120 0.155 0.220 0.370 0.12 0.145 0.22 0.355 0.66

fHCLK = fHSE, bypass mode, 2 MHz 0.060 0.070 0.110 0.180 0.340 TBD TBD TBD TBD TBD
mA
peripherals disabled 1 MHz 0.035 0.045 0.085 0.155 0.315 TBD TBD TBD TBD TBD
Supply current in Low-power
IDD (LPSleep) -
run mode 400 kHz 0.020 0.035 0.070 0.140 0.305 TBD TBD TBD TBD TBD
100 kHz 0.015 0.025 0.065 0.135 0.295 TBD TBD TBD TBD TBD

Table 36. Current consumption in Sleep and Low-power sleep modes, flash memory ON, MSI clock used as system clock

Conditions Typ Max

Symbol Parameter Unit
Clock source Range fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

48 MHz 1.30 1.35 1.40 1.50 1.65 1.45 1.5 1.65 1.8 2.2
32 MHz 0.915 0.940 0.95 1.10 1.25 1 1.065 1.15 1.35 1.7
Range 1
24 MHz 0.715 0.740 0.800 0.870 1.05 0.785 0.835 0.94 1.1 1.47
16 MHz 0.525 0.545 0.590 0.670 0.84 0.575 0.615 0.715 0.88 1.24
16 MHz 0.455 0.475 0.515 0.585 0.735 0.5 0.535 0.625 0.765 1.08
IDD (Sleep) Supply current in Run mode 8 MHz 0.275 0.280 0.320 0.385 0.535 0.295 0.32 0.4 0.54 0.85
4 MHz 0.190 0.200 0.240 0.305 0.450 0.21 0.235 0.31 0.445 0.755
fHCLK = fMSI, peripherals
Range 2 2 MHz 0.150 0.160 0.200 0.265 0.410 0.165 0.19 0.265 0.4 0.705 mA
disabled
1 MHz 0.130 0.140 0.180 0.245 0.400 0.145 0.165 0.24 0.375 0.685
400 kHz 0.115 0.125 0.165 0.230 0.375 0.125 0.15 0.225 0.36 0.665
100 kHz 0.110 0.120 0.155 0.220 0.370 0.12 0.14 0.215 0.355 0.655
2 MHz 0.060 0.070 0.110 0.180 0.345 TBD TBD TBD TBD TBD

Supply current in Low-power run 1 MHz 0.040 0.050 0.090 0.160 0.315 TBD TBD TBD TBD TBD
IDD (LPSleep) -
mode

STM32U073x8/B/C
400 kHz 0.025 0.035 0.070 0.145 0.305 TBD TBD TBD TBD TBD

Electrical characteristics
100 kHz 0.015 0.025 0.065 0.135 0.295 TBD TBD TBD TBD TBD
page 57/146
 Table 37. Current consumption in Sleep and Low-power sleep modes, flash memory in power-down mode
DS14548 - Rev 2

Conditions Typ Max

Symbol Parameter Unit
Clock source fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

2 MHz 61.5 72.5 110 180 340 TBD TBD TBD TBD TBD
1 MHz 38.5 49.5 88.5 160 315 TBD TBD TBD TBD TBD
IDD (LPSleep) Supply current in Low-power sleep mode fHCLK = fMSI, peripherals disabled μA
400 kHz 22.5 33.0 72.0 140 300 TBD TBD TBD TBD TBD
100 kHz 15.5 26.0 65.0 135 295 TBD TBD TBD TBD TBD

Table 38. Current consumption in Stop 0 mode

Conditions Typ Max

Symbol Parameter Unit
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

1.8 V 100 110 140 195 310 254 276 350 490 770
2.4 V 100 110 140 195 315 257 279 356 490 795
IDD (Stop 0) Supply current in Stop 0 mode, RTC disabled 3.0 V 105 110 145 200 320 260 281 359 495 805 μA
3.3 V 105 110 145 200 320 260 282 360 495 805
3.6 V 105 115 145 200 325 262 285 362 500 810

Table 39. Current consumption in Stop 1 mode

Conditions Typ Max

Symbol Parameter 125 105 Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 30 °C 55 °C 85 °C 130 °C
°C °C

1.8 V 3.20 10.5 39.5 91.5 200 8.10 27.5 99 230 500
2.4 V 3.20 10.5 39.5 91.5 210 8.10 27.5 100 230 520
EN_ULP = 0 3.0 V 3.30 10.5 39.5 92.5 210 8.00 27.5 100 230 530
3.3 V 3.30 11.0 40.0 93.5 215 8.00 27.5 100 235 535
3.6 V 3.35 11.0 40.0 93.5 215 8.10 27.5 100 235 535

STM32U073x8/B/C
Supply current in Stop 1 mode, LCD disabled
IDD (Stop 1) μA

Electrical characteristics
RTC disabled 1.8 V 3.20 10.5 39.5 92.0 195 8.10 27.5 100 230 495
2.4 V 3.20 10.5 39.5 91.5 205 8.10 27.5 99 230 520
EN_ULP = 1 3.0 V 3.30 10.5 39.5 92.5 210 8.00 27.5 100 230 530
3.3 V 3.30 10.5 40.0 93.0 210 8.00 27.5 100 230 530
page 58/146

3.6 V 3.35 11.0 40.0 93.5 215 8.10 27.5 100 235 535
 DS14548 - Rev 2

Conditions Typ Max

Symbol Parameter 125 105 Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 30 °C 55 °C 85 °C 130 °C
°C °C

1.8 V 3.50 11.0 39.5 92.0 200 9.00 29.0 100 230 500
2.4 V 3.60 11.0 39.5 92.0 210 9.00 29.0 100 230 525
Supply current in Stop 1 mode,
RTC disabled LCD enabled, clocked by LSI EN_ULP = 0 3.0 V 3.70 11.0 40.0 93.0 210 9.00 29.0 100 230 530
3.3 V 3.80 11.5 40.5 93.5 215 10.0 29.0 100 235 535
3.6 V 3.90 11.5 40.5 94.5 215 10.0 30.0 100 235 535
1.8 V 3.60 11.0 40.0 92.0 195 9.00 29.0 100 230 495
2.4 V 3.70 11.0 40.0 92.0 210 9.00 29.0 100 230 520
EN_ULP = 0
RTC clocked by LSI 3.0 V 3.90 11.5 40.0 93.0 210 10.0 29.0 100 230 530
LPCAL = 1
3.3 V 3.90 11.5 40.5 93.5 215 10.0 30.0 100 235 535
3.6 V 4.10 11.5 41.0 94.5 215 10.0 30.0 100 235 535
1.8 V 3.40 11.0 39.5 92.5 195 9.00 27.5 100 230 485
2.4 V 3.40 11.0 39.5 91.5 210 9.00 27.5 100 230 525
EN_ULP = 0
3.0 V 3.50 11.0 39.5 93.5 215 9.00 27.5 100 235 535
LPCAL = 1
3.3 V 3.50 11.0 39.5 93.0 215 9.00 29.0 100 235 535
IDD (Stop 1) RTC clocked by LSE, 3.6 V 3.55 11.0 40.0 94.0 215 9.10 29.0 100 235 540 μA
bypassed at 32768 Hz, LCD
disabled 1.8 V 3.50 11.0 39.5 92.5 195 9.00 29.0 100 230 485
2.4 V 3.60 11.0 39.5 92.0 210 9.00 29.0 100 230 530
Supply current in Stop 1 mode, EN_ULP = 0
RTC enabled 3.0 V 3.80 11.0 40.0 93.0 215 10.0 29.0 100 230 535
LPCAL = 0
3.3 V 3.80 11.5 40.0 93.5 215 10.0 29.0 100 235 535
3.6 V 4.00 11.5 40.5 94.5 215 10.0 30.0 101 235 540
1.8 V 3.40 11.0 39.5 92.0 190 9.00 29.0 100 230 4800
2.4 V 3.70 11.0 39.5 92.5 210 9.00 29.0 100 230 5300
EN_ULP = 0
3.0 V 3.80 11.5 40.0 93.0 215 10.0 29.0 100 230 5350
LPCAL = 0

STM32U073x8/B/C
3.3 V 3.90 11.5 40.5 93.5 215 10.0 29.0 100 235 5350

Electrical characteristics
RTC clocked by LSE quartz in 3.6 V 4.05 11.5 41.0 94.5 215 10.0 30.0 100 235 5400
low-drive mode, LCD disabled
1.8 V 3.30 11.0 39.5 92.0 195 8.00 27.5 100 230 4850

EN_ULP = 0 2.4 V 3.40 11.0 39.5 92.0 210 9.00 27.5 100 230 5250
page 59/146

LPCAL = 1 3.0 V 3.40 11.0 39.5 93.5 215 9.00 27.5 100 235 5350
3.3 V 3.50 11.0 40.0 93.5 215 9.00 29.0 100 235 5350
 DS14548 - Rev 2

Conditions Typ Max

Symbol Parameter 125 105 Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 30 °C 55 °C 85 °C 130 °C
°C °C
EN_ULP = 0
3.6 V 3.65 11.0 40.5 93.5 215 9.10 29.0 100 235 5350
LPCAL = 1
1.8 V 3.40 11.0 39.5 91.5 190 9.00 27.5 100 230 4800
RTC clocked by LSE quartz in
2.4 V 3.40 11.0 39.5 92.0 210 9.00 27.5 100 230 5300
low-drive mode, LCD disabled EN_ULP = 1
3.0 V 3.50 11.0 39.5 93.0 215 9.00 27.5 100 230 5350
LPCAL = 1
Supply current in Stop 1 mode, 3.3 V 3.50 11.0 40.0 93.5 215 9.00 29.0 100 235 5350
IDD (Stop 1) μA
RTC enabled 3.6 V 3.65 11.0 40.5 94.0 215 9.10 29.0 100 235 5350
1.8 V 3.30 11.0 39.5 92.0 190 8.00 27.5 100 230 4800
2.4 V 3.40 11.0 39.5 92.0 210 9.00 27.5 100 230 5300
RTC clocked by LSE quartz in
- 3.0 V 3.50 11.0 39.5 93.0 210 9.00 27.5 100 230 5300
low-drive mode, LCD enabled
3.3 V 3.50 11.0 40.0 93.5 215 9.00 29.0 100 235 5350
3.6 V 3.65 11.0 40.5 94.0 215 9.10 29.0 100 235 5400

Table 40. Current consumption in Stop 2 mode

Conditions Typ Max

Symbol Parameter Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

1.8 V 695 2250 9550 22500 53000 2450 5650 24000 56000 130000
2.4 V 720 2350 9850 23000 54500 2500 5900 24500 57500 135000
EN_ULP = 0 3.0 V 750 2500 10000 23500 56000 2550 6200 25500 59500 140000
3.3 V 770 2550 10500 24000 57500 2550 6400 26000 60500 145000
3.6 V 805 2650 11000 25000 58500 2600 6650 27000 62000 145000
LCD disabled
1.8 V 760 2250 8800 21500 52000 2450 5650 22000 54000 130000
Supply current in Stop 2 2.4 V 775 2300 8950 22000 53500 2500 5700 22500 55500 135000
IDD (Stop 2) nA
mode, RTC disabled

STM32U073x8/B/C
EN_ULP = 1 3.0 V 795 2300 9150 22500 55000 2550 5800 23000 56500 135000

Electrical characteristics
3.3 V 805 2350 9250 23000 56000 2550 5850 23000 57500 140000
3.6 V 830 2400 9450 23500 57500 2600 6000 23500 58500 145000
1.8 V 1000 2500 9100 22000 52500 2550 6250 22500 55000 130000
LCD enabled, clocked by
page 60/146

EN_ULP = 0 2.4 V 1100 2600 9250 22500 54000 2750 6500 23000 56500 135000
LSI
3.0 V 1200 2700 9550 23000 55500 2950 6800 24000 57500 140000
 DS14548 - Rev 2

Conditions Typ Max

Symbol Parameter Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

Supply current in Stop 2 LCD enabled, clocked by 3.3 V 1250 2800 9700 23500 56500 3100 6950 24500 58500 140000
EN_ULP = 0
mode, RTC disabled LSI
3.6 V 1300 2850 9950 24000 58000 3250 7200 25000 60000 145000
1.8 V 1100 2600 9150 22000 52500 2750 6500 23000 55000 130000
2.4 V 1200 2700 9400 22500 54000 3000 6800 23500 56500 135000
RTC clocked by LSI, LCD EN_ULP = 0
3.0 V 1300 2850 9700 23000 55500 3300 7150 24000 58000 140000
disabled LPCAL = 1
3.3 V 1400 2950 9850 23500 56500 3500 7350 24500 59000 140000
3.6 V 1450 3050 10000 24000 58000 3650 7650 25500 60000 145000
1.8 V 830 2350 9000 22000 53000 2550 5850 22500 55000 130000
2.4 V 870 2400 9200 22500 54500 2600 6000 23000 56500 135000
EN_ULP = 0
3.0 V 935 2450 9400 23000 56500 2650 6200 23500 58000 140000
LPCAL = 1
3.3 V 955 2550 9600 23500 57000 2700 6300 24000 59000 145000
RTC clocked by LSE , 3.6 V 995 2600 9800 24000 58500 2750 6550 24500 60000 145000
bypassed at 32768 Hz, LCD
disabled 1.8 V 985 2500 9050 22000 53000 2450 6250 22500 55500 130000
2.4 V 1100 2600 9350 22500 54500 2750 6550 23500 56500 135000
EN_ULP = 0
3.0 V 1250 2750 9650 23000 56500 3100 6950 24000 58000 140000
IDD (Stop 2) LPCAL = 0 nA
3.3 V 1300 2850 9850 23500 57500 3250 7150 24500 59000 145000
Supply current in Stop 2
mode, RTC enabled 3.6 V 1400 3000 10000 24000 58500 3500 7500 25000 60500 145000
1.8 V 840 2550 9850 22500 54500 2100 6450 24500 57000 135000
2.4 V 1100 2750 10000 23500 57000 2800 6900 25500 59000 140000
EN_ULP = 0
3.0 V 1250 3000 11000 24500 59000 3100 7500 27000 61000 150000
LPCAL = 0
3.3 V 1300 3150 11000 25000 60500 3300 7850 28000 62000 150000
3.6 V 1400 3350 11500 25500 61500 3550 8400 28500 63500 155000
1.8 V 890 2400 9000 22000 52500 2200 6050 22500 54500 130000
RTC clocked by LSE quartz
in low-drive mode, LCD 2.4 V 945 2450 9200 22500 54000 2350 6150 23000 56000 135000

STM32U073x8/B/C
disabled EN_ULP = 0

Electrical characteristics
3.0 V 985 2500 9400 23000 56000 2450 6300 23500 57500 140000
LPCAL = 1
3.3 V 1000 2550 9550 23000 56500 2550 6450 24000 58000 140000
3.6 V 1050 2650 9750 24000 57500 2650 6600 24500 59500 145000
1.8 V 825 2400 9700 22500 54000 2050 6050 24000 56500 135000
page 61/146

EN_ULP = 1
2.4 V 885 2500 10000 23000 56000 2200 6300 25000 58000 140000
LPCAL = 1
3.0 V 940 2700 10500 24000 58500 2350 6750 26000 60000 145000
 DS14548 - Rev 2

Conditions Typ Max

Symbol Parameter Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C
RTC clocked by LSE quartz EN_ULP = 1 3.3 V 975 2800 10500 24500 59500 2450 7000 27000 61500 150000
in low-drive mode, LCD
disabled LPCAL = 1 3.6 V 1050 2900 11000 25000 60500 2600 7250 27500 62500 150000

1.8 V 890 2400 9050 22000 52500 2200 6050 22500 54500 130000
Supply current in Stop 2
IDD (Stop 2) 2.4 V 945 2450 9150 22500 54000 2350 6150 23000 56000 135000 nA
mode, RTC enabled RTC clocked by LSE quartz
in low-drive mode, LCD - 3.0 V 985 2500 9400 23000 56000 2450 6300 23500 57500 140000
enabled
3.3 V 1000 2550 9500 23500 56500 2550 6450 23500 58500 140000
3.6 V 1050 2650 9750 23500 57500 2650 6600 24500 59500 145000

Table 41. Current consumption in Standby mode

Conditions Typ Max

Symbol Parameter Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

1.8 V 30.5 195 1200 3700 9400 77.5 485 3050 9300 23500
2.4 V 48.0 260 1550 4300 11000 120 650 3900 11000 27000
EN_ULP = 0 3.0 V 68.5 345 2000 5050 12000 170 865 5050 12500 30500
3.3 V 82.0 395 2250 5450 13000 205 990 5650 13500 32500
3.6 V 105 460 2550 5750 14000 260 1150 6400 14500 34500
No independent watchdog
1.8 V 100 235 1050 3050 8750 250 585 2600 7600 22000
2.4 V 115 265 1200 3450 10000 285 665 2950 8600 25000
Supply current in Standby mode
IDD (Standby) (backup registers retained), EN_ULP = 1 3.0 V 130 305 1350 3900 11000 320 765 3400 9800 28000
RTC disabled
3.3 V 135 330 1450 4250 12000 345 830 3600 10500 29500
nA
3.6 V 150 370 1550 4500 12500 380 925 3900 11000 31500
1.8 V 195 335 1150 3150 8800 490 835 2850 7850 22000
2.4 V 215 375 1300 3600 10000 545 945 3250 8950 25500

STM32U073x8/B/C
Independent watchdog EN_ULP = 0 3.0 V 240 425 1500 4000 11500 605 1050 3700 10000 28500

Electrical characteristics
3.3 V 260 460 1600 4350 12000 650 1150 4000 11000 30000
3.6 V 280 505 1700 4700 13000 700 1250 4300 11500 32000
1.8 V 195 335 1150 3150 8750 490 840 2850 7850 22000
IDD (Standby with Supply current in Standby mode
RTC clocked by LSI, no
EN_ULP = 0 2.4 V 220 380 1300 3600 10000 545 945 3250 8950 25500
page 62/146

(backup registers retained),

RTC) independent watchdog
RTC enabled
3.0 V 245 430 1500 4050 11500 610 1050 3700 10000 28500
 DS14548 - Rev 2

Conditions Typ Max

Symbol Parameter Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

RTC clocked by LSI, no 3.3 V 260 460 1600 4350 12000 655 1150 4000 11000 30000
EN_ULP = 0
independent watchdog
3.6 V 285 505 1700 4650 13000 710 1250 4250 11500 32000
1.8 V 200 340 1150 3150 8850 500 850 2850 7900 22000
2.4 V 225 385 1300 3600 10000 560 960 3250 9000 25500
RTC clocked by LSI,
EN_ULP = 0 3.0 V 245 435 1500 4050 11500 620 1100 3700 10000 28500
independent watchdog
3.3 V 265 465 1600 4350 12000 665 1150 4000 11000 30000
3.6 V 290 515 1750 4700 13000 720 1300 4350 11500 32000
1.8 V 155 290 1100 3150 8800 385 725 2750 7850 22000
2.4 V 195 355 1300 3600 10000 495 885 3200 9000 25500
RTC clocked by LSE,
LPCAL = 0 3.0 V 245 430 1500 4100 11500 615 1050 3750 10500 28500
bypassed at 32768 Hz
3.3 V 280 475 1600 4500 12000 695 1200 4050 11000 30500
3.6 V 315 540 1750 4800 13000 785 1350 4400 12000 33000
1.8 V 245 565 1400 3400 9550 620 1400 3450 8550 24000
IDD (Standby with Supply current in Standby mode
(backup registers retained), 2.4 V 510 680 1600 3900 11000 1250 1700 4050 9750 28000
RTC) RTC enabled EN_ULP = 0
3.0 V 625 820 1900 4550 12500 1550 2050 4750 11500 31500
LPCAL = 0 nA
3.3 V 690 905 2050 4900 13500 1750 2250 5150 12000 33500
3.6 V 770 1000 2250 5200 14000 1900 2500 5600 13000 35500
1.8 V 230 400 1200 3250 9050 580 1000 3050 8100 22500
2.4 V 280 450 1400 3700 10500 705 1100 3450 9200 26000
RTC clocked by LSE EN_ULP = 0
3.0 V 320 510 1600 4200 11500 800 1300 3950 10500 29000
quartz in low-drive mode LPCAL = 1
3.3 V 345 555 1650 4550 12500 865 1400 4200 11500 31000
3.6 V 380 615 1850 4800 13000 955 1550 4600 12000 33000
1.8 V 160 360 1400 3900 11000 400 900 3500 9800 27500
2.4 V 215 440 1750 4550 13000 540 1100 4400 11500 32500

STM32U073x8/B/C
EN_ULP = 1

Electrical characteristics
3.0 V 260 550 2250 5300 14500 650 1350 5600 13000 37000
LPCAL = 1
3.3 V 285 620 2500 5700 15500 720 1550 6250 14000 39000
3.6 V 330 700 2800 6050 16500 825 1750 7000 15000 41500
1.8 V 89.0 190 605 1400 3200 225 470 1500 3550 8050
page 63/146

Supply current to be added in Standby mode when SRAM2 2.4 V 90.0 190 605 1400 3250 225 470 1500 3550 8050
IDD (SRAM2) -
is retained
3.0 V 90.0 190 610 1450 3250 225 475 1500 3550 8100
 DS14548 - Rev 2

Conditions Typ Max

Symbol Parameter Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

Supply current to be added in Standby mode when SRAM2 3.3 V 90.0 190 620 1450 3300 225 475 1550 3500 8250
IDD (SRAM2) - nA
is retained
3.6 V 90.5 190 640 1500 3400 225 480 1600 3550 8500

Table 42. Current consumption in Shutdown mode

Conditions Typ Max

Symbol Parameter Unit
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

1.8 V 10.0 92.5 595 1950 5950 42 280 2000 7050 25500
2.4 V 41.5 135 725 2250 7100 105 400 2400 8200 28500
Supply current in Shutdown
IDD (Shutdown) mode (backup registers - EN_ULP = 0 3.0 V 52.5 165 840 2600 7900 145 495 2850 9500 32000
retained), RTC disabled
3.3 V 53.5 175 910 2800 8450 160 540 3100 10000 34000
3.6 V 65.0 205 1000 3050 9100 190 620 3350 11000 36500
1.8 V 67.0 150 660 2050 6150 195 370 1650 5100 15500
2.4 V 120 220 820 2400 7350 305 550 2050 5950 18500
RTC clocked by
LSE bypassed at - 3.0 V 165 285 980 2750 8200 420 710 2450 6950 20500
32768 Hz
3.3 V 195 320 1050 3000 8850 485 800 2700 7500 22000
3.6 V 225 370 1200 3200 9550 565 930 3000 8050 24000
nA
1.8 V 160 425 955 2300 12000 400 1050 2400 5800 30000
2.4 V 425 535 1150 2700 13000 1050 1350 2850 6750 32500
IDD (Shutdown with Supply current in Shutdown
EN_ULP = 0
mode (backup registers 3.0 V 535 665 1350 3150 14000 1350 1650 3400 7850 35000
RTC) LPCAL = 0
retained), RTC enabled
3.3V 600 740 1500 3400 15500 1500 1850 3750 8550 38500

RTC clocked by 3.6 V 675 835 1650 3650 17000 1700 2100 4100 9200 42500
LSE quartz 1.8 V 145 260 785 2150 12000 360 655 1950 5400 30000
2.4 V 200 310 915 2450 13500 500 770 2300 6150 33500
EN_ULP = 0

STM32U073x8/B/C
3.0 V 235 360 1050 2850 14500 585 900 2650 7100 36000
LPCAL = 1

Electrical characteristics
3.3 V 255 395 1150 3050 16000 640 985 2850 7650 40000
3.6 V 290 445 1250 3250 17000 720 1100 3150 8200 42500
page 64/146
 Table 43. Current consumption in VBAT mode
DS14548 - Rev 2

Conditions TYP MAX

Symbol Parameter Unit
- - VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 30 °C 55 °C 85 °C 105 °C 130 °C

1.8 V 9.00 22.5 190 700 2600 25.5 56.5 470 1750 6550
2.4 V 10.5 36.5 230 815 2950 27.5 91.5 570 2050 7450
RTC disabled - 3.0 V 13 44 270 945 3350 33.5 110 675 2350 8450
3.3 V 13 47.5 295 100 3600 33.5 120 735 2550 9000
3.6 V 15.5 56 330 110 3850 40.5 140 820 2800 9650
1.8 V 53 73.5 200 535 1550 13.5 185 505 1350 3900
2.4 V 86 110 260 645 1800 21.5 275 655 1600 4550
RTC clocked by LSE, bypassed at
- 3.0 V 120 150 330 775 2100 305 380 820 1950 5300
32768 Hz
3.3 V 140 175 370 860 2300 355 440 930 2150 5750
3.6 V 165 205 430 960 2500 415 520 1050 2400 6300
IDD (VBAT) Supply current in VBAT mode nA
1.8 V 130 190 380 905 2900 320 475 950 2250 7200
2.4 V 165 215 435 100 3250 415 545 1100 2550 8100
LPCAL = 0 3.0 V 205 250 500 115 3650 510 625 1250 2950 9150
3.3 V 220 270 540 125 3900 550 675 1350 3150 9750

RTC clocked by LSE quartz in low- 3.6 V 240 300 595 1350 4200 605 745 1500 3450 10500
drive mode 1.8 V 130 355 545 905 2900 320 885 1350 2250 7200
2.4 V 300 445 665 100 3250 750 1100 1650 2550 8100
LPCAL = 1 3.0 V 505 555 810 115 3650 1250 1400 2050 2950 9150
3.3 V 565 620 895 125 3900 1400 1550 2250 3150 9800
3.6 V 630 690 995 1350 4200 1550 1750 2500 3450 10500

STM32U073x8/B/C
Electrical characteristics
page 65/146
 STM32U073x8/B/C
Electrical characteristics

6.3.5.1 I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull resistors generate a current consumption when the pin is externally held to
the opposite level. The value of this current consumption can be simply computed by using the pull-up/pull-down
resistors values given in Table 64. I/O static characteristics.
For the output pins, any internal or external pull-up or pull-down resistor and external load must also be
considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally
applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input
value. Unless this specific configuration is required by the application, this supply current consumption can be
avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of
external electromagnetic noise. To avoid current consumption related to floating pins, they must either be
configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-
up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see Table 44. Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin
switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the
internal or external capacitive load connected to the pin:
ISW = VDDIOx × fSW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

6.3.5.2 On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 44. Peripheral current consumption. The
MCU is placed under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 19. Voltage
characteristics
• The power consumption of the digital part of the on-chip peripherals is given in Table 44. Peripheral current
consumption. The power consumption of the analog part of the peripherals (where applicable) is indicated
in each related section of the datasheet.

DS14548 - Rev 2 page 66/146

 STM32U073x8/B/C
Electrical characteristics

Table 44. Peripheral current consumption

Peripheral Range 1 Range 2 Unit

Bus matrix(1) 0.40 0.40

ADC 1.90 0.40

CRC 0.50 0.42
DMA1 5.44 4.52
DMA2 5.28 4.39
DMA1+DMA2 6.76 5.63

GPIOA(2) 0.08 0.07

AHB GPIOB(2) 0.08 0.07

GPIOC(2) 0.07 0.06

GPIOD(2) 0.06 0.04

GPIOE(2) 0.05 0.04

GPIOF(2) 0.05 0.04

RNG 1.21 NA
TSC 2.72 2.26
ALL AHB bridges 18.1 15.1

AHB to APB bridge(3) 0.27 0.21

RTCA 4.12 3.41

I2C1(4) 0.80 0.65

I2C1(5) 2.63 0.73

I2C2 0.94 0.77

μA/MHz
I2C3(4) 0.66 0.54

I2C3(5) 2.20 0.61

I2C4 0.89 0.73

USART1(4) 8.64 7.19

USART1(5) 2.46 2.06

USART2(4) 2.23 1.85

USART2(5) 2.30 1.92

APB
USART3(4) 2.32 1.93

USART3(5) 2.32 1.93

USART4 2.30 1.90

LPUART1(4) 1.47 1.22

LPUART1(5) 1.55 1.30

LPUART2(4) 5.01 4.18

LPUART2(5) 2.06 1.72

LPUART3(4) 1.92 1.58

LPUART3(5) 1.99 1.65

LPTIM1(4) 2.06 1.71

LPTIM1(5) 2.13 1.78

LPTIM2(4) 1.37 1.13

DS14548 - Rev 2 page 67/146

 STM32U073x8/B/C
Electrical characteristics

Peripheral Range 1 Range 2 Unit

LPTIM2(5) 1.44 1.21

LPTIM3(4) 2.02 1.67

LPTIM3(5) 2.10 1.75

OPAMP 0.27 0.21

DAC 1.02 0.83
PWR 0.66 0.54
SPI1 1.75 1.45
SPI2 1.74 1.44
SPI3 1.71 1.41
TIM1 0.64 0.54
APB TIM2 5.36 4.45 μA/MHz

TIM3 4.23 3.52

TIM6 0.86 0.71
TIM7 0.86 0.70
TIM15 0.49 0.41
TIM16 2.46 2.05
WWDG 0.38 0.29
SYSCFG 0.32 0.27
USB 3.67 NA
LCD 0.55 0.45
ALL APB bridges 46.0 38.5

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The GPIOx (x= A…F) dynamic current consumption is approximately divided by a factor two versus this table values when
the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current
consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog
mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).
3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.
4. Independent clock domain.
5. Clock domain.

6.3.6 Wake-up time from low-power modes and voltage scaling transition times
The wake-up times given in Table 45 are the latency between the event and the execution of the first user
instruction.
The device goes in low-power mode after the WFE (Wait for event) instruction.

Table 45. Low-power mode wake-up timings

Evaluated by characterization, not tested in production.
Symbol Parameter Conditions Typ Max Unit

tWUSLEEP Wake-up time from Sleep mode to Run mode - 6 6

Nb of
Wake-up in flash with flash in power-down during low- CPU
Wake-up time from Low-power sleep mode to
tWULPSLEEP power sleep mode (SLEEP_PD = 1 in FLASH_ACR) 6 8.3 cycles
Low-power run mode
and with clock MSI = 2 MHz
Wake-up clock MSI =
6.3 6.7
24 MHz
Wake up time from Stop 0 mode to Run mode
tWUSTOP0 Range 1 or range 2 µs
in flash Wake-up clock HSI16 =
6.5 6.7
16 MHz

DS14548 - Rev 2 page 68/146

 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions Typ Max Unit

Wake up time from Stop 0 mode to Run mode
Range 1 or range 2 Wake-up clock MSI = 1 MHz 33.0 36.0
in flash
Wake-up clock MSI =
1.92 2.30
tWUSTOP0 24 MHz µs
Wake up time from Stop 0 mode to Run mode
Range 1 or range 2 Wake-up clock HSI16 =
in SRAM1 1.90 2.00
16 MHz
Wake-up clock MSI = 1 MHz 19.0 22.0
Wake-up clock MSI =
11.5 17.5
24 MHz
Wake up time from Stop 1 mode to Run in
Range 1 or range 2 Wake-up clock HSI16 =
flash 11.0 13.5
16 MHz
Wake-up clock MSI = 1 MHz 35.0 38.4
tWUSTOP1 µs
Wake-up clock MSI =
7.2 13.0
24 MHz
Wake up time from Stop 1 mode to Run mode
Range 1 or range 2 Wake-up clock HSI16 =
in SRAM1 6.9 8.8
16 MHz
Wake-up clock MSI = 1 MHz 21.9 25.0
Wake-up clock MSI =
12.0 16.5
24 MHz
Wake up time from Stop 2 mode to Run mode
Range 1 or range 2 Wake-up clock HSI16 =
in flash 13.4 17.0
16 MHz
Wake-up clock MSI = 1 MHz 40.0 43.5
tWUSTOP2 µs
Wake-up clock MSI =
7.67 12.0
24 MHz
Wake up time from Stop 2 mode to Run mode
Range 1 or range 2 Wake-up clock HSI16 =
in SRAM1 11.0 17.0
16 MHz
Wake-up clock MSI = 1 MHz 26.0 29.0

Wake-up time from Standby mode to Run Wake-up clock MSI = 4 MHz 62.0 67.0
tWUSTBY Range 1 µs
mode Wake-up clock MSI = 1 MHz 63.0 67.0
Wake-up time from Shutdown mode to Run
tWUSHDN Range 1 Wake-up clock MSI = 4 MHz 292 360 μs
mode

Table 46. Regulator mode transition times

Evaluated by characterization, not tested in production.
Symbol Parameter Conditions Typ Max Unit

tWULPRUN Wake-up time from Low-power run mode to Run mode(1) Code run with MSI 2 MHz 5 7
μs
tVOST Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(2) Code run with MSI 16 MHz 20 40

1. Time until REGLPF flag is cleared in PWR_SR2.

2. Time until VOSF flag is cleared in PWR_SR2.

Table 47. Wake-up time using USART/LPUART

Evaluated by characterization, not tested in production.
Symbol Parameter Conditions Typ Max Unit

Stop 0 mode - 1.7

tWUUSART Wake-up time needed to calculate the maximum USART/LPUART baud rate
Stop 1 mode and Stop 2 µs
tWULPUART allowing to wake up up from stop mode when USART/LPUART clock source is HSI - 8.5
mode

DS14548 - Rev 2 page 69/146

 STM32U073x8/B/C
Electrical characteristics

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14: I/O port characteristics.
However, the recommended clock input waveform is shown in Figure 16. AC timing diagram for high-speed
external clock source .

Table 48. High-speed external user clock characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

Voltage scaling Range 1 - 8 48

fHSE_ext User external clock source frequency MHz
Voltage scaling Range 2 - 8 19
VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx

tw(HSEH) Voltage scaling Range 1 7 - -

OSC_IN high or low time ns
tw(HSEL) Voltage scaling Range 2 18 - -

Figure 16. AC timing diagram for high-speed external clock source

VHSE
tw(HSEH)

VHSEH
70%
30%
VHSEL

DT67850V3
t
THSE tw(HSEL)

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14: I/O port characteristics.
However, the recommended clock input waveform is shown in Figure 17. AC timing diagram for low-speed
external clock source.

Table 49. Low-speed external user clock characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx

tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)

DS14548 - Rev 2 page 70/146

 STM32U073x8/B/C
Electrical characteristics

Figure 17. AC timing diagram for low-speed external clock source

VLSE_ext
tw(LSEH)
VLSEH
70%
VLSE_ext_PP
30%
VLSEL

DT67851V3
t
tLSE = 1/fLSE_ext tw(LSEL)

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph are based on design simulation results obtained with typical external
components specified in Table 50. HSE oscillator characteristics. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and
startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 50. HSE oscillator characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions(1) Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 - 48 MHz

RF Feedback resistor - - 200 - kΩ

During startup(2) - - 5.5

VDD = 3 V,
Rm = 30 Ω, - 0.58 -
CL = 10 pF @ 8 MHz

VDD = 3 V,
Rm = 45 Ω, - 0.59 -
CL = 10 pF @ 8 MHz

IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 0.89 -
C = 5 pF @ 48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.14 -
CL = 10 pF @ 48 MHz

VDD = 3 V,
Rm = 30 Ω, - 1.94 -
CL = 20 pF @ 48 MHz

Gm Maximum critical crystal transconductance Startup - - 1.5 mA/V

tSU(HSE) (3) VDD is stabilized

Startup time - 2 - ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

DS14548 - Rev 2 page 71/146

 STM32U073x8/B/C
Electrical characteristics

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range
(typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator (see Figure 18. Typical application with an 8 MHz crystal). CL1 and CL2 are usually the same size. The
crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB
and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and
board capacitance) when sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.

Figure 18. Typical application with an 8 MHz crystal

Resonator with integrated

capacitors
CL1

OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain

REXT (1) OSC_OUT

CL2

DT19876V1
1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the
information given in this paragraph are based on design simulation results obtained with typical external
components specified in Table 51. LSE oscillator characteristics (fLSE = 32.768 kHz). In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the
resonator characteristics (frequency, package, accuracy).

Table 51. LSE oscillator characteristics (fLSE = 32.768 kHz)

Specified by design, not tested in production.
Symbol Parameter Conditions(1) Min Typ Max Unit

LSEDRV[1:0] = 00, low drive capability - 250 -

LSEDRV[1:0] = 01, medium low drive capability - 315 -
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10, medium high drive capability - 500 -
LSEDRV[1:0] = 11, high drive capability - 630 -
LSEDRV[1:0] = 00, low drive capability - - 0.5
LSEDRV[1:0] = 01, medium low drive capability - - 0.75
Gmcritmax Maximum critical crystal gm µA/V
LSEDRV[1:0] = 10, medium high drive capability - - 1.7
LSEDRV[1:0] = 11, high drive capability - - 2.7

tSU(LSE)(2) Startup time VDD is stabilized - 2 - s

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST
microcontrollers”.
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This
value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

DS14548 - Rev 2 page 72/146

 STM32U073x8/B/C
Electrical characteristics

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.

Figure 19. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

CL1
OSC32_IN fLSE
32.768 kHz resonator Drive
CS programmable
amplifier

OSC32_OUT
CL2

DT70418V1
Note: CL1 and CL2 are external load capacitances. Cs (stray capacitance) is the sum of the device OSC32_IN/OSC32_OUT pins
equivalent parasitic capacitance (CS_PARA), and the PCB parasitic capacitance.

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

6.3.8 Internal clock source characteristics

The parameters given in Table 52. HSI16 oscillator characteristics are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Section 6.3.1: General operating conditions.
The provided curves are evaluated by characterization, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 52. HSI16 oscillator characteristics

Evaluated by characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

From code 127 to 128 -8 -6 -4

From code 63 to 64
TRIM HSI16 user trimming step -5.8 -3.8 –1.8 %
From code 191 to 192
For all other code increments 0.2 0.3 0.4

DuCy(HSI16)(1) Duty Cycle - 45 - 55 %

TA= 0 to 85 °C -1 - 1 %
∆Temp(HSI16) HSI16 oscillator frequency drift over temperature
TA= -40 to 125 °C -2 - 1.5 %

∆VDD(HSI16) HSI16 oscillator frequency drift over VDD VDD=1.62 V to 3.6 V -0.1 - 0.05 %

tsu (HSI16)(1) HSI16 oscillator start-up time - - 0.8 1.2 μs

tstab(HSI16)(1) HSI16 oscillator stabilization time - - 3 5 μs

IDD (HSI16)(1) HSI16 oscillator power consumption - - 155 190 μA

1. Specified by design, not tested in production.

DS14548 - Rev 2 page 73/146

 STM32U073x8/B/C
Electrical characteristics

Figure 20. HSI16 frequency versus temperature

MHz
16.4
+2%
16.3
+1.5%
16.2 +1%

16.1

16

15.9

-1%
15.8
-1.5%
15.7
-2%
15.6
-40 -20 0 20 40 60 80 100 120 °C

DT39299V1
min mean max

Multi-speed internal (MSI) RC oscillator

Table 53. MSI oscillator characteristics

Evaluated by characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

Range 0 98.7 100 101.3

Range 1 197.4 200 202.6
kHz
Range 2 394.8 400 405.2
Range 3 789.6 800 810.4
Range 4 0.987 1 1.013
Range 5 1.974 2 2.026
MSI mode
Range 6 3.948 4 4.052
Range 7 7.896 8 8.104
MHz
MSI frequency after factory Range 8 15.79 16 16.21
fMSI calibration, done at VDD = 3 V
and TA = 30 °C Range 9 23.69 24 24.31
Range 10 31.58 32 32.42
Range 11 47.38 48 48.62
Range 0 - 98.304 -
Range 1 - 196.608 -
kHz
Range 2 - 393.216 -
PLL mode
XTAL = 32.768 kHz Range 3 - 786.432 -
Range 4 - 1.016 -
MHz
Range 5 - 1.999 -

DS14548 - Rev 2 page 74/146

 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

Range 6 - 3.998 -
Range 7 - 7.995 -
MSI frequency after factory
PLL mode Range 8 - 15.991 -
fMSI calibration, done at VDD = 3 V MHz
XTAL = 32.768 kHz Range 9 - 23.986 -
and TA = 30 °C
Range 10 - 32.014 -
Range 11 - 48.005 -
TA = 0 to 85 °C -3.5 - 3
MSI oscillator frequency drift
∆TEMP(MSI)(1) MSI mode %
over temperature TA = -40 to 125 °C -8 - 6

VDD = 1.62 V to
-1.2 -
3.6 V
Range 0 to 3 0.5
VDD = 2.4 V to
-0.5 -
3.6 V
VDD = 1.62 V to
-2.5 -
MSI oscillator frequency drift 3.6 V
∆VDD(MSI)(1) MSI mode Range 4 to 7 0.7 %
over VDD (reference is 3 V) VDD = 2.4 V to
-0.8 -
3.6 V
VDD = 1.62 V to
-5 -
3.6 V
Range 8 to 11 1.2
VDD = 2.4 V to
-1.6 -
3.6 V

∆FSAMPLING TA = -40 to 85 °C - 1 2
Frequency variation in sampling
MSI mode %
(MSI)(1)(5) mode(2) TA = -40 to 125 °C - 2 4

for next
- - - 3.458
P_USB PLL mode transition
Period jitter for USB clock(3) ns
Jitter(MSI)(5) Range 11 for paired
- - - 3.916
transition
for next
- - - 2
MT_USB Medium term jitter for USB PLL mode transition
ns
Jitter(MSI)(5) clock(4) Range 11 for paired
- - - 1
transition

CC jitter(MSI)(5) RMS cycle-to-cycle jitter PLL mode Range 11 - - 60 - ps

P jitter(MSI)(5) RMS Period jitter PLL mode Range 11 - - 50 - ps

Range 0 - - 10 20
Range 1 - - 5 10
Range 2 - - 4 8
tSU(MSI)(5) MSI oscillator start-up time μs
Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
10 % of final
- - 0.25 0.5
frequency
PLL mode 5 % of final
tSTAB(MSI)(5) MSI oscillator stabilization time - - 0.5 1.25 ms
Range 11 frequency
1 % of final
- - - 2.5
frequency

MSI oscillator power MSI and Range 0 - - 0.6 1

IDD(MSI)(5) µA
consumption PLL mode

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 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

Range 1 - - 0.8 1.2

Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
Range 5 - - 6.5 9
MSI oscillator power MSI and
IDD(MSI)(5) Range 6 - - 11 15 µA
consumption PLL mode
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190

1. This is a deviation for an individual part once the initial frequency has been measured.
2. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
3. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter of MSI
@48 MHz clock.
4. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28 cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over 56 cycles.
5. Specified by design, not tested in production.

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Figure 21. Typical current consumption versus MSI frequency

High-speed internal 48 MHz (HSI48) RC oscillator

Table 54. HSI48 oscillator characteristics

VDD = 3 V, TA = -40 to 125 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 Frequency VDD = 3.0 V, TA = 30 °C - 48 - MHz

TRIM HSI48 user trimming step - - 0.11(1) 0.18(1) %

USER TRIM COVERAGE HSI48 user trimming coverage ±64 steps ±6(2) ±7(2) - %

DuCy(HSI48) Duty Cycle - 45(1) - 55(1) %

VDD = 3.0 V to 3.6 V,

- - ±3(2)
TA = -15 to 85 °C
Accuracy of the HSI48 oscillator over temperature
ACCHSI48_REL %
(factory calibrated) VDD = 1.65 V to 3.6 V,
- - ±4.5(2)
TA = -40 to 125 °C

VDD = 3 V to 3.6 V - 0.025(2) 0.05(2)

DVDD(HSI48) HSI48 oscillator frequency drift with VDD %
VDD = 1.65 V to 3.6 V - 0.05(2) 0.1(2)

tsu(HSI48) HSI48 oscillator start-up time - - 2.5(1) 6(1) μs

IDD(HSI48) HSI48 oscillator power consumption - - 340(1) 380(1) μA

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 STM32U073x8/B/C
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Symbol Parameter Conditions Min Typ Max Unit

Next transition jitter

NT jitter - - +/-0.15(1) - ns
Accumulated jitter on 28 cycles(3)
Paired transition jitter
PT jitter - - +/-0.25(1) - ns
Accumulated jitter on 56 cycles(3)

1. Specified by design, not tested in production.

2. Evaluated by characterization, not tested in production.
3. Jitter measurement are performed without clock source activated in parallel.

Figure 22. HSI48 frequency versus temperature

%
6

-2

-4

-6

DT40989V1
-50 -30 -10 10 30 50 70 90 110 130
°C
Avg min max

Low-speed internal (LSI) RC oscillator

Table 55. LSI oscillator characteristics

Evaluated by characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96

fLSI LSI Frequency kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34

tSU(LSI)(1) LSI oscillator start-up time - - 80 130 μs

tSTAB(LSI)(1) LSI oscillator stabilization time 5% of final frequency - 125 180 μs

IDD (LSI)(1) LSI oscillator power consumption - - 110 180 nA

1. Specified by design, not tested in production.

6.3.9 PLL characteristics

The parameters given in Table 56. PLL characteristics are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Section 6.3.1: General operating conditions.

Table 56. PLL characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLL_IN PLL input clock frequency(1) - 2.66 - 16 MHz

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 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

DPLL_IN PLL input clock duty cycle - 45 - 55 %

Voltage scaling Range 1 3.09 - 122

fPLL_P_OUT PLL multiplier output clock P MHz
Voltage scaling Range 2 3.09 - 40
Voltage scaling Range 1 12 - 128
fPLL_Q_OUT PLL multiplier output clock Q MHz
Voltage scaling Range 2 12 - 33
Voltage scaling Range 1 12 - 64
fPLL_R_OUT PLL multiplier output clock R MHz
Voltage scaling Range 2 12 - 16
Voltage scaling Range 1 96 - 344
fVCO_OUT PLL VCO output MHz
Voltage scaling Range 2 96 - 128
tLOCK PLL lock time - - 15 40 μs

RMS cycle-to-cycle jitter - 50 -

Jitter System clock 56 MHz ±ps
RMS period jitter - 40 -
VCO freq = 96 MHz - 200 260
IDD(PLL) PLL power consumption on VDDnot found VCO freq = 192 MHz - 300 380 μA
VCO freq = 344 MHz - 520 650

1. Make sure to use the appropriate division factor M to obtain the specified PLL input clock values.

6.3.10 Flash memory characteristics

Table 57. Flash memory characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions Typ Max Unit

- 85 125
tprog 64‑bit programming time µs
Burst mode 48 48
Normal programming 2.7 4.6
tprog_row Row (32 double word) programming time
Fast programming 1.7 2.8
Normal programming 21.8 36.6 ms
tprog_page Page (2 Kbytes) programming time
Fast programming 13.7 22.4
tERASE Page (2 Kbytes) erase time - 22.0 40.0

Normal programming 1.4 2.4

tprog_bank One 256-Kbyte bank programming time(1) s
Fast programming 0.9 1.5
tME Mass erase time - 22.1 40.1 ms

Programming 3 -
IDD(Flash A) Average consumption from VDD Page erase 3 -
Mass erase 5 mA
Programming, 2 μs peak duration 7 -
IDD(Flash P) Maximum current (peak)
Erase, 41 μs peak duration 7 -

1. The values provided also apply to devices with less flash memory than one 256-Kbyte bank.

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 STM32U073x8/B/C
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Table 58. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA = -40 to +105 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30

1 kcycle(2) at TA = 105 °C 15

1 kcycle(2) at TA = 125 °C 7
tRET Data retention Years
10 kcycles(2) at TA = 55 °C 30

10 kcycles(2) at TA = 85 °C 15

10 kcycles(2) at TA = 105 °C 10

1. Evaluated by characterization, not tested in production.

2. Cycling performed over the whole temperature range.

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed
by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional
disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF
capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 59. EMS characteristics. They are based on the EMS levels and classes
defined in application note AN1709.

Table 59. EMS characteristics

Symbol Parameter Conditions Level/Class

VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin to induce a functional
VFESD fHCLK = 54 MHz, LPQF80 2B
disturbance
conforming to IEC 61000-4-2
VDD = 3.3 V, TA = +25 °C,
Fast transient voltage burst limits to be applied through 100 pF on VDD
VEFTB fHCLK = 54 MHz, LPQF80 5A
and VSS pins to induce a functional disturbance
conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment
and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user
application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation
with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

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 STM32U073x8/B/C
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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually
forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring
(see application note AN1015).

Electromagnetic Interference
The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2
LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test
board and the pin loading.

Table 60. EMI characteristics for fHSE = 8 MHz and fHCLK = 54 MHz

Symbol Parameter Conditions Monitored frequency band Value Unit

0.1 MHz to 30 MHz 5

VDD = 3.6 V, TA = 25 °C, 30 MHz to 130 MHz 2

Peak dBµV
SEMI LQFP64 package 130 MHz to 1 GHz 1
compliant with IEC 61967-2 1 GHz to 2 GHz 8
Level 0.1 MHz to 2 GHz 2 -

1. Refer to AN1709 “EMI radiated test” section.

2. Refer to AN1709 “EMI level classification” section.

6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to
determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each
sample according to each pin combination. The sample size depends on the number of supply pins in the device
(3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Table 61. ESD absolute maximum ratings

TBD stands for "to be defined".
Maximum
Symbol Ratings Conditions Package Class Unit
value

Electrostatic discharge voltage TA = +25 °C, conforming to ANSI/ESDA/JEDEC

VESD(HBM) All 2D 2000
(human body model) JS-001
V
Electrostatic discharge voltage TA = +25 °C, conforming to ANSI/ESDA/ WLCSP42 TBD TBD
VESD(CDM)
(charge device model) JEDEC-002 All others C2a 500

1. Evaluated by characterization, not tested in production.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.

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 STM32U073x8/B/C
Electrical characteristics

Table 62. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +130 °C conforming to JESD78A II

6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for
standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give
an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens,
susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins
programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked
for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE),
out of conventional limits of induced leakage current on adjacent pins (out of the 5 µA/+0 µA range) or other
functional failure (for example reset occurrence or oscillator frequency deviation).
The characterization results are given in Table 63. I/O current injection susceptibility.
Negative induced leakage current is caused by negative injection and positive induced leakage current is caused
by positive injection.

Table 63. I/O current injection susceptibility

Evaluated by characterization, not tested in production.
Functional susceptibility
Symbol Description Unit
Negative injection Positive injection

Injected current on all pins except PA4, PA5 -5 N/A(1)

IINJ mA
Injected current on PA4, PA5 pins -5 0

1. Injection is not possible.

6.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 64. I/O static characteristics are derived from tests
performed under the conditions summarized in Section 6.3.1: General operating conditions. All I/Os are designed
as CMOS- and TTL-compliant.
Note: For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO configuration for
hardware settings and low-pow er consumption” available from the ST website www.st.com.

Table 64. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

I/O input low level voltage 1.62 V < VDDIOx < 3.6 V - - 0.3 x VDDIOx (2)
VIL (1)
0.39 x VDDIOx - V
I/O input low level voltage 1.62 V < VDDIOx < 3.6 V - -
0.06(3)

I/O input high level voltage 1.62 V < VDDIOx < 3.6 V 0.7 x VDDIOx (2) - -
VIH(1) V
I/O input high level voltage 1.62 V < VDDIOx < 3.6 V 0.49 x VDDIOX + 0.26 (3) - -

TT_xx, FT_xxx and NRST

Vhys(3) 1.62 V < VDDIOx < 3.6 V - 200 - mV
I/O input hysteresis
FT_xx input leakage VIN ≤ Max(VDDXXX)(6)(7) - - ±100
Ilkg(4) nA
current(3)(5)

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 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

FT_xx input leakage Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX) + 1 V(6)(7) - - 650

current(3)(5)
Max(VDDXXX) + 1 V < VIN ≤ 5.5 V(6)(7) - - 200

VIN ≤ Max(VDDXXX)(6)(7) - - ±150

Ilkg (4)
PC3 I/O Max(VDDXXX) ≤ VIN ≤ Max(VDDXXX) + 1 V(6)(7) - - 2500(3) nA

Max(VDDXXX) + 1 V < VIN ≤ 5.5 V(6)(7) - - 250

VIN ≤ Max(VDDXXX)(6) - - ±150

TT_xx input leakage
current Max(VDDXXX) ≤ VIN < 3.6V(6) - - 2000(3)

Weak pull-up equivalent

RPU VIN = VSS 25 40 55 kΩ
resistor(8)
Weak pull-down equivalent
RPD VIN = VDDIOx 25 40 55 kΩ
resistor(8)
CIO I/O pin capacitance - - 5 - pF

1. Refer to Figure 23. I/O input characteristics.

2. Tested in production.
3. Specified by design, not tested in production.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] × Ilkg(Max).
5. All FT_xx GPIOs except FT_u and PC3 I/O.
6. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.
7. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB) + 0.3 V, the internal Pull-up and Pull-Down resistors must be disabled.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS
contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than
the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 23. I/O
input characteristics.

DS14548 - Rev 2 page 83/146

 STM32U073x8/B/C
Electrical characteristics

Figure 23. I/O input characteristics

TTL requirement Vih min = 2V

DDIO
x
x>1
.62
0. 7xV or VDDIO
min = x+0
.26 f
nt Vi h 9xVD
DIO
eme r 0.4
quir <1 .62 o .62
S re VD DIOx
r VDDIO
x>1
MO .08< .06 fo
on C or 1 x-0
ucti +0 .05 f 9 xVDDIO
rod DIOx or 0.3
in p 0.61xVD x<1
.62
ted min = .08<V
DDIO
Tes for 1
n Vih x-0.1
sim ulatio 3 xVDDIO
d on = 0.4
Base il max TTL requirement Vil max = 0.8V
tion V 0.3xVdd
simula il max =
Based o n
re q u ir ement V
OS
ction CM
in produ
Tested

DT37613V1
Current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA
(with a relaxed VOL/VOH).
GPIOs PC13, PC14 and PC15 are supplied through the power switch, limiting source capability up to 3 mA only.
In the user application, the number of I/O pins which can drive current must be limited to respect the absolute
maximum rating specified in Section 6.2: Absolute maximum ratings:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum consumption of the MCU
sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 19. Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on
VSS, cannot exceed the absolute maximum rating ΣIVSS (see Table 19. Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Section 6.3.1: General operating conditions.
All I/Os are CMOS- and TTL-compliant (FT or TT unless otherwise specified).

Table 65. Output voltage characteristics

The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19. Voltage characteristics, ,
and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO.
Symbol Parameter Conditions Min Max Unit

VOL Output low level voltage for an I/O pin CMOS port (1) - 0.4
|IIO| = 8 mA(2)
VOH Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx - 0.4 -
V
VOL(3) Output low level voltage for an I/O pin TTL port(1) - 0.4
|IIO| = 8 mA(4)
VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V 2.4 -

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 STM32U073x8/B/C
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Symbol Parameter Conditions Min Max Unit

VOL (3)
Output low level voltage for an I/O pin PC13, PC14 and PC15 - 0.07
|IIO| = 3 mA
VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx - 0.35 -

VOL(3) Output low level voltage for an I/O pin |IIO = 20 mA(4) - 1.3

VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx - 1.3 -

VOL(3) Output low level voltage for an I/O pin |IIO| = 4 mA(2) - 0.45 V

VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 1.62 V VDDIOx - 0.45 -

|IIO| = 20 mA
- 0.4
VOLFM+ VDDIOx ≥ 2.7 V
(3)
Output low level voltage for an FT I/O pin in FM+ mode (FT I/O with "f" option)
|IIO| = 10 mA
- 0.4
VDDIOx ≥ 1.62 V

1. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
2. PC13, PC14 and PC15 are tested/characterized at their maximum current of 3 mA.
3. Specified by design, not tested in production.
4. Not applicable to PC13, PC14 and PC15.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24. I/O AC characteristics
definition and Table 66. I/O AC characteristics, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Section 6.3.1: General operating conditions.

Table 66. I/O AC characteristics

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the
RM0503 reference manual for a description of GPIO Port configuration register.
2. Specified by design, not tested in production.
Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1

Fmax Maximum frequency MHz
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5

00
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 52

Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 17

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 10

Fmax Maximum frequency MHz
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 50

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 15

01
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 9

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 16

Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 4.5

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 9

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 STM32U073x8/B/C
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Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25

Fmax Maximum frequency MHz
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(1)

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.5

10
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5.8

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 11

Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 2.5

C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 5

C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 120(1)

C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 50

Fmax Maximum frequency MHz
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 180(1)
11
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 75

C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 3.3

Tr/Tf Output rise and fall time ns
C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 6

Fmax Maximum frequency - 1 MHz

Fm+ C=50 pF, 1.62 V≤VDDIOx≤3.6 V
Tf Output fall time(2) - 5 ns

1. This value represents the I/O capability but the maximum system frequency is limited to 56 MHz.
2. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.

Figure 24. I/O AC characteristics definition

90% 10%

50% 50%

10% 90%

t r(IO)out t f(IO)out

Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.
DT32132V4

1. Refer to Table 66. I/O AC characteristics.

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Section 6.3.1: General operating conditions.

Table 67. NRST pin characteristics

Specified by design, not tested in production.

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 STM32U073x8/B/C
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Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST input low level voltage - - - 0.3 × VDDIOx

V
VIH(NRST) NRST input high level voltage - 0.7 × VDDIOx - -

Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV

RPU Weak pull-up equivalent resistor(1) VIN = VSS 25 40 55 kΩ

VF(NRST) NRST input filtered pulse - - - 70 ns

VNF(NRST) NRST input not filtered pulse 1.71 V ≤ VDD ≤ 3.6 V 350 - - ns

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal
(~10% order).

Figure 25. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 µF(3)

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the voltage level on the NRST pin can go above the VIH(NRST) minimum level
specified in Table 67. NRST pin characteristics during each power on, otherwise the device does not exit from
reset. This is applicable to all NRST configurations selected through the NRST_MODE[1:0] bitfield of the
FLASH_OPTR register, including GPIO mode.
3. The external capacitor on NRST must be placed as close as possible to the device.

6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is detected by the event
controller.

Table 68. EXTI Input Characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

PLEC Pulse length to event controller - 20 - - ns

6.3.17 Analog switches booster

Table 69. Analog switches booster characteristics

Specified by design, not tested in production.
Symbol Parameter Min Typ Max Unit

VDD Supply voltage 1.62 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs

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 STM32U073x8/B/C
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Symbol Parameter Min Typ Max Unit

Booster consumption for

- - 250
1.62 V ≤ VDD ≤ 2.0 V

Booster consumption for

IDD(BOOST) - - 500 µA
2.0 V ≤ VDD ≤ 2.7 V

Booster consumption for

- - 900
2.7 V ≤ VDD ≤ 3.6 V

6.3.18 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 70. ADC characteristics are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions
summarized in Section 6.3.1: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 70. ADC characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions(1) Min Typ Max Unit

VDDA Analog supply voltage - 1.62 - 3.6

VDDA ≥ 2 V 2 - VDDA V
VREF+ Positive reference voltage
VDDA < 2 V VDDA

Range 1 0.14 - 35
fADC ADC clock frequency MHz
Range 2 0.14 - 16
12 bits - - 2.50
10 bits - - 2.92
fs Sampling rate MSps
8 bits - - 3.50
6 bits - - 4.38
fADC = 35 MHz; 12 bits - - 2.33
fTRIG External trigger frequency MHz
12 bits - - fADC/15

VAIN(2) Conversion voltage range - VSSA - VREF+ V

RAIN External input impedance - - - 50 kΩ

Internal sample and hold

CADC - - 5 - pF
capacitor
tSTAB ADC power-up time - 2 Conversion cycle

fADC = 35 MHz 2.35 µs

tCAL Calibration time
- 82 1/fADC

CKMODE = 00 2 - 3 1/fADC

CKMODE = 01 6.5
tLATR Trigger conversion latency
CKMODE = 10 12.5 1/fPCLK

CKMODE = 11 3.5
0.043 - 4.59 µs
fADC = 35 MHz; VDDA > 2V
1.5 - 160.5 1/fADC
ts Sampling time
0.1 - 4.59 µs
fADC = 35 MHz; VDDA < 2V
3.5 - 160.5 1/fADC

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Symbol Parameter Conditions(1) Min Typ Max Unit

ADC voltage regulator start-up

tADCVREG_STUP - - - 20 µs
time
fADC = 35 MHz
0.40 - 4.95 µs
Resolution = 12 bits
Total conversion time
tCONV ts + 12.5 cycles for successive
(including sampling time)
Resolution = 12 bits approximation 1/fADC
= 14 to 173
Laps of time allowed between
tIDLE - - - 100 µs
two conversions without rearm
fs = 2.5 MSps - 410 -

IDDA(ADC) ADC consumption from VDDA fs = 1 MSps - 164 - µA

fs = 10 kSps - 17 -

fs = 2.5 MSps - 65 -

IDDV(ADC) ADC consumption from VREF+ fs = 1 MSps - 26 - µA

fs = 10 kSps - 0.26 -

1. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥
2.4 V.
2. VREF+ is internally connected to VDDA on some packages. Refer to Section 4: Pinouts/ballouts, pin description, and alternate functions for
further details.

Table 71. Maximum ADC RAIN

Sampling time at 35 MHz Max. RAIN (1)(2)

Resolution Sampling cycle at 35 MHz
[ns] (Ω)

1.5(3) 43 50

3.5 100 680

7.5 214 2200
12.5 357 4700
12 bits
19.5 557 8200
39.5 1129 15000
79.5 2271 33000
160.5 4586 50000

1.5(3) 43 68

3.5 100 820

7.5 214 3300
12.5 357 5600
10 bits
19.5 557 10000
39.5 1129 22000
79.5 2271 39000
160.5 4586 50000

1.5(3) 43 82

3.5 100 1500

8 bits
7.5 214 3900
12.5 357 6800

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Sampling time at 35 MHz Max. RAIN (1)(2)

Resolution Sampling cycle at 35 MHz
[ns] (Ω)

19.5 557 12000

39.5 1129 27000
8 bits
79.5 2271 50000
160.5 4586 50000

1.5(3) 43 390

3.5 100 2200

7.5 214 5600
12.5 357 10000
6 bits
19.5 557 15000
39.5 1129 33000
79.5 2271 50000
160.5 4586 50000

1. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥
2.4 V.
2. Specified by design, not tested in production.
3. Only allowed with VDDA > 2 V

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Table 72. ADC accuracy

1. Evaluated by characterization, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on another analog input.
It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive negative current.
Symbol Parameter Conditions(1) Min Typ Max Unit

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 3 6
TA = 25 °C

2 V < VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; - 3 6.5
ET Total unadjusted error LSB
TA = entire range

1.65 V < VDDA=VREF+ < 3.6 V;

TA = entire range
- 3 7.5
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 1.5 5
TA = 25 °C

2 V < VDDA = VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; - 1.5 5.5
EO Offset error LSB
TA = entire range

1.65 V < VDDA=VREF+ < 3.6 V;

TA = entire range
- 1.5 6
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 3 3.5
TA = 25 °C

2 V < VDDA = VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; - 3 5
EG Gain error LSB
TA = entire range

1.65 V < VDDA = VREF+ < 3.6 V;

TA = entire range
- 3 6.5
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - 1.2 2.5
TA = 25 °C

2 V < VDDA = VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; - 1.2 2.5
ED Differential linearity error LSB
TA = entire range

1.65 V < VDDA = VREF+ < 3.6 V;

TA = entire range
- 1.2 2.5
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

VDDA = VREF+ = 3 V;
fADC = 35 MHz;
EL Integral linearity error - 2.5 3 LSB
fs ≤ 2.5 MSps;
TA = 25 °C

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Symbol Parameter Conditions(1) Min Typ Max Unit

2 V < VDDA = VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; - 2.5 3.5
TA = entire range
EL Integral linearity error 1.65 V < VDDA = VREF+ < 3.6 V; LSB
TA = entire range
- 2.5 3.5
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; 10.1 10.2 -
TA = 25 °C

2 V < VDDA = VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; 9.6 10.2 -
ENOB Effective number of bits bit
TA = entire range

1.65 V < VDDA = VREF+ < 3.6 V;

TA = entire range
9.5 10.2 -
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; 62.5 63 -
TA = 25 °C

2 V < VDDA = VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; 59.5 63 -
SINAD Signal-to-noise and distortion ratio dB
TA = entire range

1.65 V < VDDA = VREF+ < 3.6 V;

TA = entire range
59 63 -
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; 63 64 -
TA = 25 °C

2 V < VDDA = VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; 60 64 -
SNR Signal-to-noise ratio dB
TA = entire range

1.65 V < VDDA = VREF+ < 3.6 V;

TA = entire range
60 64 -
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps; - -74 -73
TA = 25 °C

2 V < VDDA = VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps; - -74 -70
THD Total harmonic distortion dB
TA = entire range

1.65 V < VDDA = VREF+ < 3.6 V;

TA = entire range
- -74 -70
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;

1. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V.

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Figure 26. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
VSSA
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+

DT19880V6
Figure 27. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch
function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter

Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing

DT67871V3
VSS VSS VSSA

1. Refer to Table 70. ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad
capacitance (refer to Table 64. I/O static characteristics for the value of the pad capacitance). A high Cparasitic
value downgrades conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 64. I/O static characteristics for the values of Ilkg.
4. Refer to Section 3.6.1: Power supply schemes.

6.3.18.1 General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13. Power supply scheme. The 100 nF
capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

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6.3.19 Temperature sensor characteristics

Table 73. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VTS linearity with temperature - ±1 ±2 °C

Avg_Slope(2) Average slope 2.3 2.5 2.7 mV/°C

V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V

tSTART(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) - 8 15 µs

tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs

tS_temp (1)
ADC sampling time when reading the temperature 5 - - µs

IDD(TS)(1) Temperature sensor consumption from VDD, when selected by ADC - 4.7 7 µA

1. Specified by design, not tested in production.

2. Evaluated by characterization, not tested in production.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

6.3.20 VBAT monitoring characteristics

Table 74. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 3×39 - kΩ

Q Ratio on VBAT measurement - 3 - -

Er(1) Error on Q -10 - 10 %

tS_vbat(1) ADC sampling time when reading the VBAT 12 - - µs

1. Specified by design, not tested in production.

Table 75. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

VBRS = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS = 1 - 1.5 -

6.3.21 Digital-to-analog converter characteristics

Table 76. DAC characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

DAC output buffer OFF, DAC_OUT pin not

1.71 -
VDDA Analog supply voltage for DAC ON connected (internal connection only) 3.6
Other modes 1.80 -
V
DAC output buffer OFF, DAC_OUT pin not
1.71 -
VREF+ Positive reference voltage connected (internal connection only) VDDA
Other modes 1.80 -

RL Resistive load DAC output buffer ON connected to VSSA 5 - - kΩ

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Symbol Parameter Conditions Min Typ Max Unit

RL Resistive load DAC output buffer ON connected to VDDA 25 - - kΩ

RO Output Impedance DAC output buffer OFF 9.6 11.7 13.8 kΩ

VDD = 2.7 V - - 2
Output impedance sample and hold
RBON kΩ
mode, output buffer ON VDD = 2.0 V - - 3.5

VDD = 2.7 V - - 16.5

Output impedance sample and hold
RBOFF kΩ
mode, output buffer OFF VDD = 2.0 V - - 18.0

CL DAC output buffer ON - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF

VREF+
DAC output buffer ON 0.2 -
VDAC_OUT Voltage on DAC_OUT output - 0.2 V
DAC output buffer OFF 0 - VREF+

±0.5 LSB - 1.7 3

Normal mode ±1 LSB - 1.6 2.9
Settling time (full scale: for a 12-bit
code transition between the lowest DAC output buffer ON
±2 LSB - 1.55 2.85
and the highest input codes when CL ≤ 50 pF,
tSETTLING RL ≥ 5 kΩ ±4 LSB - 1.48 2.8 µs
DAC_OUT reaches final value
±0.5LSB, ±1 LSB, ±2 LSB, ±4 LSB,
±8 LSB - 1.4 2.75
±8 LSB)
Normal mode DAC output buffer OFF, ±1LSB, CL
- 2 2.5
= 10 pF

Wake-up time from off state (setting Normal mode DAC output buffer ON
- 4.2 7.5
tWAKEUP (1)
the ENx bit in the DAC Control CL ≤ 50 pF, RL ≥ 5 kΩ µs
register) until final value ±1 LSB Normal mode DAC output buffer OFF, CL ≤ 10 pF - 2 5
Normal mode DAC output buffer ON
PSRR VDDA supply rejection ratio - -80 -28 dB
CL ≤ 50 pF, RL = 5 kΩ, DC
Minimum time between two DAC_MCR:MODEx[2:0] = 000 or 001
1 - -
consecutive writes into the CL ≤ 50 pF; RL ≥ 5 kΩ
TW_to_W DAC_DORx register to guarantee a µs
correct DAC_OUT for a small DAC_MCR:MODEx[2:0] = 010 or 011
1.4 - -
variation of the input code (1 LSB) CL ≤ 10 pF

DAC output buffer ON,

- 0.7 3.5
CSH = 100 nF
Sampling time in sample and hold DAC_OUT pin connected ms
mode (code transition between the DAC output buffer
tSAMP - 10.5 18
lowest input code and the highest OFF, CSH = 100 nF
input code when DACOUT reaches
final value ±1LSB) DAC_OUT pin not
DAC output buffer
connected (internal - 2 3.5 µs
OFF
connection only)
Sample and hold mode,
Ileak Output leakage current - - -(2) nA
DAC_OUT pin connected
CIint Internal sample and hold capacitor - 5.2 7 8.8 pF

tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs

VREF+ = 3.6 V - 1500 -

Middle code offset for 1 trim code
Voffset µV
step VREF+ = 1.8 V - 750 -

No load, middle code

- 315 500
(0x800)
IDDA(DAC) DAC consumption from VDDA DAC output buffer ON µA
No load, worst code
- 450 670
(0xF1C)

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Symbol Parameter Conditions Min Typ Max Unit

No load, middle code

DAC output buffer OFF - - 0.2
(0x800)
IDDA(DAC) DAC consumption from VDDA 670 ₓ µA
315 ₓ Ton/
Sample and hold mode, CSH = 100 nF - Ton/
(Ton+Toff)(3)
(Ton+Toff)(3)

No load, middle code

- 185 240
(0x800)
DAC output buffer ON
No load, worst code
- 340 400
(0xF1C)
No load, middle code
DAC output buffer OFF - 155 205
(0x800)
IDDV(DAC) DAC consumption from VREF+ µA
185 ₓ 400 ₓ
Sample and hold mode, buffer ON, CSH = 100 nF,
- Ton/ Ton/
worst case
(Ton+Toff)(3) (Ton+Toff)(3)

155 ₓ 205 ₓ
Sample and hold mode, buffer OFF, CSH = 100 nF,
- Ton/ Ton/
worst case
(Ton+Toff)(3) (Ton+Toff)(3)

1. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
2. Refer to Table 64. I/O static characteristics.
3. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0503 reference manual for more details.

Figure 28. 12-bit buffered / non-buffered DAC

Buffered/non-buffered DAC

Buffer(1)

RLOAD

12-bit DAC_OUTx
digital-to-analog
converter
CLOAD
DT47959V2

(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads
directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in
the DAC_CR register.

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring
the BOFFx bit in the DAC_CR register.
.

Table 77. DAC accuracy

Specified by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

DAC output buffer ON - - ±2

DNL Differential non linearity(1)
DAC output buffer OFF - - ±2
- monotonicity 10 bits guaranteed
DAC output buffer ON LSB
- - ±4
CL ≤ 50 pF, RL ≥ 5 kΩ
INL Integral non linearity(2)
DAC output buffer OFF
- - ±4
CL ≤ 50 pF, no RL

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Symbol Parameter Conditions Min Typ Max Unit

DAC output buffer ON VREF+ = 3.6 V - - ±12

CL ≤ 50 pF, RL ≥ 5 kΩ VREF+ = 1.8 V - - ±25
Offset Offset error at code 0x800(2)
DAC output buffer OFF
- - ±8
CL ≤ 50 pF, no RL
LSB
DAC output buffer OFF
Offset1 Offset error at code 0x001(3) - - ±5
CL ≤ 50 pF, no RL

DAC output buffer ON VREF+ = 3.6 V - - ±5

OffsetCal Offset Error at code 0x800 after calibration
CL ≤ 50 pF, RL ≥ 5 kΩ VREF+ = 1.8 V - - ±7

DAC output buffer ON

- - ±0.5
CL ≤ 50 pF, RL ≥ 5 kΩ
Gain Gain error(4) %
DAC output buffer OFF
- - ±0.5
CL ≤ 50 pF, no RL
DAC output buffer ON
- - ±30
CL ≤ 50 pF, RL ≥ 5 kΩ
TUE Total unadjusted error LSB
DAC output buffer OFF
- - ±12
CL ≤ 50 pF, no RL
DAC output buffer ON
TUECal Total unadjusted error after calibration - - ±23 LSB
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ - 71.2 -
1 kHz, BW 500 kHz
SNR Signal-to-noise ratio dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz - 71.6 -
BW 500 kHz
DAC output buffer ON
- -78 -
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
THD Total harmonic distortion dB
DAC output buffer OFF
- -79 -
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON
- 70.4 -
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD Signal-to-noise and distortion ratio dB
DAC output buffer OFF
- 71 -
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON
- 11.4 -
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
ENOB Effective number of bits bits
DAC output buffer OFF
- 11.5 -
CL ≤ 50 pF, no RL, 1 kHz

1. Difference between two consecutive codes - 1 LSB.

2. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
3. Difference between the value measured at Code (0x001) and the ideal value.
4. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and
from code giving 0.2 V and (VREF+ - 0.2) V when buffer is ON.

6.3.22 Voltage reference buffer characteristics

Table 78. VREFBUF characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage Normal mode VRS = 0 2.4 - 3.6 V

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Symbol Parameter Conditions Min Typ Max Unit

Normal mode VRS = 1 2.8 - 3.6
VDDA Analog supply voltage VRS = 0 1.65 - 2.4
Degraded mode(1)
VRS = 1 1.65 - 2.8

VRS = 0 2.038 2.042 2.046 V

VREFBUF_ Iload = 100 µA VRS = 1 2.497 2.5 2.503

Voltage reference output
OUT T = 30 °C VRS = 0 VDDA-150 mV - VDDA

VRS = 1 VDDA-150 mV - VDDA

TRIM Trim step resolution - - - ±0.05 ±0.1 %

CL Load capacitor - - 0.5 1 1.5 µF

esr Equivalent Serial Resistor of Cload - - - - 2 Ω

Iload Static load current - - - - 4 mA

Iload = 500 µA - 200 1000

Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 500

Iload_reg Load regulation 500 μA ≤ Iload ≤4 mA Normal mode - 50 500 ppm/mA

TCoeff_vrefbuf Temperature coefficient of VREFBUF(2) -40 °C < TJ < +125 °C - - 50 ppm/ °C

DC 40 60 -
PSRR Power supply rejection dB
100 kHz 25 40 -

CL = 0.5 µF(3) - 300 350

tSTART Start-up time CL = 1.1 µF(3) - 500 650 µs

CL = 1.5 µF(3) - 650 800

Control of maximum DC current drive on

IINRUSH - - 8 - mA
VREFBUF_OUT during start-up phase(4)
Iload = 0 µA - 16 25

IDDA(VREFBUF) VREFBUF consumption from VDDA Iload = 500 µA - 18 30 µA

Iload = 4 mA - 35 50

1. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA - drop voltage).
2. The temperature coefficient at VREF+ output is the sum of TCoeff_vrefint and TCoeff_vrefbuf.
3. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
4. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in the range [2.4 V
to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.

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6.3.23 Comparator characteristics

Table 79. COMP characteristics

Specified by design, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.62 - 3.6

VIN Comparator input voltage range - 0 - VDDA V

VBG(1) Scaler input voltage - VREFINT

VSC Scaler offset voltage - - ±5 ±10 mV

BRG_EN=0 (bridge disable) - 200 300 nA

IDDA(SCALER) Scaler static consumption from VDDA
BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs

VDDA ≥ 2.7 V - - 5
High-speed mode
VDDA < 2.7 V - - 7
Comparator startup time to reach
tSTART VDDA ≥ 2.7 V - - 15 µs
propagation delay specification
Medium mode
VDDA < 2.7 V - - 25

Ultra-low-power mode - - 40
VDDA ≥ 2.7 V - 55 80
High-speed mode ns
VDDA < 2.7 V - 65 100
tD(2) Propagation delay with 100 mV overdrive
Medium mode - 0.55 0.9
µs
Ultra-low-power mode - 4 7
Full common mode
Voffset Comparator offset error - - ±5 ±20 mV
range
No hysteresis - 0 -
Low hysteresis 4 8 16
Vhys Comparator hysteresis mV
Medium hysteresis 8 15 30
High hysteresis 15 27 52
Static - 400 600
Ultra-low-power mode With 50 kHz ±100 mV nA
- 1200 -
overdrive square signal
Static - 5 7
IDDA(COMP) Comparator consumption from VDDA Medium mode With 50 kHz ±100 mV
- 6 -
overdrive square signal
µA
Static - 70 100
High-speed mode With 50 kHz ±100 mV
- 75 -
overdrive square signal
Ibias Comparator input bias current - - - -(3) nA

1. Refer to Table 25. Embedded internal voltage reference.

2. Evaluated by characterization, not tested in production.
3. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 64. I/O static characteristics.

DS14548 - Rev 2 page 99/146

 STM32U073x8/B/C
Electrical characteristics

6.3.24 Operational amplifiers characteristics

Table 80. OPAMP characteristics

Evaluated by characterization, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage(1) - 1.8 - 3.6 V

CMIR Common mode input range - 0 - VDDA V

25 °C, No Load on output. - - ±1.5

VIOFFSET Input offset voltage mV
All voltage/temperature - - ±3
Normal mode - ±5 -
∆VIOFFSET Input offset voltage drift μV/°C
Low-power mode - ±10 -
TRIMOFFSETP Offset trim step at low common
- - 0.8 1.1
TRIMLPOFFSETP input voltage (0.1 ₓ VDDA)
mV
TRIMOFFSETN Offset trim step at high common
- - 1 1.35
TRIMLPOFFSETN input voltage (0.9 ₓ VDDA)
Normal mode - - 500
ILOAD Drive current Low-power VDDA ≥ 2 V
- - 100
mode
µA
Normal mode - - 450
ILOAD_PGA Drive current in PGA mode Low-power VDDA ≥ 2 V
- - 50
mode

Resistive load Normal mode 4 - -

RLOAD (connected to VSSA or to Low-power VDDA < 2 V
VDDA) 20 - -
mode
kΩ
Resistive load in PGA mode Normal mode 4.5 - -
RLOAD_PGA (connected to VSSA or to Low-power VDDA < 2 V
VDDA) 40 - -
mode
CLOAD Capacitive load - - - 50 pF

Normal mode - -85 -

CMRR Common mode rejection ratio dB
Low-power mode - -90 -
CLOAD ≤ 50 pf,
Normal mode 70 85 -
RLOAD ≥ 4 kΩ DC
PSRR Power supply rejection ratio dB
Low-power CLOAD ≤ 50 pf,
72 90 -
mode RLOAD ≥ 20 kΩ DC

Normal mode 550 1600 2200

VDDA ≥ 2.4 V
Low-power (OPA_RANGE = 1) 100 420 600
mode
GBW Gain Bandwidth Product kHz
Normal mode 250 700 950
VDDA < 2.4 V
Low-power (OPA_RANGE = 0) 40 180 280
mode
Normal mode - 700 -
Low-power VDDA ≥ 2.4 V
Slew rate - 180 -
mode
SR(2) (from 10 and 90% of output V/ms
voltage) Normal mode - 300 -
Low-power VDDA < 2.4 V
- 80 -
mode

AO Open loop gain Normal mode 55 110 - dB

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 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

AO Open loop gain Low-power mode 45 110 - dB

VDDA
Normal mode - -
Iload = max or Rload = min Input -100
VOHSAT (2)
High saturation voltage
Low-power at VDDA.
VDDA -50 - -
mode mV
Normal mode - - 100
Iload = max or Rload = min Input
VOLSAT(2) Low saturation voltage Low-power at 0. - - 50
mode
Normal mode - 74 -
φm Phase margin °
Low-power mode - 66 -
Normal mode - 13 -
GM Gain margin dB
Low-power mode - 20 -
CLOAD ≤ 50 pf,
Normal mode RLOAD ≥ 4 kΩ follower - 5 10
configuration
tWAKEUP Wake up time from OFF state. µs
CLOAD ≤ 50 pf,
Low-power
RLOAD ≥ 20 kΩ - 10 30
mode
follower configuration
Ibias OPAMP input bias current General purpose input - - -(3) nA

- 2 -
- 4 -
PGA gain(2) Non inverting gain value - -
- 8 -
- 16 -
PGA Gain = 2 - 80/80 -
120/
PGA Gain = 4 - -
40
R2/R1 internal resistance
Rnetwork 140/ kΩ/kΩ
values in PGA mode(4) PGA Gain = 8 - -
20
150/
PGA Gain = 16 - -
10
Delta R Resistance variation (R1 or R2) - -15 - 15 %
PGA gain error PGA gain error - -1 - 1 %
Gain = 2 - - GBW/2 -

PGA bandwidth for different non Gain = 4 - - GBW/4 -

PGA BW MHz
inverting gain Gain = 8 - - GBW/8 -
Gain = 16 - - GBW/16 -
at 1 kHz, Output loaded with
Normal mode - 500 -
4 kΩ
Low-power at 1 kHz, Output loaded with
- 600 -
mode 20 kΩ
en Voltage noise density nV/√Hz
at 10 kHz, Output loaded with
Normal mode - 180 -
4 kΩ
Low-power at 10 kHz, Output loaded with
- 290 -
mode 20 kΩ
OPAMP consumption from
IDDA(OPAMP)(2) Normal mode no Load, quiescent mode - 120 260 µA
VDDA

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 STM32U073x8/B/C
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Symbol Parameter Conditions Min Typ Max Unit

OPAMP consumption from Low-power
IDDA(OPAMP)(2) no Load, quiescent mode - 45 100 µA
VDDA mode

1. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V

2. Evaluated by characterization, not tested in production.
3. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 64. I/O static characteristics.
4. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between OPAMP inverting
input and ground. The PGA gain =1+R2/R1

6.3.25 LCD controller characteristics

The devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from
the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter.

Table 81. LCD controller characteristics

Specified by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

VLCD LCD external voltage - - 3.6

VLCD0 LCD internal reference voltage 0 - 2.62 -

VLCD1 LCD internal reference voltage 1 - 2.76 -

VLCD2 LCD internal reference voltage 2 - 2.89 -

VLCD3 LCD internal reference voltage 3 - 3.04 - V

VLCD4 LCD internal reference voltage 4 - 3.19 -

VLCD5 LCD internal reference voltage 5 - 3.32 -

VLCD6 LCD internal reference voltage 6 - 3.46 -

VLCD7 LCD internal reference voltage 7 - 3.62 -

Buffer OFF
0.2 - 2
(BUFEN=0 is LCD_CR register)
Cext VLCD external capacitance μF
Buffer ON
1 - 2
(BUFEN=1 is LCD_CR register)
Buffer OFF
Supply current from VDD at VDD = 2.2 V - 3 -
(BUFEN=0 is LCD_CR register)
ILCD(1) μA
Buffer OFF
Supply current from VDD at VDD = 3.0 V - 1.5 -
(BUFEN=0 is LCD_CR register)
Buffer OFF
- 0.5 -
(BUFFEN = 0, PON = 0)
Buffer ON
- 0.6 -
(BUFFEN = 1, 1/2 Bias)
IVLCD Supply current from VLCD (VLCD = 3 V) μA
Buffer ON
- 0.8 -
(BUFFEN = 1, 1/3 Bias)
Buffer ON
- 1 -
(BUFFEN = 1, 1/4 Bias)
RHN Total High Resistor value for Low drive resistive network - 5.5 - MΩ

RLN Total Low Resistor value for High drive resistive network - 240 - kΩ

V44 Segment/Common highest level voltage - VLCD -

V34 Segment/Common 3/4 level voltage - 3/4 VLCD - V

V23 Segment/Common 2/3 level voltage - 2/3 VLCD -

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 STM32U073x8/B/C
Electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

V12 Segment/Common 1/2 level voltage - 1/2 VLCD -

V13 Segment/Common 1/3 level voltage - 1/3 VLCD -

V
V14 Segment/Common 1/4 level voltage - 1/4 VLCD -

V0 Segment/Common lowest level voltage - 0 -

1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected.

6.3.26 Timer characteristics

The parameters given in the following tables are specified by design, and not tested in production.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics
(output compare, input capture, external clock, PWM output).

Table 82. TIMx characteristics

TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz 20.8 - ns

- 0 fTIMxCLK/2 MHz
fEXT Timer external clock frequency on CH1 to CH4
fTIMxCLK = 48 MHz 0 24 MHz

TIMx (except TIM2) - 16

ResTIM Timer resolution bit
TIM2 - 32

- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 48 MHz 0.0208 1363.1 µs

- - 65536 × 65536 tTIMxCLK

tMAX_COUNT Maximum possible count with 32-bit counter
fTIMxCLK = 48 MHz - 89.34 s

Table 83. IWDG min/max timeout period at 32 kHz (LSI)

The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC
period of uncertainty.
Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF Unit

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768

Table 84. WWDG min/max timeout at 56 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.0358 2.2938
2 1 0.0717 4.5875 ms
4 2 0.1434 9.1750

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 STM32U073x8/B/C
Electrical characteristics

Prescaler WDGTB Min timeout value Max timeout value Unit

8 3 0.2867 18.3501 ms

6.3.27 I2C-bus interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
When the I2C peripheral is properly configured, the I2C timings requirements are specified by design, and not
tested in production (refer to RM0503 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is
disabled, but is still present. Only FT_f I/O pins support Fm+ low level output current maximum requirement. Refer
to Section 6.3.14: I/O port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Table 85. I2C analog filter characteristics

Specified by design, not tested in production.
Symbol Parameter Min Max Unit

tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(1) 205(2) ns

1. Spikes with widths below tAF(min) are filtered.

2. Spikes with widths above tAF(max) are not filtered

6.3.28 USART characteristics

Unless otherwise specified, the parameters given in Table 86 are derived from tests performed under the ambient
temperature, fPCLK frequency and supply voltage conditions summarized in Section 6.3.1: General operating
conditions. The additional general conditions are:
• Output speed is set to OSPEEDRy[1:0] = 11 (output speed)
• Capacitive load CL = 30 pF
• Measurement points are done at CMOS levels: 0.5×VDD
• Voltage scale is set to VOS[1:0] = 01
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternatefunction
characteristics (NSS, CK, TX, and RX for USART).

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 STM32U073x8/B/C
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Table 86. USART characteristics

Symbol Parameter Conditions Min Typ Max Unit

Master mode - - 6.75

fCK USART clock frequency MHz
Slave mode - - 18
tsu(NSS) NSS setup time tker + 2 - -
Slave mode
th(NSS) NSS hold time 0.5 - -

tw(CKH) SCK high time

Master mode 1 / fCK / 2 - 1 1 / fCK / 2 1 / fCK / 2 + 1
tw(CKL) SCK low time

Master mode 22 - -
tsu(RX) Data input setup time
Slave mode 5 - -
Master mode 0 - - nsnsns
th(RX) Data input hold time
Slave mode 0.5 - -
Master mode 0 0.5 1

tv(TX) Data output valid time, Slave mode, 2.7 V ≤ VDD ≤ 3.6 V 16 - 19.5

Slave mode, 1.71 V ≤ VDD ≤ 3.6 V 16 - 27.5

Master mode 0 - -
th(TX) Data output hold time
Master mode 10 - -

Figure 29. USART timing diagram in SPI master mode

1/fCK
tw(CKH)
CPHA=0
CK output

CPOL=0

CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CK output

CPOL=0

CPHA=1
CPOL=1
tsu(RX) th(RX)

RX input MSB IN BIT6 IN LSB IN

TX output MSB OUT BIT1 OUT LSB OUT

DT65386V3

tv(TX) th(TX)

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 STM32U073x8/B/C
Electrical characteristics

Figure 30. USART timing diagram in SPI slave mode

NSS input

1/fCK th(NSS)

tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input

CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)

TX output First bit OUT Next bits OUT Last bit OUT

tsu(RX) th(RX)

DT65387V3
RX input First bit IN Next bits IN Last bit IN

6.3.29 SPI characteristics

Unless otherwise specified, the parameters given in Table 87 for SPI are derived from tests performed under the
ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Section 6.3.1: General
operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 × VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO for SPI).

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 STM32U073x8/B/C
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Table 87. SPI characteristics

Evaluated by characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit

Master mode receiver/full duplex

1.71 < VDD < 3.6 V 27
Voltage Range 1
Master mode transmitter
1.71 < VDD < 3.6 V 27
Voltage Range 1
Slave mode receiver
fSCK 1.71 < VDD < 3.6 V 27
SPI clock frequency Voltage Range 1 - - MHz
1/tc(SCK)
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V 27(1)
Voltage Range 1
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V 21.5(1)
Voltage Range 1
Voltage Range 2 9.5
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4 - -

th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2 - -

TPCLK
tw(SCKH)
SCK high and low time Master mode TSCK2 - 1.5(2) TSCK2(2) TSCK2 + 1.5(2)
tw(SCKL)

tsu(MI) Master mode 3 - -

Data input setup time ns
tsu(SI) Slave mode 3 - -

th(MI) Master mode 2.5 - -

Data input hold time ns
th(SI) Slave mode 2.5 - -

ta(SO) Data output access time Slave mode 10 12.5 20 ns

tdis(SO) Data output disable time Slave mode 6 7.5 18 ns

Slave mode 2.7 < VDD < 3.6 V

- 15 18
Voltage Range 1
Slave mode 1.71 < VDD < 3.6 V
tv(SO) - 15 23
Data output valid time Voltage Range 1 ns
Slave mode 1.71 < VDD < 3.6 V
- 22 30
Voltage Range 2
tv(MO) Master mode - 3 5.5

th(SO) Slave mode 10 - -

Data output hold time ns
th(MO) Master mode 1 - -

1. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase
preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while
Duty(SCK) = 50 %.
2. TSCK2 = TPCLK × prescaler / 2

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Electrical characteristics

Figure 31. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH)
CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

DT41658V2
MOSI input First bit IN Next bits IN Last bit IN

Figure 32. SPI timing diagram - slave mode and CPHA = 1

NSS input

tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
CPOL=0
SCK input

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)
DT41659V2

MOSI input First bit IN Next bits IN Last bit IN

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

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 STM32U073x8/B/C
Electrical characteristics

Figure 33. SPI timing diagram - master mode

High

NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

DT72626V1
tv(MO) th(MO)

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

6.3.30 USB characteristics

The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed
device operation).

Table 88. USB electrical characteristics

TA = -40 to 125 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit

VDDUSB USB transceiver operating voltage - 3.0(1) - 3.6 V

Tcrystall_less USB crystal-less operation temperature - -15 - 85 °C

tSTARTUP(2) USB transceiver startup time - - - 1.0 μs

RPUI Embedded USB_DP pull-up value during idle - 900 1250 1600

RPUR Embedded USB_DP pull-up value during reception - 1400 2300 3200 Ω

ZDRV(2) Output driver impedance(3) High and low driver 28 36 44

1. USB functionality is ensured down to 2.7 V, but some USB electrical characteristics are degraded in 2.7 to 3.0 V range.
2. Specified by design, not tested in production.
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-). The matching impedance is already included in
the embedded driver.

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Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 Device marking

Refer to technical note "Reference device marking schematics for STM32 microcontrollers and microprocessors"
(TN1433 ) available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the
marking areas versus pin 1 / ball A1.
Parts marked as "ES", "E" or accompanied by an engineering sample notification letter, are not yet qualified and
therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection.

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 STM32U073x8/B/C
Package information

7.2 UFQFPN32 package information (A0B8)

This UFQFPN is a 32 pins, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package.

Figure 34. UFQFPN32 - Outline

fff C A B
D2 EXPOSED PAD

b
fff C A B

bbb C A B
ddd C

E2
e

PIN 1 identifier
Chamfer or
Circular arc shape
e L

R0.20 BOTTOM VIEW

A
ccc C A3
A1
eee C SEATING PLANE

DETAIL A
FRONT VIEW

A3
A1
SEATING PLANE

ddd C

PIN 1 IDENTIFIER
B
C
LASER MARKING AREA

DETAIL A

E
A0B8_UFQFPN32_ME_V4

D A

TOP VIEW

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.

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 STM32U073x8/B/C
Package information

Table 89. UFQFPN32 - Mechanical data

millimeters(1) inches(2)
Symbol
Min Typ Max Min Typ Max

A(3)(4) 0.50 0.55 0.60 0.0197 0.0217 0.0236

A1(5) 0.00 - 0.05 0.000 - 0.0020

A3(6) - 0.15 - - 0.0060 -

b(7) 0.18 0.25 0.30 0.0071 0.010 0.0118

D(8)(9) 5.00 BSC 0.1969 BSC

D2 3.50 3.60 3.70 0.139 0.143 0.147

E(8)(9) 5.00 BSC 0.1969 BSC

E2 3.50 3.60 3.70 0.139 0.143 0.147

e(9) - 0.50 - - 0.02 -

N(10) 32

K 0.15 - - 0.006 - -
L 0.30 - 0.50 0.0119 - 0.0199
R 0.09 - - 0.004 - -

1. All dimensions are in millimetres. Dimensioning and tolerancing schemes are conform to ASME Y14.5M-2018 except
European .
2. Values in inches are converted from mm and rounded to 4 decimal digits.
3. UFQFPN stands for Ultra thin Fine pitch Quad Flat Package No lead: A ≤ 0.60mm / Fine pitch e ≤ 1.00mm.
4. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured
perpendicular to the seating plane.
5. A1 is the vertical distance from the bottom surface of the plastic body to the nearest metallized package feature.
6. A3 is the distance from the seating plane to the upper surface of the terminals.
7. Dimension b applies to metallized terminal. If the terminal has the optional radius on the other end of the terminal, the
dimension b must not be measured in that radius area.
8. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.
9. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances refer to
Table 90
10. N represents the total number of terminals.

Table 90. Tolerance of form and position

Tolerance of form and position(2) Tolerance of form and position(3)

Symbol(1)
In millimeters In inches

aaa 0.15 0.006

bbb 0.10 0.004
ccc 0.10 0.004
ddd 0.05 0.002
eee 0.10 0.004
fff 0.10 0.004

1. For the tolerance of form and position definitions see Table 91.
2. All dimensions are in millimetres. Dimensioning and tolerancing schemes are conform to ASME Y14.5M-2018 except
European .
3. Values in inches are converted from mm and rounded to 4 decimal digits.

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 STM32U073x8/B/C
Package information

Table 91. Tolerance of form and position symbol definition

Symbol Definition

The bilateral profile tolerance that controls the position of the plastic body sides. The centres of the profile zones are
aaa
defined by the basic dimensions D and E.
The tolerance that controls the position of the terminals with respect to Datums A and B. The centre of the tolerance
bbb
zone for each terminal is defined by basic dimension e as related to datums A and B.
ccc The tolerance located parallel to the seating plane in which the top surface of the package must be located.
The tolerance that controls the position of the terminals to each other. The centres of the profile zones are defined
ddd
by basic dimension e.
The unilateral tolerance located above the seating plane wherein the bottom surface of all terminals must be located
eee
= coplanarity
The tolerance that controls the position of the exposed metal heat feature. The centre of the tolerance zone is the
fff
data defined by the centrelines of the package body

Figure 35. UFQFPN32 - Footprint example

5.50

3.75

0.65

3.60

5.50 3.75

3.60
0.50

A0B8_UFQFPN32_FP_V1
0.25

3.75 A0B8_FP_V2

1. Dimensions are expressed in millimeters.

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 STM32U073x8/B/C
Package information

7.3 WLCSP42 package information (B0K9)

This WLCSP is a 42-ball, 2.82 x 2.93 mm, 0.40 mm pitch, wafer level chip scale package.

Figure 36. WLCSP42 - Outline

A2 BALL
LOCATION
11 9 7 5 3 1
12 10 8 6 4 2
eD
A
B eS
C

D1 D
E (Datum A)

SD F
G

eE (Datum B)
b (N balls)
SE ddd C A B
eee C
E1

BOTTOM VIEW

Detail A
A

Seating plane

C 8
FRONT VIEW

bbb C
Back side coating
A3
Silicon
E B
Solder balls
A2

A1
Seating plane
D 8 C ccc C

(Datum A)
DETAIL A

aaa C A
(Datum B)
(4x)
A2 CORNER
9
TOP VIEW
B0K9_WLCSP42_ME_V2

1. Drawing is not to scale

Table 92. WLCSP42 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 0.58 - - 0.0228

A1(3) - 0.17 - - 0.0067 -

DS14548 - Rev 2 page 114/146

 STM32U073x8/B/C
Package information

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A2 - 0.38 - - 0.0150 -
A3 (if applicable) - 0.025 - - 0.0010 -

b(4) 0.23 0.25 0.28 0.0090 0.0098 0.0110

D(5) 2.82 BSC 0.1110 BSC

D1(5) 2.078 BSC 0.0818 BSC

E(5) 2.93 BSC 0.1153 BSC

E1(5) 2.200 BSC 0.0866 BSC

eD(5)(6) 0.693 BSC 0.0273 BSC

eE(5)(6) 0.400 BSC 0.0157 BSC

eS(5)(6) 0.400 BSC 0.0157 BSC

N(7) 42

SD(5)(8) 0.346 BSC 0.0136 BSC

SE(5)(8) 0.300 BSC 0.0118 BSC

aaa(9) 0.030 0.0012

bbb(9) 0.060 0.0023

ccc(9) 0.030 0.0012

ddd(9) 0.015 0.0006

eee(9) 0.050 0.0020

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. The profile height A is the distance from the seating plane to the highest point on the package. It is measured perpendicular
to the seating plane.
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to Datum C.
5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances, refer to form
and position table. On the drawing, these dimensions are framed. For the tolerances, refer to form and position values.
6. e represents the solder balls grid pitch(es).
7. N represents the total number of balls.
8. Basic dimensions SD & SE are defining the ball matrix position with respect to datums A and B.
9. Tolerance of form and position drawing

Figure 37. WLCSP42 - Footprint example

Dpad

Dsm

DS14548 - Rev 2 page 115/146

 STM32U073x8/B/C
Package information

1. Dimensions are expressed in millimeters.

Table 93. WLCSP42 - Example of PCB design rules

Dimension Values

Pitch 0.400 mm
Dpad 0,250 mm
Dsm 0.325 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.325 mm
Stencil thickness 0.100 mm

7.3.1 Device marking for WLCSP42

The following figure gives an example of topside marking versus ball A2 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 38. WLCSP42 marking example

Ball A2 identifier

Product
identification(1)

Revision code

Date code

Y WW
DT72630V2

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting from
such use. In no event will ST be liable for the customer using any of these engineering samples in production.
ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a
qualification activity.

DS14548 - Rev 2 page 116/146

 STM32U073x8/B/C
Package information

7.4 LQFP48 package information (5B)

This LQFP is a 48-pins, 7 x 7 mm, low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 39. LQFP48- Outline(15.)

BOTTOM VIEW
Package LQFP48 (package code 5B)
4x N/4 TIPS
aaa C A-B D
2 1
(2)
R1

H
R2

B
B-
D 1/4

N
(6)

O
TI
C
SE
B GAUGE PLANE
E 1/4

0.25
S
B
bbb H A-B D 4x
L
3
(13) (L1)
0.05 (N – 4)x e (1) (11)

A A2 C SECTION A-A

(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING

1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)

SECTION B-B

TOP VIEW

Table 94. LQFP48 - Mechanical data

millimeters inches(14.)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630

A1(12.) 0.05 - 0.15 0.0020 - 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b(9.)(11.) 0.17 0.22 0.27 0.0067 0.0087 0.0106

b1(11.) 0.17 0.20 0.23 0.0067 0.0079 0.0090

c(11.) 0.09 - 0.20 0.0035 - 0.0079

c1(11.) 0.09 - 0.16 0.0035 - 0.0063

DS14548 - Rev 2 page 117/146

 STM32U073x8/B/C
Package information

millimeters inches(14.)
Symbol
Min Typ Max Min Typ Max

D(4.) 9.00 BSC 0.3543 BSC

D1(4.)(5.) 7.00 BSC 0.2756 BSC

E(4.) 9.00 BSC 0.3543 BSC

E1(4.)(5.) 7.00 BSC 0.2756 BSC

e 0.50 BSC 0.1970 BSC

L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF

N(13.) 48

θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -

aaa(1.)(7.) 0.20 0.0079

bbb(1.)(7.) 0.20 0.0079

ccc(1.)(7.) 0.08 0.0031

ddd(1.)(7.) 0.08 0.0031

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25
mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width
to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius
or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch
packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits
15. Drawing is not to scale.

DS14548 - Rev 2 page 118/146

 STM32U073x8/B/C
Package information

Figure 40. LQFP48 - Footprint example

0.50
1.20

36 25
37 24 0.30

0.20

9.70 7.30

48 13
1 12

5.80

9.70
5B_LQFP48_FP_V1

1. Dimensions are expressed in millimeters.

DS14548 - Rev 2 page 119/146

 STM32U073x8/B/C
Package information

7.5 UFQFPN48 package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 41. UFQFPN48 - Outline

EXPOSED PAD
D1

E2 E1
e

PIN 1 idenfier
L
D2
BOTTOM VIEW
A
A3
A1
SEATING PLANE

C
DETAIL A
ddd C
LEADS COPLANARITY
FRONT VIEW

A1 A
SEATING PLANE

ddd C
PIN 1 IDENTIFIER C
LASER MAKER AREA

E
DT_A0B9_UFQFPN48_ME_V4

D
TOP VIEW

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the under side of the UFQFPN48 package. It is recommended to connect and
solder this back-side pad to PCB ground.

DS14548 - Rev 2 page 120/146

 STM32U073x8/B/C
Package information

Table 95. UFQFPN48 - Mechanical data

Millimeters Inches (1)

Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118

D(2) 6.900 7.000 7.100 0.2717 0.2756 0.2795

D1 5.400 5.500 5.600 0.2126 0.2165 0.2205

D2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244

E(2) 6.900 7.000 7.100 0.2717 0.2756 0.2795

E1 5.400 5.500 5.600 0.2126 0.2165 0.2205

E2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244

e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031

1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.
3. Dimensions D2 and E2 are not in accordance with JEDEC.

Figure 42. UFQFPN48 - Footprint example

7.30

6.20

48 37

1 36

0.20 5.60

7.30

DT_A0B9_UFQFPN48_FP_V3
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80

1. Dimensions are expressed in millimeters.

DS14548 - Rev 2 page 121/146

 STM32U073x8/B/C
Package information

7.6 LQFP64 package information (5W)

This is a 64-pins, 10 x 10 mm, low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 43. LQFP64 - Outline(15.)

BOTTOM VIEW Package LQFP64 (package code 5W)

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4

0.25
(6)
S
B

E 1/4 L
4x N/4 TIPS
3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A

(13) (N – 4)x e

C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C

D (4)

(5) (2) D1 (9) (11)

(10)
D (3) b WITH PLATING
N (4)

1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)

A A SECTION B-B
(Section A-A)

TOP VIEW

Table 96. LQFP64 - Mechanical data

millimeters inches(14.)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630

A1(12.) 0.05 - 0.15 0.0020 - 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b(9.)(11.) 0.17 0.22 0.27 0.0067 0.0087 0.0106

b1(11.) 0.17 0.20 0.23 00067 0.0079 0.0091

DS14548 - Rev 2 page 122/146

 STM32U073x8/B/C
Package information

millimeters inches(14.)
Symbol
Min Typ Max Min Typ Max

c(11.) 0.09 - 0.20 0.0035 - 0.0079

c1(11.) 0.09 - 0.16 0.0035 - 0.0063

D(4.) 12.00 BSC 0.4724 BSC

D1(2.)(5.) 10.00 BSC 0.3937 BSC

E(4.) 12.00 BSC 0.4724 BSC

E1(2.)(5.) 10.00 BSC 0.3937 BSC

e 0.500 BSC 0.0197 BSC

L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -

N(13.) 64

Θ 0° 3.5° 7° 0° 3.5° 7°
Θ1 0° - - 0° - -
Θ2 10° 12° 14° 10° 12° 14°
Θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -

aaa(1.) 0.20 0.0079

bbb(1.) 0.20 0.0079

ccc(1.) 0.08 0.0031

ddd(1.) 0.08 0.0031

Notes
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25
mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width
to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius
or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch
packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

DS14548 - Rev 2 page 123/146

 STM32U073x8/B/C
Package information

Figure 44. LQFP64 - Footprint example

48 33

0.3
49 0.5 32

12.7

10.3

10.3
64 17

1.2
1 16

7.8

12.7

1. Dimensions are expressed in millimeters.

DS14548 - Rev 2 page 124/146

 STM32U073x8/B/C
Package information

7.7 UFBGA64 package information (A019)

This UFBGA is a 64-ball, 5 x 5 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Note: See list of notes in the notes section.

Figure 45. UFBGA64 - Outline(13.)

E1

e SE

H
G
SD F
E e
D1
D
C
B
A

1 2 3 4 5 6 7 8
Øb (N balls)
A1 ball pad corner Ø eee M C A B
Ø fff M C
Mold resin
ccc C

Substrate

Detail A A
SIDE VIEW Seating plane

(8)

A1 A2
B C
E A Detail A
A1 ball pad corner ddd C
(9) Solder balls

(DATUM A)

D
A019_UFBGA64_ME_V2

(DATUM B)

aaa C
TOP VIEW (4X)

Table 97. UFBGA64 - Mechanical data

millimeters(1.) inches (12.)

Symbol
Min. Typ. Max. Min. Typ. Max.

A(2.)(3.) - - 0.60 - - 0.0236

A1(4.) 0.05 - - 0.0020 - -

A2 - 0.43 - - 0.0169 -

DS14548 - Rev 2 page 125/146

 STM32U073x8/B/C
Package information

millimeters(1.) inches (12.)

Symbol
Min. Typ. Max. Min. Typ. Max.

b(5.) 0.23 0.28 0.33 0.0090 0.0110 0.0130

D(6.) 5.00 BSC 0.1969 BSC

D1 3.50 BSC 0.1378 BSC

E 5.00 BSC 0.1969 BSC
E1 3.50 BSC 0.1378 BSC

e(9.) 0.50 BSC 0.0197 BSC

N(10.) 64

SD(11.) 0.25 BSC 0.0098 BSC

SE(11.) 0.25 BSC 0.0098 BSC

aaa 0.15 0.0059

ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart European projection.
2. UFBGA stands for ultra profile fine pitch ball grid array: 0.50 mm < A ≤ 0.65 mm / fine pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured
perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary datum
C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances
refer to form and position table. On the drawing these dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or more solder balls that
support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner chamfer,
ink or metallized markings, or other feature of package body or integral heat slug. A distinguish feature is
allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner
is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the position of the centre
ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale

DS14548 - Rev 2 page 126/146

 STM32U073x8/B/C
Package information

Figure 46. UFBGA64 - Footprint example

DT_BGA_WLCSP_FT_V1
Dpad

Dsm

Table 98. UFBGA64 - Recommended PCB design rules (0.50 mm pitch BGA)

Dimension Recommended values

Pitch 0.50 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask registration
Dsm
tolerance)
Stencil opening 0.280 mm aperture diameter
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm

DS14548 - Rev 2 page 127/146

 STM32U073x8/B/C
Package information

7.8 LQFP80 package information (9X)

This is a 80-pins, 12 x 12 mm, low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 47. LQFP80 - Outline(15.)

BOTTOM VIEW

2 1
(2)
R1
R2

B
H

B-
N
O
TI
C
SE
B GAUGE PLANE

0.25
S
D 1/4 (6) B
L
3
(L1) (1) (11)
E 1/4
4x N/4 TIPS SECTION A-A
aaa C A-B D bbb H A-B D 4x

(N – 4)x e (13)
C
A
(9) (11)
0.05 A2 A1(12) b ddd C A-B D ccc C b WITH
PLATING
D (4)
(2) (5) D1
e D (3) (11) (11)
(10)
N c c1
(4)

1
2
3
E 1/4 b1 BASE METAL
(11)
(3)
(3) A (6) B SECTION B-B
D 1/4
E1 E
(2)
(5)

A A

9X_LQFP80_ME_V2
(Section A-A)

TOP VIEW

Table 99. LQFP80 - Mechanical data

millimeters inches(14.)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630

A1(12.) 0.05 - 0.15 0.0020 - 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b(9.)(11.) 0.17 0.22 0.27 0.0067 0.0087 0.0106

b1(11.) 0.17 0.20 0.23 00067 0.0079 0.0091

c(11.) 0.09 - 0.20 0.0035 - 0.0079

c1(11.) 0.09 - 0.16 0.0035 - 0.0063

DS14548 - Rev 2 page 128/146

 STM32U073x8/B/C
Package information

millimeters inches(14.)
Symbol
Min Typ Max Min Typ Max

D(4.) 14.00 BSC 0.5512 BSC

D1(2.)(5.) 12.00 BSC 0.4724 BSC

E(4.) 14.00 BSC 0.5512 BSC

E1(2.)(5.) 12.00 BSC 0.4724 BSC

e 0.50 BSC 0.0197 BSC

L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 - 1.00 - - 0.0394 -

N(13.) 80

Θ 0° 3.5° 7° 0° 3.5° 7°
Θ1 0° - - 0° - -
Θ2 10° 12° 14° 10° 12° 14°
Θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -

aaa(1.) 0.20 0.0079

bbb(1.) 0.20 0.0079

ccc(1.) 0.08 0.0031

ddd(1.) 0.08 0.0031

Notes
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25
mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width
to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius
or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch
packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

DS14548 - Rev 2 page 129/146

 STM32U073x8/B/C
Package information

Figure 48. LQFP80 - Footprint example

0.5

1.25
0.3
14.70

12.30

9X_LQFP80_FP_V1
1.2

9.80

14.70

1. Dimensions are expressed in millimeters.

DS14548 - Rev 2 page 130/146

 STM32U073x8/B/C
Package information

7.9 UFBGA81 package information (B0B8)

This UFBGA is a 81-ball, 5 x 5 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Note: See list of notes in the notes section.

Figure 49. UFBGA81 - Outline(13.)

E1

e SE

J
H
G
SD F e
E D1
D
C
B
A

A1 ball pad
corner 1 2 3 4 5 6 7 8 9
Øb (N balls)
BOTTOM VIEW Ø eee M C A B
Ø fff M C

DETAIL A

A
SIDE VIEW C

B E A
Mold resin
8 A1 ball pad ccc C
corner
(DATUM A)
Seating
plane
7

B0B8_UFBGA81_ME_DT_V1
D
Substrate A1 A2
(DATUM B)
Solder balls
ddd C
(4x)
aaa C
DETAIL A

Table 100. UFBGA81 - Mechanical data

millimeters(1.) inches (12.)

Symbol
Min. Typ. Max. Min. Typ. Max.

A(2.)(3.) - - 0.60 - - 0.0236

A1(4.) 0.05 - - 0.0020 - -

A2 - 0.43 - - 0.0169 -

b(5.) 0.23 0.28 0.33 0.0090 0.0110 0.0130

D(6.) 5.00 BSC 0.1969 BSC

D1 3.50 BSC 0.1378 BSC

DS14548 - Rev 2 page 131/146

 STM32U073x8/B/C
Package information

millimeters(1.) inches (12.)

Symbol
Min. Typ. Max. Min. Typ. Max.

E 5.00 BSC 0.1969 BSC

E1 3.50 BSC 0.1378 BSC

e(9.) 0.50 BSC 0.0197 BSC

N(10.) 81

SD(11.) 0.25 BSC 0.0098 BSC

SE(11.) 0.25 BSC 0.0098 BSC

aaa 0.15 0.0059

ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart European projection.
2. UFBGA stands for ultra profile fine pitch ball grid array: 0.50 mm < A ≤ 0.65 mm / fine pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured
perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary datum
C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances
refer to form and position table. On the drawing these dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or more solder balls that
support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner chamfer,
ink or metallized markings, or other feature of package body or integral heat slug. A distinguish feature is
allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner
is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the position of the centre
ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale

DS14548 - Rev 2 page 132/146

 STM32U073x8/B/C
Package information

Figure 50. UFBGA81 - Footprint example

DT_BGA_WLCSP_FT_V1
Dpad

Dsm

Table 101. UFBGA81 - Example of PCB design rules (0.50 mm pitch BGA)

Dimension Values

Pitch 0.50 mm
Dpad 0.250 mm
0.300 mm typ. (depends on the soldermask registration
Dsm
tolerance)
Stencil opening 0.356 mm aperture diameter
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm

7.10 Package thermal characteristics

The operating junction temperature, TJ, must never exceed the maximum given in Section 6.3.1: General
operating conditions.
The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:
operating conditions, is:
T J max = TA max + PD max × Θ JA
where:
• TAmax is the maximum ambient temperature, in °C.
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W.
• PD = PINT + PI/O
– PINT is the power dissipation contribution from product to IDD and VDD, expressed in Watts.
– PI/O is the power dissipation contribution from output ports where:
PI/O = VOL × IOL + VDDIOx − VOH × IOH taking into account the actual VOL/IOL and
VOH/IOH of the I/Os at low and high level in the application.

Table 102. Package thermal characteristics

Symbol Parameter Package Value Unit

UFQFPN32 39.9
WLCSP42 62.9
ΘJA Thermal resistance junction-ambient °C/W
LQFP48 53.2
UFQFPN48 29.5

DS14548 - Rev 2 page 133/146

 STM32U073x8/B/C
Package information

Symbol Parameter Package Value Unit

LQFP64 43.9
UFBGA64 54.2
ΘJA Thermal resistance junction-ambient
LQFP80 42.4
UFBGA81 51.5
UFQFPN32 21.8
WLCSP42 38.2
LQFP48 28.1
UFQFPN48 13.8
ΘJB Thermal resistance junction-board
LQFP64 28.6
UFBGA64 37.3
°C/W
LQFP80 26.7
UFBGA81 34.4
UFQFPN32 16.8
WLCSP42 3.9
LQFP48 16.5
UFQFPN48 10.3
ΘJC Thermal resistance junction-top case
LQFP64 13.9
UFBGA64 15.4
LQFP80 13.6
UFBGA81 15.4

7.10.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
available on www.jedec.org.
• For information on thermal management, refer to application note "Guidelines for thermal management on
STM32 applications" (AN5036) available on www.st.com.

DS14548 - Rev 2 page 134/146

 STM32U073x8/B/C
Ordering information

8 Ordering information

Example: STM32 U 073 M C T 6 TR

Device family

STM32 = Arm®-based 32-bit microcontroller

Product type
U = Ultra!-low-power

Device subfamily
073 = STM32U073xx

Pin count
K = 32 pins
H = 42 balls
C = 48 pins
R = 64 pins/balls
M = 80/81 pins/balls

Flash memory size

8 = 64 Kbytes of flash memory
B = 128 Kbytes of flash memory
C = 256 Kbytes of flash memory

Package
T = LQFP ECOPACK2
U = UFQFPN ECOPACK2
I = UFBGA ECOPACK2
Y = WLCSP ECOPACK2

Temperature range
3 = Industrial temperature range, –40 to 125 °C (130 °C junction)
6 = Industrial temperature range, –40 to 85°C (105 °C junction)

Packing
TR = Tape and reel
xxx = Programmed parts

Note: For a list of available options (such as speed and package) or for further information on any aspect of this
device, contact your nearest ST sales office.

DS14548 - Rev 2 page 135/146

 STM32U073x8/B/C
Ordering information

Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST
product(s) identified in this documentation may be certified by various security certification bodies and/or may
implement our own security measures as set forth herein. However, no level of security certification and/or built-in
security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the
customer needs both in relation to the ST product alone, as well as when combined with other components and/or
software for the customer end product or application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such as Platform
Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms
(www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received
security certification along with the level and current status of such certification, either visit the relevant
certification standards website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can change from time to
time, customers should re-check security certification status/level as needed. If an ST product is not shown
to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST
products. These certification bodies are therefore independently responsible for granting or revoking
security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations,
assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard
technologies which may be used in conjunction with an ST product are based on standards which were not
developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open
technologies or for any methods which have been or may be developed to bypass, decrypt or crack such
algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections
against all attacks, including, for example, against advanced attacks which have not been tested for,
against new or unidentified forms of attack, or against any form of attack when using an ST product outside
of its specification or intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance against such
attacks. As such, regardless of the incorporated security features and/or any information or support that
may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for
meets their needs, both in relation to the ST product alone and when incorporated into a customer end
product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like),
including but not limited to any enhanced security features added by ST, are provided on an "AS IS"
BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

DS14548 - Rev 2 page 136/146

 STM32U073x8/B/C

Revision history
Table 103. Document revision history

Date Revision Changes

01-Mar-2024 1 Initial release.

Updated ULPMark™-CP value on cover page.

Added Section 3.22: Touch sensing controller (TSC).
Updated Table 39. Current consumption in Stop 1 mode.
18-Mar-2024 2
Added IDD (Stop 2) maximum values in Table 40. Current consumption in Stop 2
mode.
Added IDD (SRAM2) maximum values in Table 41. Current consumption in Standby
mode.

DS14548 - Rev 2 page 137/146

 STM32U073x8/B/C
Contents

Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.1 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6.4 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.9 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9.1 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9.2 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.12 Direct memory access controller (DMA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.13 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.14.1 Nested vectored interrupt controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.15 Cyclic redundancy check calculation unit (CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.16 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.16.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.16.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.16.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.17 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.18 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.19 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DS14548 - Rev 2 page 138/146

 STM32U073x8/B/C
Contents

3.20 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.21 Liquid crystal controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.22 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.23 True random-number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.24.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.24.2 General-purpose timers (TIM2, 3, 15, 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.24.4 Low-power timers (LPTIM1, LPTIM2, and LPTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.24.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.24.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.24.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.25 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.26 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.27 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . . . . . . . . 24
3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . 25
3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.30 Universal serial bus device (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.31 Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.31.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Pinouts/ballouts, pin description, and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . .27
4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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 STM32U073x8/B/C
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6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.6 Wake-up time from low-power modes and voltage scaling transition times . . . . . . . . . . . . 68
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.15 NRST pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . . . . . . . . . . . . . . . . 87
6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.18 Analog-to-digital converter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.19 Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.20 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.21 Digital-to-analog converter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.23 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.24 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.27 I2C-bus interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.28 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.29 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.30 USB characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.2 UFQFPN32 package information (A0B8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.3 WLCSP42 package information (B0K9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.3.1 Device marking for WLCSP42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.4 LQFP48 package information (5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.5 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.6 LQFP64 package information (5W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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Contents

7.7 UFBGA64 package information (A019) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.8 LQFP80 package information (9X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.9 UFBGA81 package information (B0B8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.10 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.10.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

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List of tables

List of tables
Table 1. Device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Functionalities depending on the mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Temperature sensor calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. STM32U073x8/B/C pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 15. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. Operating conditions at power-up / power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Current consumption in Run and Low-power run modes, code with data processing running from flash memory,
bypass mode, ART enabled (cache ON, prefetch OFF), HSE clock used as system clock . . . . . . . . . . . . . . . . . 49
Table 27. Current consumption in Run and Low-power run modes, code with data processing running from flash memory, ART
enabled (cache ON, prefetch OFF), MSI clock used as system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Current consumption in Run and Low-power run modes, code with data processing running from flash memory,
bypass mode, ART disabled (cache ON, prefetch OFF), HSE clock used as system clock . . . . . . . . . . . . . . . . 51
Table 29. Current consumption in Run and Low-power run modes, code with data processing running from flash memory,
bypass mode, ART disabled (cache ON, prefetch OFF), MSI clock used as system clock . . . . . . . . . . . . . . . . . 52
Table 30. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, bypass
mode, HSE clock used as system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, MSI clock
used as system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. Typical current consumption in Run and Low-power run modes, with different codes running from flash memory,
ART enabled (cache ON, prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 33. Typical current consumption in Run and Low-power run modes, with different codes running from flash memory,
ART disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . 56
Table 35. Current consumption in Sleep and Low-power sleep modes, flash memory ON, HSE clock used as system clock 56
Table 36. Current consumption in Sleep and Low-power sleep modes, flash memory ON, MSI clock used as system clock . 57
Table 37. Current consumption in Sleep and Low-power sleep modes, flash memory in power-down mode . . . . . . . . . . . . 58
Table 38. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 39. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 40. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 41. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 42. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 43. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 44. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 45. Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 46. Regulator mode transition times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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Table 47. Wake-up time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 48. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 49. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 50. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 51. LSE oscillator characteristics (fLSE = 32.768 kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 52. HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 53. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 54. HSI48 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 55. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 56. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 57. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 58. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 59. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 60. EMI characteristics for fHSE = 8 MHz and fHCLK = 54 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 61. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 62. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 63. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 64. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 65. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 66. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 67. NRST pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 68. EXTI Input Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 69. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 70. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 71. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 72. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 73. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 74. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 75. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 76. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 77. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 78. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 79. COMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 80. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 81. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 82. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 83. IWDG min/max timeout period at 32 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 84. WWDG min/max timeout at 56 MHz (PCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 85. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 86. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 87. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 88. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 89. UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 90. Tolerance of form and position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 91. Tolerance of form and position symbol definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table 92. WLCSP42 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table 93. WLCSP42 - Example of PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 94. LQFP48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 95. UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 96. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 97. UFBGA64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 98. UFBGA64 - Recommended PCB design rules (0.50 mm pitch BGA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 99. LQFP80 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 100. UFBGA81 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 101. UFBGA81 - Example of PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

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 STM32U073x8/B/C
List of tables

Table 102. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 103. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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 STM32U073x8/B/C
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6
Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4. WLCSP42 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5. LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6. UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7. LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. UFBGA81 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 14. Current consumption measurement scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. AC timing diagram for high-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 17. AC timing diagram for low-speed external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 20. HSI16 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 21. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 22. HSI48 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 23. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 26. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 27. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function . . . . . . . . . 93
Figure 28. 12-bit buffered / non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 29. USART timing diagram in SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 30. USART timing diagram in SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 31. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 32. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 33. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 34. UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Figure 35. UFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Figure 36. WLCSP42 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Figure 37. WLCSP42 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Figure 38. WLCSP42 marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Figure 39. LQFP48- Outline(15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Figure 40. LQFP48 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Figure 41. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 42. UFQFPN48 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 43. LQFP64 - Outline(15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 44. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 45. UFBGA64 - Outline(13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 46. UFBGA64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 47. LQFP80 - Outline(15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 48. LQFP80 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 49. UFBGA81 - Outline(13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 50. UFBGA81 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

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 STM32U073x8/B/C

IMPORTANT NOTICE – READ CAREFULLY

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DS14548 - Rev 2 page 146/146