EE537 Circuit Simulation Lab

Experiment 6

Name: Ahmad Raza Ansari

ID Number: 2024EEM1016 October 4, 2024

AIM: A differential amplifier with NMOS input transistors and resistive load is shown in Fig.
1 IREF = 100 µA, Vincm = 900 mV, (W/L)M 1 = (W/L)M 2 = 20 µ/1 µ, (W/LM3 = (W/L)M4
= 2 µ/1 µ, RD = 10 KΩ. Derive the expressions for: 1) the small signal differential voltage
gain(Av,dm ), 2) the small signal common-mode voltage gain (Av,cm ).

1 Plot Vout1 , Vout2 , Vp , ID1 , ID2 vs common mode input voltage.

Sweep the common mode input voltage from 0 to Vdd .
We sketched a differential amplifier with NMOS as input transistors and resistive load as shown in
Fig. 1. We first make a common potential and differential potential separately and take reference
to the NMOS input transistor. For common mode input voltage sweep we have to fix differential
voltage to zero and in this circuit, we are using the current mirror concept that is we are mirroring
Iref as Iss.

Figure 1: Differential amplifier with NMOS input transistors

We know the equation of Vout1 , Vout2 , Vp , ID1 , ID2 as shown in 1, 2 and 3.

RD I SS
I out1 = I out2 = V DD − (1)
2
V p = V in1 − V GS1 = V in2 − V GS2 (2)
I SS = I D1 + I D2 (3)

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 The meaning of these symbols is shown in the above equation:

• Iout1 is the current through resistor 1.

• Iout2 is the current through resistor 2.

• Vout1 is the ouput voltage from transistor 1.

• Vout2 is the ouput voltage from transistor 2.

• Vp is the voltage at P.

• RD is the resistance between VDD and Vout .

• ISS is the total current or current through M3 transistor.

Plot of these parameters

We verified these plots from Behzad Razavi’s book and these plots. we note that M1 and M2 turn
on if Vin,CM ≥ VT H . Beyond this point, ID1 and ID2 continue to increase, and VP also rises. In
a sense, M1 and M2 constitute a source follower, forcing VP to track Vin,CM . For a sufficiently
high Vin,CM , the drain-source voltage of M3 exceeds VGS3 − VT H3 , allowing the device to operate
in saturation. The total current through M1 and M2 then remains constant. We conclude that for
proper operation, Vin,CM ≥ VGS1 + (VGS3 - VT H3 ) as shown in figure 2.

(a) Vout1 (b) Vout2 (c) VP

(d) Iout1 (e) Iout2

Figure 2: Plot of various parameters vs common mode input voltage

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2 Plot Vout1 , Vout2 , ,Vp , Vout1 - Vout2 ,ID1 , ID2 vs differential input volt-
age for a common mode input voltage of 0.9 V. Sweep the dif-
ferential input voltage from -400 mV to 400 mV .
The circuit remains the same but we have to change the input voltage configuration. we are fixing
the common voltage at 900 mV and varying differential voltage from -400 mV to 400 mV and we
are comparing the result from Behzad Razavi’s book and verifying the result that we get from the
simulation.

Figure 3: Differential amplifier with NMOS input transistors

Plot of these parameters

Vout1 As you increase the differential input voltage from -400mV to +400mV, Vout1 will grad-
ually decrease for a differential pair. This is because as one side of the differential pair is turned
on more strongly, the output voltage at the corresponding node Vout1 will drop. For negative dif-
ferential input voltage: Vout1 will start near the positive supply rail (if the transistor is off). For
positive differential input voltage: Vout1 will drop towards a lower voltage (approaching ground if
fully on).
Vout2 will have the opposite behavior of Vout1 .
Vout1 - Vout2 Trend: This plot will give you the differential output voltage. It will vary symmetri-
cally around zero. The plot will have a steep slope when the differential input voltage is near zero
(the region where the transistors are in active mode). For Vin,dif f = 0: The differential output
(Vout1 - Vout2 ) is zero. For negative Vin,dif f Vout1 will be larger than Vout2 , and the difference will
increase. For positive Vin,dif f Vout2 will be larger than Vout1 , and the difference will increase in the
opposite direction.
Vp : Vp typically refers to the output common mode voltage. This will remain roughly constant if
you have perfect current matching and an ideal differential pair, but it can shift slightly depending
on circuit imbalances or non-idealities.
ID1 refers to the drain current of the first transistor. As the differential input voltage increases,
ID1 will increase as well (assuming Vout1 decreases). For negative Vin,dif f : ID1 will be small (as
the transistor is less active). For positive Vin,dif f : ID1 will increase significantly as the transistor
turns on more.
ID2 refers to the drain current of the second transistor. This will behave oppositely to ID1 .

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 (a) Vout1 (b) Vout2 (c) VP

(d) Vout1 - Vout2 (e) Iout1 (f) Iout2

Figure 4: Plot of various parameters vs differential input voltage

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3 Plot differential mode gain(Av,dm ) with common mode input
voltage sweep from 0 to Vdd . What is the observed input com-
mon mode range(ICMR).
The circuit remains the same but we are change the input voltage configuration for finding differ-
ential mode gain. Use a small AC signal of 1V to create a differential input across the differential
amplifier. This small signal will allow you to calculate the differential gain while sweeping the
common-mode voltage.

Figure 5: Differential amplifier with NMOS input transistors

Plot of differential mode gain

The plot will show how the differential gain changes as the common-mode input voltage is swept
from 0V to Vdd. The differential gain should remain relatively constant within the ICMR.
ICMR (Input Common Mode Range): This is the common-mode input voltage range where the
amplifier maintains proper operation and provides consistent gain. Outside this range, the amplifier
will lose gain, marking the limits of its input range. the range of ICMR is V2 -V1 = 0.95V.

Figure 6: Plot of differential mode gain

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4 Plot the differential mode gain(Av,dm ), common mode to dif-
ferential mode gain (Av,cmdm ), common mode to common mode
gain (Av,cmcm ) vs. frequency. Verify the low-frequency values
from calculations and simulations.
Differential mode gain (Av,dm ):

At low frequencies, the differential gain tends to remain constant. Still, as frequency increases,
parasitic capacitances and other frequency-dependent effects reduce the gain, leading to a roll-off
in the high-frequency region. The frequency response of Av,dm can be analyzed using AC sweep
analysis, and key performance metrics such as bandwidth and midband gain can be extracted.

Figure 7: Differential mode gain (Av,dm )

Common mode to differential mode gain (Av,cmdm ):

At low frequencies,Av,cmdm is typically small, as common-mode signals are largely rejected. How-
ever, as frequency increases, parasitic capacitances and inductances can cause imbalances, leading
to a higher,AV,cmdm Therefore, it is important to analyze this gain over a wide frequency range to
ensure sufficient common-mode rejection across the amplifier’s operating bandwidth.

Figure 8: Common mode to differential mode gain (Av,cmdm )

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Common mode to common mode gain (Av,cmcm )

The common-mode to common-mode gain (Av,cmcm ) represents how much of a common-mode

signal applied to the inputs is reflected at the output as a common-mode signal. This parameter
is crucial in evaluating the performance of differential amplifiers and circuits because ideal differ-
ential amplifiers should reject common-mode signals completely, resulting in an Av,cm-cm of zero.
However, in practical circuits, there is always a small common-mode gain due to mismatches in
component values, parasitics, and non-idealities in the active devices.
In AC analysis, (Av,cmcm ) typically varies with frequency. At lower frequencies, common-mode gain
is often minimal but may increase at higher frequencies due to parasitic capacitances and other
frequency-dependent effects in the circuit. This highlights the importance of ensuring that Av,cm-
cm remains low over the entire operating frequency range to maintain effective noise rejection.

Figure 9: Common mode to differential mode gain (Av,cmdm )

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5 Plot the differential mode gain(Av,dm ), common mode to dif-
ferential mode gain (Av,cmdm ), common mode to common mode
gain (Av,cmcm ) and CMRR vs. frequency with 10 percentage
mismatch in RD .
Differential mode gain(Av,dm )

The 10 percent mismatch in the load resistors of RD f the MOSFET differential amplifier results
in a small but measurable deviation in the differential mode gain (Av,dm ). At low frequencies, the
gain is relatively unaffected, staying close to the ideal value. However, at mid to high frequencies,
the gain decreases more rapidly due to the mismatch, which amplifies parasitic effects and intro-
duces asymmetry in the output signals. For practical applications, this highlights the importance
of careful resistor matching to maintain high differential mode gain and performance across a wide
frequency range.

Figure 10: Differential mode gain(Av,dm ) of mismatch

Common mode to common mode gain (Av,cmcm )

The 10 percent mismatch in the load resistance of RD of the differential amplifier results in a clear
increase in the Common mode to common mode gain (Av,cmcm At low frequencies, the impact of
the mismatch is less pronounced, but as the frequency increases, the common-mode gain grows
significantly due to both the mismatch and frequency-dependent parasitic effects. This mismatch
also leads to a degradation in the common mode rejection ratio (CMRR), making the circuit less
effective at rejecting common-mode noise and interference.

Figure 11: Common mode to common mode gain (Av,cmcm of mismatch

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 Common mode to differential mode gain (Av,cmdm )

The 10 percent mismatch in the load resistance of RD results in a significant increase in the
Common mode to differential mode gain (Av,cmdm ) While the mismatch has a relatively small
impact at low frequencies, it becomes more pronounced at mid and high frequencies, where the
common-mode signals are partially converted into differential signals. This conversion degrades
the common-mode rejection of the differential amplifier, allowing noise and interference that are
present in the common-mode signal to appear as differential output.

Figure 12: Common mode to differential mode gain (Av,cmdm ) of mismatch

CMRR

This circuit remains the same but we copy it twice to take CMRR if we did not take it twice
it becomes zero that’s why we take it twice and differentiate nodes so that we can take CMRR that
is non-zero zero as shown in figure 13 circuit given below.

Figure 13: CMRR of mismatch

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Plot of CMRR

The simulation results clearly demonstrate that transistor mismatch significantly impacts the
CMRR of a differential amplifier. As mismatch increases, the ability of the amplifier to reject
common-mode signals deteriorates, leading to poorer performance in applications requiring high
precision and signal integrity. I got 57 dB of CMRR as shown in figure 14. CMRR is a criti-
cal parameter for differential amplifiers, defined as the ratio of the differential mode gain to the
common-mode gain. Ideally, a differential amplifier should amplify differential signals while re-
jecting common-mode signals. However, mismatches between transistors can lead to poor CMRR
performance.

Figure 14: CMRR of mismatch

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6 Plot the power spectral density of input referred noise and out-
put noise. Also present the integrated noise summary. The
integration bandwidth is from 1 Hz to π2 f3dB .
The circuit remains the same and we are finding noise of this circuit.The analysis of input-referred
noise and output noise provides essential insights into the noise performance of the differential
amplifier. The Power Spectral Density plots illustrate how noise varies with frequency, while the
integrated noise summary quantifies the total noise performance within the relevant bandwidth. It
is crucial to minimize input noise sources and maintain appropriate gain settings to ensure a low
output noise level. Careful selection of components, layout practices, and biasing conditions can
help achieve optimal noise performance

Plot of Noise

Figure 15: Noise

Summary of Noise
The PSD plot for input-referred noise typically reveals significant contributions from thermal noise
(due to resistors) and flicker noise (low-frequency noise from transistors). The noise level tends to
decrease with increasing frequency beyond the flicker noise region.
Data of Noise

Figure 16: Noise summary

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