EE537 Circuit Simulation Lab

Experiment 3

Name: Ahmad Raza Ansari

ID Number: 2024EEM1016 August 20, 2024

AIM: To simulate circuits with MOS Transistor of GPDK 180nm.

1 NMOS Transistor Characterization

We sketched an NMOS as shown in Figure 1. For NMOS we are using the GPDK180nm library.

Figure 1: NMOS Transistor

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1.1 Plot the input and output characteristic plots (i.e. ID vs VGS for different
VDS and ID vs VDS for different VGS )
Simulation result as shown in Figure 2 for different values of VDS drain current ID .

Figure 2: ID vs VGS

Simulation result as shown in Figure 3 for different values of VGS drain current ID .

Figure 3: ID vs VDS

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1.2 Print the operating points of the MOSFET while keeping it in the satura-
tion region.
DC Operating point of MOSFET when it is in saturation region 2.

Figure 4: DC Operating Point

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1.3 Verify the results from the characteristic plots and operating point and
make a specification table

Table 1: DC Operation point simulation table

Component Simulation Result Hand Calcultion

gm 0.125m 0.153m
Un Cox 0.328m 0.251m
V th 0.489 0.439
βef f 3.28m 2.511m

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2 PMOS Transistor Characterization
We sketched an PMOS as shown in Figure 5. For PMOS we are using the GPDK180nm library.

Figure 5: PMOS Transistor

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2.1 Plot the input and output characteristic plots (i.e. ID vs VSG for different
VSD and ID vs VSD for different VSG )
Simulation result as shown in Figure 6 for different values of VSD drain current ID .

Figure 6: ID vs VSG

Simulation result as shown in Figure 7 for different values of VSG drain current ID .

Figure 7: ID vs VSD

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2.2 Print the operating points of the MOSFET while keeping it in saturation
region.
DC Operating point of MOSFET when it is in saturation region 2.

Figure 8: DC Operating Point

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2.3 Verify the results from the characteristic plots and operating point and
make a specification table

Table 2: DC Operation point simulation table

Component Simulation Result Hand Calcultion

gm 0.088m 0.12m
Un Cox 0.181m 0.136m
V th -0.459 -0.418
βef f 1.81m 1.36m

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3 NMOS as a Capacitor
We sketched an NMOS as shown in Figure 9. For NMOS we are using the GPDK180nm library.

Figure 9: NMOS as Capacitor

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3.1 Plot the equivalent gate capacitance Cgg with respect to VGS .

Figure 10: Cgg vs VGS

3.2 Explain the behaviour of Cgg in accumulation, depletion, and inversion in-
tuitively. Also, calculate Cgg in strong-inversion
Accumulation Region
In this region, the capacitance is high because the gate capacitance Cox is in series with the capac-
itance of the accumulated charge layer, which is very high. Thus, Cgg ≈ Cox .
Depletion Region
The capacitance decreases because the depletion region acts as a dielectric layer, increasing the
effective distance between the gate and the semiconductor. The capacitance in this region is given
by the series combination of Cox and the depletion capacitance Cdep , which is lower than Cox .
Inversion Region
In strong inversion, the capacitance increases again because the inversion layer forms a conductive
channel, effectively reducing the distance between the gate and the inversion layer. The capacitance
in this region is again close to Cox .
ϵox
Cox =
tox
Cox = 2.21 mF
Cgg = 873 F By plot

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3.3 Calculate Cdepletion from your simulation results.
C cox ∗ C dep
C gg = (1)
C cox + C dep
Cgg = 238 F
Cox = 873 F
After calculation:

C dep = 327.2 F (2)

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4 NMOS with a constant current source.
We sketched a circuit as shown in Figure 11.

Figure 11: NMOS with constant current source

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4.1 For L=180nm
Transconductance (Gm ) The ratio of the drain current (ID ) to the gate-source voltage (VGS )
when the drain-source voltage is constant.

Figure 12: Gm vs W

Figure of merit (Gm /ID ) It measures how efficiently a transistor translates current into gain.

Figure 13: Gm /ID vs W

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 Drain Conductance (GDS ) It can be defined as the derivative of the ID by VDS when VGS
is constant.

Figure 14: GDS vs W

rout /ID

Figure 15: rout vs W

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 Gate to Source Voltage (VGS )

Figure 16: VGS vs W

Drain to Source Voltage (VDS )

Figure 17: VDS vs W

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4.2 L=1um
Gm

Figure 18: Gm vs W

Gm /ID

Figure 19: Gm /ID vs W

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 GDS

Figure 20: GDS vs W

rout /ID

Figure 21: rout vs W

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 VGS

Figure 22: VGS vs W

VDS

Figure 23: VDS vs W

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4.3 L=5um
Gm

Figure 24: Gm vs W

Gm /ID

Figure 25: Gm /ID vs W

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 GDS

Figure 26: GDS vs W

rout /ID

Figure 27: rout vs W

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 VGS

Figure 28: VGS vs W

VDS

Figure 29: VDS vs W

Expalin the significance of gm/ID

Efficiency Indicator: The gm/ID ratio is a measure of how efficiently a transistor converts cur-
rent into transconductance. A higher gm/ID value indicates better efficiency, meaning you get
more transconductance for a given amount of current.
Design Flexibility: This ratio helps designers understand the operating region of the transistor
(weak, moderate, or strong inversion). It provides a unified approach to design across different
regions, making it easier to optimize performance.

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 Mark different channel inversion regions in the plot.
We got a plot of gm /Id and Vgs for width varying and I made a graph in red line that is gm /Id Vs
Vgs . The region left of the V1 mark is weak inversion, and the right is strong.

Figure 30: VDS vs W

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5 Small Signal model of NMOS and PMOS transistor.
5.1 Tabulate the operating points of NMOS and PMOS transistors.
NMOS

Figure 31: NMOS DC Operating point

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Figure 32: NMOS DC operating Point

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PMOS

Figure 33: PMOS DC operating Point

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Figure 34: PMOS DC operating Point
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6 Present the small signal of NMOS and PMOS transistors at low
frequency

Figure 35: Small Signal NMOS at Low Frequency

Figure 36: Small Signal PMOS at Low Frequency

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6.1 Present the small signal of NMOS and PMOS transistors at high frequency

Figure 37: Small Signal NMOS at High Frequency

Figure 38: Small Signal PMOS at High Frequency

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