Sequential Circuits

▪ A sequential circuit consists of a feedback path, and

employs some memory elements.
Combinational Memory outputs
outputs

Combinational Memory
logic elements

External inputs

Sequential circuit = Combinational logic + Memory Elements

Sequential circuits are digital circuits in which the outputs depend not only
on the current inputs, but also on the previous state of the output.
 Example Needing Bit Storage

• Flight attendant call button Call

button Bit
Blue light

– Press call: light turns on Cancel

button
Storage

• Stays on after button released 1. Call button pressed – light turns on

– Press cancel light turns off
Call Blue light
– Logic gate circuit to implement button Bit
Storage
this? Cancel
button

2. Call button released – light stays on

a Call Q
Cancel
Call Blue light
button Bit
Doesn’t work. Q=1 when Call=1, but Cancel Storage
doesn’t stay 1 when Call returns to 0 button

3. Cancel button pressed – light turns off

Need some form of “feedback” in the circuit
Introduction
▪ There are two types of sequential circuits:
❖ synchronous: outputs change only at specific time
❖ asynchronous: outputs change at any time

▪ Multivibrator: a class of sequential circuits. They can be:

❖ bistable (2 stable states)
❖ monostable or one-shot (1 stable state)
❖ astable (no stable state)

▪ Bistable logic devices: latches and flip-flops.

▪ Latches and flip-flops differ in the method used for
changing their state.
The circuit have two stable states, so it is called bistable circuit. Pair of
two inverters is called Latch.
Memory Elements
▪ Memory element: a device which can remember value
indefinitely, or change value on command from its
inputs.

Memory Q
command element stored value

▪ Characteristic table:
Command Q(t) Q(t+1)
(at time t) Q(t): current state
Set X 1
Q(t+1) or Q+: next state
Reset X 0
Memorise / 0 0
No Change 1 1
SR Latch
 Latches
• SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R 0 0
Q

S Q
0 1

Initial Value
 Latches
• SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R 0 1
Q

S Q
0 0
 Latches
• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 0
Q

S Q
0 1
 Latches
• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 1
Q
0 1 1 0 1 Q=0

S Q
0 0
 Latches
• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0 Q=1

S Q
1 1
 Latches
• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
1 0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0
 Latches
• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10
 Latches
• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
10 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0
 Latches
• SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
 S-R Latch
▪ Complementary outputs: Q and Q'.
▪ When Q is HIGH, the latch is in SET state.
▪ When Q is LOW, the latch is in RESET state.
▪ For active-HIGH input S-R latch (also known as NOR
gate latch),
R=HIGH (and S=LOW) a RESET state
S=HIGH (and R=LOW) a SET state
both inputs LOW a no change
both inputs HIGH a Q and Q' both LOW (invalid)!
 S-R Latch
▪ For active-LOW input S'-R' latch (also known as
NAND gate latch),
R'=LOW (and S'=HIGH) a RESET state
S'=LOW (and R'=HIGH) a SET state
both inputs HIGH a no change
both inputs LOW a Q and Q' both HIGH (invalid)!

▪ Drawback of S-R latch: invalid condition

exists and must be avoided.
 Controlled Latches
• NAND Based SR Latch with Control Input

En S R Q
0 x x Q0 No change
1 0 0 Q0 No change S S
Q
1 0 1 0 Reset
En
1 1 0 1 Set
R Q
1 1 1 Q=Q’ Invalid R
 Controlled Latches
• NOR Based SR Latch with Control Input

E S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
 D Latch
• One way to eliminate the undesirable indeterminate
state in the RS flip flop is to ensure that inputs S and
R are never 1 simultaneously. This is done in the D
latch:
 Gated D Latch
▪ When EN is HIGH,
❖ D=HIGH → latch is SET
❖ D=LOW → latch is RESET
▪ Hence when EN is HIGH, Q ‘follows’ the D (data)
input.
▪ Characteristic table:
EN D Q(t+1)
1 0 0 Reset
1 1 1 Set
0 X Q(t) No change

When EN=1, Q(t+1) = D

 Flip-Flops
• Controlled latches are level-triggered

• Flip-Flops are edge-triggered

CLK Positive Edge

Rising edge
Low– high transition
0-1 transition
CLK

Negative Edge/ Falling edge

Memory Elements
▪ Two types of triggering/activation/sensitive:
❖ pulse-triggered/level triggering
❖ edge-triggered

▪ Pulse-triggered/level triggering(Latches)
◆ High-level sensitive
◆ Low-level sensitive
▪ Edge-triggered (Flip-flops)
◆ Rising (positive) edge triggered(ON = from 0 to 1; OFF = other time)
◆ Falling (negative) edge triggered (ON = from 1 to 0; OFF = other time)
◆ Dual-edge triggered
 Controlled Latches
• D Latch (D = Data/Delay) Timing Diagram

D S C
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set
 CLOCK SIGNAL
➢ The clock signal is generally a rectangular pulse train that has
fixed interval.
➢ The clock signal used to synchronize the operations of an
electronic system.

➢ The clock signal is a periodic square wave that switches values

from 0 to 1 and 1 to 0 for infinite time.

➢ Clock period = clock cycle (time)

➢ Clock Frequency = 1/ clock period

➢ Duty cycle = Thigh/ Tcycle

 Latch Circuits: Not Suitable
▪ Latch circuits are not suitable in synchronous logic
circuits.
▪ When the enable signal is active, the excitation inputs are
gated directly to the output Q. Thus, any change in the
excitation input immediately causes a change in the latch
output.
▪ The problem is solved by using a special timing control
signal called a clock to restrict the times at which the
states of the memory elements may change.
▪ This leads us to the edge-triggered memory elements
called flip-flops.
 Flip Flop vs. Latch
Latches and flip-flops (FFs) are the basic building blocks of sequential circuits.
Latch:
➢ Bistable memory device with level sensitive triggering (no clock), all of
its inputs continuously and changes its outputs, independent of a
clocking signal.
➢ Latch is based on Enable function inputs.

Flip-flop:
➢ Bistable memory device with edge-triggering (with clock), samples its
inputs, and changes its output only at times determined by a clocking
signal.
➢ It works on basis of clock pulse.
 Edge-Triggered Flip-flops
▪ Flip-flops: synchronous bistable devices
▪ Output changes state at a specified point on a triggering
input called the clock.
▪ Change state either at the positive edge (rising edge) or at
the negative edge (falling edge) of the clock signal.

Clock signal

Positive edges Negative edges

 D Flip-Flop
• D Flip-flop Timing Diagram

D S CLK
Q
CLK D
R Q
Q

t
CLK D Q
Output may
0 x Q0 No change
change
1 0 0 Reset
1 1 1 Set
 SR Flip-flop
• NAND Based SR Flip-flop

CLK S R Q
0 x x Q0 No change
1 0 0 Q0 No change S S
Q
1 0 1 0 Reset
CLK
1 1 0 1 Set
R Q
1 1 1 Q=Q’ Invalid R
 Edge-Triggered Flip-flops
▪ S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the
clock input.

S D J Q
Q Q
C C C
R K
Q' Q' Q'

Positive edge-triggered flip-flops

S D Q J Q
Q
C C C
R K
Q' Q' Q'

Negative edge-triggered flip-flops

NOR Based J-K flip-flop