EXP.

NO:1
SIMULATION OF BASIC LOGIC GATES

AIM:
To write a verilog program for basic logic gates to synthesize and simulate using Xilinx
software tool.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite 12.1

ALGORITHM:

1. Start the program.

2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.
5. Write the functionality of the gates.
6. Terminate the program.

THEORY:

AND GATE:

The AND gate performs logical multiplication which is most commonly known as the AND
junction. The operation of AND gate is such that the output is high only when all its inputs are high
and when any one of the inputs is low the output is low.
Y=a&b
OR GATE:

The OR gate performs logical addition which is most commonly known as the OR junction.
The operation of OR gate is such that the output is high only when any one of its input is high and
when both the inputs are low the output is low.
Y=a|b
NOT GATE:
The Inverter performs a basic logic gate function called Inversion or Complementation. The
purpose of an inverter is to change one logic level to opposite level. When a high level is applied
top an inverter, the low level will appear at the output and vice versa.
Y = ~a
NAND GATE:
The term NAND is derived from the complement of AND. It implies the AND junction with
an inverted output. The operation of NAND gate is such that the output is low only when all its
inputs are high and when any one of the inputs is low the output is high.
Y = ~(a & b)
NOR GATE:
The term NOR is derived from the complement of OR. It implies the OR junction with an
inverted output. The operation of NOR gate is such that the output is high only when all its inputs
are low and when any one of the inputs is high the output is low.
Y = ~(a | b)
EX-OR GATE:
The output is high only when the inputs are at opposite level.
Y=a^b
EX-NOR GATE:
The output is high only when the inputs are at same level.
Y = ~(a ^ b)

PROGRAM:
Verilog Code for basic logic gates

module logicgates(a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
and(c,a,b);
or(d,a,b);
not(e,a);
nand(f,a,b);
xor(g,a,b);
xnor(h,a,b);
endmodule

PROCEDURE:

Software part

1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of
PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
4. clicking on the synthesis in the process window.
5. Perform the functional simulation using Xilinx ISE simulator.
6. The output wave form can be observed in model sim.

SIMULATION REPORT

RESULT:
Thus the verilog program for basic logic gates were written, synthesized and simulated using Xilinx
tool.
EXP: NO: 2
SIMULATION OF HALF ADDER AND FULL ADDER

AIM:
To write a verilog program for half adder and full adder to synthesize and simulate using
Xilinx software tool.

TOOLS REQUIRED:
SOFTWARE:
1. Xilinx ISE Design Suite 12.1
ALGORITHM:
1. Start the program.
2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.
5. Terminate the program.

THEORY:
HALF ADDER:
The half adder consists of two input variables designated as Augends and Addend bits.
Output variables produce the Sum and Carry. The ‘carry’ output is 1 only when both inputs are 1
and ,sum’ is 1 if any one input is 1. The Boolean expression is given by,
sum = x ^ y
carry = x & y

FULL ADDER:
A Full adder is a combinational circuit that focuses the arithmetic sum of three bits. It
consists of 3 inputs and 2 outputs. The third input is the carry from the previous Lower Significant
Position. The two outputs are designated as Sum (S) and Carry (C). The binary variable S gives the
value of the LSB of the Sum. The output S=1 only if odd number of 1’s are present in the input and
the output C=1 if two or three inputs are 1.
sum = x ^ y ^ z
carry= (x & y) | (y & z) | (x & z)
PROCEDURE:

Software part
1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of
PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed by using model sim.

PROGRAM:

Verilog code for half adder

module halfadder(a, b, sum, carry);

input a;
input b;
output sum;
output carry;
xor(sum,a,b);
and(carry,a,b);
endmodule

SIMULATION REPORT
PROGRAM:

Verilog code for full adder

module fulladder(a,b,c,d,e,f,sum,carry);
input a,b,c;
output sum,carry,d,e,f;
wire d,e;
xor(d,a,b);
xor(sum,d,c);
and(e,d,c);
and(f,a,b);
or(carry,e,f);
endmodule

SIMULATION REPORT

RESULT:
Thus the verilog program for half adder and full adder were written, synthesized and simulated
using Xilinx tool.
EXP: NO: 3
SIMULATION OF MULTIPLEXER AND DEMULTIPLEXER

AIM:
To write a verilog program for multiplexer and demultiplexer to synthesize and simulate
using Xilinx software tool.

TOOLS REQUIRED:

SOFTWARE:
1. Xilinx ISE Design Suite 12.1

ALGORITHM:
1. Start the program.
2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.
5. Terminate the program.

THEORY:

MULTIPLEXER

A Multiplexer is a Combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The set of selection of a particular line is controlled
by selection lines. Normally there are 2n input lines and n selection lines whose bit combinations
determine which input is selected.
The 4:1 MUX has four inputs I0, I1, I2 and I3 and select lines S0 and S1. The select lines s0
and s1 are decoded to select a particular AND gate. The outputs of the AND gates are applied to a
single OR gate that provides the one line output Y.
DEMULTIPLEXER

A Demultiplexer is a Combinational circuit that selects binary information from one of

input line and directs it to many output line. The set of selection of a particular output is controlled
by selection lines. Normally there are 1 input line and 2 n selection lines whose bit combinations
determine the output.
The 1:4 DEMUX has one input and select lines S0 and S1. The select lines s0 and s1 are
decoded to select a particular AND gate. The outputs of the AND gates provides the various line
output Y1, Y2, Y3 and Y4.

PROCEDURE: (SAME FOR BOTH MUX & DEMUX)

Software part

1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of
PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed using model sim.

PROGRAM:

Verilog code for Multiplexer

module mux4to1(s0,s1,t0,t1,t2,t3,out);
input s0,s1,t0,t1,t2,t3;
output out;
wire s0n,s1n,n1,n2,n3,n4;
not(s0n,s0);
not(s1n,s1);
and(n1,s0n,s1n,t0);
and(n2,s0,s1n,t1);
and(n3,s0n,s1,t2);
and(n4,s0,s1,t3);
or(out,n1,n2,n3,n4);
endmodule

SIMULATION REPORT: (FOR MUX)

VERILOG CODE FOR DEMULTIPLEXER

module demux1to4(s0,s1,s0n,s1n,in,t0,t1,t2,t3);
input s0,s1,in;
output s0n,s1n,t0,t1,t2,t3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and(t0,s0n,s1,in);
and(t1,s0n,s1n,in);
and(t2,s0,s1,in);
and(t3,s0,s1n,in);
endmodule
SIMULATION REPORT: (FOR DEMUX)

RESULT:
Thus the verilog program for multiplexer and demultiplexer were written, synthesized and
simulated using Xilinx tool.
EXP: NO: 4
SIMULATION OF ENCODER AND DECODER
AIM:
To write a verilog program for encoder and decoder to synthesize and simulate using Xilinx
software tool.

TOOLS REQUIRED:
SOFTWARE:
1. Xilinx ISE Design Suite 12.1

ALGORITHM:
1. Start the program.
2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.
5. Terminate the program.

THEORY:

ENCODER
An Encoder is a digital circuit that has 2n (or fewer) input lines and n output lines. The
output lines generate the binary the binary code corresponding to the input value. In encoder it is
assumed that only one input has a value of 1 at any given time.

DECODER
Discrete quantities of information are represented in digital systems by binary codes. A
binary code of n bits is capable of representing up to 2n distinct elements of coded information. A
decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines. If the n bit coded information unused combinations. The
decoder may have fewer than 2n outputs.
The decoder are also called ‘n’ to ‘m’ line decoders, where is less than or equal to 2 n. Their
purpose is to generate the 2n (or fewer) minterms of input variables. The name decoder is also used
in conjunction with other code converters such as BCD to SEVEN SEGMENT decoder.
PROCEDURE: (FOR ENCODER & DECODER)

Software part

1. Click on the Xilinx ISE Design Suite 12.1 or Xilinx Project navigator icon on the desktop of
PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed using model sim.

PROGRAM:

Verilog code for Encoder

module encoder(a,b,c,d,s0,s1);
input a,b,c,d;
output s0,s1;
or(s0,c,d);
or(s1,b,d);
endmodule

SIMULATION REPORT: (FOR ENCODER)

VERILOG CODE FOR DECODEER

module decoder(s0,s1,t0,t1,t2,t3);
input s0,s1;
output t0,t1,t2,t3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and(t0,s0n,s1n);
and(t1,s0n,s1);
and(t2,s0,s1n);
and(t3,s0,s1);
endmodule

SIMULATION REPORT: (FOR DECODER)

RESULT:
Thus the verilog program for encoder and decoder were written, synthesized and simulated
using Xilinx tool.
EXP: NO: 5
SIMULATION OF D FLIP FLOP AND D LATCH

AIM:
To write a verilog program for D-flip flop and D-latch to synthesize and simulate using
Xilinx software tool.

TOOLS REQUIRED:
SOFTWARE:
1. Xilinx ISE Design Suite 12.1

ALGORITHM:
1. Start the program.
2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.
5. Terminate the program.

THEORY:

D-FLIP FLOP:
It has only a single data input. That data input is connected to the S input of RS-flip
flop, while the inverse of D is connected to the R input. This prevents that the input combination
ever occurs. To allow the flip flop to be in holding state, a D-flip flop has a second input called
“clock”. The clock input is AND-ed with the D input, such that when clock=0, the R and S inputs
of the RS-flip flop are 0 and the state is held.

D-LATCH:
It has only a single data input. That data input is connected to the S input of RS-flip flop,
while the inverse of D is connected to the R input. This prevents that the input combination ever
occurs. To allow the flip flop to be in holding state, a D-flip flop has a second input called “enable”.
The enable input is AND-ed with the D input, such that when enable=0, the R and S inputs of the
RS-flip flop are 0 and the state is held.
PROCEDURE:

Software part:

1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop
of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed using model sim.

PROGRAM:

Verilog code for D flipflop

module dff(d,clk,rst,q);
input d,clk,rst;
output q;
reg q;
always@(posedge clk or posedge rst)
begin
if (rst)
q<=1'b0;
else
if(clk)
q<=d;
end
endmodule
SIMULATION REPORT:

Verilog code for D latch

module dlatch(d,en,b,c,a,q,qbar);
input d,en;
output b,c,a,q,qbar;
wire b,c,a,q,qbar;
not(a,d);
nand(b,d,en);
nand(c,a,en);
nand(q,b,qbar);
nand(qbar,c,q);
endmodule

SIMULATION REPORT:

RESULT:
Thus the verilog program for D-flip flop and D-latch were written, synthesized and simulated using
Xilinx tool.
 Experiment No.6
OBJECT: - Design and Simulation of a Differential Amplifier (with Resistive Load, Current Source Biasing)

SOFTWARE REQUIRED: - Tina-TI/TARGET 3001

COMPONENTS USED:

PART PARTNAME /LIBRARY PICTURE

THEORY:-
A differential amplifier circuit amplifies the difference of any two input signals and rejects any two common
signals. The ideal characteristics of an amplifier are infinite gain, infinite bandwidth and infinite common mode
rejection ratio, high input impedance and low output admittance, less distortion, sensitivity.

Two different types of differential amplifiers are studied, designed and analyzed in terms of its performance.
1. Differential Amplifier with Resistive Load:

Fig 1.Basic differential amplifier with passive load

The basic differential amplifier is shown in fig 1, it i s designed by using two n-channel MOSFETs M1 and M2
to form a differential pair. The resistors RD are used as load to drive the transistors into saturation.

2. Differential Amplifier with Active Load:

Fig 2.Basic differential amplifier with active load

Here the circuit is designed by using different load using active components and they can be like diode-
connected or current source loads. The diode connected load has an advantage of overcoming the problem of
lowering the voltage swing and effect on gain due to common mode.

SIMULATION RESULT:

Fig.3 .Transfer characteristic of differential amplifier with resistive load

Fig.4 .Transfer characteristic of differential amplifier with active load

 Experiment No.7

OBJECT: - Analysis of frequency response of Common drain (source follower) amplifiers.

SOFTWARE REQUIRED: - Tina-TI/TARGET 3001

COMPONENTS USED:

PART PARTNAME /LIBRARY PICTURE

THEORY:-
In electronics, a common-drain amplifier, also known as a source follower, is one of three basic single-stage field
effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit (NMOS) the gate
terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and
output), hence its name. The analogous bipolar junction transistor circuit is the common-collector amplifier. This
circuit is also commonly called a "stabilizer."
 Fig.1.Schematic Of Common Drain Amplifier

This is a common-source amplifier, which amplifies the input voltage about X times. X depending upon chosen
value of device parameters.

SIMULATION RESULT:

Fig.2.Result of transient Analysis of Common Drain Amplifier

Fig.3.Result of AC Analysis of Common Drain Amplifier
Exp. No.: 8
LAYOUT EXTRACTION AND SIMULATION
OF C-MOS INVERTOR

AIM:

To draw the layout of an CMOS inverter

SOFTWARE USED:
 Microwind
 DSCH

DESCRIPTION:

CMOS INVERTER:

The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS)
device. When a low voltage (0 V) is applied at the input, the top transistor (P-type) is
conducting (switch closed) while the bottom transistor behaves like an open circuit.
Therefore, the supply voltage (5 V) appears at the output. Conversely, when a high voltage
(5 V) is applied at the input, the bottom transistor (N-type) is conducting (switch closed)
while the top transistor behaves like an open circuit. Hence, the output voltage is low (0 V).

LAYOUT DIAGRAM
ALGORITHM:

 Open the DSCH2

 Drag the components like pmos,nmos,voltage source, ground, and LED from the
symbol library.

 Connect the circuit as in the circuit diagram.

 Save the circuit & run the simulation

 Make verilog file go to Microwind and compile the verilog file saved in DSCH2

 Compile it and obtain the layourt diagram & draw the waveform

CIRCUIT DIAGRAM:

MOS LAYOUT

We use MICROWIND2 to draw the MOS layout and simulate its behavior. Go to the
directory in which the software has been copied (By default MICROWIND2). Double-click
on the MicroWind2 icon. The MICROWIND2 display window includes four main windows:
the main menu, the layout display window,the icon menu and the layer palette. The layout
the
minimum available lithography of the technology. The default technology is a CMOS 6-
metal layers 0.25μm technology, consequently lambda is 0.125 μm.
Verilog code:

module cmosInv( in2,out2)

input in2;
output out2;
pmos #(17) pmos(out2,vdd,in2); // 1.0u 0.12u
nmos #(114) nmos(out2,vss,in2); // 0.48u 0.12u
endmodule

LAYOUT FOR C-MOS INVERTOR:

ANALOG SIMULATION:

Click on Simulate à Start Simulation. The timing diagrams will appears as follows

RESULT:

Thus the Layout design of a CMOS inverter has been drawn, verified and timing
analysis perform.