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RISC vs. CISC

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7 views

RISC vs. CISC

Uploaded by

mahimadec2000
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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RISC vs.

CISC
Towards CISC
• Wired logic  microcode control
– Temptingly easy extensibility
• Performance tuning
– HW implementation of some high-level functions
• Marketing
– Add successful instructions of competitors
– “New feature” hype
– Compatibility: only extensions are possible
CISC Problems
• Performance tuning unsuccessful
– Rarely used high-level instructions
– Sometimes slower than equivalent sequence
• High complexity
– Pipelining bottlenecks  lower clock rates
– Interrupt handling can complicate even more
• Marketing
– Prolonged design time and frequent microcode errors hurt
competitiveness
RISC Features
• Low complexity
– Generally results in overall speedup
– Less error-prone implementation by hardwired logic or
simple microcodes
• VLSI implementation advantages
– Less transistors
– Extra space: more registers, cache
• Marketing
– Reduced design time, less errors, and more options
increase competitiveness
RISC Compiler Issues
• The compilers themselves
– Computationally more complex
– More portable

• The compiler writer


– Less instructions  probably easier job
– Simpler instructions  probably less bugs
– Can reuse optimization techniques
RISC vs. CISC misconceptions

• Arguments favoring RISC: simple design,


short design time, speed, price…

• Study of RISC should include


hardware/software tradeoffs, factors
influencing computer performance and
industry-side evaluation.
RISC vs. CISC misconceptions
• Incorrect implication from the two acronyms:
RISC and CISC.
– They are not bifurcations between which designers have to
choose

• Carelessly leaving out the ‘participation’ of


Operating System
RISC vs. CISC misconceptions
• Reduced design time?
– academic <-> industrial

• Performance claims of RISC proponent do not


decouple design features like MRSs.
– MRSs can have a remarkable effect on program execution
Conclusion – RISC vs. CISC?

• CISC
– Effectively realizes one particular High Level Language
Computer System in HW - recurring HW development
costs when change needed

• RISC
– Allows effective realization of any High Level Language
Computer System in SW - recurring SW development
costs when change needed
Conclusion – Optimum?
• Hybrid solutions
– RISC core & CISC interface
– Still has specific performance tuning

• Optimal ISA
– Between RISC & CISC
– Few, carefully chosen, useful complex instructions
– Still has complexity handling problems
RISC
Reduced Instruction Set Computers

• Microprocessor architecture
• Designed to perform a set of smaller
computer instructions so that it can operate
at higher speeds
What will we cover?
• History
• Theory
• Advantages
• Pipelining
Before the RISC era
• Compilers were hard to build especially for machines with
registers
– Make machine do more work than software
– Have instructions load and store directly to memory (memory-
to-memory operations)
• Software costs were rising and hardware costs were
dropping
– Move as much functionality to hardware
• Magnetic core memory was used as main memory which
was slow and expensive
– Minimize assembly code
• Complex Instruction Set Computers (CISC)
– Use complex instructions “MULT”, “ADD”…
Technology was advancing
• Compilers were improving
– Simple compilers found it difficult to use more complex
instructions
– Optimizing compilers rarely needed more powerful
instructions
• Caches
– allowed main memory to be accessed at similar speeds to
control memory
• Semiconductor memory was replacing magnetic core
memory
– Reduced performance gap between control and main
memory
Inception of RISC
• 1974 – John Cocke (IBM) proved that 80% of
work was done using only 20% of the
instructions
• Three RISC projects
– IBM 801 machine (1974)
– Berkeley’s RISC-I and RISC-II processors (1980)
– Stanford’s MIPS processor (1981)
• 1986 – announcement of first commercial
RISC chip
RISC Approach
• Use only simple instructions that can be
executed within one clock cycle
– Fewer transistors for instructions = more registers
• Pipelining
• Register-to-register operations
– Operand reuse
– Reduction of load/store
Pipelining
Sequential
IF ID O OE O
F S
IF ID O OE O
F S
Clock Cycle IF ID O OE O
F S

Pipelined
IF ID O OE O IF – Instruction Fetch
F S ID – Instruction Decode
IF ID O OE O
Clock Cycle

OF – Operand Fetch
F S
IF ID O OE O OE – Operand Execution
F S OS – Operation Store

Time
Pipelining
Data Dependency
IF – Instruction Fetch
IF ID O OE O ID – Instruction Decode
F S
IF ID O OE O OF – Operand Fetch
F S OE – Operand Execution
OS – Operation Store

IF ID O OE O
F S

Branch Address Dependency


IF ID O OE O
F S
IF ID O OE O
F S
Pipelining
• Data dependencies can be addressed by
reordering the instructions when possible
(compiler)
• Performance degradation from branches can
be reduced by branch prediction or executing
instructions for both branches until the
correct branch is identified
Other Advantages
• New microprocessors can be developed and
tested more quickly if being less complicated
is one of it’s aims
• Smaller instruction sets are easier for compiler
programmers to use
Use of RISC today
• X86 is one of the only chips that retain CISC
architecture
– Large base of proprietary PC applications were written
for X86 or compiled into X86 machine code
– Intel was able to spend vast amounts of money on
processor development to offset the RISC advantages
enough to maintain PC market share
• CISC and RISC architectures are nearly
indistinguishable
– CISC processors use pipelining and can complete
multiple instructions per cycle
– Transistor technology has allowed more room on
chips allowing RISC to have more CISC like instruction

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