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Lec7 ch4 Part2

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26 views21 pages

Lec7 ch4 Part2

Uploaded by

mostafayounis630
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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COMPUTER ORGANIZATION AND DESIGN 5th

Edition
The Hardware/Software Interface

Chapter 4
The Processor
§4.1 Introduction
Introduction
◼ CPU performance factors
◼ Instruction count
◼ Determined by ISA and compiler
◼ CPI and Cycle time
◼ Determined by CPU hardware
◼ We will examine two MIPS implementations
◼ A simplified version
◼ A more realistic pipelined version
◼ Simple subset, shows most aspects
◼ Memory reference: lw, sw
◼ Arithmetic/logical: add, sub, and, or, slt
◼ Control transfer: beq, j

Chapter 4 — The Processor — 2


Instruction Execution
◼ PC → instruction memory, fetch instruction
◼ Register numbers → register file, read registers
◼ Depending on instruction class
◼ Use ALU to calculate
◼ Arithmetic result
◼ Memory address for load/store
◼ Branch target address
◼ Access data memory for load/store
◼ PC  target address or PC + 4

Chapter 4 — The Processor — 3


CPU Overview

Chapter 4 — The Processor — 4


Multiplexers
◼ Can’t just join
wires together
◼ Use multiplexers

Chapter 4 — The Processor — 5


Control

Chapter 4 — The Processor — 6


§4.2 Logic Design Conventions
Logic Design Basics
◼ Information encoded in binary
◼ Low voltage = 0, High voltage = 1
◼ One wire per bit
◼ Multi-bit data encoded on multi-wire buses
◼ Combinational element
◼ Operate on data
◼ Output is a function of input
◼ State (sequential) elements
◼ Store information

Chapter 4 — The Processor — 7


Combinational Elements
◼ AND-gate ◼ Adder A
Y
+
◼ Y=A&B ◼ Y=A+B B

A
Y
B

◼ Arithmetic/Logic Unit
◼ Multiplexer ◼ Y = F(A, B)
◼ Y = S ? I1 : I0
A
I0 M
u Y ALU Y
I1 x
B
S F

Chapter 4 — The Processor — 8


Sequential Elements
◼ Stores data in a circuit
◼ Uses a clock signal to determine when to
update the stored value
◼ Edge-triggered: update when Clk changes
from 0 to 1

Clk
D Q
D

Clk
Q

Chapter 4 — The Processor — 9


Sequential Elements
◼ Storing with write control
◼ Only updates on clock edge when write
control input is 1
◼ Used when stored value is required later

Clk

D Q Write

Write D
Clk
Q

Chapter 4 — The Processor — 10


Clocking Methodology
◼ Combinational logic transforms data during
clock cycles
◼ Between clock edges
◼ Input from state elements, output to state
element
◼ Longest delay determines clock period

Chapter 4 — The Processor — 11


Datapath and Control

Chapter 4 — The Processor — 12


§4.3 Building a Datapath
Building a Datapath
◼ Datapath
◼ Elements that process data and addresses
in the CPU
◼ Registers, ALUs, mux’s, memories, …
◼ We will build a MIPS datapath
incrementally
◼ Refining the overview design

Chapter 4 — The Processor — 13


Datapath

Chapter 4 — The Processor — 14


Instruction Fetch

Increment by
4 for next
32-bit instruction
register

Chapter 4 — The Processor — 15


R-Format Instructions
◼ Read two register operands
◼ Perform arithmetic/logical operation
◼ Write register result

Chapter 4 — The Processor — 16


Load/Store Instructions
◼ Read register operands
◼ Calculate address using 16-bit offset
◼ Use ALU, but sign-extend offset
◼ Load: Read memory and update register
◼ Store: Write register value to memory

Chapter 4 — The Processor — 17


R-Type/Load/Store Datapath

Chapter 4 — The Processor — 19


Branch Instructions
◼ Read register operands
◼ Compare operands
◼ Use ALU, subtract and check Zero output
◼ Calculate target address
◼ Sign-extend displacement
◼ Shift left 2 places (word displacement)
◼ Add to PC + 4
◼ Already calculated by instruction fetch
◼ Branch Address = (PC + 4) + (Offset << 2)

Chapter 4 — The Processor — 20


Branch Instructions
Just
re-routes
wires

Chapter 4 — The Processor — 21


Full Datapath

Chapter 4 — The Processor — 22

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