Advancements and Challenges on Parasitic Extraction for

Advanced Process Technologies

Wenjian Yu, Mingye Song, and Ming Yang
Dept. Computer Science & Tech., BNRist, Tsinghua Univ., Beijing, China
[email protected], [email protected], [email protected]
ABSTRACT field solver directly simulates electrostatic field, and therefore has
As the feature size scales down, the process technology becomes the best accuracy. However, due to the excessive computing time
more complicated and the design margin shrinks, accurate parasitic and memory bottleneck it is only capable of solving a small-size
extraction during IC design is largely demanded. In this invited structure, instead of a circuit module or the whole design.
paper, we survey the recent advancements on parasitic extraction The pattern-matching based method is suitable for large or full-
techniques, especially those enhancing the floating random walk chip circuit layout [4, 29]. The commonly used extraction tools in
based capacitance solver and incorporating machine learning meth- the industry adopt it, such as StarRC of Synopsys, QRC of Cadence,
ods. The work dealing with process variation are also addressed. etc. The method includes three major steps: 1) generating pattern
After that, we briefly discuss the challenges for capacitance extrac- structures of interconnect wires, 2) building capacitance models for
tion under advanced process technologies, including manufacture- pattern structures, and 3) layout parasitic extraction. The first two
aware geometry variations and middle-end-of-line (MEOL) parasitic steps are performed once for each process technology, while the
extraction, etc. third step runs for each circuit design. The pattern-matching based
method is depicted as Fig. 1, where the part on the right represents
KEYWORDS step 1) and 2). 2-D or 3-D capacitance field solver is used to build the
pattern capacitance library, which consists of thousands of pattern
Advanced Process Technology, Capacitance Field Solver, Floating
structures and the corresponding capacitance values.
Random Walk, Machine Learning, Parasitic Extraction
ACM Reference Format: Process Profile Design Layout Process Profile
Wenjian Yu, Mingye Song, and Ming Yang, Dept. Computer Science &
Tech., BNRist, Tsinghua Univ., Beijing, China, [email protected],
Pattern Structure
[email protected], [email protected], . 2021. Wire Segmentation & Generation
Advancements and Challenges on Parasitic Extraction for Advanced Process Environment Extraction
Technologies. In 26th Asia and South Pacific Design Automation Conference
Capacitance Capacitance
(ASPDAC ’21), January 18–21, 2021, Tokyo, Japan. ACM, New York, NY, USA, Pattern Models Field Solver
6 pages. https://doi.org/10.1145/3394885.3431626 Resistance Matching
Extraction

1 INTRODUCTION Pattern Capacitance

Library
Device Capacitance
Accurate parasitic extraction is crucial to the success of today’s Extraction Extraction
high-performance integrated circuit (IC) design [29]. The parasitics
Capacitance
mainly refer to resistances (R) and capacitances (C) among inter- Netlist Generation Models
connect wires in ICs, which have become the key factors affecting
the signal delay and other circuit performance metrics [4, 7]. Figure 1: The pattern-matching based parasitic extraction.
Parasitic extraction means modeling electromagnetic effects In addition to the usage in building pattern capacitance library,
among the wires with the parasitics, and calculating the values of 3-D capacitance field solver is also employed to simulate/extract
these R/C components. The calculation of capacitances, i.e. capaci- the structures of critical nets for highly accurate analysis. And for
tance extraction, is of the major concern, due to its computational foundry, 3-D field solver is used to calibrate the pattern-matching
complexity and the challenge brought by the massive coupling based extraction tools, to simulate device structures, and for the
among millions of on-chip interconnect segments [5, 12]. optimization of new process technology. With the continuous down
There are two kinds of methods for capacitance extraction. One is scaling of process technology, 3-D coupling between interconnect
called field solver, while the other is based on pattern matching. The wires and the devices increases. This makes the accuracy of pattern
matching method not sufficiently good [3]. Directly applying 3-D
Permission to make digital or hard copies of all or part of this work for personal or
classroom use is granted without fee provided that copies are not made or distributed capacitance solver to the design is more and more demanded.
for profit or commercial advantage and that copies bear this notice and the full citation
on the first page. Copyrights for components of this work owned by others than ACM
must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, 1.1 3-D Capacitance Field Solver
to post on servers or to redistribute to lists, requires prior specific permission and/or a
fee. Request permissions from [email protected]. A lot of field solver techniques have been proposed for capacitance
ASPDAC ’21, January 18–21, 2021, Tokyo, Japan extraction. They can be classified into two categories: 1) the tra-
© 2021 Association for Computing Machinery.
ACM ISBN 978-1-4503-7999-1/21/01. . . $15.00 ditional deterministic methods, like the finite difference method
https://doi.org/10.1145/3394885.3431626 (FDM) [21] and boundary element method (BEM) [12, 30], and 2)

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ASPDAC ’21, January 18–21, 2021, Tokyo, Japan Yu, et al.

the floating random walk (FRW) method [2, 9, 34]. The idea of FRW the transition probabilities to the panels, and then randomly choos-
method is to convert the calculation of conductor charge to the ing a panel [34]. The transition probability is the integral of surface
Monte Carlo integration performed with floating random walks. Green’s function on a panel. Its value distribution depends on the
In [34], an efficient 3-D FRW solver was proposed, including an dielectric configuration within T, and should be pre-calculated and
approach to handle multilayer dielectrics and a variance reduction stored as tables (called GFTs) for transition cubes with various
approach to accelerate convergence. The solver was later enhanced dielectric configurations [34]. By loading these tables before per-
with a space management technique suitable for structures with a forming FRWs, we can make the FRW hops executed quickly.
large number of conductor blocks [38] and an improved approach
for handling multilayer dielectrics [15, 37]. Compared with tradi- 2 RECENT ADVANCEMENTS ON PARASITIC
tional methods, the FRW method is advantageous in scalability, EXTRACTION TECHNIQUES
reliability and parallelism. Recently, the FRW method has been
extended to efficiently deal with cylindrical inter-tier-vias in 3-D In this section, we survey the recent research advancements on
ICs [40], the non-Manhattan conductors [25], and general-shape parasitic extraction, which are mainly on the FRW based 3-D ca-
floating metals [31]. It has also been implemented on GPUs [1, 35], pacitance solver, the machine-learning based techniques, etc. Most
FPGA [24] and distributed parallel computing environments [17]. of them were developed or published in recent two years.
The FRW method can be derived from the integral formula for
electric potential [9, 34]: 2.1 Enhancements to the Floating Random
∮
Walk Based Capacitance Solver
𝜙 (𝒓) = 𝑃 (𝒓, 𝒓 (1) )𝜙 (𝒓 (1) )𝑑𝒓 (1) , (1)
𝑆 Although the FRW method has been employed in commercial EDA
where 𝜙 (𝒓) is the potential of point 𝒓 and 𝑃 (𝒓, 𝒓 (1) ) is called surface tools [22], there is no complete theory presented on how it handles
Green’s function. The cubic domain enclosing 𝒓 is called transition actual multi-dielectric interconnect structures. Research is con-
cube, whose surface is 𝑆. 𝑃 (𝒓, 𝒓 (1) ) can be regarded as a probability ducted to enhance the FRW method for efficiently handling actual
density function. With Monte Carlo method, 𝜙 (𝒓) can be estimated design under advanced process technology.
by the mean of 𝜙 (𝒓 (1) ) values.
2.1.1 Improved technique handling non-stratified dielectrics. Under
When computing the capacitances related to a master conductor
modern manufacturing technologies, interconnect wires are sepa-
𝑖, we first construct a Gaussian surface 𝐺𝑖 enclosing it (see Fig. 2).
rated by multiple stratified and/or conformal dielectrics. For better
According to the Gauss theorem, the charge of conductor 𝑖 is:
∮ ∮ performance, air bubble as a special dielectric with the lowest per-
𝑄𝑖 = 𝐹 (𝒓)𝑔 𝜔 (𝒓, 𝒓 (1) ) 𝑃˜ (𝒓, 𝒓 (1) )𝜙 (𝒓 (1) )𝑑𝒓 (1) 𝑑𝒓, (2) mittivity may also be introduced. These non-stratified dielectrics
𝐺𝑖 𝑆 (1) bring challenges to efficient FRW based capacitance extraction. In
where 𝐹 (𝒓) is the dielectric permittivity at point 𝒓, 𝑃˜ (𝒓, 𝒓 (1) ) is the this case, the random walk has to stop at the surface of non-stratified
probability density function, probably different from 𝑃 (𝒓, 𝒓 (1) ), for dielectric to ensure accuracy but sacrifice performance. Otherwise,
sampling on 𝑆 (1) , and 𝜔 (𝒓, 𝒓 (1) ) is called weight value [9, 34]. Thus, an approximate approach based on the eight-octant transition cube
𝑄𝑖 can be estimated as the stochastic mean of sampled values on 𝐺𝑖 , and equivalent permittivities would be used. In [18] we presented
which is further the mean of sampled potentials on 𝑆 (1) multiplying the techniques based on the approximate FRW approach for the
the weight value. If the potential of a sample point 𝒓 (1) is unknown, structure with non-stratified dielectrics. We revealed that the tran-
(2) is expanded by using (1) to substitute 𝜙 (𝒓 (1) ) recursively. The sition probabilities of the eight-octant transition cube have the
computation can be viewed as a floating random walk procedure, symmetry property, and therefore proposed an on-the-fly sampling
which starts from the Gaussian surface and repeatedly jumps until scheme during the FRW procedure. It avoids the pre-calculation and
reaching conductor surface. After performing a number of walks, runtime memory cost for characterizing the eight-octant transition
the stochastic mean of the weight values for the walks terminating cubes. The complete proof of the symmetry property is presented in
at conductor 𝑗 is capacitance 𝐶𝑖 𝑗 between conductors 𝑖 and 𝑗. [26]. The proof is based on the Markov-chain model for interpreting
Each FRW includes a sequence of hops, each of which is from the the transition cube’s pre-characterization.
center of a transition cube T to a random point selected following A difficulty occurs for solving the structure including a large
the surface Green’s function. In practice, this random sampling is re- quantity of non-stratified dielectrics. When the transition cube in-
alized by first discretizing T’s surface into 6𝑛 2 panels and obtaining volving non-stratified dielectric is approximated by an eight-octant
transition cube, the volume weighted average permittivites are to
Gaussian surface be calculated. This causes a lot of computation if we traverse all
these dielectrics to check if/how they intersect the transition cube.
 i
  Conductor To accelerate this computation, we have extended the space man-
agement technique in [38] for conductors by adding a “dielectric”
 r candidate list to each spatial cell [18]. The technique relies on the
y
  transition cubes neighbor region in the space management approach in [38], and
x  simply stores the non-stratified dielectrics inside the spatial cell’s
neighbor region into the “dielectric” candidate list for further use.
Figure 2: Two random walks starting from 𝒓 in the FRW Then, we only need to traverse this candidate list. With this idea, the
based capacitance extraction (2-D top view). grid-Octree hybrid structure for space management was extended

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Advancements and Challenges on Parasitic Extraction for Advanced Process Technologies ASPDAC ’21, January 18–21, 2021, Tokyo, Japan

and an efficient algorithm was presented in [18] for constructing enclose each block of the master net (master conductor). However,
the structure including the “dielectric” candidate lists. determining the placement of BGS needs the nearest environment
Three test cases are generated to validate the extended space conductor and its distance. This may cause a lot of computation
management approach. Two of them are three-parallel-wire struc- if calculating the distance through traversing all the environment
tures between two parallel conductor plates. The size of wire is conductor blocks. And, it further leads to large runtime for the step
45nm×450nm×90nm with 45nm spacing. One includes an 11×157×2 of Gaussian surface generation.
array of cubic air bubbles above the wires, while the other includes In order to accelerate the distance calculation between conductor
11×209×3 bubbles (see Fig. 3(a)). The edge size of each bubble is blocks, we propose to use a grid-based space management structure.
13.4nm and their spacing is 16.7nm. The last case contains 2302984 A 3-D spatial grid is generated, each cell of which includes an
conductors in 3 metal layers, where each of 774911 conductors is ID list of the conductors intersecting the cell. With this spatial
enclosed with a conformal dielectric (see Fig. 3(b)). structure, the minimal distance to environment conductor can be
5.0 5.0
calculated by only traversing the conductors pointed by the ID lists
of the intersected or neighbor cells of the master conductor block.
2.6 2.6
The runtime overhead for constructing the grid-based structure is
5.0 5.0 } } negligible. Therefore, it accelerates the Gaussian surface generation
without sacrifice. We have tested a case with 1467360 conductor
2.6 2.6 blocks, where the master net includes 6450 blocks. Without the
accelerating skill, the CPU time for the Gaussian surface generation
5.0 5.0 is 341 seconds. It is reduced to just 0.93 seconds with the grid-based
2.6 2.6 space management, which means a remarkable 367X speedup.
(a) (b)
2.1.3 Reduction of pre-characterization data. In FRW method, the
Figure 3: (a) The 2nd case’s cross-section view, where gray transition probabilities for a multi-dielectric transition cube are
cubes are air bubbles. (b) A partial cross-section view of the pre-calculated and stored as GFT. Accordingly, the weight values
3rd case including conformal dielectrics (with relative per- are also pre-calculated and stored as weight weight table (WVT).
mittivity 3.7). Relative permittivity of each stratified dielec- The transition probability from cube’s center to its surface panel
tric is labeled in the both cases [18]. is the integral of surface Green’s function 𝑃 (𝒓, 𝒓 (1) ) on that panel.
The computational results are listed in Table 1. 𝑇𝑠𝑝 denotes the The weight value for the transition cube’s surface point 𝒓 (1) is [34]
time for constructing the space management structure, and 𝑇𝑓 𝑟 𝑤
𝒏 𝒓 · ∇𝒓 𝑃 (𝒓, 𝒓 (1) )
denotes the time for the FRW procedure executed with 16 threads. 𝜔 (𝒓, 𝒓 (1) ) ≡ 𝑤 (𝒓 (1) ) = , (3)
The termination criterion is 1% 1-𝜎 error. For the largest Case 3, 𝑔 · 𝑃 (𝒓, 𝒓 (1) )
the result reveals that our algorithm can be 1441X faster than the where 𝒏 𝒓 is the outward normal direction of Gaussian surface at 𝒓,
brute force method traversing all non-stratified dielectrics. This and ∇𝒓 𝑃 (𝒓, 𝒓 (1) ) is the gradient of surface Green’s function with
validates the efficiency of extended space management for large respect to 𝒓. The approach for calculating 𝑤 (𝒓 (1) ) was presented in
structures. Case 1 is also calculated with Raphael [21]. The result [34], which leverages the pre-calculated WVT including discretized
on total capacitance is 89.53 aF. Regarding it as the standard, we values of the following quantities:
see that the error of FRW based method is only -1.2%.
⎧
⎪ 𝜕𝑃 (𝒓,𝒓 (1) )
Table 1: The comparison between the brute force approach ⎪
⎪𝑤 (𝑥) (𝒓 (1) ) = 𝜕𝑥 /𝑃 (𝒓, 𝒓 (1) )
⎨
⎪ 𝜕𝑃 (𝒓,𝒓 (1) )
and the extended space management approach for handling (𝑦)
𝑤 (𝒓 ) = (1) /𝑃 (𝒓, 𝒓 (1) ) , (4)
⎪ 𝜕𝑦
structures with non-stratified dielectrics. ⎪
⎪ (1)
⎪𝑤 (𝑧) (𝒓 (1) ) = 𝜕𝑃 (𝒓,𝒓 ) /𝑃 (𝒓, 𝒓 (1) )
Case Algorithm Memory (MB) Cap. (aF) 𝑇𝑠𝑝 (s) 𝑇𝑓 𝑟 𝑤 (s) ⎩ 𝜕𝑧
brute force 52.7 88.44 0.02 89.96 where 𝒓 = (𝑥, 𝑦, 𝑧) is the cube’s center. For pre-characterizing the
1
proposed 52.7 88.44 0.02 4.94
multilayer dielectrics at advanced technology nodes, the GFTs and
brute force 54.5 89.05 0.03 176.3
2
proposed 54.5 89.05 0.03 8.26
WVTs for a large number of dielectric configures in transition cube
brute force 1140 761.6 29.9 5478 should be pre-calculated. This causes large-size pre-charaterization
3 data (at least several hundreds megabytes), and thus much time for
proposed 1200 761.6 114 3.78
initialization and large memory cost.
2.1.2 Improved technique handling large net. There are some large Recently, we realized that the geometric symmetry of the tran-
nets including thousands of wire segments in VLSI circuits. Power sition cube can be utilized to reduce the pre-charaterization data.
grid is such an example, and its modeling and analysis is increas- Take the transition cube with multilayer dielectrics in Fig. 4(a) as
ingly important for the success of IC design under advanced process an example. 𝑨𝑙 , 𝑨𝑟 and 𝑨𝑏 are three surface panel’s center points.
technology. When applying the FRW method for extracting large Point 𝑨𝑟 can be regarded as the mirror image of point 𝑨𝑙 , while 𝑨𝑟
net, one may encounter the difficulty of constructing the Gauss- coincides with 𝑨𝑏 if the transition cube rotates 90◦ anti-clockwise
ian surface. In [39], a virtual Gaussian surface sampling (VGSS) around the vertical axis across the cube’s center 𝑪. Because the
technique was proposed to avoid generating a Gaussian surface en- transition probability is the probability that a discrete random walk
closing thousands of conductor blocks within a net. With the VGSS starting at 𝑪 finally reaches the corresponding surface panel and
approach, only the block Gaussian surface (BGS) is generated to surface Green’s function is the limit of transition probability over

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ASPDAC ’21, January 18–21, 2021, Tokyo, Japan Yu, et al.

Ab In 2017, it was declared that machine learning has been used

in industry to obtain fast models for parasitic extraction [6]. Al-
Al Ar
H2 H2 though the details are not disclosed, we see that it is about pattern
H1 matching and for estimating in-design capacitance. For building
H1
C the capacitance models in pattern matching method, the neural
network (NN) is certainly a potential solution due to its strong
approximation capability. An NN based method for capacitance ex-
z y traction was presented in [8], where a simple multilayer perceptron
x
(a) (b) NN with one hidden layer (see Fig. 5) is used to estimate the total
Figure 4: A transition cube with two stratified dielectrics, capacitance for three 3-D interconnect structures. Unfortunately,
where red lines outline the dielectric interface. (a) Illustra- it makes too much constraint to the structure and only considers
tion of the uniformed FDM grids for calculating GFT and homogeneous dielectric environment. The experimental results are
WVT values. 𝑪 is the cube’s center point, while 𝑨𝑙 , 𝑨𝑟 and not good enough either, which show that with the NN based model
𝑨𝑏 are three surface panel’s center points at symmetric po- the root mean square error on total capacitance is from 1.7% to
sitions. (b) Only the GFT and WVT values for the panels in 4.5%. Obviously, this work seems not useful for general problem of
blue-shade region need to be stored, due to the property de- capacitance extraction. It is not clear yet if the NN based method
rived from geometric symmetry. is able to outperform and replace the traditional model building
methods based on empirical formula and look-up table.
the area of surface panel [26], it is easy to see:
𝑃 (𝑪, 𝑨𝑙 ) = 𝑃 (𝑪, 𝑨𝑟 ) = 𝑃 (𝑪, 𝑨𝑏 ) (5)
This means the surface Green’s function (transition probability) has
same value for surface points in mirror symmetry and 90◦ rotation
symmetry. For each point, like 𝑨𝑙 , there are 7 other points at the
symmetric positions for which the transition probability is the same.

From (4) and (5), one can derive that the values in WVT also Figure 5: A neural network based capacitance model [8].
inherit the symmetry of surface Green’s function. Specifically,
An automatic approach for pattern classification and capaci-
𝑤 (𝑧) (𝑨𝑙 ) = 𝑤 (𝑧) (𝑨𝑟 ) = 𝑤 (𝑧) (𝑨𝑏 ), (6) tance formulas building was recently proposed for pattern match-
while there is a little difference on the partial derives along 𝑥 and 𝑦: ing based capacitance extraction [10]. It considers 2-D interconnect
cross-section, and clusters 2-D pattern structures sharing same ca-
⎧
⎪𝑤 (𝑥) (𝑨𝑙 ) = −𝑤 (𝑥) (𝑨𝑟 )
⎪
⎪ pacitance formula. The multilayer perceptron NNs are employed
⎪
⎨𝑤 (𝑦) (𝑨𝑙 ) = 𝑤 (𝑦) (𝑨𝑟 )
⎪
. (7) to realize the pattern matching step (see Fig. 1), and enable high
⎪
⎪
⎪𝑤 (𝑥) (𝑨𝑟 ) = 𝑤 (𝑦) (𝑨𝑏 ) accuracy of the layout parasitic extraction. This work does not build
⎪
⎪𝑤 (𝑦) (𝑨 ) = −𝑤 (𝑥) (𝑨 ) capacitance models based on machine learning. Instead, it explores
⎩ 𝑟 𝑏
another opportunity to improve the pattern matching method with
Based on (6) and (7) it is clear that the WVT values for one surface machine learning. Experiments are carried out with synthesized
panel can easily derive those for the 7 other symmetric points. 3-layer interconnect structures and validate accuracy improvement.
We proposed an approach to exploiting the above analysis, which Two interesting work were presented on DAC’2020, both from
reduces the pre-characterization data by about 8X. As shown in Fig. industry, for parasitic prediction with pre-layout design of analog
4(b), we only need to store the GFT and WVT values for the surface circuit. One focuses on analog IP design, and predicts effective re-
panels in the blue-shade region. This also brings the reduction of sistance and capacitance (𝑅𝑒 𝑓 𝑓 and 𝐶𝑒 𝑓 𝑓 ) of each net through a
memory cost by a similar ratio. We further developed an elaborate synthesized star topology of post-layout net [16]. The random forest
technique to accelerate the pre-characterization through solving a model is employed with input features regarding net’s connections
much smaller structure with FDM to obtain the GFTs and WVTs. to make prediction. Experiments with over 800 analog blocks (in-
Although the surface Green’s function and weight value may be cluding over 400K nets) on 14nm and 10nm processes show that
different from those in (3), as stated in (2) if the variance reduction the presented technique reduces the error between pre-layout and
is employed [34], their values can be easily derived from those post-layout circuit simulation from 37% to 8% averagely, thus reduc-
we discussed. And, the benefit of the symmetry of transition cube ing the number of iterations between pre-layout and post-layout
preserves. design phases. The other predicts net’s total capacitance and device
parameters by converting circuit schematics into graphs and lever-
2.2 Machine-Learning Based Parasitic aging fantastic graph convolutional network (GCN) techniques [14].
Extraction and Electrostatic Analysis The schematics of analog and mixed-signal circuits are viewed as
With rapid development of big data technology and high perfor- heterogeneous graphs inputting to a GCN called ParaGraph, which
mance computing, machine learning and deep learning methods incorporates key ideas from GraphSage, Relational GCN and Graph
have been applied in many areas. However, the application of them Attention Network. An ensemble modeling technique is also pre-
to parasitic extraction is not widely recognized. sented to improve the accuracy of capacitance over a large range.

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Advancements and Challenges on Parasitic Extraction for Advanced Process Technologies ASPDAC ’21, January 18–21, 2021, Tokyo, Japan

With 18 industrial circuits built on a sub-10nm process ParaGraph macromodel generated with BEM can cause large error in capaci-
is trained, and shows much better prediction accuracy than the tance results. This flaw was recently fixed by a reliable approach
models based on XGBoost and existing GCN models. On 67 circuit based on FDM [27]. The new macromodel generation technique
metrics of testing circuits, the simulation errors between pre-layout utilizes a modified FDM, and ensures the macromodel matrix’s
predictions and post-layout circuit is reduced to 9.6% on average. properties, so that it largely improves the reliability/accuracy of
There is also attempt applying machine learning to capacitance the macromodel-aware FRW algorithm. Another relevant work is
field solver. In [28], a single-layer perceptron NN was proposed to [42], which extends FEM and FRW method for simulating infinite
interpret the method of moments (MoM), a kind of BEM, for capac- large domain through new absorbing boundary conditions.
itance extraction. The solving process of MoM equation is turned
to machine learning training process. Though the idea is novel and 3 CHALLENGES FOR ADVANCED PROCESS
shows benefit, its application is limited due to the limitation of TECHNOLOGIES
MoM. As a related problem to capacitance extraction, electrostatic
simulation is also of concern. In [23], the convolutional neural net- In this section, we briefly review the challenges faced by parasitic
work (CNN) was presented to solve a toy electrostatic problem for extraction at advanced technology nodes.
computing the electric potential caused by a point excitation, in a
2-D square region. It presents an interesting idea expressing the 3.1 Manufacture-Aware Geometry Variation
input as image-like data and trains a CNN structure for the infer- Under advanced process technologies, the layout/geometry varia-
ence of potential map. Another CNN based method was recently tions of interconnect wires and dielectrics caused by manufacture
proposed for solving the electrostatics within VLSI layout, used in process (see Fig. 6) have larger impact on resistance and capaci-
time dependent dielectric breakdown (TDDB) aging analysis [13]. tance, and thus cannot be ignored. They can be modeled by foundry
It trains a CNN with same structure as that for image transforma- and provided to the extraction tool through the technology file.
tion to convert 2-D layout to map of electric potential. This runs However, these layout-dependent variations cause many conduc-
much faster than conventional method like finite element method tor/dielectric distortions and fragments, and bring challenge to
(FEM) and shows good accuracy for TDDB aging analysis. It should capacitance extraction. Firstly, some approximation must be used
be pointed out that deep learning is good at providing prediction in the pattern matching based method, and then causes inaccuracy.
instead of accurate solution. So, its application to capacitance field Secondly, for field solver, handling a large amount of fragment
solver or other scientific computations is still very limited. conductors/dielectrics may lead to considerable runtime cost.
Etch value
Thickness variation
H2
2.3 Other Related Work
H1 ILD thickness variation
Process variation becomes considerably large under advanced pro-
cess technology [33]. Several work involving random process vari-
ation were recently presented. In [11], the combination of FRW- (a) (b)
based capacitance extraction and the uncertainty quantification Figure 6: The manufacture-aware geometry variations,
based on generalized polynomial chaos (gPC) expansion with sto- where dashed line and solid line depict design and actual ge-
chastic testing method [41] is considered. To tackle the problem ometries, respectively. (a) conductor thickness variation and
that the randomness of capacitance values extracted with the FRW ILD thickness variation. (b) variation caused by etch effect.
algorithm deteriorates the accuracy of gPC interpolation, they pro- If multiple-patterning lithography technique is used, the mis-
posed a least-squares approximation based technique to accurately alignment of layouts affects capacitance extraction. How to effi-
deduce the detailed variational capacitance distribution due to wire ciently and effectively handling it is also of concern.
width and spacing variability. In [20], the process variation was
modeled with the corner based approach. Based on different par- 3.2 Random Process Variation
asitic extraction corner data from foundry on middle-end-of-line
Random process variation has larger impact at advanced technology
(MEOL) and back-end-of-line (BEOL) parasitics, a technique was
nodes. Existing corner based analysis and Monte Carlo simulation
proposed to tighten the parasitic corner range of customized design
cause either over design or large computational cost. Better random
pattern (𝑅𝑒 𝑓 𝑓 and 𝐶𝑒 𝑓 𝑓 ) through Monte Carlo simulation. It allevi-
variation modeling and accelerated variation-aware extraction for
ates the over-pessimistic or over-optimistic parasitic variation, and
actual scenarios are important research topics.
benefits the design with the advanced FinFET technology.
A topic on capacitance extraction is how to encrypt the structure
information from foundry or IP vendor while performing accurate 3.3 Accurate MEOL Capacitance Modeling
extraction. The idea of macromodel provides a potential solution. FinFETs are used under advanced process technology [36]. Due
A macromodel-aware random walk algorithm which combines the to its 3-D nature, it is not easy to accurately calculate the MEOL
macromodel and the FRW based extraction was proposed [32]. capacitances around FinFET (see Fig. 7). Even though additional 3-D
It not only resolves the contradiction between encrypting sensi- patterns are added to the pattern matching based method, the error
tive substructures and accurate extraction, but also accelerates the of capacitance extraction often exceeds 10% [19]. 3-D field solver is
extraction of structure with cyclic substructures. However, the able to deliver accurate result, but sacrifices CPU time. With more

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ASPDAC ’21, January 18–21, 2021, Tokyo, Japan Yu, et al.

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