FPGA Implementation of IoT-Based Health

Monitoring System
2021 15th International Conference on Telecommunication Systems, Services, and Applications (TSSA) | 978-1-6654-2892-7/21/$31.00 ©2021 IEEE | DOI: 10.1109/TSSA52866.2021.9768261

Shaker F. K. Abushukor, Infall Syafalni, Rahmat Mulyawan, Nana Sutisna, Nur Ahmadi, and Trio Adiono
University Center of Excellence on Microelectronics, Bandung Institute of Technology, Bandung, Indonesia
School of Electrical Engineering and Informatics, Bandung Institute of Technology, Bandung, Indonesia

Abstract—The electrocardiogram (ECG) is a very important II. P RELIMINARIES

biomedical signal that evaluates the electrical activity of the
heart. To diagnose heart disorders, different features should A. Electrocardiogram (ECG)
be extracted from the ECG signals. In this context, a fully The electrocardiograph signal has a specific shape. The ECG
FPGA-based system for ECG signal monitoring is proposed. The waveform reflects the electrical activity of the heart. It is widely
proposed QRS detection method is inspired by the Pan and
Tompkins algorithm. This paper shows a prototype for IoT-based used as a routine and a reference for determining heart health
health monitoring system design using FPGA. The system uses conditions by cardiologists. The ECG signal is a repetitive
a System-on-Chip FPGA with an embedded ARM processor and waveform that comprises several waves distinguished by each
the WiFi 802.11b/g/n operated at 2.4 GHz channel. The heart other by frequencies and amplitudes. An ECG is taken by
rate is monitored using an ECG sensor module. And, the body placing electrodes at certain points on the patient’s body. These
temperature is monitored using an NTC thermistor sensor with a
steel head. The ARM processor runs a RTOS to support real time waves originate from different parts of the heart. The ECG
monitoring. Moreover, the QRS module reads out the heart rate. signal is recorded using an electrocardiograph [5]. The order
The proposed design is implemented on the FPGA. The system of occurrence of the Electrocardiograph signal is as follows [6]:
extracts vital signals then sends the values to a smart device. • Vector depolarization (changes in electrical charge) atrial
The experimental results show that our system can detect the
heart rate. Moreover, the data is received successfully to the web contraction from the atrial sinus to the atrioventricular
interface. nodule as it occurs, generates a P -wave.
Keywords—FPGA Zynq, IoT, QRS detection, electrocardiogram • The R-wave signals the end of atrial contraction and the
(ECG), Pan and Tompkins algorithm beginning of ventricular contraction.
• The vector generated by ventricular depolarization gener-
I. I NTRODUCTION ates a QRS complex.
The field programmable gate array (FPGA) has been used • The vector generates a T -wave due to ventricular repolar-
for fast prototyping in many research fields. FPGA is preferred ization.
due to its high speed, low cost, and easy reconfiguration • The P -R interval is the time from the start of atrial
[1], [2]. It combines the high performance of ASICs and the contraction to the start of ventricular contraction.
flexibility of DSPs. Recently, the hardware implementation on • The R-T interval indicates muscle contraction (ventricular
FPGA is widely used for biomedical signal applications such systole), and the T -R interval indicates muscle relaxation
as electrocardiograms (ECG), electroencephalograms (EEG), (ventricular diastole).
and electromyograms (EMG). The electrocardiogram is the A signal obtained from a normal ECG is as shown in Fig. 1,
electrical recording tool using in the heart activity diagnosis. a normal ECG wave has the following characteristics [5]:
It consists of three main waves: P wave, T wave, and QRS
complex [4]. The electrocardiogram (ECG) signal is one of
the physiological signals that can be monitored by wearable
devices [3]. It can be used to keep track of the person’s heart
rate and to detect cardiac problems and other health issues. A
highly reliable algorithm for these tasks can be computationally
demanding and has real-time constraints. One of QRS and
arrhythmia detection algorithms is Pan and Tompkins scheme.
Hardware solution that is implemented in an FPGA has been
proposed [4]. This work explores the use of a SoC FPGA device
with a WiFi connection for the development of an IoT-based
health monitoring system design using FPGA. The heart rate is Fig. 1. Typical ECG of a healthy person [5]
calculated from the person’s ECG signal. Moreover, the body Basically there are three techniques used in electrocardiog-
temperature is also measured. The heart rate detection algorithm raphy as follows:
is partially running on custom hardware implemented in the • Standard Clinical ECG: 10 electrodes (12 leads) are used
FPGA. to analyze the patient’s heart health condition.

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 • Vectorcardiogram Modeling: The body potential is used 15 Hz, the first step of the signal will be passed through a
for a three-dimensional vector using Einthoven’s bipolar low pass filter formed from the transfer function equation:
leads. The method takes heart signals through 3 specific (1 − z −6 )2
points on the body. H(Z) = (1)
(1 − z −1 )2
• ECG Monitoring: This technique uses 1 or 2 electrodes
placed at certain body points. This technique is used to • High Pass Filter (HPF): After passing through the low
monitor patients. pass filter, as part of the signal filter process, the filtering
process will then be carried out through the high pass
The ECG signal analyzed is a signal taken using 3 leads
filter. After limiting the upper frequency through the low
according to the Einthoven triangle as shown in Fig. 2. In this
pass filter, in the process through this high pass filter, the
system, the ECG signal for each lead has potential difference
lower frequency limitation will be carried out. This high
[7].
pass filter is the result of subtraction of a first-order low
pass filter from an all pass filter with a delay. The low pass
filter for a sampling frequency of 200 Hz has a transfer
function as follows:
(1 − z −32 )
H(Z) = (2)
(1 − z −1 )
• Derivative: After filtering, the signal is differentiated to
provide the QRS-complex slope information. We use a
five-point derivative beside the transfer function:
1
H(Z) = (−z −2 − 2z −1 + 2z 1 + z 2 ) (3)
8T
Fig. 2. Einthoven’s triangle.
• Squaring Function: Squaring of the differentiated output
Lead I: The positive electrode is located on the left arm (LA).
signal makes the output signal positive and shows the
The negative electrode is located on the right arm (RA). We
larger QRS complex compared to other waves. The equa-
measure the potential difference between the two arms. For the
tion of squaring is given by:
other two limb leads, an electrode on the right leg serves as a
reference electrode for recording purposes. y(nT ) = [x(nT )]2 (4)
Lead II: The potential difference is found by the positive
• Moving Window Integration: It extracts the information
electrode on the left leg (LL) and the negative electrode on the
of QRS complex in addition to R wave. The window size
right arm (RA).
has to be taken properly if it is too large, then due to the
Lead III: The potential difference if found by the positive
integration QRS complex and T wave will merge and if it
electrode on the left leg (LL) and the negative electrode on the
is too small, then a single QRS complex produces multiple
left arm (LA).
peaks. The purpose of moving-window integration is to
obtain waveform feature information in addition to the
B. Pan-Tompkins Algorithm slope of the R wave. It is calculated from the following:
In this part, we describe the QRS detection method. It was N
1 X
inspired by the popular Pan and Tompkins algorithm. The Pan- y(nT ) = x(nT − (N − i)T ) (5)
Tompkins algorithm is a method for detecting QRS complexes N i=1
in real time developed by Jiapu Pan and Willis J. Tompkins
published in 1985 [1]. QRS waves are the waveforms that III. P ROPOSED S YSTEM U SING QRS M ETHOD
seem in most ECG signals. There are many strategies for A. System Design
detecting QRS waves on an electrocardiograph. The accuracy In general, the proposed system using QRS method block
of the detection of the R peak is a demand for the appropriate diagram is illustrated in Fig. 3 by implementing the 5 steps;
functioning of the ECG analysis. It computes the derivative of LPF, HPF, derivative, squaring, and thresholding. Moreover,
the ECG signal, squares the derivative point-by-point to per- the architecture of the implemented system can be seen below
form nonlinear amplification, uses moving-window integration Fig. 4.
to determine the width of the QRS complexes, and uses 2 The ECG signal is extracted from an ECG device by taking
adaptive thresholds to determine the position of the R-peaks. the electrical signals of the heart through electrodes mounted
This method is proposed to process the ECG signal on five on the patient’s body. The ECG signal preprocessed before
steps. The threshold is obtained before the QRS detection phase being converted to digital format using an Analog to Digital
[1]. These steps are described as follow: Converter (ADC) so that data processing can be carried out
• Low Pass Filter (LPF): In obtaining the maximum power by the FPGA. The ADC is shown as part of the FPGA board
from the QRS complex which is at a frequency of 5 Hz to as there is an ADC component included in the FPGA. The

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 Fig. 3. Proposed QRS Block Diagram

as a consumer interface.

B. Software and Hardware Design

1) Zynq SoC: The structure of the Xilinx Zynq-7000 con-
tains two elements [8]: the Processing System (PS) and the
Programmable Logic (PL). The PS is associated with the
processor and software program improvement and the PL is
associated with the FPGA board and hardware programmable
logic. The two elements could be interfaced with each other
with peripherals. Zynq projects can be entirely developed
on Xilinx’s Vivado Design Suite [8]. It includes the Vivado
Integrated Development Environment (IDE) and the Software
Development Kit (SDK), which can handle the hardware and
the software design respectively.
2) XADC: The Xilinx Analog-to-Digital Converter (XADC)
is a dual 12-bit ADC included as a hard component in the PL
of the Zynq device with a maximum sampling rate of a million
samples per second. It has an input range of 1V (0–1V). The
XADC is included in the hardware system using the XADC
Wizard core in this project. The PS interfaces directly with
Fig. 4. General architecture of system the XADC through the PS-XADC interface. Two channels of
the XADC are used to convert the analog signal from the
FPGA can read the ADC data and then send the data serially,
temperature and ECG sensors to digital format.
which will become the FPGA input data. The data will be
3) UART series: Communication between the ESP Module
stored in a register and will be converted into decimal form
and the FPGA uses a UART with a configuration of 8 data
for digital signal processing. In order to maximize the hardware
bits, no parity, and a baud rate of 115200 bps. Because the
capabilities of this device, the Pan Tomkins algorithm was used
communication is one-way, the pins used in the FPGA are the
to detect the modified QRS ECG signal by eliminating some
receive (rx) and ground (gnd) pins.
parts of the algorithm, namely the derivative process to reduce
processing time while saving resource usage logic gates in the 4) Heart Rate Calculator Core: This IP core was used to
FPGA. On other hand, the temperature sensor is a steel-head implement the Pan-Tomkins algorithm begins with determining
thermistor. Its conditioning circuit includes a simple voltage the specifications of the designed block. Furthermore, it de-
divider that displays the sensor’s resistance alteration with the scribes the constituent parts of the Pan-Tomkins algorithm to
change of the temperature. then be translated into the VHDL programming language. The
use of the Pan-Tomkins algorithm is modified by eliminating
The ESP module allows microcontrollers to connect to the derivative and integration parts.the axi wrapper RTL(IP)
a Wi-Fi network and performs simple TCP/IP connections creat for Pan-Tomkins algorithm on Vivado IDE.
using Hayes-style commands. It receives the heart rate and 5) Web Page: A simple web page was developed by html
temperature from the SoC FPGA through a one-way UART language to serve as the user interface for this system. The user
serial connection. Those values are received by a smart device will see the values updated once every second. Fig. 6 shows a
connected to this module and display webpage which is used screen capture of the web page when connected to the system.

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 6) ECG module: The AD8232 is an integrated signal con- 3) Derivative Filter: After passing through the band pass
ditioning block for ECG and other biopotential measurement filter, the ECG signal which now has left its optimal frequency
applications. It is designed to extract, amplify, and filter small will be differentiated in order to obtain slope information. This
biopotential signals in the presence of noisy conditions, such differentiation system is implemented based on the equation:
as those created by motion or remote electrode placement [9]. 1
7) Temperature Sensor: We use an analog thermometer 3950 y(n) = [2x(n) + x(n − 1) − x(n − 3) − 2x(n − 4)] (8)
8
NTC (negative temperature coefficient) with a steel-head NTC 4) Square Function: The process carried out on the next
thermistor. Its voltage range is 3.0V to 5V. And, it measures signal is squaring with the aim of obtaining the absolute
temperatures from -55C to +105C. This sensor has a nominal value of the signal. This process occurs in the block quadratic
resistance of 10k at 25C and an accuracy of 1%. function system, which in this implementation is designed as a
8) Modul NodeMCU ESP8266: NodeMCU is an electronic block consisting of a 10 × 10 bit multiplier with both operands
board based on the ESP8266 chip with the ability to run mi- being x(n). So, it represents (x(n))2 .
crocontroller functions and also an internet connection (WiFi). 5) Integration: In this block, the system is integrated with
There are several I/O pins so that they can be developed into a the aim of obtaining a graph of the trend of the signal value for
monitoring and controlling application for IOT projects. The a certain period. The technique used is to find the average value
NodeMCU ESP8266 can be programmed with the Arduino of the input during the period. In the system implemented this
compiler, using the Arduino IDE. time, the period used is 32 sampling, meaning that the value
taken is the result of the sum of the previous 32 inputs then
C. Proposed ECG Signal Processing divided by 32. This value of 32 is the best multiple of two
This section explains the processing steps that the system of the simulated results. Thus, the following equation for the
is set to perform on the ECG signal, with the goal of getting moving window integral is obtained:
the person’s heart rate as shown in Fig. 4. The QRS detection 1
y(n) = [x(n − 32) + x(n − 31) + . . . + x(n)]
algorithm used in this system is Pan-Tompkins method [1]. Fur- 32
thermore, it will be explained about the implementation of the 32
1 X
QRS detection system in the VHDL program architecture. The = x(n − i) (9)
32 i=0
designed VHDL program architecture is divided into 5 blocks
according to the block in the Pan-Tompkins QRS detection 6) Threshold: The next block of the system to be realized
algorithm where for each block it will be further divided into is the threshold block. In this block, a limit value of the signal
several sub-blocks that adapt to the block’s working system. from the output of the integration block will be given, where
Then it will be implemented on the FPGA board. In this a signal that has a value above the threshold will be identified
algorithm, the principle used in detecting the QRS complex as a signal peak and given a value of ’1’, while values below
is to perform signal processing in the form of signal filtering the threshold will not be identified and assigned a value of ’0’.
at the optimal frequency where the QRS complex works.In
IV. R ESULTS AND D ISCUSSIONS
its implementation, each block of the Pan-Tompkins algorithm
system will be translated into the architecture of the VHDL A. System Simulation On Vivado IDE
program. Firstly, The system tested by ECG signal generated on ECG
1) Low Pass Filter: In this block a system will be designed simulator on several frequencies and positions. The system
that can limit the frequency of the input signal, the frequency gives a correct response and results the signals that are gen-
used here is around 11 Hz with a sampling of 200 samples per erated by the ECG simulator. Moreover, the system need to
second so that according to the Pan-Tompkins algorithm the be tested in real time through the implementation of the ECG
difference filter equation used is: sensor that connect with the FPGA. The verification has to be
no errors in the testbench simulation.
y(n) = 2y(n − 1) − y(n − 2) The generated ECG signal is set to output a normal ECG
+ x(n) − 2x(n − 6) + x(n − 12) (6) signal with a heart rate of around 60-70 bpm as shown in Fig. 7.
Generally, the system has been capable to detect all data of
2) High Pass Filter: After passing through the low pass signal QRS complex that is generated in the testbench when
filter, the ECG signal will then undergo a second filtering which the system is tested. The tested system is shown in Fig. 5.
this time is used to limit the low frequencies that will be passed. B. Testing the Implementation Results on ZYBO
The cut off frequency used is 5 Hz with the difference equation
of the filter: After the simulation on Vivado IDE is done, since the tested
result is correct and working properly, the next step is to
implementation of the ECG sensor and temperature sensor that
y(n) = y(n − 1) + x(n − 16) − x(n − 17) connect with FPGA on real time. The ECG signal comes from
1 ECG sensor that connects directly to the FPGA through FPGA’s
− [x(n) − x(n − 32)] (7) ADC to convert the signal from the analog to the digital form.
32

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 2
Generated Heart Pulse
1.5

Amplitude (mv)
1

Fig. 5. ECG decision and derivative signal 0.5

It is the same for temperature sensor that connect to FPGA’s
ADC too. The converted ECG signal then is processed on the 0
heart rate calculator core based on the Pan Tompkins algorithm.
Finally, it sends the data to the ESP module by serial UART-lite
−0.5
module to display the result on the web page.
The test also was performed on a normal person in a good
health. A temperature result of 36°C was obtained, for the heart −1
0 1 2 3 4 5
rate of 74 beats per minute (bpm). It was obtained as shown in
Fig. 6. Time in Second
Fig. 7. Generated Normal Heart Pulse

50
Detected Heart Pulse

25
Detected Data

−25

−50
0 100 200 300 400 500
Clock Cycle
Fig. 6. Web page as interface system
Fig. 8. Detected Heart Pulse by the Proposed System
Fig. 8 is shown a plot of the ECG signal that generated
from the ECG sensor and acquired by the system. The signal R EFERENCES
evaluation shows that the algorithm is capable to avoid false [1] J. Pan and W. J. Tompkins, “A Real-Time QRS Detection Algorithm,”
QRS detections during the T wave while its amplitude is IEEE Transations on Biomedical Engineering, pp. 230-236, 1985.
[2] J. Heaffey, et. al., “Live demonstration: Wearable device for remote EMG
superior to the R peak. As seen in the Fig. 8, the signal has and muscle fatigue monitoring,” IEEE Biomedical Circuits and Systems
little noise caused by the moving of the person while doing the Conference (BioCAS), pp. 1–5, 2015.
test. [3] Toshiyo Tamura, et. al., “Wearable photoplethysmographic sensors—past
and present,” Electronics, pp. 282–302, 2014.
V. C ONCLUSIONS [4] T. Shany, et. al., “Sensors-based wearable systems for monitoring of
human movement and falls,” IEEE Sensors journal, 12.3, pp. 658–670,
The IoT-based health monitoring system design using FPGA 2011.
[5] Adam Page, et. al., “Low-power manycore accelerator for personalized
to monitor heart rate and body temperature has been suc- biomedical applications,” Proceedings of the 26th edition on Great Lakes
cessfully implemented. This system is based on the Pan and Symposium on VLSI, pp. 63–68, 2016.
Tompkins algorithm and optimized to be implemented in FPGA [6] Patrick S. Hamilton, Willis J. Tomkins, “Quantitative investigation of
QRS detection rules using the MIT/BIH arrhythmia database,” IEEE
board (ZYBO) using the VHDL language to create custom IP Transactions on Biomedical Engineering, No. 12, pp. 1157-1165, 1986.
core for heart rate detection on Vivado IDE. The results of the [7] Richard E. Klabunde, Cardiovascular Physiology Concepts, Lippincott
project’s test show that the system is able to give reliable data Williams and Wilkins, 2011.
[8] Mohcin Mekhfioui, et. al., “Hardware Implementation of Blind Source
on the real-time heart rate and temperature of the user. The web Separation Algorithm Using ZYBO Z7 and Xilinx System Generator,”
page displays the result on the smart device while connecting to 2020 REDEC, pp. 1-5, 2020.
internet server and it makes easier user experience. The design [9] AD8232, Data Sheet. “Single-Lead, Heart Rate Monitor Front End”,
Analog Device, 2013.
is useful for health monitoring devices.

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