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Logic Eqations On Xilinx

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aaditi.aspatil
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14 views6 pages

Logic Eqations On Xilinx

Uploaded by

aaditi.aspatil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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F=m(1,3,5)

CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logic_fuc is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
y : out STD_LOGIC);
end logic_fuc;
architecture Behavioral of logic_fuc is
begin
y<=(not (b) and c) or (c and not (a));
end Behavioral;
Binary to gray

1.

2.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b_gray is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
g0 : out STD_LOGIC;
g1 : out STD_LOGIC;
g2 : out STD_LOGIC;
g3 : out STD_LOGIC);
end b_gray;

architecture Behavioral of b_gray is

begin
g0<=a xor b;
g1<=b xor c;
g2<=c xor d;
g3<=d;

end Behavioral;
GRAY TO BINARY
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gray_bin is
Port ( g : in STD_LOGIC_VECTOR (3 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0));
end gray_bin;
architecture Behavioral of gray_bin is
begin
b(3)<=g(3);
b(2)<=g(2);
b(1)<=(g(1) and not (g(0))) or (g(1) and g(2))or (g(3)and g(1))or (not
(g(3))and not (g(2))and not (g(1)) and g(0));
b(0)<=g(0);
end Behavioral;

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