ADC0816/ADC0817 8-Bit mP Compatible A/D Converters with 16-Channel Multiplexer

December 1994

ADC0816/ADC0817 8-Bit mP Compatible A/D Converters

with 16-Channel Multiplexer
General Description Features
The ADC0816, ADC0817 data acquisition component is a Y Easy interface to all microprocessors, or operates
monolithic CMOS device with an 8-bit analog-to-digital con- ‘‘stand alone’’
verter, 16-channel multiplexer and microprocessor compati- Y Operates ratiometrically or with 5 VDC or analog span
ble control logic. The 8-bit A/D converter uses successive adjusted voltage reference
approximation as the conversion technique. The converter Y 16-channel multiplexer with latched control logic
features a high impedance chopper stabilized comparator, a Y Outputs meet TTL voltage level specifications
256R voltage divider with analog switch tree and a succes- Y 0V to 5V analog input voltage range with single 5V sup-
sive approximation register. The 16-channel multiplexer can ply
directly access any one of 16-single-ended analog signals, Y No zero or full-scale adjust required
and provides the logic for additional channel expansion. Sig-
nal conditioning of any analog input signal is eased by direct
Y Standard hermetic or molded 40-pin DIP package
access to the multiplexer output, and to the input of the 8-bit
Y Temperature range b40§ C to a 85§ C or b55§ C to
a 125§ C
A/D converter.
The device eliminates the need for external zero and full-
Y Latched TRI-STATE output
scale adjustments. Easy interfacing to microprocessors is
Y Direct access to ‘‘comparator in’’ and ‘‘multiplexer out’’
provided by the latched and decoded multiplexer address for signal conditioning
inputs and latched TTL TRI-STATEÉ outputs. Y ADC0816 equivalent to MM74C948
The design of the ADC0816, ADC0817 has been optimized
Y ADC0817 equivalent to MM74C948-1
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0816, ADC0817 offers high Key Specifications
speed, high accuracy, minimal temperature dependence, Y Resolution 8 Bits
excellent long-term accuracy and repeatability, and con- Y Total Unadjusted Error g (/2 LSB and g 1 LSB
sumes minimal power. These features make this device Y Single Supply 5 VDC
ideally suited to applications from process and machine Y Low Power 15 mW
control to consumer and automotive applications. For simi- Y Conversion Time 100 ms
lar performance in an 8-channel, 28-pin, 8-bit A/D convert-
er, see the ADC0808, ADC0809 data sheet. (See AN-258
for more information.)

Block Diagram

TL/H/5277 – 1

C1995 National Semiconductor Corporation TL/H/5277 RRD-B30M115/Printed in U. S. A.

 Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required, ESD Susceptibility (Note 9) 400V
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications. Operating Conditions (Notes 1 & 2)
Supply Voltage (VCC) (Note 3) 6.5V Temperature Range (Note 1) TMINsTAsTMAX
Voltage at Any Pin b 0.3V to (VCC a 0.3V) ADC0816CCJ, ADC0816CCN, b 40§ C s TA s a 85§ C
Except Control Inputs ADC0817CCN
Voltage at Control Inputs b 0.3V to 15V Range of VCC (Note 1) 4.5 VDC to 6.0 VDC
(START, OE, CLOCK, ALE, EXPANSION CONTROL, Voltage at Any Pin 0V to VCC
ADD A, ADD B, ADD C, ADD D) Except Control Inputs
Storage Temperature Range b 65§ C to a 150§ C Voltage at Control Inputs 0V to 15V
Package Dissipation at TA e 25§ C 875 mW (START, OE, CLOCK, ALE, EXPANSION CONTROL,
Lead Temp. (Soldering, 10 seconds) ADD A, ADD B, ADD C, ADD D)
Dual-In-Line Package (Plastic) 260§ C
Dual-In-Line Package (Ceramic) 300§ C
Molded Chip Carrier Package
Vapor Phase (60 seconds) 215§ C
Infrared (15 seconds) 220§ C

Electrical Characteristics
Converter Specifications: VCC e 5 VDC e VREF( a ), VREF(b) e GND, VIN e VCOMPARATOR IN,TMINsTMAX and fCLK e 640 kHz
unless otherwise stated.
Symbol Parameter Conditions Min Typ Max Units
ADC0816
Total Unadjusted Error 25§ C g (/2 LSB
(Note 5) TMIN to TMAX g */4 LSB
ADC0817
Total Unadjusted Error 0§ C to 70§ C g1 LSB
(Note 5) TMIN to TMAX g 1(/4 LSB
Input Resistance From Ref( a ) to Ref(b) 1.0 4.5 kX
Analog Input Voltage Range (Note 4)V( a ) or V(b) GNDb0.10 VCC a 0.10 VDC
VREF( a ) Voltage, Top of Ladder Measured at Ref( a ) VCC VCC a 0.1 V
VREF( a ) a VREF(b)
Voltage, Center of Ladder VCC/2b0.1 VCC/2 VCC/2 a 0.1 V
2
VREF(b) Voltage, Bottom of Ladder Measured at Ref(b) b 0.1 0 V
Comparator Input Current fc e 640 kHz, (Note 6) b2 g 0.5 2 mA

Electrical Characteristics
Digital Levels and DC Specifications: ADC0816CCJ, ADC0816CCN, ADC0817CCNÐ4.75VsVCCs5.25V, b40§ CsTAs a 85§ C
unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
ANALOG MULTIPLEXER
RON Analog Multiplexer ON (Any Selected Channel)
Resistance TA e 25§ C, RL e 10k 1.5 3 kX
TA e 85§ C 6 kX
TA e 125§ C 9 kX
DRON DON Resistance Between Any (Any Selected Channel) 75 X
2 Channels RL e 10k
IOFF a OFF Channel Leakage Current VCC e 5V, VIN e 5V,
TA e 25§ C 10 200 nA
TMIN to TMAX 1.0 mA
IOFF(b) OFF Channel Leakage Current VCC e 5V, VIN e 0,
TA e 25§ C b 200 nA
TMIN to TMax b 1.0 mA
CONTROL INPUTS
VIN(1) Logical ‘‘1’’ Input Voltage VCCb1.5 V
VIN(0) Logical ‘‘0’’ Input Voltage 1.5 V

2
Electrical Characteristics (Continued)
Digital Levels and DC Specifications: ADC0816CCJ, ADC0816CCN, ADC0817CCNÐ4.75VsVCC s5.25V, b40§ CsTAs a 85§ C
unless otherwise noted.

Symbol Parameter Conditions MIn Typ Max Units

CONTROL INPUTS (Continued)
IIN(1) Logical ‘‘1’’ Input Current VIN e 15V 1.0 mA
(The Control Inputs)
IIN(0) Logical ‘‘0’’ Input Current VIN e 0 b 1.0 mA
(The Control Inputs)
ICC Supply Current fCLK e 640 kHz 0.3 3.0 mA
DATA OUTPUTS AND EOC (INTERRUPT)
VOUT(1) Logical ‘‘1’’ Output Voltage IOb360 mA, TA e 85§ C VCCb0.4 V
IO eb300 mA, TA e 125§ C
VOUT(0) Logical ‘‘0’’ Output Voltage IO e 1.6 mA 0.45 V
VOUT(0) Logical ‘‘0’’ Output Voltage EOC IO e 1.2 mA 0.45 V
IOUT TRI-STATE Output Current VO e VCC 3.0 mA
VO e 0 b 3.0 mA

Electrical Characteristics
Timing Specifications: VCC e VREF( a ) e 5V, VREF(b) e GND, tr e tf e 20 ns and TA e 25§ C unless otherwise noted.

Symbol Parameter Conditions Min Typ Max Units

tWS Minimum Start Pulse Width (Figure 5) (Note 7) 100 200 ns
tWALE Minimum ALE Pulse Width (Figure 5) 100 200 ns
ts Minimum Address Set-Up Time (Figure 5) 25 50 ns
TH Minimum Address Hold Time (Figure 5) 25 50 ns
tD Analog MUX Delay Time RS e OX(Figure 5) 1 2.5 mS
from ALE
tH1, tH0 OE Control to Q Logic State CL e 50 pF, RL e 10k (Figure 8) 125 250 ns
t1H, t0H OE Control to Hi-Z CL e 10 pF, RL e 10k (Figure 8) 125 250 ns
tC Conversion Time fc e 640 kHz, (Figure 5) (Note 8) 90 100 116 ms
fc Clock Frequency 10 640 1280 kHz
tEOC EOC Delay Time (Figure 5) 0 8 a 2ms Clock
Periods
CIN Input Capacitance At Control Inputs 10 15 pF
COUT TRI-STATE Output At TRI-STATE Outputs (Note 8) 10 15 pF
Capacitance
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the VCC supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of
4.900 VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3 . None of these A/Ds requires a zero or full-scale adjust. However, if an
all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages can be
adjusted to achieve this. See Figure 13 .
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6) . See paragraph 4.0.
Note 7: If start pulse is asynchronous with converter clock or if fc l 640 kHz, the minimum start pulse width is 8 clock periods plus 2 ms. For synchronous operation
at fc s 640 kHz take start high within 100 ns of clock going low.
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9: Human body model, 100 pF discharged through a 1.5 kX resistor.

3
Functional Description
Multiplexer: The device contains a 16-channel single-end- Additional single-ended analog signals can be multiplexed
ed analog signal multiplexer. A particular input channel is to the A/D converter by disabling all the multiplexer inputs
selected by using the address decoder. Table 1 shows the using the expansion control. The additional external signals
input states for the address line and the expansion control are connected to the comparator input and the device
line to select any channel. The address is latched into the ground. Additional signal conditioning (i.e., prescaling, sam-
decoder on the low-to-high transition of the address latch ple and hold, instrumentation amplification, etc.) may also
enable signal. be added between the analog input signal and the compara-
TABLE 1 tor input.
Selected Address Line Expansion CONVERTER CHARACTERISTICS
Analog Channel D C B A Control The Converter
IN0 L L L L H The heart of this single chip data acquisition system is its 8-
bit analog-to-digital converter. The converter is designed to
IN1 L L L H H
give fast, accurate, and repeatable conversions over a wide
IN2 L L H L H
range of temperatures. The converter is partitioned into 3
IN3 L L H H H major sections: the 256R ladder network, the successive
IN4 L H L L H approximation register, and the comparator. The converter’s
IN5 L H L H H digital outputs are positive true.
IN6 L H H L H The 256R ladder network approach (Figure 1) was chosen
IN7 L H H H H over the conventional R/2R ladder because of its inherent
IN8 H L L L H monotonicity, which guarantees no missing digital codes.
IN9 H L L H H Monotonicity is particularly important in closed loop feed-
IN10 H L H L H back control systems. A non-monotonic relationship can
IN11 H L H H H cause oscillations that will be catastrophic for the system.
Additionally, the 256R network does not cause load varia-
IN12 H H L L H
tions on the reference voltage.
IN13 H H L H H
The bottom resistor and the top resistor of the ladder net-
IN14 H H H L H
work in Figure 1 are not the same value as the remainder of
IN15 H H H H H the network. The difference in these resistors causes the
All Channels OFF X X X X L output characteristic to be symmetrical with the zero and
X e don’t care full-scale points of the transfer curve. The first output tran-
sition occurs when the analog signal has reached a (/2 LSB
and succeeding output transitions occur every 1 LSB later
up to full-scale.

TL/H/5277 – 2
FIGURE 1. Resistor Ladder and Switch Tree

4
 TL/H/5277 – 3 TL/H/5277 – 4
FIGURE 2. 3-Bit A/D Transfer Curve FIGURE 3. 3-Bit A/D Absolute Accuracy Curve

TL/H/5277 – 5
FIGURE 4. Typical Error Curve

Timing Diagram

TL/H/5277 – 7
FIGURE 5

5
The successive approximation register (SAR) performs 8 it- The most important section of the A/D converter is the
erations to approximate the input voltage. For any SAR type comparator. It is this section which is responsible for the
converter, n-iterations are required for an n-bit converter. ulimate accuracy of the entire converter. It is also the com-
Figure 2 shows a typical example of a 3-bit converter. In the parator drift which has the greatest influence on the repeat-
ADC0816, ADC0817, the approximation technique is ex- ability of the device. A chopper-stabilized comparator pro-
tended to 8 bits using the 256R network. vides the most effective method of satisfying all the convert-
The A/D converter’s successive approximation register er requirements.
(SAR) is reset on the positive edge of the start conversion The chopper-stabilized comparator converts the DC input
(SC) pulse. The conversion is begun on the falling edge of signal into an AC signal. This signal is then fed through a
the start conversion pulse. A conversion in process will be high gain AC amplifier and has the DC level restored. This
interrupted by receipt of a new start conversion pulse. Con- technique limits the drift component of the amplifier since
tinuous conversion may be accomplished by tying the end- the drift is a DC component which is not passed by the AC
of-conversion (EOC) output to the SC input. If used in this amplifier. This makes the entire A/D converter extremely
mode, an external start conversion pulse should be applied insensitive to temperature, long term drift and input offset
after power up. End-of-conversion will go low between 0 errors.
and 8 clock pulses after the rising edge of start conversion. Figure 4 shows a typical error curve for the ADC0816 as
measured using the procedures outlined in AN-179.

Connection Diagram
Dual-In-Package

TL/H/5277 – 6
Order Number ADC0816CCN, ADC0817CCN,
ADC0816CCJ or ADC0816CJ
See NS Package Number J40A or N40A

6
Typical Performance Characteristics

TL/H/5277 – 8
FIGURE 6. Comparator IIN vs VIN FIGURE 7. Multiplexer RON vs VIN
(VCC e VREF e 5V) (VCC e VREF e 5V)

TRI-STATE Test Circuits and Timing Diagrams

TL/H/5277 – 9

TL/H/5277 – 10
FIGURE 8

7
Applications Information
OPERATION
1.0 RATIOMETRIC CONVERSION Ratiometric transducers such as potentiometers, strain
The ADC0816, ADC0817 is designed as a complete Data gauges, thermistor bridges, pressure transducers, etc., are
Acquisition System (DAS) for ratiometric conversion sys- suitable for measuring proportional relationships; however,
tems. In ratiometric systems, the physical variable being many types of measurements must be referred to an abso-
measured is expressed as a percentage of full-scale which lute standard such as voltage or current. This means a sys-
is not necessarily related to an absolute standard. The volt- tem reference must be used which relates the full-scale
age input to the ADC0816 is expressed by the equation voltage to the standard volt. For example, if VCC e VREF e
5.12V, then the full-scale range is divided into 256 standard
VIN DX
e steps. The smallest standard step is 1 LSB which is then 20
VfsbVZ DMAXbDMIN (1) mV.
VIN e Input voltage into the ADC0816 2.0 RESISTOR LADDER LIMITATIONS
Vfs e Full-scale voltage The voltages from the resistor ladder are compared to the
VZ e Zero voltage selected input 8 times in a conversion. These voltages are
DX e Data point being measured coupled to the comparator via an analog switch tree which
DMAX e Maximum data limit is referenced to the supply. The voltages at the top, center
and bottom of the ladder must be controlled to maintain
DMIN e Minimum data limit proper operation.
The top of the ladder, Ref( a ), should not be more positive
A good example of a ratiometric transducer is a potentiome- than the supply, and the bottom of the ladder, Ref(b),
ter used as a position sensor. The position of the wiper is should not be more negative than ground. The center of the
directly proportional to the output voltage which is a ratio of ladder voltage must also be near the center of the supply
the full-scale voltage across it. Since the data is represent- because the analog switch tree changes from N-channel
ed as a proportion of full-scale, reference requirements are switches to P-channel switches These limitations are auto-
greatly reduced, eliminating a large source of error and cost maticaly satisfied in ratiometric systems and can be easily
for many applications. A major advantage of the ADC0816, met in ground referenced systems.
ADC0817 is that the input voltage range is equal to the sup- Figure 10 shows a ground referenced system with a sepa-
ply range so the transducers can be connected directly rate supply and reference. In this system, the supply must
across the supply and their outputs connected directly into be trimmed to match the reference voltage. For instance, if
the multiplexer inputs, (Figure 9 ). a 5.12V reference is used, the supply should be adjusted to
the same voltage within 0.1V.

TL/H/5277 – 11
FIGURE 9. Ratiometric Conversion System

8
Applications Information (Continued)
The ADC0816 needs less than a milliamp of supply current The top and bottom ladder voltages cannot exceed VCC
so developing the supply from the reference is readily ac- and ground, respectively, but they can be symmetrically less
complished. In Figure 11 a ground references system is than VCC and greater than ground. The center of the ladder
shown which generates the supply from the reference. The voltage should always be near the center of the supply. The
buffer shown can be an op amp of sufficient drive to supply sensitivity of the converter can be increased, (i.e., size of
the millliamp of supply current and the desired bus drive, or the LSB steps decreased) by using a symmetrical reference
if a capacitive bus is driven by the outputs a large capacitor system. In Figure 13 , a 2.5V reference is symmetrically cen-
will supply the transient supply current as seen in Figure 12 . tered about VCC/2 since the same current flows in identical
The LM301 is overcompensated to insure stability when resistors. This system with a 2.5V reference allows the LSB
loaded by the 10 mF output capacitor. to be half the size of the LSB in a 5V reference system.

TL/H/5277 – 12
FIGURE 10. Ground Referenced
Conversion System Using Trimmed Supply

TL/H/5277 – 13
FIGURE 11. Ground Referenced Conversion System with
Reference Generating VCC Supply

9
Applications Information (Continued)

TL/H/5277 – 14
FIGURE 12. Typical Reference and Supply Circuit

TL/H/5277 – 15
FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
The transition between adjacent codes N and N a 1 is The output code N for an arbitrary input are the integers
given by: within the range:

Ð (V Ð 256 ( (
N 1 VINbVREF(b)
VIN e REF( a ) b VREF(b)) a g VTUE a VREF(b) (2) Ne c 256 g Absolute Accuracy (4)
512
VREF( a )bVREF(b)
The center of an output code N is given by:
where: VIN e Voltage at comparator input
Ð (V Ð 256 ( (
N
VIN e REF( a ) b VREF(b)) g VTUE a VREF(b) (3) VREF e Voltage at Ref( a )
VREF e Voltage at Ref(b)
VTUE e Total unadjusted error voltage (typically
VREF( a ) d 512)

10
Applications Information (Continued)
4.0 ANALOG COMPARATOR INPUTS If no filter capacitors are used at the analog or comparator
The dynamic comparator input current is caused by the peri- inputs and the signal source impedances are low, the com-
odic switching of on-chip stray capacitances These are con- parator input current should not introduce converter errors,
nected alternately to the output of the resistor ladder/switch as the transient created by the capacitance discharge will
tree network and to the comparator input as part of the die out before the comparator output is strobed.
operation of the chopper stabilized comparator. If input filter capacitors are desired for noise reduction and
The average value of the comparator input current varies signal conditioning they will tend to average out the dynamic
directly with clock frequency and with VIN as shown in Fig- comparator input current. It will then take on the character-
ure 6 . istics of a DC bias current whose effect can be predicted
conventionally. See AN-258 for further discussion.
Typical Application

TL/H/5277 – 16
*Address latches needed for 8085 and SC/MP interfacing the ADC0816, 17 to a microprocessor

Microprocessor Interface Table

PROCESSOR READ WRITE INTERRUPT (COMMENT)
8080 MEMR MEMW INTR (Thru RST Circuit)
8085 RD WR INTR (Thru RST Circuit)
Z-80 RD WR INT (Thru RST Circuit, Mode 0)
SC/MP NRDS NWDS SA (Thru Sense A)
6800 VMA # w 2 # R/W VMA # Q2 # R/W IRQA or IRQB (Thru PIA)

Ordering Information
TEMPERATURE RANGE b 40§ C to a 85§ C

g (/2 Bit Unadjusted ADC0816CCN ADC0816CCJ

Error
g 1 Bit Unadjusted ADC0817CCN
Package Outline N40A Molded DIP J40A Hermetic DIP

11
12
Physical Dimensions inches (millimeters)

Cavity Dual-In-Line Package (J)

NS Package Number J40A

13
ADC0816/ADC0817 8-Bit mP Compatible A/D Converters with 16-Channel Multiplexer
Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

NS Package Number N40A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, Kowloon
Fax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong
Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.