Logic Design and Computer

Organization
TCS 308

Dr. Gourav Verma

Associate Prof. /ECE
 Karnaugh Maps (K-Maps)

• A visual way to simplify logic expressions

• It gives the most simplified form of the expression
 Karnaugh Maps…

• Algebraic procedures:
• Difficult to apply in a systematic way.
• Difficult to tell when you have arrived at a minimum solution.
• Karnaugh map (K-map) can be used to minimize functions of up to 6
variables.
– K-map is directly applied to two-level networks composed of AND and OR gates.
• Sum-of-products, (SOP)
• Product-of-sum, (POS).
 Minimum SOP
• It has a minimum no. of terms.
– That is, it has a minimum number of gates.
• It has a minimum no. of gate inputs.
– That is, minimum no. of literals.
– Each term in the minimum SOP is a prime implicant, i.e., it cannot be
combined with others.
• It may not be unique.
– Depend on the order in which terms are combined or eliminated.
 Minimum POS
• It has a minimum no. factors.
• It has a minimum no. of literals.
• It may not be unique.
– Use (X+Y) (X+Y’) = X
– Use (X +C) (X’ + D)(C+D) = (X+C)(X’+D) to eliminate term.
 Rules to obtain the most simplified expression
•Simplification of logic expression using Boolean algebra is awkward
because:
– it lacks specific rules to predict the most suitable next step in the simplification
process
– it is difficult to determine whether the simplest form has been achieved.
•A Karnaugh map is a graphical method used to obtained the most
simplified form of an expression in a standard form (Sum-of-Products or
Product-of-Sums).
•The simplest form of an expression is the one that has the minimum
number of terms with the least number of literals (variables) in each term.
•By simplifying an expression to the one that uses the minimum number of
terms, we ensure that the function will be implemented with the minimum
number of gates.
•By simplifying an expression to the one that uses the least number of
literals for each terms, we ensure that the function will be implemented
with gates that have the minimum number of inputs.
Three-Variable K-Maps
 K Map Example

– K-map of F(a,b,c) = ∑m(1,3,5)

=∏M(0,2,4,6,7)
Place Product Terms on
K Map
• Example
– Place b, bc’ and ac’ in the 3-variable
K map.
 More Example

– Exercise. Plot f(a, b, c) = abc’ +

b’c + a’ into the K-map.
 Simplication Example
• Exercise. Simplify: F(a,b,c) =
∑m(1,3,5)
• Procedure: place minterms into map.
• Select adjacent 1’s in group of two 1’s
or four 1’s etc.
• Kick off x and x’.
 More Example

– The complement of F
• Using four 1’s to eliminate two
variables.
 Redundant Terms

• If a term is covered by two other terms, that term is redundant. That is, it is
a consensus term.
• Example: yz is the redundant.
 More Than Two Minimum Solutions

• F = ∑ m(0,1,2,5,6,7)
Three-Variable K-Map Examples
 4-Variable K Map

– Each minterm is adjacent to 4 terms with which it can

combine.
• 0, 8 are adjacent squares
• 0, 2 are adjacent squares, etc.
• 1, 4, 13, 7 are adjacent to 5.
 Plot a 4-variable Expression

• F(a,b,c,d) = acd + a’b + d’

acd = 1 if a=1, c=1, d=1
 Simplification Example

– Minterms are combined in groups of 2, 4, or 8 to

eliminate 1, 2, 3 variables.
– Corner terms.
 Simplification with Don’t Care

• Don’t care “x” is covered if it helps. Otherwise leave it along.

 Get a Minimum POS Using K Map

• Cover 0’s to get simplified POS.

– We want 0 in each term.
Determination of Minimum Expressions Using Essential Prime Implicants

• Definitions:
– Implicants: An implicant of a function F is a single
element of the on set (1) or any group of elements
that can be combined together in a K-map.
– Prime Implicants: An implicant that cannot be
combined with another to eliminate a literal.
– Essential Prime Implicants: If a particular element
of the on-set is covered by a single prime implicant.
That implicant is called an essential prime
implicant.
• All essential primes must be part of the
minimized expression.
 Implicant of F
• Implicant
– Any single 1 or any group of 1’s
• Prime implicant
– An implicant that can not be combined with another term to eliminate a variable.
– a’b’c, a’cd’, ac’ are prime implicant.
– a’b’c’d’ is not (combined with a’b’cd’). abc’ and ab’c’ are not.
 Prime Implicant
• A single 1 which is not adjacent to any other 1’s.
• Two adjacent 1’s which are not contained in a group of four 1’s. And so
on.
– Shaded loops are also prime implicants, but not part of the minimum
solution.
– a’c’d and b’cd are already covered by other group. So we do not need
them.
 Essential Prime Implicants for Minimum SOP
• If CD is chosen first, then f has 4 terms. We don’t need CD since it is covered
by other group. CD is not a essential prime implicant.
• m2 is essential prime implicant since it is covered only be one prime
implicant. So does m5, and m14. We need them in the answer.
 Rule of Thumb

– Look at all squares adjacent to a minterm.

– If the given minterm and all of the 1’s adjacent to it are covered by a single term, then that term
is an essential prime implicant
– But if it is covered by more than two prime implicant, we can not tell whether this term is
essential or not.
– The solution is A’C’ + A’B’D’ +ACD + (A’BD or BCD).
PI/EPI/RPI examples…
 Ex…

Given F = ∑(1, 5, 6, 7, 11, 12, 13, 15), find number of implicant, PI,
EPI, RPI

No. of Implicants = 8
No. of Prime Implicants(PI) = 5
No. of Essential Prime Implicants(EPI)
=4
No. of Redundant Prime
Implicants(RPI) = 1
No. of Selective Prime Implicants(SPI)
=0
Given F = ∑(0, 1, 5, 8, 12, 13), find number of implicant, PI, EPI, RPI

No. of Implicants = 6
No. of Prime Implicants(PI) = 6
No. of Essential Prime
Implicants(EPI) = 0
No. of Redundant Prime
Implicants(RPI) = 3
No. of Selective Prime
Implicants(SPI) = 6
Ex..

No. of Implicants = 7
No. of Prime Implicants(PI) = 6
No. of Essential Prime
Implicants(EPI) = 2
No. of Redundant Prime
Implicants(RPI) = 2
No. of Selective Prime
Implicants(SPI) = 4
Flow Chart
 Example
• Find the 1 that is covered by only one term first (Do not share with other circle).
Four-Variable K-Maps
Four-Variable K-Maps
 5-Variable K Map
– Use two 4-variable map to form a 5-variable K map (16 + 16 = 32) (A,B,C,D,E)
• A’ in the bottom layer
• A in the top layer.
 5 Neighbors

• Same plane and above or under

 Example: 5-variables
• Ans: F = A’B’D’ + ABE’ + ACD + A’BCE + {AB’C or B’CD’}
– P1 + P2 + P3 + P4 + AB’C or B’CD’
 One More
• F = B’C’D’ + B’C’E + A’C’D’ + A’BCD + ABDE + {C’D’E or AC’E}
• (17,19,25,27 =AC’E), (1,9,17,25 = C’D’E)
QUINE-MC CLUSKY METHOD
 Design of combinational digital circuits
• Steps to design a combinational digital circuit:
– From the problem statement derive the truth table
– From the truth table derive the unsimplified logic expression
– Simplify the logic expression
– From the simplified expression draw the logic circuit
• Example: Design a 3-input (A,B,C) digital circuit that will give at its output (X) a logic
1 only if the binary number formed at the input has more ones than zeros.
 Design of combinational digital circuits (Cont.)
• Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a
logic 1 only if the binary number formed at the input is between 2 and 9 (including).
 Design of combinational digital circuits (Example)
• Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a
logic 1 only if there more ones than zeros in the binary number formed at the input.
NAND & NOR Implementation
 NAND and NOR Implementations

• NAND & NOR gates are universal gates.

• Digital circuit are frequently constructed with
NAND or NOR gates rather than AND and OR
gates.
• NAND and NOR gates are easier to fabricate
with electronic components and are the basic
gates used in all IC digital logic
families.(covering AND,OR,NOT)
 DeMorgan’s Law

Recall the DeMorgan’s Law:

(a + b)’ = a’ b’ (a b)’ = a’ + b’
a + b = (a’ b’)’ (a b) = (a’ + b’)’

= =

= =
 Universal Gate – NAND

I will demonstrate
•The basic function of the NAND gate.
•How a NAND gate can be used to replace an AND gate, an OR
gate, or an INVERTER gate.
•How a logic circuit implemented with AOI logic gates can be
re-implemented using only NAND gates.
•That using a single gate type, in this case NAND, will reduce the
number of integrated circuits (IC) required to implement a logic
circuit.
AOI Logic NAND Logic

4
More ICs = More $$ Less ICs = Less $$
 NAND Gate

X
Z=XY=X+Y
Y

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0

61
NAND Gate as an Inverter Gate

(Before Bubble)
X∙X=X

X Z=X

X Z
0 1
Equivalent to Inverter
1 0

62
 NAND Gate as an AND Gate

XY
X
Z=XY=XY
Y

NAND Gate Inverter

X Y Z
0 0 0
0 1 0
Equivalent to AND Gate
1 0 0
1 1 1

63
 NAND Gate as an OR Gate

X Y
Z=XY=X+Y=X+Y
Y

Inverters NAND Gate

X Y Z
0 0 0
0 1 1
Equivalent to OR Gate
1 0 1
1 1 1

64
NAND Gate Equivalent to AOI Gates

AND OR INVERTER

65
 Process for NAND Implementation

1. If starting from a logic expression, implement the

design with AOI logic.
2. In the AOI implementation, identify and replace
every AND,OR, and INVERTER gate with its NAND
equivalent.
3. Redraw the circuit.
4. Identify and eliminate any double inversions (i.e.,
back-to-back inverters).
5. Redraw the final circuit.
66
 NAND Implementation
Example:
Design a NAND Logic Circuit that is equivalent to the AOI circuit shown
below.

=BC+AC

67
 NAND Implementation
Solution – Step 2

Identify and replace every AND,OR, and INVERTER gate with its
NAND equivalent.

68
 NAND Implementation
Solution – Step 3
Redraw the circuit.

6
NAND Implementation
Solution – Step 4

Identify and
eliminate any
double
inversions.

7
 NAND Implementation
Solution – Step 5
Redraw the circuit.

7
 Proof of Equivalence

C
BC

=BCAC

Z=BC+AC
AC
Z=BC+AC

72
 AOI vs. NAND

IC Type Gates Gate / IC # ICs IC Type Gates Gate / IC # ICs

74LS04 1 6 1 74LS00 4 4 1
74LS08 2 4 1 Total Number of ICs → 1
74LS32 1 4 1
Total Number of ICs → 3

73
 Summary - NAND Universality

A A A AB
B
Inverter AND gate

A A
A+B A+B
B B

OR gate NOR gate

 Self Task
•Implement the following Boolean
express using only NAND gates

•Y = ABC’ + ABC + A’BC

•Y = AB + CDE + F
•Y = ∑ (0,1,5)
 Universal Gate – NOR

Now I will demonstrate…

•The basic function of the NOR gate.
•How an NOR gate can be using to replace an AND gate, an OR
gate or an INVERTER gate.
•How a logic circuit implemented with AOI logic gates could be
re-implemented using only NOR gates
•That using a single gate type, in this case NOR, will reduce the
number of integrated circuits (IC) required to implement a logic
circuit.
AOI Logic NOR Logic

20
More ICs = More $$ Less ICs = Less $$
 NOR Gate

X
Z=X+Y=X Y
Y

X Y Z
0 0 1
0 1 0
1 0 0
1 1 0

79
NOR Gate as an Inverter Gate

(Before Bubble)
X+X=X

X Z=X

X Z
0 1
Equivalent to Inverter
1 0

80
 NOR Gate as an OR Gate

X+Y
X
Y Z=X+Y=X+Y

NOR Gate “Inverter”

X Y Z
0 0 0
0 1 1
Equivalent to OR Gate
1 0 1
1 1 1

81
 NOR Gate as an AND Gate

X Y

Z=X+Y=XY=XY
Y

“Inverters” NOR Gate

X Y Z
0 0 0
0 1 0
Equivalent to AND Gate
1 0 0
1 1 1

82
NOR Gate Equivalent of AOI Gates

AND OR INVERTER

83
 Process for NOR Implementation
1. If starting from a logic expression, implement the design with AOI
logic.
2. In the AOI implementation, identify and replace every AND,OR, and
INVERTER gate with its NOR equivalent.
3. Redraw the circuit.
4. Identify and eliminate any double inversions. (i.e. back-to- back
inverters)
5. Redraw the final circuit.

84
 NOR Implementation
Example:
Design a NOR Logic Circuit that is equivalent to the AOI circuit shown
below.

=BC+AC

85
 NOR Implementation
Solution – Step 2

Identify and replace every AND,OR, and INVERTER gate with its
NAND equivalent.

86
 NOR Implementation
Solution – Step 3

Redraw Circuit.

8
NORSolution
Implementation
– Step 4

Identify and
eliminate any
double
inversions.

8
 NOR Implementation
Solution – Step 5

Redraw Circuit.

8
 Proof of Equivalence

B+C=BC=B
C C

B =BC+AC
C
Z=BC+AC
BC+AC
A
A+C=AC=AC
90
 AOI vs NOR

IC Type Gates Gate / IC # ICs IC Type Gates Gate / IC # ICs

74LS04 1 6 1 74LS02 7 4 2
74LS08 2 4 1 Total Number of ICs → 2
74LS32 1 4 1
Total Number of ICs → 3

91
 Summary NOR - Universality

A A A A+B
B
Inverter OR gate

A A
AB
B B

AND gate NAND gate

 Self Task
•Implement the following Boolean
express using only NOR gates

Y = (A’+B+C)(A + B)D
Y = ∏ (0,1,2,4,6)
 Conversion to NAND
Implementation
• Minimized expressions are AND-OR combinations
–Two illustrations for NAND gates
• AND-invert
• Invert-OR

•Key observation: two “bubbles” eliminate each other

•Two bubbles equal straight wire
•How to generate a sum of minterms using NAND?
–Use AND-invert for minterms
–Use invert-OR for sum
Conversion to NAND
Implementation

´
 NAND Example
• Function F = Σ(1,2,3,4,5,7)Minimize and implement
with NAND

Solution
Draw K-Map 1st

Implementation
 Multilevel NAND circuits
• Multilevel circuits conversion rules:
1.Convert all AND gates to NAND with AND-invert symbols
2.Convert all OR gates to NAND with invert-OR symbols
3.Check all bubbles in diagram. For every bubble that is not
compensated by another bubble, insert inverter.
• Example
 Self Task
• Simplify the equation by simple gates & NAND
F=(AB’+A’B)(C+D’)
 Self Task
•Implement the following Boolean
express using only NAND gates

Y = ABC’ + ABC + A’BC Y

= AB + CDE + F
Y = ∑ (0,1,5)
 Logic Operation with NOR gate
• NOR can also replace NOT, AND, OR

• Two representations of NOR:

–OR-invert and invert-AND
 Converting to NOR
Implementations
• Same rules as for NAND implementations
 Self Task
•Implement the following Boolean
express using only NOR gates

Y = (A’+B+C)(A + B)D
Y = ∏ (0,1,2,4,6)
 Ex-OR/NOR function

X-OR X-NOR
 Ex-OR implementations

• In fig.(b), the first NAND gate performs the operation (xy)’ = (x’ + y’).
xy’ + x’y = x ⊕ y
 Odd function
• Boolean expression of three-variable of the XOR:
A ⊕B ⊕C = (AB’ + A’B)C’ + (AB + A’B’)C
= AB’C’ + A’BC’ + ABC + A’B’C
=Σ(1, 2, 4, 7)
 Odd and Even functions

• The 3-input odd function is implemented by

means of 2-input exclusive-OR gates.
A ⊕B ⊕C = (AB’ + A’B)C’ + (AB + A’B’)C
 Applications of Ex- OR/NOR

• Comparator
• Binary to Gray code
convertor
• Adder & Subtractor circuits
• Parity generator
• And etc ...