VLSI Assignment 3
VLSI Assignment 3
logie togic
block
100olololoO
ooOololoolo
Static
RAM
Troarmiscion
gatt
The diaqzamalio DATE
hich shoon
direcond becoC tbic case
tranmniLogiccihotonh 1
pauses signal a
The Crent
to
melt and thot
Antifue PPGA betueeh the foc ma
DATE
polysilicoh
ar chDuon
cootact cut to
Polys he on cortact cut o
mctal-4
Baulc
rmetal -z typlcal archit c hut of FPGA
Bilon k tranitor FPGA
cOmplexity of
PPGA
Tcon - consitt ot amau of
didechic
pogrammahli nterconnect logic calle and
Can
campldtelyproqrararnabe iewer
prcpare pnqram
chanqce n the proqramas perCantheoake
oich.
Substrate
Baslc compontnt
DATE
SATE
maln
nlbplacere
elemeot fox
elemeot
Lotch Alipflop
LUTS can alo
Logte implerm. cntahon can bcconfiguz 1opleraent coall RAMS
to implement combinabonal laglc
LImplumenting the truth tabl Contaponding and cPLDEthaExplaintccbnoloqlzynvolw.cd Jn FPaA
al the tccbnologlca
to the Logle corcuik.
a)Toput / utput block
CPLDprog zaromin technolagi
T/O blocku poicle inkrface
CLBs and the packagepias
hetween the JEloaing qate technalagl ea
UV EPROM
ulta WLolet EP
laer conhigurable input /Duput klock pznuide 2)
alechically erasable EPROM) RoM)Elash
EP ROM
Mernony
the nzerfac bctwcen externalL packagepine syatem
EE PROM
programinable
and the internal loglc and Floth memoy
Each ToB conhule package pin and Re-programmable
cah be defined for nput autput flash
memony
bidrechionalsignal
3) Bzgranmahle Switchmatix
The oltchatix Lcon nect
Tnttrcobnecte
to the
QCroa the
Anifuse
Thls
Rohpalagy
tcchnolagy compniee
difterent kiodd of fuata that
devlce. cxhibite Yeny hlgh istanc wder normad
draumstanceu bot prngrainmud by
The hicsarchical and trtical sinq u and hlocoing them
Jdouble Iios Interret at a box kn0 wn asa
DATE
4)LElasb
The main aduantages of anttuse i It
bavelow
osata
ictaDce
Aluo anhfue
aod paraihc capacitence EPROM coobine featuz of both
and EEPROIMprbgrarooingo
EE PROM Je
lcompard hathepagzamming thnalagie badtdon bot
Lapproachuhil clecron
ytem prngramning
approach.
Erasurel ising inccho
hunneing
these devic entir chip
eperformed Is bwlk toy the
2) Stabc memor prrgramaing tehnalogie subsechon.
Main alon behind SRAM pngramming Dfcrence betwcen
tchnalogy gaining
pgpramab lty capability
EPGA ond CPLD.
FPGA
CRAM
CPLD
cella can be prerammal
bumher of bmafach hme the poutr
denaity Tongeinoide
fom. CPLD
Laupply
accoroing
ONPPGA
to supplzdconhgurahon afew thouAcnd pertor cnance having hlgh
but Contoin
gak to sevcral tew regícker, than
EPaAc
) Elash EPROM/ EE PROM echnolagy million gatea
These ccllearenon-voltalite and thuy
donot Loce the nformatoh ohen the )EPGAs coulo pot
CPLD can irmplement
pouer Lonplament larg
Auncionin on pasa lange function h one pads.
EPROM non -vo tatile Memon obich
the data to be FPGA contoin anay
alloux
of oqic cellc and CPLDUTCU are
to erase the data tored in leas paatoned partioned
blocky
into Jogtc.
than CPL D
Baslc acte deyice sed n £PROM )
caled EAMOC translstorfAMOS stand fz Number of0 pind Numbcr of I/0 plns
lon
en the £PGA areon th
fleahing gate avalanchenjechion MDs les than CpLD. CPLD are higher
Shortdetgncyda
Elesiblfundtonquh
trattr. -
abakilty
Htahdensltyand -Operakca
pccdCperateatvry
hlgh
laspad. 0plnt Rich
fcoboadätdattranda conitqunabe -Easily
agral xcararalog
d lto crcut
cdaa andanalgeis
that Kchenac
dealqn feature
atmoxcdntoauorknggetn
chLD ocertoni
The Hot
aoaidsk.
dthaggingatura dutgr.
acriphionndptd and centol fzaddd
prntaLbaThe
deick balltn
ig VibgHbLand
matd hashaa
ard compl onalyzs oablaa MX emitaycanguraba
MentryiNonselabile
m
txedlariguage pafrmandele frfexranaHlgh
L.elg Cmulaior
adtlcuhprucom Liftoor udator
Rpqammabhdtulckchecpngranr
Graphlca Fcaturta. CPLD
alaclnNelng
TLdlgrikItpgot FPafand
ChLD heafart
f
and
than CELD tha
DCodhnclatys
SmsatnTk tatd
fecbnalglca
yotheeal
th plalr haiakCPLDhadcati 9TnFnaA
the
Out o£
fixed and thec tuuo
Syotheaig Toal
Tn the ORplane aaue AND plane
leprogrammobla
is
0LatHce. syntbelis
ynthete Support forc Indiut
PROM the AD
Lattice
standard vilog and VHDL language and
decoderohich
addres has ill decod
ay will at
Lhe
mlxcd languag wsth Ibdutytandard
altribute and cOnstrcç ntr it
andSDC
ealy synthul zedcalstinq
enabls Tnput buffers
and Inverttrs
deigna Laing attica aynthuie
(2) Mento rapbic leonadaspectrum Fix ed
Leonarda spechhum dewelsped by AND -amray Progxaminahle
0R ayray
mentoxqrophicl Jeanando spcchmpport
both VHDL and wenilagAsIClanguage
cheate PLD, LPGA and compancnta
2 PAL
8 Synopsiy deslgn compilz Thua nan
Deaign compilbynihui solutibn cpabl pog0mmakle archit
and bp ecturt AND amat
udexs to meet todaydenigr challnga. developed. Thi ls Aixed s
Concurnt
pouoer and tct
opholzation of bming pngzammabl devtceknouh
Iogic devtor
Since PAL' an
The ncarpz deatqn envionmeot inelud less expenlrePAL'couily- manuachuabl_and
at popudar in praci
applicationa. A not
VHDL Y Venlog tynthesis the PLD commbny
programoablewcd typL
OCompat EPROM,PAL CPLD, £POA ASeC.
)pROM
prnqrammable ztad only mu
a devic. that include both the AND
plane and ORplanc erhin a single Ic
packoge.
Draand
can bcexplainconaldsred
XL X2
and arbitccue of
CPLD
Toput bu here
staucturt Conalt an evaluaton
PAL
and Tovertors To the
CPLD m0crocella
availoble
macrocell packageall
to each
mocrocell inpt
Fxed
Pecarannable each pins
ohere as are
OR -aay
AND -ray
pins basa dedicated output
Khe
9) Asrci
fnllauaingblockdiag ram of CPLD.
AsrCstand for application Specific IlO block
Inegrotd cireuit. Thic In~qrated circuit
AsIC microchip Mictccel
aptly named tnce an PLA CY PAL Macraccl
andnanufactue d Ao One PLA or PAL IMacraccL MacocclL
DDtallas PLA or PAL
pecific applicabion and doc PLA oY PAL
you to eprgn madify
Programmab le
intrconnect
oeand
nt oBended to PLA or PAU PLA Or PAL
PLA Cr PAL
guneral Le macro call
maubces
PLA tY PAL
macroce
multiple macroL
function block
PAGE tO.
OATE
The marocellu
ProgamOable
aeConpetd
oterconnect thouah
alaoreferred to as GIM
rrM_ different or
By recon figunng
circute Cah
the
ealized lag
CPLD intract with the outerworld
atil zing digital Elos