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Lec 13 CLD

Computer Graphics

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23 views16 pages

Lec 13 CLD

Computer Graphics

Uploaded by

Zahid Abbas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EE 105 Computer Logic Design

Lecture 13
Decoders
 Discrete quantities of information are represented in
digital systems by Binary Codes
n Bits Code 2n distinct elements of coded information
 A decoder circuit converts binary information from:
n Input Lines A maximum of 2n unique Output Lines
 If the n -bit coded information has unused combinations,
the decoder may have fewer than 2n outputs
 n -to-m -line decoders
 m <= 2n
 Generate 2n (or fewer) minterms of n input variables
 Each combination of inputs will assert a unique output
Decoders
 Example, Consider a Three-to-Eight-line Decoder circuit
 Three inputs are decoded into Eight outputs
 Each output representing one of the minterms
 Three inverters provide complement of the inputs, and
each AND gate generates one of the eight minterms
 Application of this decoder is Binary-to-Octal conversion
 Inputs represent a binary number, and Outputs represent
eight digits of a number in octal number system
 However, a three-to-eight-line decoder can be used for
decoding any three-bit code to provide eight outputs, one
for each element of the code
Decoders

Three-to-Eight-line
Decoder circuit
Decoders
 Operation of decoder may be clarified by Truth Table
 For each possible input combination, there are seven
outputs that are equal to 0 and only one that is equal to 1
 Output that is equal to 1 represents minterm equivalent of
the binary number currently available in the input lines
Decoders
• Assuming that each output is connected to an LED
8 outputs are connected to 8 LEDs
• Input combination is decoded by circuit to turn ON an LED
• Minterm no. formed by Inputs will turn ON corresponding LED

LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8


Decoders
 Construction with NAND gates:
 Some decoders are constructed with NAND gates. Since a
NAND gate produces the AND operation with an inverted
output, it becomes more economical to generate the decoder
minterms in their complemented form
 Enable inputs to control the circuit operation:
 Decoders may include one or more enable inputs to control the
circuit operation
 Example: A Two-to-four-line Decoder
 Constructed with Enable input and NAND gates
 Circuit operates with complemented outputs and a complement
enable input
Decoder is enabled when E is 0 (i.e., active-low enable)
Decoders
 When E=1, Circuit is Disabled (regardless of the values of
other two inputs) None of the outputs are 0
 When E=0, Circuit is Enabled, Only one output is 0 at
any given time
Decoders
 A decoder may operate with complemented or
uncomplemented outputs
 Enable input may be activated with a 0 or with a 1 signal
 Some decoders have two or more enable inputs that must
satisfy a given logic condition in order to enable the circuit

 A decoder with enable input can function as a demultiplexer


 Demultiplexer is a circuit that receives information from a
single line and directs it to one of 2n possible output lines
 Selection of a specific output Controlled by the bit
combination of n selection lines
Decoder as Demultiplexer
 Two-to-four-line Decoder can function as a One-to-four-
line Demultiplexer when E is taken as Data Input line and
A and B are taken as the Selection Inputs Input E is directed
to one of the
Outputs by Selection
Inputs A & B
Decoder as Demultiplexer
 Single input variable E has a path to all four outputs
 But the input E is directed to only one of the output lines
as specified by combination of two selection lines A and B
 For example, if the selection lines AB = 10, output D2 will
be the same as the input value E , while all other outputs
are maintained at 1
 Because decoder and demultiplexer operations are
obtained from the same circuit, a decoder with an enable
input is referred to as a decoder –demultiplexer
Decoders Connected Together
 Decoders are connected together to form a larger decoder
 Two 3-to-8-line decoders with enable inputs can be
connected to form a 4-to-16-line decoder Enable input
When w=0, Top decoder is very important!
enabled and the other is
disabled. Bottom decoder
outputs are all 0’s;Top eight
outputs generate minterms
0000 to 0111
When w=1, Bottom decoder is
enabled and the other is
disabled. Bottom decoder
outputs generate minterms 1000
to 1111, while the outputs of Top
decoder are all 0’s
Decoders for Combinational Logic
Implementation
 A decoder provides the 2n minterms of n input variables
 Any Boolean function can be expressed in sum-of-minterms
 A decoder that generates the minterms of the function,
together with an external OR gate that forms their logical
sum Hardware implementation of the function
 In this way, any combinational circuit with n inputs and
m outputs can be implemented with
 an n-to-2n -line decoder and
 m OR gates
Decoders for Combinational Logic
Implementation
 Procedure for implementing a combinational circuit by
means of a decoder and OR gates requires that
 Boolean function for circuit expressed as a sum of minterms
 A decoder is then chosen that generates all the minterms
 Inputs to each OR gate are selected from the decoder
outputs according to the list of minterms of each function
Example: Implement a Full-adder using Decoder and OR gates
From Truth table of Full adder, we obtain the functions for the
combinational circuit in sum-of-minterms form:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
Decoders for Combinational Logic
Implementation
 In Full-Adder, there are three inputs (and a total of eight
minterms), we need a Three-to-Eight-line decoder
 Decoder generates the eight minterms for x , y , and z
 OR gate for output S
forms the logical sum
of minterms
1, 2, 4, and 7
 OR gate for output C
forms the logical sum
of minterms
3, 5, 6, and 7
Decoders for Combinational Logic
Implementation
 A function with a long list of minterms requires an OR
gate with a large number of inputs
 A function having a list of k minterms can be expressed in
its complemented form F’ with 2n - k minterms
 Sometimes F’ can be expressed with fewer minterms
 Then NOR gate is used to sum the minterms of F’ as
output of the NOR gate gives normal output F
 If NAND gates are used for the decoder, then the
external gates must be NAND gates instead of OR gates
 This is because a two-level NAND gate circuit implements a
sum-of-minterms function and is equivalent to a two-level
AND–OR circuit

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