EE 105 Computer Logic Design

Lecture 10
 Combinational Logic
 Logic circuits may be combinational or sequential
 A Combinational Circuit
 Consists of logic gates
 Outputs are a function of the present inputs
 Specified logically by a set of Boolean functions
 A Sequential Circuit
 Employs storage elements in addition to logic gates
 Outputs are a function of inputs and state of the storage elements
i.e., outputs of a sequential circuit depend not only on present
values of inputs, but also on past inputs
 Circuit behavior must be specified by a time sequence of inputs and
internal states
 Combinational Logic
 A combinational circuit is an interconnection of logic gates

 The n input binary variables come from an external source

 The m output variables go to an external destination
 Thus, a combinational circuit can be specified with a truth
table that lists the output values for each combination
 A combinational circuit also can be described by m Boolean
functions, one for each output variable
 Each output function is expressed in terms of the n inputs
 Combinational Logic
 Chapter 1  Binary numbers and binary codes that represent
discrete quantities of information
 Chapter 2  Boolean algebra as a way to express logic functions
 Chapter 3  How to simplify Boolean functions to achieve
economical (simpler) gate implementations
 Chapter 4 The purpose is to formulate systematic analysis
and design procedures for combinational circuits
 We’ll address three tasks:
 (1) Analyze the behavior of a given logic circuit
 (2) Synthesize a circuit that will have a given behavior, and
 (3) Write hardware description language (HDL) models for some common
circuits
 Combinational Logic
 The most important standard combinational circuits will be
studied, such as
 Adders, Subtractors
 Comparators
 Decoders, Encoders
 Multiplexers
 These components are available in integrated circuits as
medium-scale integration (MSI) circuits
 They are also used as standard cells in complex very large
scale integrated (VLSI) circuits such as application-specific
integrated circuits (ASICs)
 Analysis Procedure
Analysis of a combinational circuit

Determine Function that the circuit implements

 Task starts with a given logic diagram and Result is
 a set of Boolean Functions
 a Truth Table
 or, possibly, an explanation of the circuit operation
 Analysis can be performed
 Manually by finding the Boolean functions or truth table
 By using a Computer simulation program
 Analysis Procedure
First step in the analysis Make sure that the given
circuit is Combinational (i.e., not Sequential)
How?
The diagram of a combinational circuit has logic gates
with no feedback paths (or memory elements)
What is a feedback path?
 A feedback path is a connection from the output of one
gate to the input of a second gate whose output forms
part of the input to the first gate
 Feedback paths in a digital circuit define a sequential
circuit and must be analyzed by special methods
 Analysis Procedure
To obtain output Boolean functions from a logic diagram,
we proceed as follows:
1. Label all gate outputs that are a function of input
variables with arbitrary symbols— but with meaningful
names. Determine Boolean functions for each gate output
2. Label the gates that are a function of input variables and
previously labeled gates with other arbitrary symbols. Find
the Boolean functions for these gates
3. Repeat the process outlined in step 2 until the outputs of
the circuit are obtained
4. By repeated substitution of previously defined functions,
obtain output Boolean functions in terms of input variables
 Analysis Procedure: Example
Label all
gate outputs
Analysis Procedure: Example
 Boolean functions for three gate outputs

 Outputs of gates that are a function of already

defined symbols
 Analysis Procedure: Example
 To obtain F1 as a function of A , B , and C , we form a
series of substitutions as follows:

 Derivation of Truth Table once the output Boolean

Functions are known: A straightforward process
 Analysis Procedure
 Derivation of Truth Table directly from Logic Diagram
(without going through the derivations of the Boolean
functions), we proceed as follows:
1. Determine the number of input variables in the circuit.
For n inputs, form the 2n possible input combinations and list
the binary numbers from 0 to (2n - 1) in a table
2. Label outputs of selected gates with arbitrary symbols
3. Obtain the truth table for the outputs of those gates
which are a function of the input variables only
4. Proceed to obtain the truth table for the outputs of
those gates which are a function of previously defined
values until the columns for all outputs are determined
 Analysis Procedure
 F2 is determined directly from the values of A , B , C
 T1 and T2 are OR and AND functions of input variables
 T3 is derived from T1 and F2
 Finally, F1 is determined from T2 and T3
 Design Procedure
 Design of combinational circuits
 Starts from the specification of the design objective
 Culminates in a logic circuit diagram (or Boolean functions)
 The procedure involves the following steps:
1. From specifications of the circuit, determine required
number of inputs and outputs and assign a symbol to each
2. Derive the truth table that defines the required
relationship between inputs and outputs
3. Obtain the simplified Boolean functions for each output
as a function of the input variables
4. Draw the logic diagram and verify the correctness of the
design (manually or by simulation)
 Design Procedure
 Output functions in Truth table are simplified by any
available method, such as
 algebraic manipulation,
 the map method, or
 a computer-based simplification program.
 Frequently, there is a variety of simplified expressions
from which to choose
 In a particular application, certain criteria will serve as a
guide in the process of choosing an implementation
 Design Procedure
 Criteria that must be taken into consideration when
designing integrated circuits
 Number of gates
 Number of inputs to a gate
 Propagation time (of the signal through the gates)
 Number of interconnections
 Limitations of the driving capability of each gate (i.e., number
of gates to which output of the circuit may be connected)

 Importance of each criteria depends on the particular

application, it is difficult to make a general statement
about what constitutes an acceptable implementation
 Design Procedure: Example
Code Conversion Example
 Different codes may be used by different digital systems
 Sometimes output of one system is the input to another
 A Conversion circuit must be inserted between two systems
if each uses different codes for same information
 Thus, A Code Converter is a circuit that makes two systems
compatible even though each uses a different code
 A combinational circuit performs this transformation by
means of logic gates
 Design procedure Example: Convert binary coded decimal
(BCD) to the excess-3 code for the decimal digits
 Design Procedure: Example
 Since each code uses four bits to represent a decimal digit,
there are 4 inputs and 4 outputs
 Design Procedure: Example
 4 inputs may have 16 bit combinations, but only 10 are
listed in truth table
 6 bit combinations not listed for the input variables are
don’t-care combinations
 These 6 combinations have no meaning in BCD and we
assume that they will never occur in actual operation of
the circuit
 Therefore, we are at liberty to assign to the output
variables either a 1 or a 0, whichever gives a simpler
circuit
 Design Procedure: Example
 4 maps to obtain simplified Boolean functions for 4 outputs
 Design Procedure: Example
 4 maps to obtain simplified Boolean functions for 4 outputs
 Design Procedure: Example
 Two-level logic diagram for each output may be obtained
directly from the Boolean expressions derived from maps
 Various other possibilities for a logic diagram of this circuit
 Expressions obtained from 4 K-maps may be manipulated
algebraically to use common gates for two or more outputs

 In Three-level logic diagram, OR gate whose output is C + D

will be used to implement partially each of three outputs
 Design Procedure: Example
 Two-level logic diagram for each output may be obtained
directly from the Boolean expressions derived from maps
 Various other possibilities for a logic diagram of this circuit
 Expressions obtained from 4 K-maps may be manipulated
algebraically to use common gates for two or more outputs

 In Three-level logic diagram, OR gate whose output is C + D

will be used to implement partially each of three outputs
Design Procedure: Example

 Three-level
logic circuit
requires
 fewer gates
 all gates have
two inputs