Lecture6 COA

BITS Pilani
Pilani Campus
DS Rao
COA -IS ZC353
Objectives
 Machine instructions and program execution,

including branching and subroutine call and
return operations.
 Addressing methods for accessing register and

memory operands.
 Assembly language for representing machine

instructions, data, and programs.
 Program-controlled Input/Output operations.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Memory Location, Addresses, and Operation
n bits
first word
Memory consists of second word
many millions of
storage cells, each •
of which can store 1 •
•
bit.
i th word
Data is usually
accessed in n-bit •
groups. n is called •
•
word length.
last word
Figure 2.5. Memory words.

32-bit word length example

32 bits
b31 b30 b1 b0
•
•
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers
(a) A signed integer
8 bits 8 bits 8 bits 8 bits
ASCII ASCII ASCII ASCII

character character character character
(b) Four characters
 To retrieve information from memory, either for one word or one

byte (8-bit), addresses for each location are needed.
 A k-bit address memory has 2k memory locations, namely 0 to 2k-1,
called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)

 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240

 It is impractical to assign distinct addresses to individual bit

locations in the memory.
 The most practical assignment is to have successive addresses

refer to successive byte locations in the memory – byte-
addressable memory.
 Byte locations have addresses 0, 1, 2, …
 If word length is 32 bits, they successive words are located at

addresses 0, 4, 8,…

Big-Endian and Little-Endian Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address Byte address Byte address
0 0 1 2 3 0 3 2 1 0
4 4 5 6 7 4 7 6 5 4
• •
• •
• •
k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4
(a) Big-endian assignment (b) Little-endian assignment

 Address ordering of bytes
 Word alignment
 Words are said to be aligned in memory if they begin at a byte address. that is a
multiple of the number of bytes in a word.
– 16-bit word: word addresses: 0, 2, 4,….
– 32-bit word: word addresses: 0, 4, 8,….
– 64-bit word: word addresses: 0, 8,16,….
Memory Operation
Load (or Read or Fetch)
Copy the content. The memory content doesn’t change.
Address – Load
Registers can be used
Store (or Write)
Overwrite the content in memory
Address and Data – Store
Registers can be used
“Must-Perform” Operations
 Data transfers between the memory and the processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers
Assembly Language Notation

 Represent machine instructions and programs.
 Move LOC, R1 = R1←[LOC]
 Add R1, R2, R3 = R3 ←[R1]+[R2]
 or
 Add R1, R2, R3 = R1 ←[R2]+[R3]

CPU Organization
 Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to memory quite
often
 General Register
 Registers hold operands thus reduce memory
traffic
 Register book keeping
 Stack
 Operands and result are always in the stack

Instruction Formats
Opcode Operand(s) or Address(es)
Three-Address Instructions
▪ ADD R1, R2, R3 R1 ← R2 + R3 or R3 ← R1 + R2
Two-Address Instructions
▪ ADD R1, R2 R1 ← R1 + R2
One-Address Instructions
▪ ADD M AC ← AC + M[AR]
Zero-Address Instructions
▪ ADD TOS ← TOS + (TOS – 1)
RISC Instructions
▪ Lots of registers. Memory is restricted to Load & Store

Instruction Formats
Example: Evaluate (A+B)  (C+D)
Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1  R2

Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1

Instruction Formats
Example: Evaluate (A+B)  (C+D) One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC
Example: Evaluate (A+B)  (C+D) RISC

1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1  R3
8. STORE X, R1 ; M[X] ← R1

ARM Data Types
 8 (byte), 16 (halfword), 32 (word) bits
Halfword and word accesses should be word aligned
Nonaligned access alternatives
▪ Default
– Treated as truncated
– Bits[1:0] treated as zero for word
– Bit[0] treated as zero for halfword
– Load single word instructions rotate right word aligned data transferred by
non word-aligned address one, two or three bytes Alignment checking
▪ Data abort signal indicates alignment fault for attempting unaligned access
▪ Unaligned access
▪ Processor uses one or more memory accesses to generate transfer of
adjacent bytes transparently to the programmer

ARM Data Types contnd.
Unsigned integer interpretation supported for all types
Twos-complement signed integer interpretation supported for all types
Majority of implementations do not provide floating-point hardware
▪ Saves power and area
▪ Floating-point arithmetic implemented in software
▪ Optional floating-point coprocessor
▪ Single- and double-precision IEEE 754 floating point data types

ARM Operation Types
 The ARM architecture provides a large collection of operation types
 The following are the principal categories:
 Load and store instructions: only load and store instructions access memory
locations; arithmetic and logical instructions are performed only on registers
and immediate values encoded in the instruction
 A Branch instructions: Allows a conditional branch forwards or backwards up to
32 MB.
 Data-processing instructions:includes logical instructions (AND, OR, XOR),
add and subtract instructions, and test and compare instructions
 Multiply instructions: The integer multiply instructions operate on word or
halfword operands and can produce normal or long results

ARM Operation Types contnd.
 Parallel addition and subtraction instructions
 Extend instructions: There are several instructions for unpacking data
by sign or zero extending bytes to halfwords or words, and halfwords to
words.
 Status register access instructions: ARM provides the ability to read and
also to write portions of the status register.

ARM Endian Support
E-bit in system control register
Under program control

Using Registers
 Registers are faster
 Shorter instructions
– The number of registers is smaller (e.g. 32 registers need 5 bits)
 Potential speedup
 Minimize the frequency with which data is moved back and forth
between the memory and processor registers.

ARM Condition Codes
Condition code flags
Condition code register / status register
N (negative)
Z (zero)
V (overflow)
C (carry)
Different instructions affect different flags

Conditional Branch Instructions
Example: A: 11110000
▪ A: 1 1 1 1 0 0 0 0
▪ B: 0 0 0 1 0 1 0 0 +(−B): 1 1 1 0 1 1 0 0
11011100
C=1 Z=0
S=1
V=0
Overflow can only happen when adding two numbers of the same sign
and getting a different sign. So, to detect overflow we don't care about any bits except
the sign bits. Ignore the other bits.

ARM Conditions for Conditional
Instruction Execution

Expression Evaluation
 Infix notation: A binary operator appears between the operands
 𝑎 + (𝑏 × 𝑐), will yield a different result from (𝑎 + 𝑏) × 𝑐
 Reverse Polish, or postfix, notation
a+b becomes a b +
𝑎 + (𝑏 × 𝑐), becomes a b c x +
(𝑎 + 𝑏) × 𝑐 becomes a b + c x
 Regardless of the complexity of an expression, no parentheses are required when

using reverse Polish
 An expression in this form is easily evaluated using a stack
 Rules
1. If the element is a variable or constant, push it onto the stack.
2. If the element is an operator, pop the top two items of the stack, perform the
operation, and push the result.
Instruction Formats
TOS= TOS (operation)(TOS-1)
Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B B
A
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)
8. POP X ; M[X] ← TOS

Instruction Formats

Zero-Address
1. PUSH A ; TOS ← A D
2. PUSH B ; TOS ← B C
A+B
3. ADD ; TOS ← (A + B)
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)

Instruction Formats

Zero-Address
2. PUSH B ; TOS ← B C+D
A+B
3. ADD ; TOS ← (A + B)
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)

Instruction Formats

Zero-Address
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B) (C+D)*(A+B)
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)

BITS Pilani
Pilani | Dubai | Goa | Hyderabad
Already included this in 8086 , students have to learn this on their own
Addressing Modes
• 8086 Intel Microprocessor Architecture

Generating Memory Addresses
How to specify the address of branch target?
Can we give the memory operand address directly

in a single Add instruction in the loop?
Use a register to hold the address of NUM1; then

increment by 4 on each pass through the loop.

Addressing Modes
Opcode Mode ...
Implied
▪ AC is implied in “ADD M[AR]” in “One-Address”
instr.
▪ TOS is implied in “ADD” in “Zero-Address” instr.
Immediate
▪ The use of a constant in “MOV R1, 5”, i.e. R1 ←
5
Register
▪ Indicate which register holds the operand

Addressing Modes
Register Indirect
▪ Indicate the register that holds the number of the register that holds
the operand
MOV R1, (R2)
Autoincrement / Autodecrement R1
▪ Access & update in 1 instr.
Direct Address R2 = 3
▪ Use the given address to access a memory location
R3 = 5

Addressing Modes
Indirect Address
▪ Indicate the memory location that holds the address of the
memory location that holds the data
AR = 101
100
101 0 1 0 4
102
103
104 1 1 0 A

Addressing Modes
Relative Address
▪ EA = PC + Relative Addr 0
1
PC = 2 2
+
100
AR = 100
101
Could be 102 1 1 0 A
Positive or 103
Negative 104
(2’s
Complement)

Addressing Modes
Indexed
▪ EA = Index Register + Relative Addr
Useful with
“Autoincrement” XR = 2
or
“Autodecrement” +
100
AR = 100
101
102 1 1 0 A
Could be 103
Positive or 104
Negative
(2’s
Complement)
Addressing Modes
Base Register
▪ EA = Base Register + Relative Addr
Could be Positive or AR = 2
Negative
(2’s Complement)
+
100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array

ARM Indexing Methods
 RISC machine, unlike a CISC machine
has simple and relatively straightforward
set of addressing modes
 ARM architecture departs somewhat from
this tradition by providing a relatively rich
set of addressing modes.

ARM Addressing Modes
Load/Store
 Only instructions that reference memory
 Indirectly through base register plus offset
 Offset
 Offset added to or subtracted from base register contents to form
the memory address
 Preindex
 Memory address is formed as for offset addressing
 Memory address also written back to base register
 So base register value incremented or decremented by offset value

ARM Addressing Modes
Load/Store
 Postindex
 Memory address is base register value
 Offset added or subtracted
Result written back to base register
 Base register acts as index register for preindex and postindex addressing
 Offset either immediate value in instruction or another register
 If register scaled register addressing available
 Offset register value scaled by shift operator

 Instruction specifies shift size
ARM Data Processing Instruction
Addressing & Branch Instructions
 Data Processing
 Register addressing
– Value in register operands may be scaled using a shift operator
 Or mixture of register and immediate addressing
 Branch
 Immediate
 Instruction contains 24 bit value
 Shifted 2 bits left
– On word boundary
– Effective range +/-32MB from PC.

ARM Load/Store Multiple Addressing
 Load/store subset of general-purpose registers
 16-bit instruction field specifies list of registers
 Sequential range of memory addresses
 Increment after, increment before, decrement after, and decrement
before
 Base register specifies main memory address
 Incrementing or decrementing starts before or after first memory
access

ARM Load/Store Multiple Addressing

Instruction Formats
 Layout of bits in an instruction
 Includes opcode
 Includes (implicit or explicit) operand(s)
 Usually more than one instruction format in an instruction set
Instruction Length
 Affected by and affects:
 Memory size
 Memory organization
 Bus structure
 CPU complexity
 CPU speed
 Trade off between powerful instruction repertoire and saving space

Allocation of Bits
 Number of addressing modes
 Number of operands
 Register versus memory
 Number of register sets
 Address range
 Address granularity

In class Example-1
Assume an instruction set that uses a fixed 16-bit instruction length. Operand specifiers are 6
bits in length. There are K two-operand instructions and L zero-operand instructions. What is
the maximum number of one-operand instructions?

In class Example-1
Design a variable-length opcode to allow all of the following to be encoded in a 36-bit
instruction:
• instructions with two 15-bit addresses and one 3-bit register number
• instructions with one 15-bit address and one 3-bit register number
• instructions with no addresses or registers

In class Example-1
Design a variable-length opcode to allow all of the following to be encoded in a 36-bit
instruction:
• instructions with two 15-bit addresses and one 3-bit register number
• instructions with one 15-bit address and one 3-bit register number
• instructions with no addresses or registers

ARM Instruction Formats
S = For data processing instructions, updates condition codes

S = For load/store multiple instructions, execution restricted to supervisor mode
P, U, W = distinguish between different types of addressing_mode
B = Unsigned byte (B==1) or word (B==0) access
L = For load/store instructions, Load (L==1) or Store (L==0)
L = For branch instructions, is return address stored in link register
Examples of Use of ARM Immediate Contants

Expanding a Thumb ADD Instruction into its
ARM Equivalent

BITS Pilani
Pilani | Dubai | Goa | Hyderabad
CPU simulator as example

How to access your Virtual lab portal?
1. Login into your BITS WILP Elearn portal (https://elearn.bits-pilani.ac.in/)

2. Click on "My Virtual Labs" under Important Links
Can also be downloaded from the below link and installed on your PC, it is
a free tool
Downloads – CPU-OS Simulator (teach-sim.com)

MSI Installer version for use by Windows Installer in silent mode. Used to
distribute and install across several systems.
CPU-OS Simulator 7-5-50-msi.zip

Examples
1.locate the instruction, which is used to store one byte of data in a memory location.
Use it to store number 65 in address location 20 (all numbers are in decimal). This is
an example of direct addressing.
STB #65,20
2.Create an instruction to move decimal number 22 to register R01 and make a note
of it below. Execute this instruction and verify the result in R01.
MOV #22,R01
3.Create an instruction to store decimal number 51 in
memory location the address of which is currently stored in register R01. This is an
example of indirect addressing. Note the use of the “@” prefix next to R01 in this
case.
STB #51,@R01
4. Make a note of what you see in data memory locations 20 and 22

3.Create an instruction to store decimal number 51 in
memory location the address of which is currently
stored in register R01. This is an example of indirect
addressing. Note the use of the “@” prefix next to R01
in this case.
STB #51,@R01
4. Make a note of what you see in data memory

locations 20 and 22

Creating A Loop
Now, let’s create a loop. First, enter the following code.
The # prefix is used to denote a literal value thus distinguishing
it from an address value which does not use it.
MOV #0, R01
ADD #1, R01
CMP #5, R01
JNE 0
HLT
in order to make the code more flexible we can use labels to

represent instruction addresses

Naming the LOOP
Type label name L0 in the box next to the ENTER LABEL

button in the window you use to enter instructions
Click the ENTER LABEL button

The new code should now look like this (modifications are in
red colour):
MOV #0, R01

L0:
ADD #1, R01
CMP #5, R01
JNE $L0
HLT

Elements of a machine instruction
 Opcode
 Operand
 Direct
 operand references
 Eg: Add A 87H
 or Add A B
 Next Instruction
Instruction Set Design Issue
 Type of Operation ?
 Kind of Data ?
 Instruction Format ?
 Number of internal Registers in CPU ?
 Addressing Modes?

Questions on simulator
 Type of Operation ?
 Kind of Data ?
 Instruction Format ?
 Number of internal Registers in CPU ?
 Addressing Modes?

Assembler
 Machines store and understand binary instructions
 E.g. N= I + J + K initialize I=2, J=3, K=4
 Program starts in location 101
 Data starting 201
 Code:
 Load contents of 201 into AC
 Add contents of 202 to AC
 Add contents of 203 to AC
 Store contents of AC to 204
 Tedious and error prone

Improvements
 Use hexadecimal rather than binary

 Code as series of lines
 Hex address and memory address
 Need to translate automatically using program
 Add symbolic names or mnemonics for instructions
 Three fields per line
 Location address
 Three letter opcode
 If memory reference: address
 Need more complex translation program

Program in:
Binary Hexadecimal
Address Contents Address Contents
101 0010 0010 101 2201 101 2201
102 0001 0010 102 1202 102 1202
103 0001 0010 103 1203 103 1203
104 0011 0010 104 3204 104 3204
201 0000 0000 201 0002 201 0002
202 0000 0000 202 0003 202 0003
203 0000 0000 203 0004 203 0004
204 0000 0000 204 0000 204 0000

Symbolic Addresses
 First field (address) now symbolic
 Memory references in third field now symbolic
 Now have assembly language and need an assembler to translate
 Assembler used for some systems programming
▪ Compliers
▪ I/O routines

Computation of the Formula N = I + J + K

Adressing Mode In class example 3
Given the following memory values and a one-address machine with an
accumulator, what values do the following instructions load into the accumulator?
• Word 20 contains 40.
a. LOAD IMMEDIATE 20
b. LOAD DIRECT 20
c. LOAD INDIRECT 20
d. LOAD IMMEDIATE 30
e. LOAD DIRECT 30
f. LOAD INDIRECT 30
Sol:
a. 20
b. 40 d. 30 e. 50 f . 70
c. 60

In class example 4
Consider a 16-bit processor in which the following appears in main memory, starting at
location 200:
The first part of the first word indicates
that this instruction loads a value into
an accumulator.
The Mode field specifies an addressing mode and, if appropriate, indicates a source register;
assume that when used, the source register is R1, which has a value of 400.There is also a
base register that contains the value 100.The value of 500 in location 201 may be part of the
address calculation. Assume that location 399 contains the value 999, location 400 contains
the value 1000, and so on. Determine the effective address and the operand to be loaded for
the following address modes:

Contnd.
Determine the effective address and the operand to be loaded for the
following address modes
a. Direct d. PC relative g. Register indirect

b. Immediate e. Displacement,
c. Indirect f. Register
h. Autoindexing with increment using R1
Mode→ R1 and contains 400 A 500 1100

B 201 500
Base register 100
C 1100 1700
Adrs 399 → 999 & 400→ 1000 D 702 1302
E 600 1200
F R1 400
G 400 1000
H 400 1000

In class example 5
Assume a stack-oriented processor that includes the stack operations PUSH and POP.
Arithmetic operations automatically involve the top one or two stack elements. Begin
with an empty stack.What stack elements remain after the following instructions
are executed?
PUSH 4
PUSH 7 Push 4 4
Push 7 7,4
PUSH 8 Push 8 8,7,4
ADD ADD 15,4
PUSH 10 10,15,4
PUSH 10 SUB 5,4
SUB MUL 20
MUL

In class example 6
Compare zero-, one-, two-, and three-address machines by writing programs to
compute
for each of the four machines.The instructions available for use are as follows:
X = (A + B X C) ∕ (D - E X F)
0 Address 1 Address 2 Address 3 Address
PUSH M LOAD M MOVE(x←y ) MOVE (x←y )
POP M STORE M ADD (x←x+y ) ADD (x←y +z)
ADD ADD M SUB (x←x-y ) SUB (x←y -z)
SUB SUB M MUL (x←x X y ) MUL (x←y X Z)
MUL MUL M DIV (x←x/y ) DIV (x←y/z )
DIV DIV M

DIV DIV M
C
B
A
X = (A + B X C) ∕ (D - E X F)

DIV DIV M
BXC
A
X = (A + B X C) ∕ (D - E X F)

DIV DIV M
F
E
D
A+BXC
X = (A + B X C) ∕ (D - E X F)

DIV DIV M
ExF
D
A+BXC
X = (A + B X C) ∕ (D - E X F)

DIV DIV M
D-ExF
A+BXC
X = (A + B X C) ∕ (D - E X F)

DIV DIV M
A+BxC /
D-ExF
X = (A + B X C) ∕ (D - E X F)

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BITS Pilani

 Machine instructions and program execution,

 Addressing methods for accessing register and

 Assembly language for representing machine

 Program-controlled Input/Output operations.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Figure 2.5. Memory words.

32-bit word length example

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

 To retrieve information from memory, either for one word or one

 24-bit memory: 224 = 16,777,216 = 16M (1M=220)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 It is impractical to assign distinct addresses to individual bit

 The most practical assignment is to have successive addresses

 Byte locations have addresses 0, 1, 2, …

 If word length is 32 bits, they successive words are located at

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

(a) Big-endian assignment (b) Little-endian assignment

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Assembly Language Notation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Opcode Operand(s) or Address(es)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example: Evaluate (A+B)  (C+D)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example: Evaluate (A+B)  (C+D) RISC

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Unsigned integer interpretation supported for all types

Twos-complement signed integer interpretation supported for all types

Majority of implementations do not provide floating-point hardware

▪ Saves power and area

▪ Floating-point arithmetic implemented in software

▪ Optional floating-point coprocessor

▪ Single- and double-precision IEEE 754 floating point data types

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Parallel addition and subtraction instructions

 Extend instructions: There are several instructions for unpacking data

by sign or zero extending bytes to halfwords or words, and halfwords to

also to write portions of the status register.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Regardless of the complexity of an expression, no parentheses are required when

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example: Evaluate (A+B)  (C+D)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example: Evaluate (A+B)  (C+D)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example: Evaluate (A+B)  (C+D)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

How to specify the address of branch target?