Registration No :

Total Number of Pages : 02

-- 3 Course: B.Tech

0 3 Sub_Code:
2 Examination: 2022-23
RCS3C001
rd
2
/DIGITAL LOGIC DESIGN
3 Semester Regular/Back
4
/
SUBJECT:
6 0
9 - 0
BRANCH(S): CSE,CSEAI,CSEAIME,CSIT,CST,IT
Time : 3 Hour
1 0 Max Marks : 100
Q.Code : L421
Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two
- 3
from Part-III.
-
2 0 23
The figures in the right hand margin indicate marks.

4 / Part-I
0hexadecimal equivalent number of (256.5) .
Q1
a) Determine 6
0 /
Answer the following
the
questions : (2 x 10)

b) What9is-the equivalent simplified result of the Boolean function z=x’y’ +xy+x’y ?

8

c) 1 0 are major differences between MUX with DMUX. -3

What
d) How many 3 to 8 line decoders with an enable input are needed
2 3 - to construct a 6 to
64 line decoder without using any other logic gates? 0
e) Compare synchronous counter with asynchronous/counter.
4 2
f) Find the Gray code of 1101 & find is 2’s compliment.
6 / 0 to design a mod-21 counter ?
g) What is the minimum number of flip-flops needed
h) Define Prime implicant & mention its9 - 0
importance.
i) What is specialty of EX-OR gate1?0
j) Draw the circuit diagram of clocked T-flip flop.

-- 3
Q2 Only Focused-Short Answer Type
0 2 3Questions- (Answer Any Eight out of
Part-II
(6 × 8)
Twelve)
a) Simplify f  A, B, C    m0,4
/ 2,6,7,8,10,12,13,15
6 / 0 2, 4 using K-map.

9 - 0functions using single 3:8 decoder.

b) Show a two bit multiplier circuit design with an example.

10
c) Implement the given
f  A, B, C   2,3,4,5,7  3 - - 3
- - 3 1

2 02
3 f  A, B, C   1,3,5 /
20
d) Find
2
out the POS result of
2
x=a’b’+ab . / 0 4
e)4/What is the Boolean expression for the output of the 0 6
6 / 0 0 9 - 4:1 MUX shown below.

9- 0 R 1
10 R’
R’
f

P Q

f) Using T-Flip Flops, design a 2 bit synchronous up/down counter.

 g) Explain operation of 4-bit SISO shift register with necessary diagram.
h) Simplify X(p,q,r)=p’+qr’ using K-map.
i) Design a magnitude comparator to compare two 2-bit binary numbers: A=A1A0
-- 3
and B=B1B0 .There should be three outputs: A>B, A=B, A<B.
j) Explain CMOS circuit as an inverter.
02 3
k)
4/ 2
Design S-R flip-flop to D-flip flop conversion. Find its conversion table.
l)
it by using K-map.
0 6 /0
Draw full subtractor logic circuit & find its truth table. Also formulate the outputs of

09 -
1 Part-III
Only Long Answer Type Questions (Answer Any Two out of Four)

Q3 i) Obtain the simplified form for the given expression using K-map. (8+8)

3 --3
Also draw the minimization result using any one type universal gate only.
f  A, B, C    m0,2,4,6,7,8,10,12,13,15   d (1,9)
2
/2 0
/ 0 4
06
ii) Find the Boolean function implemented in the figure using 4:1 MUX.

9 -
10 -- 3
02 3
4/ 2
0 6 /0
-
109
Q4 (8+8)
i)
- 3
A majority circuit is a combinational circuit whose output is equal to 1 if the
-
02 3
input variables have more 1’s than 0’s. The output is 0 otherwise.
Design a 3 input majority circuit.

0 4 /2
/
ii) Explain BCD adder with necessary diagram.
06
0 9 -
Q5 1 Mod-3 synchronous counter using JK-flip flop.
i) Design
-- 3 (10+6)

- 3 0 2 3 and timing
2 3 -
ii) Discuss the working of 4-bit ring counter with circuit
/ 2
diagram

2 0 diagram.
/0 4
/
4 i) Highlight the salient features of ASM chart - 6
0& explain it by taking a suitable
Q66/0 9
- 0 1 0 (8+8)

109 example.

ii) Illustrate the operation of a serial Decade counter & its timing diagram