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Simulation of FeinProbe Probe Card Model For A5g WLCSP Application

SWtest Asia 2018 presentation "Simulation of FeinProbe Probe Card Model for a5G WLCSP Application", authors: Krzysztof Dabrowiecki, Adrian Lim, Jose Moreira, Thomas Gneiting, Ali Abdallah and Paul Hurst

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0% found this document useful (0 votes)
24 views24 pages

Simulation of FeinProbe Probe Card Model For A5g WLCSP Application

SWtest Asia 2018 presentation "Simulation of FeinProbe Probe Card Model for a5G WLCSP Application", authors: Krzysztof Dabrowiecki, Adrian Lim, Jose Moreira, Thomas Gneiting, Ali Abdallah and Paul Hurst

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jalvesmo
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Simulation of FeinProbe®

Probe Card Model for a 5G


WLCSP Application
Krzysztof Dabrowiecki Jose Moreira Thomas Gneiting Paul Hurst
Adrian Lim Ali Abdallah
FEINMETALL ADVANTEST AdMOS HARBOR
Overview
• Introduction
• Motivation
• 5G application test challenges
• FeinProbe® model simulation up to 30GHz
• Probe head design optimization
• Summary and Conclusion
• Follow-On Work

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 2
Hurst
Introduction

- Diversification of semiconductor products


- WLCSP market drivers

- WLCSP electrical and mechanical


requirements

- Internal qualification and various tests of


spring pin as one of few technologies for
WLCSP testing

http://www.swtest.org/swtw_library/2017proc/PDF

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 3
Hurst
5G - Technology and Life Evolution

Source: Companies and government materials


Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 4
Hurst
5G Application Test Challenges
❑ ATE
– Frequency range from 24 GHz to 44 GHz (might change!)
– Modulation frequency in the range of 800 MHz
– Devices with antennas integrated in package require over the air test at package level
– Silicon vendors would like to keep testing infrastructure modifications as small as possible
– Costs of test is critical
❑ PCB
– PCB size (can be as larger than 600x500mm)
– Material choice
– Copper profile, micro-strip plating
– Signal trace type
– PCB stack-up

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 5
Hurst
Wafer Probing Technologies for 5G
❑ Membrane Probe Technology ❑ Cantilever Probe Technology
• Validated for mmWave frequencies and • Uncontrolled impedance
in use by several IC companies • Very high inductance
• Good electrical performance • Bandwidth <2GHz
• High cost and long lead time • Limited DUT bump and multi-DUT layouts
• Limited compliance • Decoupling components far from DUT’s
• Very limited repairability • Limited repairability

❑ MEMS Probe Technology ❑ Spring Contact Probe Technology


• Very small probe size • Stable and consistent contact resistance
• Tough to get controlled impedance • Self-aligning crown plunger tip
• Lower inductance than cantilever • Bandwidth >20GHz
• Not yet proven for mmWave frequencies • High Current Carrying Capability (CCC)
• Low cost and lead time
Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 6
Hurst
5G Simulation WLCSP Project
Description
– The RF probe card simulation analysis includes the wafer solder bump, probe head and
contact with the PCB and PCB traces up to perfect termination measurement interface
– The single die layout shows 16 RF peripheral ports
Scope
- The board is a single site WLCSP board which is for a 5G application operating at ~29 GHz.
- The transmission lines is connected from the probe head via a micro-strip trace to a suitable
connector. A cable then makes the connection to a blind-mate connector
- Simulation includes BGA ball, probe head model, pad on PCB, 1.0 mm of transmission line
with perfect termination
- In the probe head is used an uncompressed spring probe of 3.7mm length.
- Simulation shows the results for impedance, insertion/return loss and crosstalk

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 7
Hurst
RF Simulation Project
RF pin locations PCB stack-up Simulated trace

• Device pitch ~0.4mm • PCB material FR4 and Isola • Simulation of trace AN0, AN1
• Equal trace lengths 38.8mm Tachyon® 100G and AN4
• PCB thickness 149.8 mils
(3.8mm)
Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 8
Hurst
Spring Contact Probe Head Investigation
Spring contact probe head model PCB simulation model
PCB

Patent
Pending

• Material choice critical for signal performance • The textbook micro-strip definition of a rectangular
• Different materials were investigated with air conducting cross-section between an inhomogeneous
between guiding plates as a reference dielectric and air is far away from the reality of an ATE
• Probe length 3.7 mm uncompressed PCB micro-strip geometry
• Maximum compressed length 3.4 mm
Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 9
Hurst
3D EM Simulation Model
3D probe head model
Component Material Dielectric Loss tangent tanδ Electric cond.
constant εr (S/m)
PCB Guiding plate Material A xxx 0.001 /
Pogo Pins CuSn6 / / 8e6
Ground CuSn6 / / 8e6
Bump Sn (Tin) / / 8.7e6
Micro strip Cu / / 5.96e7
Isolator PCB Isola 3.5 0.005 /
Filling Material B 1.0 0.002 /
(with option)
PCB Isola Tachyon 3.02 0.0021 /

• WLCSP DUT with ~0.4 mm pitch between antennas outputs


and the two adjacent GND pads
• A microstrip trace with 1.0 mm length and 0.2mm wide in
WAFER Isola Tachyon dielectric was also included
GND AN1 AN2 AN3 • Transition to the micro-strip trace included
• AN1, AN2 and AN3 are the RF outputs
GND GND GND
• PWR pins were shorted to GND for simulation
PWR PWR PWR PWR • 3D EM simulation performed in CST
Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 10
Hurst
Probe Head Design Optimization
Before Optimization After Optimization

An initial probe head design with air as a filling The optimized design with different filling materials
between guiding plates and asymmetrical guiding plates

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 11
Hurst
Insertion Loss Simulation Results

• Insertion loss can be compensated by the ATE system as long at it is measurable, stable and repeatable
• Note that the simulation only include a small length microstrip trace. A real probe card PCB would have a much
longer PCB trace

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 12
Hurst
Return Loss Simulation Results

• Results for different probe head holder materials


• Air shows the worst results
• Return loss cannot be compensated by ATE system so it is critical to be minimized

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 13
Hurst
Animation of EM Field Intensity (28 GHz)
Air Material B Option 1

• Max EM field intensity with air gap at • Max EM field intensity with material B option 1
28GHz is 186k V/m at 28GHz is 147k V/m

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 14
Hurst
Simulation Results
TDR Impedance Results Crosstalk Results (NEXT)

• Impedance for different material options • Crosstalk is high for 28 GHz for non-air probe heads
• High crosstalk is expected for a non-coaxial spring pin
solution. This drawback can be addressed by testing
one antenna at each time with the corresponding hit on
test time
Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 15
Hurst
Crosstalk Field Animation at 28 GHz
Air Material B Option 1

• Crosstalk max field intensity with air gap at • Crosstalk max field intensity with material B option 1
28GHz is 193k V/m at 28GHz is 149k V/m

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 16
Hurst
Probe Head Air Gap Optimization
Insertion Loss Return Loss

• Reduced air gap between probe head and wafer


(probe extension) improves IL and RL at high
frequency

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 17
Hurst
Probe Head Air Gap Optimization
Impedance before and after Impedance with different air gaps

• Because of the air gap between the wafer and the probe • The air gap between the wafer and the probe
head body, a non-symmetrical guiding plate construction head filling material are critical for impedance
provides performance improvements as shown in this
example
Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 18
Hurst
Probe Head Simulation up to 40GHz
Impedance Insertion Loss for AN1

• TDR Zw with Trise 20ps • ANT1 IL comparison for different air gaps
• The simulation was only performed for AN1, since the signal between head and wafer
path corresponds to the worst case
• The optimization shows an improvement between 0.5-0.7Ω
Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 19
Hurst
Probe Head Simulation up to 40GHz
Return Loss Crosstalk NEXT AN1 and AN4

• AN1 RL comparison for different air gap • AN1 & AN4 crosstalk comparison for different air
between head and wafer gaps between head and wafer

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 20
Hurst
Summary and Conclusion
➢ The choice of the right probing solution for mmWave WLCSP applications like 5G
depends on the performance objectives, volume, cost etc. There is no single right
answer.
➢ The probe head only defines part of the test fixture performance, the probe card
PCB signal trace and interconnect to ATE are also critical factors.
➢ Different optimization options of the probe head were presented and their impact
analyzed. With a good model of the probe head it might also be possible to
optimize the connecting micro-strip trace geometry to provide additional
compensation
➢ The simulation results are showing a room for probe head design improvement
especially to reduce the air gap which is crucial for impedance and signal integrity

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 21
Hurst
Summary and Conclusion

➢ These simulation results provide a first indication of the feasibility of using a


spring pin probe head for 5G WLCSP applications. The final proof is with the real
DUT

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 22
Hurst
Follow-On Work
➢ Verification study to confirm the simulation results

➢ Study of expected probe card PCB loss


➢ Testing of a FeinProbe® probe card at production environment

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 23
Hurst
Thank You

Dabrowiecki, Moreira,
Lim, Gneiting, Abdallah, 24
Hurst

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