Welcome to

Conference Expo
January 28 - 30, 2020 January 29 - 30, 2020

Santa Clara Convention Center

Introduction to the IEEE P370 Standard
and its Applications for High Speed
Interconnect Characterization

IEEE P370 WorkGroup

AGENDA
Topic Time Speaker
IEEE P370 development overview 15 min Xiaoning Ye Intel Corp.
IEEE P370 Draft D6 15 min Jay Diepenbrock SIRF Consultants, LLC.
Test Fixture Design Criteria 20 min Heidi Barnes Keysight Technologies
De-Embedding Verification 20 min Eric Bogatin Teledyne LeCroy
S-Parameter Integrity 20 min Mikheil Tsiklauri MS&T
Break 10 min
IEEE P370 Briefcase - Fixture electrical requirements 20 min Jason Ellison Amphenol
IEEE P370 Briefcase De-embedding verification and S 20 min Se-Jung Moon Intel Corp.
parameter Integrity
ATE PCB Test Fixture Example 20 min Jose Moreira Advantest
High Speed connector example 20min Ching-Chao Huang ATaiTec Corp.

3
IEEE P370 Development Overview

Speaker: Xiaoning Ye
Principal Engineer
Intel Corporation

IEEE P370 Workgroup Chair

IEEE EMC Society Technical Advisory Committee Chair

4
Common Industry Problems
• Poor design of test-fixture
• Poorly designed test-fixture  Inaccurate de-embedded S-parameters 
Electrical requirements of test fixture needed.
• Lack of de-embedding verification
• Various de-embedding/calibration approaches are available  
Algorithms are often proprietary (black-box magic)   Verification of the
accuracy left to user 
• Low quality S-parameter
• The quality of measured S-parameters of the DUT can vary widely  IEEE
standard to check and validate is needed before distribution

5
Measurement with Coaxial Connectors
SMA 18 GHz
 Most instruments, such as VNA, TDR/TDT can
make very good measurements at the end of a
3.5mm 26 GHz
coaxial interface.
2.92mm 40 GHz
Calibration Standard

2.4mm 50 GHz
Quality of SOLT calibration depends on
accuracy of the SOLT standards – In this
case, usually very good up to rated 1.85mm 65 GHz
frequencies!
1mm 110 GHz

6
Fixture Removal: Co-axial Connector to
PCB/PKG
Test fixtures need to be inserted between an instrument’s coaxial interface and the
Device Under Test (DUT) (PCB, package, connector, cable, etc.).
Fixture removal (de-
embedding) needed

Fixture Fixture
DUT
Your measurement can be
easily ruined by improper
fixture design. And even worse,
you may not be aware of it!
Calibration plane Calibration plane
(end of Co-axial connector) (end of Co-axial connector)

7
Fixture Removal: Microwave Probing

Calibration Plane

SOLT Calibration Substrate Fixture DUT Fixture

In this case, typical calibration is done at probe tip.

8
 IEEE P370 Development Timeline

Study Group kicked off to

define scope, and write the P370 Approved by
PAR (project authorization IEEE Standard We received 403
request Association comments
Initial proposal of IEEE P370 Work
standard work at TC10 Group kickoff 2nd Draft 3rd Draft 6th Draft
meeting of EMC PAR submitted
society 7/8/2015 08/2017 04/2019 Ballot Re-circulation
4/17/2015

6/11/2015 01/2018
8/6/2014 8/29/2014 12/2016 05/2019 12/2019
DesignCon
Initial Draft:
Plug fest

9
P370 Scope
 This standards development  The standard is applicable to:
project: • PCB and related interconnects (including
• addresses the quality of package, connector, cable, etc.) used in
measured data for electrical high speed digital applications, operating
printed circuit board (PCB) and with signals at frequencies up to 50GHz
related interconnect at
frequencies up to 50GHz. • most industries using such interconnects
• includes but is not limited to: test • major measurement approaches (Time
fixturing, methods and processes Domain or Frequency Domain) for
for controlling the accuracy and collecting S-Parameter data
consistency of measured data for • significant methods of removing/de-
broadband signals with frequency embedding fixture and instrumentation
content up to 50GHz. effects.

10
P370 Objectives

Proper Fixture
Bad S parameter Design
 Before After Task Group 1

Bad measurement De-embedding

Verification
Bad de-embedding tool Task Group 2
S-Param
Bad fixture design Integrity Check
Task Group 3
Bad PCB manufacturing Good S
parameter 

11
P370: Three Task Groups (TG)

 TG1: Test-fixture Design Criteria

 TG2: De-embedding Verification
 TG3: S-parameter Integrity

12
P370 Officers
• Workgroup
• Xiaoning Ye, Chair • Task Groups
• Jay Diepenbrock, Technical Editor • TG1 Test Fixture Quality
• Eric Bogatin, Past Technical Editor • Jim Nadolny, Chair
• Sam Connor, Vice Chair • Jason Ellison, Technical Editor
• Brice Achkir, co-Vice Chair • Heidi Barnes, Secretary
• Alistair Duffy, Secretary • TG2 De-embedding and Verification
• Eric Bogatin, Chair and Technical Editor
• Kai Xiao, Co-Chair
• Clement Luk, Secretary
• TG3 S-parameter Integrity
• Jun Fan, Chair
• Mikheil Tsiklauri, Co-Chair and Technical Editor
• Shuai Lin, Secretary

13
Acknowledgments

Many thanks to all P370 members (past and current)

for their contributions!

14
IEEE P370 Draft D6

Speaker: Jay Diepenbrock

SIRF Consultants, LLC
Technical Editor
P370 Contributors
What’s in the Standard? – Draft D6 Table of Contents
How to use the Standard - Application Block Diagram

15
P370 Contributors (subset)
• Component Suppliers
• Jim Nadolny, Samtec; Jason Ellison, Amphenol; Clement Luk, Samtec
• Test Equipment Suppliers
• Heidi Barnes, Keysight; Jose Moreira, Advantest; Eric Bogatin, Teledyne LeCroy; Lisa
Ward, Rohde&Schwarz
• Analysis Software Suppliers
• Ching-Chao Huang, Ataitec; Yuriy Shlepnev, Simberian
• Academia
• Jun Fan, Missouri U. of Science & Technology
• Mikheil Tsiklauri, Missouri U. of Science & Technology (now at Apple)
• Systems Companies
• Xiaoning Ye, Kai Xiao, Se-Jung Moon, Eric Gantner, Intel; Sam Connor, IBM; Brice Achir,
Cisco
• Design/Test
• Al Neves, Wild River Technology

16
IEEE P370 Draft D6 – Table of Contents excerpt
 Overview
 References
 Definitions
o Glossary
o S-parameter terms
o Touchstone file header
 Test fixture design criteria
o Fixture Design Requirements
o Fixture Electrical Requirements
 De-embedding verification
 Consistency tests
 S-parameter Integrity and Validation
 Annexes

17
IEEE P370 Draft D6 – Annexes
 A: Bibliography
 B: Network parameters tutorial
 C: Mixed mode network parameters
 D: Calibration and de-embedding
 E: Test fixture definition
 F: Verification structures
 G: Methods for comparison of S-parameters
 H: Quality Checking of Raw S-parameters
 I: Best practice: Design and Manufacturing
 J: Best practice: Fixture design
 K: Best practice: Measurement guidance
 L: S-parameter library

18
IEEE P370 Draft D6 – Annexes, cont’d
 M: Typical Application of the S-parameter library
 N: Sensitivity Analysis testing with synthesized S-parameter models
 O: Synthesized S-parameter library and circuits in the QUCS library
 P: Plug and Play test boards kit with separable connectors
 Q: Test typical manufactured board design
 R Creation of an input pulse
 S: Best practice: DC Extrapolation methodology
 T: Best practice- interpolation methodology

19
 Fixture Design and
VNA Calibration

IEEE P370 Manufacturing

4.2, 4.4

2X-Thru Measurement

Application FIX-DUT-FIX Measurement

Fixture Crosstalk Measurement

Initial Quality Checking of

Raw Data 7.3

- Block De-embedding Tool Evaluation

FER Classification 4.3

Diagram and Selection

Self-Deembedding Test of 2X-

Thru 6.5.1
TDR comparison of 2X-Thru and
FIX-DUT-FIX 6.5.2
De-embedding using 370 S-
paremeter library 5.2 Fixture Symmetry Check
6.5.3
De-embedding Verification
Sturctures Annex F
De-embedding using 370 Plug
& Plug Kit 5.3 Perform De-embedding

Initial Quality Checking of De-

Compare De-embedded DUT to embeded Data 7.3
Actual DUT 5.4
Application -based Quality
Checking 7.4
Report of De-embedding Tool
Evaluation
Document 370 Required Info in
Touchstone Header 3.6 (TBD)
Ma ndatory for Tool vendor
Opti onal for Tool user

20
IEEE P370 Draft D6 access
 By IEEE policy, draft specs. are only available prior to approval and
release to:
o Members of the spec. (P370) Working Group
o Members of the IEEE Standards Association

 Available to the general public at publication (this year)

21
Test Fixture Design Criteria

Speaker: Heidi Barnes

Keysight Technologies
[email protected]

P370 TG1 Secretary

22
IEEE P370 Objectives

Task Group 1 Proper Fixture

Design

Task Group 2 De-embedding

Verification

Task Group 3 S-Param Integrity

Check

Good S-parameter 

23
Designing a 2X-Thru Fixture – The Basics
P370 Fixture Design Requirements (FDRs) –
 P370 Supports 2X-Thru De-embedding
 P370 Supports Single Ended and Multi-mode Differential Pair Fixtures
 P370 Requires a Crosstalk Fixture when there is crosstalk between DUT fixtures.
1) The signal must reach the DUT –
Myth: Shorter is better

2) The 2x-Thru fixture removal math assumes symmetry across a TEM plane –
Common mistake: 2x-Thru Fixture is longer than DUT Fixture

3) Return path is just as important as the signal path –

Common mistake: Lack of Ground Vias when transitioning between PCB layers

4) Differential pairs can be routed without coupling –

Myth: Tight coupling is better.

5) Beware of multi-port crosstalk –

Common mistake: Failure to fabricate a crosstalk fixture.

24
A Shorter Fixture is not Always Better
Can I ignore the fixture losses if I shorten the length?
A shorter PCB path does not
eliminate impedance reflections from
the connector to PCB transition

Insertion Loss
SMA only 20 mils from the DUT Short 20mil

Long 700mil

Shorter fixture can be worse!

25
Don’t Include DUT Length In the 2X-Thru!
Correct 2X-Thru
Fixture-DUT-Fixture Wrong 2X-Thru Fixture A plus Fixture B

Fix A
Failure to
DUT Remove DUT
Length
Fix B

…. And don’t forget Fixture A + Fixture B Symmetry, not just length!

Don’t Forget the Return Path
“Ground is for potatoes and carrots!”... Bruce Archambeault
Electrical signals have a return path

27
Differential Routing Does not Need Coupling!
Differential Pairs use differential excitation, but the routing does not require coupling.

Coupled routing reduces the trace width….. Just think about what this does to fabrication ????!!!!

Reduced trace width  Higher resistive losses, higher sensitivity to fabrication etching, sensitive to edge tolerances

Coupling through vias  Differential to Common Mode Conversion

Single Ended went past 50GHz Differential made it to 35 GHz

2 0 2 0

-10 0 -10

Differential Insertion Loss, dB

Differential Return Loss, dB

0
Insertion Loss, dB

-2 -20
Return Loss, dB

-20
-2
-30 -4 -30
-4
-40 -6 -40
DUT
-6 -50 -8 -50
DE-EMBEDDED

-8 -60 -10 -60

0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
freq, GHz freq, GHz freq, GHz freq, GHz
10 10 0 10
0 0 -10
-20 -10
-20 -20

Error, dB

Error, dB
-30
Error, dB

Error, dB

-30
-40 -40 -40
-50 -50
-60 -60
-60
ABSOLUTE ERROR RELATIVE ERROR RELATIVE ERROR ABSOLUTE ERROR
-80 -80 -70 -70
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
freq, GHz freq, GHz freq, GHz freq, GHz

28
Multi-Port Fixture Crosstalk Must be Measured
2-Differential Pairs
2-Single Ended Traces

Additional Crosstalk Fixture Additional Crosstalk Fixture

29
How Good is Your Fixture - FERs
P370 Fixture Electrical Requirements (FERs) The Devil is in the Details
Class A, B, C because it is not easy to get to 50GHz, and it depends on the required application accuracy.
Enables common terminology for evaluating and describing fixture quality.
Mixed Mode Differential Ports
Single Ended Ports

30
Asymmetric Fixtures and Beyond

TA =Fixture Removal Algorithm(Т2x-Thru)

TB =Fixture Removal Algorithm(Т2x-Thru)
Additional
Т2x-ThruA = TATA
Fixture B
Т2x-ThruB = TBTB
2X-Thru
ТFullpath = TATDUTTB

TDUT= TA-1 TFullpathTB-1

31
IEEE P370 Objectives

Task Group 1 Proper Fixture

Design

Task Group 2 De-embedding

Verification

Task Group 3 S-Param Integrity

Check

Good S-parameter 

32
P370: Three Task Groups (TG)

 TG1: Test-fixture Design Criteria

 TG2: De-embedding Verification
 TG3: S parameter Integrity and Validation

33
P370 Objectives

Proper Fixture
Bad S parameter Design
 Before After Task Group 1

Bad measurement De-embedding

Verification
Bad de-embedding tool Task Group 2
S-Param
Bad fixture design Integrity Check
Task Group 3
Bad PCB manufacturing Good S
parameter 

34
TG2: De-embedding Verification
 Problem statement:
o De-embedding approaches are
commercially available, but
algorithms are often proprietary,
and verification of the accuracy of
the de-embedded S-parameters is
left to the user.
 Key P370 Contributions
o S-parameter library to verify de-
embedding tools.
o Plug-and-play kit to practice and
verify de-embedding
o Demonstration boards
o Standard procedures to verify the
de-embedding in the lab

35
TG2 De-embedding Verification

Speaker: Eric Bogatin

Signal Integrity Evangelist
Teledyne LeCroy

Adjunct prof at Univ of Colorado, Boulder

Technical Editor of the Signal Integrity Journal

TG2 Chair.

36
 An overview of P370-Task Group
Eric Bogatin, Teledyne LeCroy

• TG2: How do we validate the de-embedded DUT result

Officers: Eric Bogatin (co-chair), Kai Xiao (co-chair), Clement Luk (secretary)

• Goal: Develop a standard method and metric to measure the accuracy of a user’s specific
de-embedding process and results.

• Four general projects in TG2

1. Evaluating the de-embed algorithm
2. Testing the measurement process and de-embedding with a specific test vehicle
3. Consistency tests
4. S-parameter similarity metrics
 Our Focus
How do you gain confidence in the de-embedded results? (validate)
Absolute test of the de-embedding algorithm: work a problem for which you know the
answer (synthesized library of S-parameter files)
Quanitatively compare two S-parameter files: similarity metric
Perform measurements on separable structures to independently measure the DUT and
the de-embedded DUT
Perform consistency tests on your as manufactured board measurements

38
 Four general projects in TG2

1. Evaluating the de-embed algorithm, using synthesized S-

parameters
• A test of the de-embedding algorithm
2. S-parameter similarity metrics
3. Testing the measurement process and de-embedding with a
specific test vehicle
4. Consistency tests
Synthesized S-parameter Library for De-embedding
Evaluation
• Features of the synthesized library: Fixture Fixture
– Fixture models, 2x fixture models Left Right
– DUT models
– Mix and match composites
– Evaluate de-embed quality when 2x thru fixture is the same as DUT fixture
– Evaluate the “sensitivity” of the de-embed process when 2x thru fixture is DUT
not the same as fixture DUT
• Approach 1: use the 2X-Thru structure to extract the fixture
model Fixture Fixture
– But what if the 2x thru FIX ≠ the FIX on the FIX-DUT-FIX? DUT
Left Right
– Potential causality problems introduced
• Approach 2: impedance corrected 2X-Thru de-embedding
– Use the 2X-Thru to get the time delay and loss of the FIX model
– Extract the FIX model from the FIX-DUT-FIX structure using “peeling”
Fixture Fixture
Left Right
Synthesize S-parameters from Simulated Examples of
DUT, FIX-FIX and FIX-DUT-FIX
Example: Using Synthesized Library to Comparing the
De-embedded DUT with the “answer”

Insertion loss of de-embedded DUT

is accurate up to 45 GHz

Return loss accurate to 35 GHz

DUT only DUT only 2x thru IL< RL at ~ 30 GHz.

 Four general projects in TG2

1. Evaluating the de-embed algorithm, using synthesized S-parameters

• A test of the de-embedding algorithm
2. S-parameter similarity metrics
3. Testing the measurement process and de-embedding with a specific
test vehicle
4. Consistency tests
 Two Approaches to the Similarity Metric: absolute
Teledyne LeCroy Signal Integrity Academy

and relative Error Vector

imag
error(f ) mag ( Sij (f )A − Sij (f )B )
error
= SA

SB
mag ( Sij (f )A − Sij (f )B ) real

error _ fraction(f ) =
0.5 × ( Sij (f )A + Sij (f )B )

Composite error vector = Define:

0.9 x mag(absolute error vector) BW below which the absolute, relative or composite
+ 0.1 x mag(relative error vector) error magnitude < -30 dB, -20 dB, -10 dB

44
 Original DUT and De-embedded DUT

The -10 dB absolute error bandwidth is…

The -20 dB absolute error bandwidth is…
The -30 dB absolute error bandwidth is…
 Four general projects in TG2

1. Evaluating the de-embed algorithm, using synthesized S-

parameters
• A test of the de-embedding algorithm
2. S-parameter similarity metrics
3. Testing the measurement process and de-embedding with a
specific test vehicle
4. Consistency tests
 Project 3: Separable “Plug and Play” Test Vehicles
(Heidi Barnes, Jose Moreira)
IEEE P370 Plug and Play Test Coupons
DUT Line DUT ZBeatty
Line Fixture A
Line Fixture B
Vias Fixture A Vias Fixture B
LowZ Fixture A LowZ Fixture B
Equal Length Adapters

Flush Short

[email protected] [email protected]
Example of the Plug and Play Board
Set

Define the -30 dB, -20 dB, -10 dB

error bandwidth of the de-
embedding process

Case where absolute error has much more value

 Four general projects in TG2
1. Evaluating the de-embed algorithm, using synthesized S-parameters
• A test of the de-embedding algorithm
2. S-parameter similarity metrics
3. Testing the measurement process and de-embedding with a specific
test vehicle
4. Consistency tests

• Purpose: verify the de-embedded results

• Test #1: test reciprocity, passivity and causality of each S-parameter file (TG3)
• Test #2: self de-embedding the 2X-Thru
• Test #3: compare TDR of fixture on DUT and fixture on reference
 Consistency test #2: self de-embedding the 2X-Thru-
a transparent interconnect

Fixture Fixture
Left Right

Fixture Fixture Fixture Fixture

Left Left Right Right

Should be transparent:
Mag S21 = 0 dB, phase S21 = 0
S11 very small reflected signal

50
 Consistency Test #3:
TDR of FIX model should match the FIX-DUT-FIX

De-Embedded Fixture Matches DUT Fixture

13-WA3-Parameter Measurement and Fixture De-Embedding Variation Across Multiple Team and De-Embedding Tools 51
S-parameters Integrity

Speaker: Mikheil Tsiklauri

Missouri University of Science and Technology

[email protected]
P370 TG3 Co-Chair

52
S-parameter Quality Estimation
• S-parameters describing a physical system are not
perfectly accurate and do not describe it
comprehensively
Causality
• It’s important to be able to estimate the quality of
existing data in order to achieve reliability of the
results and conclusions developed based on it

• The goal is to estimate S-parameter quality based

on three properties:
• Passivity
• Reciprocity
• Causality

53
General Idea
• Estimation should be intuitive and have physical explanation
• Estimation in % can not explain to engineer why the data is acceptable or vice versa
General idea of the estimation:
• Estimation is in mV units for each property:
• Passivity
• Reciprocity
• Causality
• It tells engineer what is a maximum difference between waveforms we can obtain if we
will use existing S-parameters and S-parameter that is closest to the original one and is
passive, reciprocal or causal
• The methodology is using pulse response technique and does not require running large
PRBS signal
• The methodology does not include Enforcement/Changing/Fixing original S-
Parameters, it just estimates
Estimation Stages
• Step 1. Create passive/causal/reciprocal S-
parameter that is closest to original one
• Step 2. Compare original and the closest
passive/causal/reciprocal S-parameter
• Comparison is performed in time domain:
• Step 2.1 Obtain pulse responses for
both S-parameters
• Step 2.2 Find the worst bit sequence
that will cause the largest difference
between original and closest
passive/causal/reciprocal S-parameters
• Step 2.3 Calculate the largest difference

55
Passivity
A passive System does not generate energy,
Mathematically it means that:
𝑆𝑆 ≤ 1
where norm is taken as max eigenvalue

Passivity estimation can be split into two stages:

1. Find the closest passive S-parameters matrix

to original one:
𝑆𝑆 − 𝑆𝑆𝑝𝑝𝑝𝑝𝑝𝑝 → min(𝑆𝑆𝑝𝑝𝑝𝑝𝑝𝑝 ) , for any 𝑆𝑆𝑝𝑝𝑝𝑝𝑝𝑝 ≤ 1

2. Create a metric that gives physical meaning to the difference between original and passive
S-parameter matrices

56
Closest Passive S-Parameters
Create Passive model by modifying eigenvalues that are more than 1:

Step1. Apply Singular Value Decomposition (SVD) to the original S-parameters matrix:
𝑆𝑆 = 𝑈𝑈𝑈𝑈𝑉𝑉 ∗
D is diagonal matrix of eigenvalues; U - left eigenvectors; V - right eigenvalues;

Step2. Replace by 1 all eigenvalues more than 1 in matrix D:

Step3. Create passive S-parameters with modified eigenvalue matrix D and left and right
eigenvector matrices U and V:

The obtained matrix will have all singular values less then one and therefore will be
passive.

57
Time Domain Estimation Algorithm
Second stage is to create a metric that will
estimate difference between two S-parameter
matrices and will have physical meaning.

The estimation value is a maximum difference

that can be obtained for the channel
responses corresponded to the S-parameter
matrices.

Create input pulse with specific data

rate/rise/fall time
Gaussian pulse with 20/80 rise time

58
Time Domain Estimation Algorithm
• Calculate pulse responses for each
component of both S-parameters
• Channel response can be
calculated if values the pulse
response separated by k*UI will be
added or subtracted
• Add or subtract depends on
corresponding bit value (1 or -1)
• Maximum difference between two
channel responses will be sum of
differences between pulse
response values separated by k*UI

59
Causality

Measurement inaccuracy, numerical errors in simulations, different assumptions or errors

in algorithm (de-embedding) can create causality problems in S-parameters

60
Causality Problems in De-Embedding
The 2X-Thru method separates Fixture A and Fixture B from Fixture A Fixture B
each other
2 conditions allows accurate separation: Non-causal
• Response from Fixture A (tail) should die at the Fixture B
boundary
• There should not be any response of Fixture B
before boundary

Second condition is causality of Fixture B

Fixture A

Non-causal Fixture B will add its non-causal artifact in

Fixture A

61
Causality Estimation
• Causality estimation also have two stages

• Stage1. Create causal model:

– Real and imaginary parts of causal transfer function are not
independent and can be reconstructed from each other;
– Similarly magnitude and phase of causal transfer function are not
independent and can be reconstructed from each other
– Magnitudes of the components of S-parameter matrices will be taken
and causal phases will be reconstructed

• Stage2. Estimated difference between original S-parameters and

reconstructed causal S-parameter matrices using a time domain metric

62
Stage 1. Create Causal Model
Direct numerical calculation of band limited integral has singularity problem near
maximum frequency. This singularity can be avoid using DHT based enforcement:

63
Delay
Pulse Response
• Front delay should be used to
create causal model
• Front delay is frequency Input pulse
independent and corresponds to
the time when the front of the
signal will appear

Front delay

64
Reciprocity
• For a reciprocal network, transmission of a signal between any two ports does not
depend on the direction of propagation
• S-Parameter matrix for reciprocal model is symmetric:
• We need to estimate level of asymmetry of S-parameters that will have physical
meaning

• Stage 1. Create another S-parameter matrix that is the transpose of original one

• Stage 2. Estimate difference between original S-parameter matrix and its

transpose using the same time domain metric

65
References
• H. Barnes, E. Bogatin, J. Moreria, J. Ellison, J. Nadolny, C.C. Huang, M. Tsiklauri, S.J. Moon, V. Herrmann, “A
NIST traceable PCB kit for evaluating the accuracy of de-embedding algorithms and corresponding metrics,”
DesignCon 2018, 01/30 to 02/01/2018, Santa Clara, CA.
• M. Tsiklauri, "P370:Electrical Characterization of Printed Circuit Board and Related Interconnects at Frequencies up
to 50 GHz," 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity
(EMCSI), Washington, DC, 2017, pp. 1-15,
• M. Tsiklauri, N. Dikhaminjia, J. Fan and J. Drewniak, "S-parameters quality estimation in physical units," 2017 IEEE
International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Washington, DC,
2017, pp. 422-426.
• M. Tsiklauri, M. Zvonkin, N. Dikhaminjia, J. Fan and J. Drewniak, "Discrete Hilbert Transform based delay causality
enforcement for network parameters," 2016 IEEE International Symposium on Electromagnetic Compatibility
(EMC), Ottawa, ON, 2016, pp. 921-926.
• M. Tsiklauri, N. Dikhaminjia, J. Fan, J. Drewniak and M. Zvonkin, "Front delay based causality for network
parameters," 2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), Shenzhen,
2016, pp. 870-872.
• M. Tsiklauri, M. Zvonkin, J. Fan, J. Drewniak, Q. B. Chen and A. Razmadze, "Causality and delay and physics in real
systems," 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC), Raleigh, NC, 2014, pp. 961-
966.

66
Break
IEEE P370 Briefcase

Se-Jung Moon (IO Architect), Intel Corporation

Jason Ellison, (Sr. Staff Signal Integrity Engineer), Amphenol

68
Contributors
• Integration: Se-Jung Moon (Intel), Hansel Dsilva (Former Intel)
• TG1: Jason Ellison (Amphenol ICC)
• TG2: Clement Luk (SAMTEC)
• TG3: Mikheil Tsiklauri (Apple), Shuai Jin (Google), Se-Jung Moon, Hansel Dsilva
Disclaimer
• This briefcase is an auxiliary tool developed by members of the IEEE P370 workgroup members to
demonstrate an example of how the P370 standard can be used for high speed interconnect
characterization.

• The tools used in this briefcase are based on the open source codes available at
http://gitlab.com/IEEE-SA/ElecChar/P370/ under a BSD 3-Clause license either within the P370 draft
or as a separate file. Any person contributing material to IEEE open source software during
standards development SA ballot or Public Review is required to provide the appropriate license to
IEEE Contributor License Agreement or CLA.

• The briefcase is developed as an implementation example of the open source code and does not
represent the only or preferred implementation.

70
Integration of Different P370 TG Scripts in GUI

TG1
Fixture Design and
Quality Criteria

TG2 TG3
S-parameter S-parameter
Similarity Quality

The P370 Briefcase is an auxiliary tool developed by members of the IEEE P370 workgroup to demonstrate an example of
how the P370 open source codes can be used for high speed interconnect characterization.

71
Briefcase Overview

Input Output

S-parameters of Metrics and qualification/grading of

• 2X-Thru • Fixture Quality
• Dogleg/spiderleg • De-embedding Quality
• Fixture-DUT-Fixture • S-parameter Quality
• Fixture models
• DUT (de-embedded, reference)

72
TG1: Fixture Quality Check
Summary of the Fixture Electrical Requirements
Required Structures
What FER results look like
Proper Filtering for Impedance Calculations
Tips to make you fixture compliant to the FERs

73
Fixture Electrical Requirement Summary
What is a class?

Class A is a transparent fixture.

Transparent means it can be removed
with basic algebra.

Class B is a typical fixture. Typical fixtures

can be removed with standard 2X-Thru
algorithms.

Class C is a challenging fixture. These

fixtures need impedance correction to
achieve acceptable results.

74
How do you evaluate your fixture?
1.) Make the fixture with the proper
structures:

 2X-Thru Structure (Single-Ended or

Differential)
Dog bone

 Dog bone (Single-ended) or Spider leg

(Differential) Structure

Spider leg

75
How do you evaluate your fixture?

FER1: 20 x log10(SDD21(f)) FER2: 20 x log10(SDD11(f))

76
How do you evaluate your fixture?

FER3: 20 x log10(SDD21(f)) - 20 x log10(SDD11(f)) FER5: [|Z2x-thru – ZFIX-DUT-FIX|/ Z2x-thru] x 100%

77
How do you evaluate your fixture?
0

Spider Leg
-10 DUT

-20

-30

Magnitude [dB]
-40

-50

-60

-70

FER4: XTFixture < XTDUT

-80
0 5 10 15 20 25 30 35 40 45 50

Frequency [GHz]

78
How do you evaluate your fixture?

79
How do you evaluate your fixture? 100

80

fmax = 50Ghz  rt = 20ps Fixture DUT

0.9
60
0.8

40

t0 = 1ns
0.7

0.6

]
20
0.5

𝐺𝐺 [𝑘𝑘 ]

Impedance[
G(t)

0
0.4

ℎ[𝑘𝑘 ] = 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖[𝑘𝑘 ] ∗
∑ 𝐺𝐺 [𝑘𝑘 ]
0.3
-20
0.2

-40
0.1

𝑛𝑛
0
-60
-0.1
0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆[𝑛𝑛] = � ℎ[𝑘𝑘 ]
-80
time [ns]

-100
70
0 0.5 1 1.5 2 2.5 3 3.5 4

65
2x-Thru
Fixture-DUT-Fixture
𝑘𝑘=−∞ time [ns]

ℎ[𝑘𝑘 ] + 1
𝑧𝑧[𝑛𝑛] = −𝑧𝑧0
60

ℎ[𝑘𝑘 ] − 1
15
55
]
Impedance[

50

45

40
𝑧𝑧𝐹𝐹𝐹𝐹𝐹𝐹 [𝑛𝑛] − 𝑧𝑧2𝑥𝑥 [𝑛𝑛]
𝐹𝐹𝐹𝐹𝐹𝐹5[𝑛𝑛] = � � × 100%
10

𝑧𝑧𝐹𝐹𝐹𝐹𝐹𝐹 [𝑛𝑛]
Fixture DUT

]
35

Impedance[
30
0 0.5 1 1.5 2 2.5 3 3.5 4
time [ns]

0
0 0.5 1 1.5 2 2.5 3 3.5 4
time [ns]

80
Tips for successful fixtures (Best Practices)
 Use vertical coaxial launches
 Model the via transition with a 3D EM
tool
 Consider the VNA cable

 More tips within the IEEE 370

document
o Via design examples
o Via stub analysis
o Fiber weave considerations
o Trace routing
o Design documentation
o PCB manufacturing considerations

81
TG2: De-embedding Quality Check

82
How do I quantify S-parameter Similarity?
How can I tell if these S-parameters are good enough?

How can I tell if this measured DUT is

similar to my actual DUT ?

83
Use S-parameter Similarity in the Briefcase!

𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒(𝑓𝑓) = �𝑆𝑆𝑖𝑖𝑖𝑖 (𝑓𝑓)𝐴𝐴 − 𝑆𝑆𝑖𝑖𝑖𝑖 (𝑓𝑓)𝐵𝐵 �

2 × 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒(𝑓𝑓)
𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑒𝑒 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒(𝑓𝑓) =
𝑆𝑆𝑖𝑖𝑖𝑖 (𝑓𝑓)𝐴𝐴 + 𝑆𝑆𝑖𝑖𝑖𝑖 (𝑓𝑓)𝐵𝐵

84
TG3: S-parameter Quality Check

85
How do I quantify the Quality of S-parameters?
SDD11 SDD12 SCD11 SCD12
0 0 -20 -30

-10 -40
-5
-40
-20 -50
-10
-30 -60
-60
-15
-40 -70

Are they
-50 -20 -80 -80
0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50

SDD21 SDD22 SDC21 SDC22

0 0 -30 0

• PASSIVE?
-20
-5 -40
-20
-40
-10 -50
-60
-40
-15 -60

• RECIPROCAL?
-80

-20 -60 -70 -100

0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50

SCD11 SCD12 SCC11 SCC12

• CAUSAL?
-20 -30 0 0

-40
-40 -10 -5

-50
-60 -20 -10
-60

-80 -30 -15

-70

-100 -80 -40 -20

0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50

SCD21 SCD22 SCC21 SCC22

-30 0 0
-20

-40 -5 -10
-40

-50 -10 -20

-60
-60 -15 -30

-70 -80 -20 -40

0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50

86
How do I quantify the Quality of S-parameters?
PASSIVITY RECIPROCITY CAUSALITY
Frequency
Domain

Contextual
Time Domain

87
ATE PCB Test Fixture Example
Jose Moreira
[email protected]

Jose Moreira is a senior staff engineer in the HW R&D Team of the SOC business unit at
Advantest in Böblingen, Germany. He focuses on the challenges of testing high-speed digital,
silicon photonics and 5G mmwave devices, especially in the area of PCB test fixture design,
signal and power integrity, focus calibration and over the air (OTA) measurements. He joined
Agilent Technologies in 2001 (later Verigy and in 2011 acquired by Advantest) and holds a
Master of Science degree in Electrical and Computer Engineering from the Instituto Superior
Técnico, Lisbon University, Portugal. He is a senior member of the IEEE and co-author of the
book “An Engineer’s Guide to Automated Testing of High-Speed Digital Interfaces”.
ATE Test Fixtures De-Embedding Challenge
• ATE Test Fixture Printed Circuit Boards can have very large sizes (e.g. 598 mm x 480 mm).

• Current ATE applications span from e. g. , 128 Gbps for High-Speed Digital to 85 GHz for mm wave testing
with current requirements from mA to hundredths of Amperes.

• An ATE system is usually calibrated only to the ATE interconnect to the PCB test fixture.

• The test engineer is only interested in measuring the DUT. He would like to completely de-embed the PCB
test fixture.
• 100% de-embedding is very challenging for ATE test fixtures
due to components like sockets and probe heads.

• Golden DUTs have been used to address this challenge but

this approach has limitations.

• Usually, 90% of the test fixture can be de-embedded with

minimal effort which for traditional ATE is a big step.

89
ATE Test Fixtures De-Embedding Challenge
• The Device Under Test (DUT) contacts the test fixture PCB thru a socket (package testing) or a probing head
(wafer probing).

• Traditionally, test engineers want the entire test fixture PCB to be de-embedded; i. e., the reference plane
to be moved to the tip of the socket/probe head.

• But this is the worst point to set a reference plane since the EM Fields at that point are not stable and DUT
dependent!!
ATE SYSTEM DUT TEST FIXTURE

ATE INTERNAL PCB TEST FIXTURE SOCKET/PROBE

SIGNAL PATH SIGNAL PATH HEAD SIGNAL PATH
ATE ATE/PCB TEST
MEASUREMENT FIXTURE DUT
INSTRUMENT INTERNCONNECT

ATE CALIBRATION TEST ENGINNER WISH

REFERENCE PLANE REFERENCE PLANE

90
 Traditional Methods: Direct Measurement

• Probing the ATE PCB test fixture directly with a micro-coaxial probe is a very traditional approach.
• It requires a special interposer if the DUT socket is to be included.
• Challenges are the BGA ballout and also the micro-coaxial probe de-embedding.
REFERENCE: Heidi Barnes et al., “Performance at the DUT: Techniques for Evaluating the Performance of an ATE System at the Device Under Test
Socket ”,DesignCon 2008.

91
 Traditional Methods: Direct Measurement
INTERPOSER
Probing Interposer in an un-modified socket

MODIFIED SOCKET

• Another approach is to create an interposer PCB that attaches to a modified or un-modifed socket. This
allows the usage of coaxial connectors on the interposer instead of micro-coaxial probes.
• But one still needs to de-embed all these added components.

REFERENCE: Jose Moreira et al., “A Pragmatic Approach for At-Speed Characterization and Loopback Correlation at 28 Gbps”, Advantest VOICE 2014.

92
ATE Test Fixtures De-Embedding Challenge
• ATE measurements rarely consist of S-parameters. Usually one needs to de-embed scalar measurements
(e. g., power) or time domain measurements (e. g., waveforms).
• Another application is to obtain the correct setting on the ATE pin-electronics continuous time linear
equalizer. Objective is to compensate for the test fixture and not to compensate for any DUT performance
issues. • On most de-embedding packages one quick way to get the DUT Test
Fixture S-parameters is to use the 2X-Thru S-parameters as the DUT
(self de-embedding).
For Most ATE Applications We • From a de-embedding quality point of view the P370 metrics can be
Only Need the Test Fixture S- used .
parameters

Т2x-Thru = TATA
ТFullpath = TATDUTTA
TDUT= TA-1 TFullpathTA-1

93
ATE De-Embedding Example with 2X-Thru
• ATE Test fixture signal trace to DUT is composed of
a 12 inch coaxial cable and a 43.5 mm, 9 mil wide
microstrip trace.
• A 2X-Thru structure was implemented on the ATE
PCB test fixture (two 12 inch coaxial cables are also
required).
• Unfortunately due to mechanical requirements
(handler/prober interaction), ATE test fixture PCB
traces are usually long.

94
IEEE P370 Briefcase Results

95
ATE De-Embedding Example with 2X-Thru
• The obtained de-embedding S-parameters are used to de-embed the
measured scalar values (e.g. power). This is done for example by importing
the s-parameter file into the ATE software
• Only missing item to de-embed is the socket. A topic that requires a full
tutorial . (2X-Thru structure)

Т2X-Thru = TATA
(Plus 12 inch Coaxial Cable)

96
Measurement to Simulation Correlation
SIMULATION MODEL
• This is a 5G over the air (OTA) testing application.
• Objective is to measure the DUT plus OTA probe head
assembly.
• To reduce simulation complexity and simulation time,
the simulation model was reduced to a minimum
without the ATE PCB test fixture and parts of the probe
head microstrip trace.

MEASUREMENT SETUP
Questions:
• How to correlate simulation
to measurement.
• How to make sure the PCB
part of the simulation
model is correct.

97
 2x-Thru Cal
Measurement to Simulation Correlation Structure

ATE Test Fixture De-Embedding

We Want To De-Embed The PCB Signal

Trace To The Socket Pad Including
Connector !!

Т2x-Thru = TATA

98
IEEE P370 Briefcase Results

99
Measurement to Simulation Correlation
• Probe Head PCB Correct Simulation Model.
• Need to De-Embed ~40 mm of trace loss
• A Beatty Structure was manufactured in the same panel as the probe head PCB.
• We will use the Betty structure to validate our simulation model first and if needed tune
it to correlate.
• To properly correlate the Beatty structure measurements with simulations we need to
de-embed the connectors (they are not simulated)
• To accomplish this a 2X-Thru structure is included on the Beatty structure test coupon.

Beatty Structure

2x-Thru

100
 Measurement to Simulation Correlation
NO TUNING (SPEC SHEET VALUE) AFTER TUNING (SPEC SHEET VALUE)
Unwrapped Phase Insertion Loss Return Loss Unwrapped Phase Insertion Loss Return Loss
500 0.0 0 500 0.0 0
-5 -5
0 -0.5 0 -0.5
-10 -10
-1.0 -15 -500 -1.0 -15
-500
-20 -20

Phase, Degrees
-1.5
Phase, Degrees

-1.5
-1000 -1000

Loss, dB

Loss, dB
Loss, dB

Loss, dB
-25 -25
-2.0 -2.0
-30 -1500 -30
-1500
-2.5 -35 -2.5 -35
-2000 -2000 -40
-3.0 -40 -3.0
-45 -45
-2500 -2500
-3.5 -3.5 -50
-50
-3000 -4.0 -55 -3000 -4.0 -55
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
freq, GHz freq, GHz freq, GHz freq, GHz freq, GHz freq, GHz
Phase Error Insertion Loss Error Return Loss Error
100 2.4 40 Phase Error Insertion Loss Error Return Loss Error
10 0.7 26
90 2.2
35 9 24
2.0 0.6
80 22
1.8 30 8
70 20
1.6 7 0.5 18
25
Error, Degrees

60 1.4

Error, Degrees
6 16
Error, dB

Error, dB
0.4

Error, dB

Error, dB
50 1.2 20 14
5
40 1.0 12
15 4 0.3
0.8 10
30
0.6 10 3 0.2 8
20 6
0.4 2
10 5 0.1 4
0.2 1 2
0 0.0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 0.0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
freq, GHz freq, GHz freq, GHz
freq, GHz freq, GHz freq, GHz

REFERENCE: Heidi Barnes José Moreira and Manuel Walz, “Non-Destructive Analysis and EM Model Tuning of PCB Signal Traces using the Beatty Standard”,
DesignCon 2017.

101
Measurement to Simulation Correlation
Simulation (Tuned Values)
• This process helps to remove the test fixture impact allowing to
concentrate on the critical part.

• By using tuned values based on the Beatty structure, there is

additional confidence on the simulation results.

Missing Microstrip Trace From

Measurement Simulation (Tuned Values)
(Could also be Achieved by a 2x-thru Structure)
PCB Test Fixture (2X-Thru De-embedding) Insertion Loss for a 4 cm Microstrip
m1

-1.0
-1.1
m1
-1.2 freq=28.00GHz

-
dB(S(12,11))=-1.618

-
-1.3
-1.4

Loss, dB
-1.5
-1.6
-1.7
-1.8
-1.9
-2.0
24 25 26 27 28 29 30 31 32
freq, GHz

102
 S21
1X-Reflect De-Embedding a
Want to extract fixture’s insertion loss
• The 1x-reflect de-embedding (S12 or S21) from S11 open/short.
S11 S22 Γ
methodology uses a short and/or b
S12
open at the DUT point.
b S12 S 21Γ
• 1X-reflect based de-embedding S open or short
= = S11 + To extract
1 − S 22 Γ
11
a
is not supported by the P370
standard.

• Most SW tools that support 2X-

Thru de-embedding also support
1x-reflect.

REFERENCE: Jose Moreira, Ching-Chao Huang and Derek Lee, “DUT ATE Test Fixture S-Parameters Estimation using 1x-Reflect Methodology”, BITS China 2017.

103
 1X-Reflect De-Embedding Example

1.2 inch 10 mil wide stripline in

Meteorwave 2000

ATE 2.4 mm COAXIAL

INTERFACE CONNECTOR

104
1X-Reflect De-Embedding Example
• 5G-NR mmWave Wafer Probing Application. SHORT OPEN THRU

• A calibration substrate was custom manufactured

for the DUT ballout that includes a short and an
open.

105
High-speed connector examples

Speaker: Ching-Chao Huang

AtaiTec Corporation
President
[email protected]

Outline
• Extract connector DUT from a much larger test fixture
• Correlate differential IL, RL, NEXT and FEXT

106
Example 1 –
Mezzanine connector in a large test fixture

Fixture

25mm
IT3 mezzanine
2x thru connector
(12” total) (DUT)

Courtesy of Hirose Electric

107
2x thru vs. impedance-corrected method
• 2X-Thru method (i.e., splitting 2X-Thru directly for de-embedding) gives
many ripples in this case.

ripples

ripples

108
TDR verification – Differential mode
• Due to impedance variation between 2X-Thru and fixture, splitting 2X-Thru
directly results in causality error before and after DUT.
Causality error

DUT

Rise time = 20ps (20/80)

109
TDR verification – Common mode
• Must also verify common-mode and single-ended data.

Causality error

DUT

110
TDR verification – Single-ended
• Impedance corrected method gives better results in all DIFF, COM and SE.

Causality error

DUT

111
Example 2 –
Correlate differential IL, RL and crosstalk

IT8 connector

96-port HFSS model

2.087”
IT8-14mm Pair 6 Pair 5 Pair 4 Pair 3 Pair 2 Pair 1
2.087”
FIX-DUT*-FIX
Pair 12 Pair 11 Pair 10 Pair 9 Pair 8 Pair 7
Blind via

2.087” 2.087” Pair 18 Pair 17 Pair 16 Pair 15 Pair 14 Pair 13

2x thru
Pair 24 Pair 23 Pair 22 Pair 21 Pair 20 Pair 19
Ref. plane

*DUT includes IT8 connector and vias Courtesy of Hirose Electric

112
Differential IL and RL
• Compute similarity metric to quantify correlation.
Similarity metric

IL

RL

113
TDR correlation
• Good correlation was observed.
Mounting IT8 Mating
side connector side

Rise time (20/80) = 12.5ps

114
Same-wafer NEXT and FEXT

0 0

-20 -20

-40 -40

-60 -60
*

S (dB)

S (dB)
-80 -80

-100 -100

-120 -120 Simulation

Simulation
Measurement Measurement
-140 -140
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Frequency (GHz) Frequency (GHz)

NEXT FEXT

* 4-port 2x thru was used so adjacent pair-to-pair fixture FEXT might be present.

FEXT NEXT 115

Different-wafer NEXT and FEXT

0
0

-20 -20

-40 -40

-60 -60

S (dB)

S (dB)
-80 -80

-100 -100

-120 -120 Simulation

Simulation
Measurement Measurement
-140 -140
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Frequency (GHz) Frequency (GHz)

NEXT FEXT

FEXT NEXT 116

Diagonal-neighbor NEXT and FEXT
• Correlate to -80 dB and below!

0 0

-20 -20

-40 -40

-60 -60

S (dB)

S (dB)
-80 -80

-100 -100

-120 Simulation -120 Simulation

Measurement Measurement
-140 -140
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Frequency (GHz) Frequency (GHz)

NEXT FEXT

FEXT NEXT 117

Thank you!
---

QUESTIONS?