Memory Classification and

Programmable Logic

1
Memory

2
3
 What is Microprocessor?

CPU - Central Processing Unit

 Control Unit- Coordinates the activity of different
blocks of Computer
 Arithmetic Logic Unit- performs arithmetic and
logical operations
 CPU fabricated in single IC chip is called Processor
 Execution time of an instruction is in microsecond
order-Microprocessor

4
Microcontroller vs. General Purpose
Microprocessor

5
 Basic Units Of Measurement for memory
 A memory unit stores binary information in groups of bits called words.
1 byte = 8 bits
1 word = 2 bytes
 The communication between a memory and its environment is achieved
through data input and output lines, address selection lines, and control
lines that specify the direction of transfer.

6
 Content of a memory
 Each word in memory is
assigned an identification
number, called an address,
starting from 0 up to 2k-1,
where k is the number of
address lines.
 The number of words in a
memory with one of the
letters K=210, M=220, or
G=230.
64K = 216 2M = 221
4G = 232
7
 Write operations
 Transferring a new word to be stored into
memory:
1. Apply the binary address of the desired word to
the address lines.
2. Apply the data bits that must be stored in
memory to the data input lines.
3. Activate the write input.

8
 Read operations
 Transferring a stored word out of memory:
1. Apply the binary address of the desired word to the
address lines.
2. Activate the read input.

9
Main and Storage Memory

• Main Memory:
• RAM,ROM,PROM,EPROM
• Auxiliary Storage Devices-Magnetic
Tape, Hard Disk, Floppy Disk
• Optical Disks: CD-R Drive, CD-RW
disks,DVD,Blue ray Discs.

10
 Storage Memory (e.g., Hard disk)
• The information is retained longer
(non-volatile)
• Slower
• Cheaper
Main Memory (e.g., RAM)

•Keep the information for a shorter period of time

(usually volatile)
•Faster
•More expensive

11
Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random EPROM Mask-Programmed

Access Access 2
E PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
 RAM
 Random write and read operation for any cell
 Volatile data
 Most of computer memory
 DRAM
 Low Cost

 High Density

 Medium Speed

 SRAM
 High Speed

 Ease of use

 Medium Cost
 Static RAM
 SRAM consists essentially of internal latches that store the
binary information.
 The stored information remains valid as long as power is
applied to the unit.
 SRAM is easier to use and has shorter read and write cycles.
 Low density, low capacity, high cost, high speed, high
power consumption.

14
 Dynamic RAM
 DRAM stores the binary information in the form of electric
charges on capacitors.
 The capacitors are provided inside the chip by MOS
transistors.
 The capacitors tends to discharge with time and must be
periodically recharged by refreshing the dynamic memory.

15
 Dynamic RAM
 DRAM offers reduced power consumption and larger
storage capacity in a single memory chip.
 High density, high capacity, low cost, low speed, low power
consumption.

16
 ROM
 Non-volatile Data
 Method of Data Writing
 Mask ROM
 Data written during chip fabrication

 PROM
 Fuse ROM: Non-rewritable

 EPROM: Erase data by UV rays

 EEPROM: Erase and write through electrical means

 Speed 2-3 times slower than RAM

 Upper limit on write operations

 Flash Memory – High density, Low Cost

 Types of ROMs
 The required paths in a ROM may be programmed in four
different ways.
1. Mask programming: fabrication process
2. Read-only memory or PROM: blown fuse /fuse intact
3. Erasable PROM or EPROM: placed under a special
ultraviolet light for a given period of time will erase the
pattern in ROM.
4. Electrically-erasable PROM(EEPROM): erased with an
electrical signal instead of ultraviolet light.

18
2 to 4 Decoder

19
2 to 4 Decoder

20
 Programming the ROM
In Table 7-3, 0  no connection
1  connection
Address 3 = 10110010 is permanent storage using fuse link

1 0 1 1 0 0 1 0

X : means connection

21
 Example
 Design a combinational circuit using a ROM. The circuit
accepts a 3-bit number and generates an output binary
number equal to the square of the input number.
Derive truth table first

22
Example

23
 Combinational PLDs
 A combinational PLD is an integrated circuit with
programmable gates divided into an AND array and an OR
array to provide an AND-OR sum of product implementation.
 PROM: fixed AND array constructed as a decoder and
programmable OR array.
 PAL: programmable AND array and fixed OR array.
 PLA: both the AND and OR arrays can be programmed.

24
Combinational PLDs

25
 7-6. Programmable Logic Array
 Fig.7-14, the decoder in PROM is replaced by an array of
AND gates that can be programmed to generate any
product term of the input variables.
 The product terms are then connected to OR gates to
provide the sum of products for the required Boolean
functions.
 The output is inverted when the XOR input is connected to
1 (since x⊕1 = x’). The output doesn’t change and connect
to 0 (since x⊕0 = x).

26
PLA
F1 = AB’+AC+A’BC’
F2 = (AC+BC)’

27
 Example 7-2
Implement the following two Boolean functions with a PLA:
F1(A, B, C) = ∑(0, 1, 2, 4)
F2(A, B, C) = ∑(0, 5, 6, 7)

The two functions are simplified in the maps of Fig.7-15

1 elements

0 elements
28
 PLA table by simplifying the function
 Both the true and complement
of the functions are simplified in
sum of products.
 We can find the same terms
from the group terms of the
functions of F1, F1’,F2 and F2’
which will make the minimum
terms.

F1 = (AB + AC + BC)’
F2 = AB + AC + A’B’C’

29
PLA implementation

AB

AC

BC

A’B’C’

30
 7-7. Programmable Array Logic
 The PAL is a programmable logic device with a fixed OR array and a
programmable AND array.

31
 PAL
 When designing with a PAL, the Boolean functions
must be simplified to fit into each section.
 Unlike the PLA, a product term cannot be shared
among two or more OR gates. Therefore, each
function can be simplified by itself without regard
to common product terms.
 The output terminals are sometimes driven by
three-state buffers or inverters.

32
 Example
w(A, B, C, D) = ∑(2, 12, 13)
x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = ∑(1, 2, 8, 12, 13)

Simplifying the four functions as following Boolean functions:

w = ABC’ + A’B’CD’
x = A + BCD
w = A’B + CD + B’D’
w = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D

33
 PAL Table
 z has four product terms, and we can replace by w with two
product terms, this will reduce the number of terms for z
from four to three.

34
PAL implementation

35
Fuse map for example

36
 Gate Array
 The basic component used in VLSI design is the
gate array.
 A gate array consists of a pattern of gates
fabricated in an area of silicon that is repeated
thousands of times until the entire chip is covered
with the gates.
 Arrays of one thousand to hundred thousand gates
are fabricated within a single IC chip depending on
the technology used.

37
 Array logic
 A typical programmable logic device may have hundreds to
millions of gates interconnected through hundreds to
thousands of internal paths.
 In order to show the internal logic diagram in a concise
form, it is necessary to employ a special gate symbology
applicable to array logic.

38
 FPGA
 FPGA is a VLSI circuit that can be programmed in the user’s
location.
 A typical FPGA logic block consists of look-up tables,
multiplexers, gates, and flip-flops.
 Look-up table is a truth table stored in a SRAM and
provides the combinational circuit functions for the logic
block.

39