NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH

(Established by Ministry of Human Resources Development, Govt. Of India)

Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

APPARATUS

Following apparatus is required to perform the practical of 8085 microprocessor:

1. 8085 Microprocessor Kit

2. Power Supply
3. Instruction Manual
4. Opcode Table

Description of 8085 Microprocessor Kit

The Intel 8085 microprocessor is an NMOS 8-bit device. It has a 16-bit address bus and an 8-bit data
bus. The total addressable memory size of 8085 microprocessor is 64 KB. It has a set of registers
which contribute to the effective and efficient working of the microprocessor.

To view the overall working of the 8085 microprocessor, a kit has been designed so that the
programming on this microprocessor can be best understood by the students.

The kit consists of the following components:

 A 6-byte display screen which is further divided into two parts, one containing 4-byte
displaying the address and the remaining 2-bytes which are used to display the data.
 A keypad which is used to operate the kit.
 A 40-pin 8085 microprocessor.
 A 20-pin address latch used to manage the address transfer from the AD bus.
 A memory unit which consists of three 28-pin IC’s which are used to provide memory
to the processor.
 A 24-pin timer controller which is used to control the clock frequency.
 A 40-pin I/O Lines which are used to provide input to the microprocessor and to store
the output from the microprocessor.
 A 40-pin KB/Display controller used to control the display.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Steps to Execute the Program on 8085 Microprocessor Kit

Follow the steps given below in order to execute the program on 8085 Microprocessor Kit:
1. Enter Program
2. Enter Data
3. Execute Program
4. Check Result
1. Enter Program
a. Press RESET
b. Press EXAMINE MEMORY (EXMEM)
c. Enter starting address of the program
d. Press NEXT
e. Start entering the opcodes
f. Press NEXT
2. Enter Data
a. Press RESET
b. Press EXAMINE MEMORY (EXMEM)
c. Enter the address of operand
d. Press NEXT
e. Enter data
f. Press FILL
3. Execute Program
a. Press RESET
b. Press GO
c. Enter starting address of the program
d. Press FILL
4. Check Result
a. Press RESET
b. Press EXAMINE MEMORY (EXMEM)
c. Enter address of result
d. Press NEXT

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Microprocessor:
 A microprocessor is a clock-driven semiconductor device consisting of electronic logic
circuits manufactured by using either a large-scale integration (LSI) or very-large-scale
integration (VLSI) technique.
 The microprocessor is capable of performing various computing functions and making
decisions to change the sequence of program execution.
 In large computers, a CPU performs these computing functions. The Microprocessor
resembles a CPU exactly.
 The microprocessor is in many ways similar to the CPU, but includes all the logic circuitry
including the control unit, on one chip.
 The microprocessor can be divided into three segments for the sake of clarity. – They are:
arithmetic/logic unit (ALU), register array, and control unit.
 A comparison between a microprocessor, and a computer is shown below:

 Arithmetic/Logic Unit: This is the area of the microprocessor where various computing
functions are performed on data. The ALU unit performs such arithmetic operations as
addition and subtraction, and such logic operations as AND, OR, and exclusive OR.
 Register Array: This area of the microprocessor consists of various registers identified by
letters such as B, C, D, E, H, and L. These registers are primarily used to store data
temporarily during the execution of a program and are accessible to the user through
instructions.
 Control Unit: The control unit provides the necessary timing and control signals to all the
operations in the microcomputer. It controls the flow of data between the microprocessor and
memory and peripherals.
 Memory: Memory stores such binary information as instructions and data, and provides that
information to the microprocessor whenever necessary. To execute programs, the
microprocessor reads instructions and data from memory and performs the computing
operations in its ALU section. Results are either transferred to the output section for display or
stored in memory for later use. Read-Only memory (ROM) and Read/Write memory (R/WM),
popularly known as Random- Access memory (RAM).

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

1. The ROM is used to store programs that do not need alterations. The monitor program of
a single-board microcomputer is generally stored in the ROM. This program interprets the
information entered through a keyboard and provides equivalent binary digits to the
microprocessor. Programs stored in the ROM can only be read; they cannot be altered.
2. The Read/Write memory (RIWM) is also known as user memory It is used to store user
programs and data. In single-board microcomputers, the monitor program monitors the Hex
keys and stores those instructions and data in the R/W memory. The information stored in
this memory can be easily read and altered.

 I/O (Input/ Output): It communicates with the outside world. I/O includes two types of
devices: input and output; these I/O devices are also known as peripherals.
 System Bus: The system bus is a communication path between the microprocessor and
peripherals: it is nothing but a group of wires to carry bits.

Microprocessor is a multi-use device which finds applications in almost all the fields. Here is
some sample applications given in variety of fields.

Electronics:

 Digital clocks & Watches

 Mobile phones
 Measuring Meters

Mechanical:

 Automobiles
 Lathes
 All remote machines

Electrical:

 Motors
 Lighting controls
 Power stations

Medical:

 Patient monitoring
 Most of the Medical equipments
 Data loggers

Computer:
 All computer accessories

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
 Laptops & Modems
 Scanners & Printers

Domestic:
 Microwave Ovens
 Television/CD/DVD players
 Washing Machines
ARCHITECHTURE or FUNCTIONAL BLOCK DIAGRAM OF 8085

The functional block diagram or architecture of 8085 Microprocessor is very important as it gives
the complete details about a Microprocessor. Fig. shows the Block diagram of a Microprocessor.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

8085 Bus Structure:

Address Bus:

 The address bus is a group of 16 lines generally identified as A0 to A15.

 The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral
devices.
 The MPU uses the address bus to perform the first function: identifying a peripheral or a
memory location.

Data Bus:

 The data bus is a group of eight lines used for data flow.
 These lines are bi-directional - data flow in both directions between the MPU and memory
and peripheral devices.
 The MPU uses the data bus to perform the second function: transferring binary information.
 The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 =
256 numbers).
 The largest number that can appear on the data bus is 11111111.

Control Bus:

 The control bus carries synchronization signals and providing timing signals.
 The MPU generates specific control signals for every operation it performs. These signals are
used to identify a device type with which the MPU wants to communicate.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Registers of 8085:

 The 8085 have six general-purpose registers to store 8-bit data during program execution.
 These registers are identified as B, C, D, E, H, and L.
 They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.

Accumulator (A):

 The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
 This register is used to store 8-bit data and to perform arithmetic and logical operations.
 The result of an operation is stored in the accumulator.

Flags:

 The ALU includes five flip-flops that are set or reset according to the result of an operation.
 The microprocessor uses the flags for testing the data conditions.
 They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The
most commonly used flags are Sign, Zero, and Carry.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

The bit position for the flags in flag register is,

1.Sign Flag (S):

After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag
is set. Otherwise it is reset.

2.Zero Flag (z):

If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is
reset.

3.Auxiliary Carry Flag (AC):

If D3 generates any carry when doing any arithmetic and logical operation, this flag is set.
Otherwise it is reset.

4.Parity Flag (P):

If the result of arithmetic and logical operation contains even number of 1's then this flag
will be set and if it is odd number of 1's it will be reset.

5.Carry Flag (CY):

If any arithmetic and logical operation result any carry then carry flag is set otherwise it is
reset.

Arithmetic and Logic Unit (ALU):

 It is used to perform the arithmetic operations like addition, subtraction, multiplication,

division, increment and decrement and logical operations like AND, OR and EX-OR.

 It receives the data from accumulator and registers.

 According to the result it set or reset the flags.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Program Counter (PC):

 This 16-bit register sequencing the execution of instructions.

 It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-
bit register.

 The function of the program counter is to point to the memory address of the next
instruction to be executed.

 When an opcode is being fetched, the program counter is incremented by one to point
to the next memory location.

Stack Pointer (Sp):

 The stack pointer is also a 16-bit register used as a memory pointer.

 It points to a memory location in R/W memory, called the stack.

 The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).

Temporary Register: It is used to hold the data during the arithmetic and logical operations.

Instruction Register: When an instruction is fetched from the memory, it is loaded in the
instruction register.

Instruction Decoder: It gets the instruction from the instruction register and decodes the
instruction. It identifies the instruction to be performed.

Serial I/O Control: It has two control signals named SID and SOD for serial data transmission.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Timing and Control unit:

 It has three control signals ALE, RD (Active low) and WR (Active low) and three status
signals IO/M(Active low), S0 and S1.

 ALE is used for provide control signal to synchronize the components of microprocessor and
timing for instruction to perform the operation.

 RD (Active low) and WR (Active low) are used to indicate whether the operation is reading
the data from memory or writing the data into memory respectively.

 IO/M (Active low) is used to indicate whether the operation is belongs to the memory or
peripherals.

If,

Interrupt Control Unit:

 It receives hardware interrupt signals and sends an acknowledgement for receiving the
interrupt signal.
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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

PIN DIAGRAM AND PIN DESCRIPTION OF 8085

 The microprocessor is a clock-driven semiconductor device consisting of electronic logic

circuits manufactured by using either a large-scale integration (LSI) or very-large-scale
integration (VLSI) technique.

 The microprocessor is capable of performing various computing functions and making

decisions to change the sequence of program execution.

 In large computers, a CPU implemented on one or more circuit boards performs these
computing functions.

 The microprocessor is in many ways similar to the CPU, but includes the logic circuitry,
including the control unit, on one chip.

 The microprocessor can be divided into three segments for the sake clarity, arithmetic/logic
unit (ALU), register array, and control unit.

 8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows

1. Power supply and clock signals

2. Address bus

3. Data bus

4. Control and status signals

5. Interrupts and externally initiated signals

6. Serial I/O ports

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

1. Power supply and Clock frequency signals:

 Vcc + 5 volt power supply

 Vss Ground
 X1, X2 : Crystal or R/C network or LC network connections to set the frequency of
internal clock generator.
 The frequency is internally divided by two. Since the basic operating timing frequency is 3
MHz, a 6 MHz crystal is connected externally.
 CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced
with the microprocessor.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Fig (a) - Pin Diagram of 8085 & Fig (b) - logical schematic of Pin diagram.

2. Address Bus:
 A8 - A15 (output; 3-state)
 It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address;

3. Multiplexed Address / Data Bus:

 AD0 - AD7 (input/output; 3-state)
 These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus.
 During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order
address A0 - A7.
 In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
 The CPU may read or write out data through these lines.

4. Control and Status signals:

 ALE (output) - Address Latch Enable.
 This signal helps to capture the lower order address presented on the multiplexed address
/ data bus.
 RD (output 3-state, active low) - Read memory or IO device.
 This indicates that the selected memory location or I/O device is to be read and that the data
bus is ready for accepting data from the memory or I/O device.
 WR (output 3-state, active low) - Write memory or IO device.
 This indicates that the data on the data bus is to be written into the selected memory location
or I/O device.
 IO/M (output) - Select memory or an IO device.
 This status signal indicates that the read / write operation relates to whether the memory or
I/O device.
 It goes high to indicate an I/O operation.
 It goes low for memory operations.

5. Status Signals:
 It is used to know the type of current operation of the microprocessor.

6. Interrupts and Externally initiated operations:

 They are the signals initiated by an external device to request the microprocessor to do a
particular task or work.
 There are five hardware interrupts called,

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(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

 On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low
INTA (Interrupt Acknowledge) signal.

Reset In (input, active low)

 This signal is used to reset the microprocessor.

 The program counter inside the microprocessor is set to zero.
 The buses are tri-stated.

Reset Out (Output)

 It indicates CPU is being reset.

 Used to reset all the connected devices when the microprocessor is reset.

7. Direct Memory Access (DMA):

Tri state devices:

 3 output states are high & low states and additionally a high impedance state.
 When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1,
otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a
high impedance state.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.

 For both high and low states, the output Q draws a current from the input of the OR gate.
 When E is low, Q enters a high impedance state; high impedance means it is electrically
isolated from the OR gate's input, though it is physically connected. Therefore, it does not
draw any current from the OR gate's input.
 When 2 or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except the one
that is communicating at a given instant.
 The CPU controls the data transfer operation between memory and I/O device. Direct
Memory Access operation is used for large volume data transfer between memory and an I/O
device directly.
 The CPU is disabled by tri-stating its buses and the transfer is effected directly by external
control circuits.
 HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the
control of the buses. After the HLDA signal the DMA controller starts the direct transfer of
data.

READY (input)

 Memory and I/O devices will have slower response compared to microprocessors.
 Before completing the present job such a slow peripheral may not be able to handle further
data or control signal from CPU.
 The processor sets the READY signal after completing the present job to access the data.
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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
 The microprocessor enters into WAIT state while the READY pin is disabled.

8. Single Bit Serial I/O ports:

 SID (input) - Serial input data line

 SOD (output) - Serial output data line
 These signals are used for serial communication.

TIMING DIAGRAM

Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle:
The time required to execute an instruction is called instruction cycle.

Machine Cycle:
The time required to access the memory or input/output devices is called machine cycle.

T-State:

 The machine cycle and instruction cycle takes multiple clock periods.
 A portion of an operation carried out in one system clock period is called as T-state.

MACHINE CYCLES OF 8085:

The 8085 microprocessor has 5 (seven) basic machine cycles. They are

1. Opcode fetch cycle (4T)

2. Memory read cycle (3 T)

3. Memory write cycle (3 T)

4. I/O read cycle (3 T)

5. I/O write cycle (3 T)

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

 Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when
the 8085 processor executes an instruction, it will execute some of the machine cycles in
a specific order.

 The processor takes a definite time to execute the machine cycles. The time taken by the
processor to execute a machine cycle is expressed in T-states.

 One T-state is equal to the time period of the internal clock signal of the processor.

 The T-state starts at the falling edge of a clock.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
Opcode fetch machine cycle of 8085 :

 Each instruction of the processor has one byte opcode.

 The opcodes are stored in memory. So, the processor executes the opcode fetch
machine cycle to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is 4T.
 In this time, the first, 3 T-states are used for fetching the opcode from memory and
the remaining T-states are used for internal operations by the processor.

Fig - Timing Diagram for Opcode Fetch Machine Cycle

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
Memory Read Machine Cycle of 8085:

 The memory read machine cycle is executed by the processor to read a data byte
from memory.
 The processor takes 3T states to execute this cycle.
 The instructions which have more than one byte word size will use the machine cycle
after the opcode fetch machine cycle.

Fig - Timing Diagram for Memory Read Machine Cycle

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
Memory Write Machine Cycle of 8085:

 The memory write machine cycle is executed by the processor to write a data byte in
a memory location.
 The processor takes, 3T states to execute this machine cycle.

Fig - Timing Diagram for Memory Write Machine Cycle

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
I/O Read Cycle of 8085:

 The I/O Read cycle is executed by the processor to read a data byte from I/O port or
from the peripheral, which is I/O, mapped in the system.
 The processor takes 3T states to execute this machine cycle.
 The IN instruction uses this machine cycle during the execution.

Fig - Timing Diagram for I/O Read Machine Cycle

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
I/O Write Cycle of 8085:

 The I/O write machine cycle is executed by the processor to write a data byte in the
I/O port or to a peripheral, which is I/O, mapped in the system.
 The processor takes, 3T states to execute this machine cycle.

Fig - Timing Diagram for I/O Write Machine Cycle

 The 8085 instructions consist of one to five machine cycles.

 Actually the execution of an instruction is the execution of the machine cycles of that
instruction in the predefined order.
 The timing diagram of an instruction ate obtained by drawing the timing diagrams
of the machine cycles of that instruction, one by one in the order of execution.

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(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Timing diagram for STA 526AH.

 STA means Store Accumulator -The contents of the accumulator is stored in the
specified address(526A).
 The opcode of the STA instruction is said to be 32H. It is fetched from the memory
41FFH(see fig). - OF machine cycle
 Then the lower order memory address is read(6A). - Memory Read Machine Cycle
 Read the higher order memory address (52).- Memory Read Machine Cycle
 The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle
 Assume the memory address for the instruction and let the content of accumulator is
C7H. So, C7H from accumulator is now stored in 526A.

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(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
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[email protected]
QUICK NOTES

Timing diagram for IN C0H.

 Fetching the Opcode DBH from the memory 4125H.

 Read the port address C0H from 4126H.
 Read the content of port C0H and send it to the accumulator.
 Let the content of port is 5EH.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

Timing diagram for INR M

 Fetching the Opcode 34H from the memory 4105H. (OF cycle)
 Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data)
 Let the content of that memory is 12H.
 Increment the memory content from 12H to 13H. (MW machine cycle)

Timing diagram for MVI B, 43H.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

 Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
 Read (move) the data 43H from memory 2001H. (memory read)

INTERRUPT STRUCTURE

 Interrupt is signals send by an external device to the processor, to request the processor
to perform a particular task or work.
 Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine cycle.
 If there is any interrupt it accept the interrupt and send the INTA (active low) signal to
the peripheral.
 The vectored address of particular interrupt is stored in program counter.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
 The processor executes an interrupt service routine (ISR) addressed in program
counter.
 It returned to main program by RET instruction. Types of Interrupts:

It supports two types of interrupts.

 Hardware
 Software

Software interrupts:
 The software interrupts are program instructions. These instructions are inserted at desired
locations in a program.
 The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these
interrupts can be calculated as follows.
 Interrupt number * 8 = vector address
 For RST 5,5 * 8 = 40 = 28H
 Vector address for interrupt RST 5 is 0028H

The Table shows the vector addresses of all interrupts.

Hardware interrupts:
 An external device initiates the hardware interrupts and placing an appropriate signal
at the interrupt pin of the processor.

 If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

TRAP:
 This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt
enable.

 TRAP bas the highest priority and vectored interrupt.

 TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and
remain high until it is acknowledged.

 In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.

 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives
HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is
recognized).

 There are two ways to clear TRAP interrupt.

1.By resetting microprocessor (External signal)

2.By giving a high TRAP ACKNOWLEDGE (Internal signal)
RST 7.5:

 The RST 7.5 interrupt is a maskable interrupt.

 It has the second highest priority.

 It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.

 Maskable interrupt. It is disabled by, 1.DI instruction

2.System or processor reset.
3.After reorganization of interrupt.

 Enabled by EI instruction. RST 6.5 and 5.5:

 The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high
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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
until it recognized.

 Maskable interrupt. It is disabled by, 1.DI, SIM instruction

2.System or processor reset. 3.After reorganization of interrupt.

 Enabled by EI instruction.

 The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR:

 INTR is a maskable interrupt. It is disabled by,

1.DI, SIM instruction 2.System or processor reset.

3.After reorganization of interrupt.

 Enabled by EI instruction.
 Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the
address of ISR.

 It has lowest priority.

 It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain
high state until it recognized.
 The following sequence of events occurs when INTR signal goes high.

1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active
low interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction OPCODE
on the data bus. In the case of multibyte instruction, additional interrupt acknowledge
machine cycles are generated by the 8085 to transfer the additional bytes into the
microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on stack
and execute received instruction.

SIM and RIM for interrupts:

 The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using
SIM instruction.
 The status of these interrupts can be read by executing RIM instruction.
 The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be
performed by moving an 8-bit data to accumulator and then executing SIM instruction.
 The format of the 8-bit data is shown below.

95
 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

 The status of pending interrupts can be read from accumulator after executing RIM
instruction.
 When RIM instruction is executed an 8-bit data is loaded in accumulator, which can be
interpreted as shown in fig.

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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES
8085 INSTRUCTION SET CLASSIFICATION:

Data Transfer
mov mvi ldax lhld lda stax shld sta
lxi sphl xthl xchg out in push pop

Arithmetic
add adc adi aci sub sbb sui sbi
dad daa inr enx dcr dcx

Logical
stc ana ani xra xri ora ori cmp
cpi rlc rrc ral rar cma cmc

Branching
jmp jnz jz jnc jc jpo jpe jp
jm pchl rst

call cnz cz cnc cc cpo cpe cp

cm

ret rnz rz rnc rc rpo rpe rp

rm

Control
nop hlt di ei rim sim

ADDRESSING MODES OF 8085

 Every instruction of a program has to operate on a data.

 The method of specifying the data to be operated by the instruction is called Addressing.
 The 8085 has the following 5 different types of addressing.

1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
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 NATIONAL INSTITUTE OF TECHNOLOGY, ARUNACHAL PRADESH
(Established by Ministry of Human Resources Development, Govt. Of India)
Yupia, District Papum Pare, Arunachal Pradesh – 791112
Fax: 0360 – 2284927, E-mail:
[email protected]
QUICK NOTES

1. Immediate Addressing:

 In immediate addressing mode, the data is specified in the instruction itself. The data
will be a part of the program instruction.
 EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP,
2700H.

2. Direct Addressing:

 In direct addressing mode, the address of the data is specified in the instruction. The
data will be in memory. In this addressing mode, the program instructions and data can
be stored in different memory.
 EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator;
SHLD 3000H

3. Register Addressing:

 In register addressing mode, the instruction specifies the name of the register in which
the data is available.
 EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.

4. Register Indirect Addressing:

 In register indirect addressing mode, the instruction specifies the name of the register in
which the address of the data is available. Here the data will be in memory and the
address will be in the register pair.
 EX. MOV A, M - The memory data addressed by H L pair is moved to A register.
LDAX B.

5. Implied Addressing:

 In implied addressing mode, the instruction itself specifies the data to be operated.
 EX. CMA - Complement the content of accumulator; RAL

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