UNIT 4

Input/Output Organisation: Peripheral devices, I/O interface, Asynchronous Data

transfer, Modes of data transfer, Direct Memory Access, I/O processor.

In addition to the CPU and a set of memory modules, another key element of a computer system
is a set of I/O module. An I/O module is not just mechanical connectors that wire a device into
the system bus but it contains some intelligence. That is contains a logic for performing a
communication function between the peripheral and the bus. Owing to the following reason we
need an I/O module:
 There are wide varieties of peripherals with variety of operation methods. It is
impractical to incorporate the necessary logic within the CPU to control a range of
devices.
 The data transfer rate of peripherals is often much slower than that of the memory or
CPU.
 Peripherals often use different data formats and word lengths than the computer system
to which they are attached .
An I/O module has two major functions –
1) Interface to the CPU and memory via the system bus or central switch.
2) Interface to one or more peripheral devices by tailored data links.

Input/Output Subsystem

The input devices such as keyboard, mouse, trackball, scanner, magnetic tape, floppy disk
drive and hard disk drive are used for feeding data to the CPU and the output devices such as
monitor, printer, plotters are used to show the data processed by the CPU to the outside world.
These input and output devices are called peripheral devices.
The I/O subsystem of a computer provides an efficient mode of communication between the
central system and the outside environment. It handles all the input- output operations of the
computer system.

Peripheral Devices

Input or output devices that are connected to computer are called peripheral devices. These
devices are designed to read information into or out of the memory unit upon command from
the CPU and are considered to be the part of computer system. These devices are also called
peripherals.
For example: Keyboards, display units and printers are common peripheral devices.

 In addition to the processor and a set of memory modules, the third key element of
acomputer system is a set of input-output subsystem referred to as I/O, provides an
efficient mode of communication between the central system and the outside
environment.
 Programs and data must be entered into computer memory for processing and results
obtained from computations must be recorded or displayed for the user.
 Devices that are under the direct control of the computer are said to be connected online.
These devices are designed to read information into or out of the memory unit upon
command from CPU.
 Input or output devices attached to the computer are also called peripherals.
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  Among the most common peripherals are keyboards, display units, and printers.
 Perhaps those provide auxiliary storage for the systems are magnetic disks and tapes.
 Peripherals are electromechanical and electromagnetic devices of some complexity.
 We can broadly classify peripheral devices into three categories:
 Human Readable: Communicating with the computer users, e.g. video display
terminal, printers etc.
 Machine Readable: Communicating with equipments, e.g. magnetic disk, magnetic
tape, sensor, actuators used in robotics etc.
 Communication: Communicating with remote devices means exchanging data with
that, e.g. modem, NIC (network interface Card) etc

Block diagram of Peripheral device

 Control signals determine the function that the device will perform such as send data to
I/O module, accept data from I/O module.
 Status signals indicate the state of the device i.e. device is ready or not.
 Data bits are actual data transformation.
 Control logic associated with the device controls the device's operation in response to
direction from the I/O module.
 The transducer converts data from electrical to other forms of energy during output and
from other forms to electrical during input.
 Buffer is associated with the transducer to temporarily hold data being transferred
between the I/O module and external devices i.e. peripheral environment.
Input Device
 Keyboard
 Optical input devices
o Card Reader
o Paper Tape Reader
o Optical Character Recognition (OCR)
o Optical Bar code reader (OBR)
o Digitizer
o Optical Mark Reader
 Magnetic Input Devices
o Magnetic Stripe Reader
o Magnetic Ink Character Recognition (MICR)

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  Screen Input Devices
o Touch Screen
o Light Pen
o Mouse
 Analog Input Devices

Output Device
 Card Puncher, Paper Tape Puncher
 Monitor (CRT, LCD, LED)
 Printer (Impact, Ink Jet, Laser, Dot Matrix)
 Plotter
 Analog
 Voice

Input devices :
Data and instructions are entered into a computer through input devices. A number of
input devices that do not require typing for inputting information have been developed. These
are :
Mouse, Joystick, Trackball, Light pen, Graphic tablet, Touch screen etc.
These devices are also called pointing devices. Voice input systems have also been developed.
A microphone is used as an input in such devices. In applications where computers with vision
are required, namely robots, computer based security systems, etc. computers use optical
systems and semiconductor devices sensitive to light. Such input devices produce digital signals
corresponding to image, pictures etc.

1. Keyboard:
Programs and data are enetered through a keyboard that is connected to a microcomputer or the
terminal of a mini or mainframe computer. A keyboaed is similar to the keyboard of a
typewriter. It contains alphabets, digits, special characters, functions keys. When a key is
pressed, an electronic signal is produced which is detected by an electronic circuit called
Keyboard encoder.

2. Mouse :

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A mouse is also a pointing device. It is held in one hand and moved across a flat surface. Its
movement and the direction of the movement is detected by two rotating wheels on the
underside of the mouse. The wheels have their axes at right angles. Each wheel is connected to
a shaft encoder which emits electrical pulses for every incremental movement of the wheel. The
pulses transmitted by the mouse determine the distance moved. When a user moves the mouse
across a flat surface, the cursor on the CRT screen also moves in the direction of the mouse's
movement. By moving the mouse, user can point to a menu on the screen. By pressing the
button on the mouse, the user communicates his choice to the computer.

The mouse is also used to draw sketches, diagrams, etc. on the CRT screen, The mouse is also
used to edit text. For editing a text on the screen the cursor is quickly moved to the desired point
of the screen by moving the mouse. A mouse has one or more buttons on the surface for
clicking and thus controlling the action.

Output Devices :
Output devices are used to transfer the information stored in the computer memory or
the result of any processing done by the CPU to the outside world. There are many output
devices manufactured for this purpose, but the most commonly used devices are the video
monitors and printers. Printers provide a permanent record on paper.

1. Video Display Unit (VDU or Monitor) :

A Visual Display Unit (VDU) is a device that displays text and graphics on a screen. It is
commonly used in computers to display the output of the computer's processing unit, allowing
the user to interact with the computer and see the results of their actions. The VDU consists of a
screen, which is usually a flat panel display such as a LCD or LED, and a circuit board that
drives the screen and processes the input and output signals. The screen is typically connected
to the circuit board through a cable, and the circuit board is usually housed in a separate
enclosure or integrated into the monitor itself. Monitors are available in 9", 12", 14", 15", 17",
19", and even in 21" size.
Working of a Monitor :
The main component inside a monitor is a picture tube or CRT (cathode ray tube). CRT
is an evacuated glass tube, roughly conical in shape. It has a phosphor coating on the inside of
the large screen end and an electron gun at the narrow end. (Fig 1)
The electron gun fires a narrow beam of electrons at the screen and when this beam
strikes the phosphor coating, light is emitted. Raster scan technique is adopted for generating
images on the CRT display.

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In this technique, horizontal and vertical deflection signals are generated to move the beam in
forward and backward directions across the screen like a raster.

The retrace portion of raster scan pattern is supperessed (blanked) by reducing the intensity of
the electron beam during the time of retrace. The complete CRT screen can be considered to be
made of thousands of dots, known as pixels (picture elements). Any pixel can be illuminated by
the electron beam when it hits the pixel during the raster scan process or it can be blanked by
reducing the intensity of the electron beam.
On a standard monochrome monitor, the electron beam scans the screen 50 times per
second. The phosphor has 'persistence', which means it keeps radiating light even after the
electron beam has moved away. The scan rate and persistence of vision together enable the user
to see a steady, flicker-free image.
A monochrome monitor needs three signals to produce a display :
a) Horizontal synchronization (HSYNC) to tell it when ascan line is about to begin.
b) Vertical synchronization (VSYNC) to tell it when the display is going to start at the top of the
screen.
c) VIDEO which switches the electron beam ON and OFF.
In addition a fourth signal (intensity) selects whether the displayed dots are dim or bright. The
display adapter card generates these signals.

2. Printers :
Printers are the most popular output devices. They provide information in a permanent readable
form. They produce printed outputs of results, programs and data. A character printer prints one
character of the text at a time. They are low – speed printers. Their printing speed lies in the
range of 30-600 characters per second. The character printers can be classified as :
a) Impact printers
b) Non impact printers
Imapct printers use an electro – mechanical mechanism that causes hammers or pins to strike
against a ribbon and paper to print the text. Two types of impact character printers are available:
dot matrix printers and letter quality printers.
Non imapct printers do not use any electro – mechanical printing head to strike against ribbon
and paper. They use thermal, chemical, electrostatic, laser beam or inkjet technology for
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printing the text. Usually a non – impact type printer is faster than an impact type. The
disadvantage of non – impact type printers is that they produce only a single copy of the text
whereas impact printers produce multiple copies of the text.

I/O modules

 I/O modules interface to the system bus or central switch (CPU and Memory), interfaces
and controls to one or more peripheral devices. I/O operations are accomplished through
a wide assortment of external devices that provide a means of exchanging data between
external environment and computer by a link to an I/O module. The link is used to
exchange control status and data between I/O module and the external devices.

Fig : Model of I/O Module

 Peripherals are not directly connected to the system bus instead an I/O module is used which
contains logic for performing a communication between the peripherals and the system bus.
The reasons due to which peripherals do not directly connected to the system bus are:
 There are a wide variety of peripherals with various methods of operation. It would be
impractical to incorporate the necessary logic within the processor to control a range of
devices.
 The data transfer rate of peripherals is often much slower than that of the memory or
processor. Thus, it is impractical to use high speed system bus to communicate directly with
a peripheral and vice versa.

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  Peripherals often use different data format and word length than the computer to which they
are connected.
 Thus an I/O module is required which performs two major functions.
 Interface to the processor and memory via the system bus.
 Interface to one or more peripherals by tailored data links.

I/O Module Functions

 The I/O module is a special hardware component interface between the CPU and
peripherals to supervise and synchronize all I/O transformation The detailed functions of
I/O modules are:

Control & Timing: I/O module includes control and timing to coordinate the flow of traffic
between internal resources and external devices. The control of the transfer of data from
external devices to processor consists following steps:
o The processor interrogates the I/O module to check status of the attached device.
o The I/O module returns the device status.
o If the device is operational and ready to transmit, the processor requests the transfer of
data by means of a command to I/O module.
o The I/O module obtains the unit of data from the external device.
o The data are transferred from the I/O module to the processor.
Processor Communication: I/O module communicates with the processor which involves:
o Command decoding: I/O module accepts commands from the processor.
o Data: Data are exchanged between the processor and I/O module over the bus.
o Status reporting: Peripherals are too slow and it is important to know the status of I/O
module.
o Address recognition: I/O module must recognize one unique address for each
peripheral it controls.
Device Communication: It involves commands, status information and data.
Data Buffering: I/O module must be able to operate at both device and memory speeds. If the
I/O device operates at a rate higher than the memory access rate, then the I/O module performs
data buffering. If I/O devices rate slower than memory, it buffers data so as not to tie up the
memory in slower transfer operation.
Error Detection: I/O module is responsible for error detection such as mechanical and
electrical malfunction reported by device e.g. paper jam, bad ink track & unintentional changes
to the bit pattern and transmission error.

I/O Module Structure :

 The I/O bus from the processor is attached to all peripheral interfaces
 To communicate with the particular devices, the processor places a device address on
the address bus.
 Each interface contains an address decoder that monitors the address line. When the
interface detects the particular device address, it activates the path between the data line
and devices that it controls.
 At the same time that the address is made available in the address line, the processor
provides a function code in the control way includes control command, output data and
input data.

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 Fig: Block diagram I/O Module
I/O Module Decisions

 Hide or reveal device properties to CPU

 Support multiple or single device
 Control device functions or leave for CPU
 Also O/S decisions
o e.g. Unix treats everything it can as a file

Interfaces
Interface is a shared boundary btween two separate components of the computer system which
can be used to attach two or more components to the system for communication purposes.
There are two types of interface:

 CPU Inteface
 I/O Interface

Input-Output interface

 Input-Output interface provides a method for transferring information between internal

storage (such as memory and CPU registers) and external I/O devices.
 Peripherals connected to a computer need special communication links for interfacing
them with the central processing unit.
 To resolve these differences, computer systems include special hardware components
(Interfaces) between the CPU and peripherals to supervise and synchronize all input and
output interfaces.
 The communication link resolves the following differences between the computer and
peripheral devices.

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 Differences Peripherals CPU or Memory
Devices and Signals Electromechanical Devices Electronic Device
Data Transfer Rate Usually slower Usually faster than peripherals
Unit of Information Byte Word
Operating Modes Autonomous, Asynchronous Synchronous

Let's understand the I/O Interface in details,

Input-Output Interface

Peripherals connected to a computer need special communication links for interfacing with
CPU. In computer system, there are special hardware components between the CPU and
peripherals to control or manage the input-output transfers. These components are called
input-output interface units because they provide communication links between processor bus
and peripherals. They provide a method for transferring information between internal system
and input-output devices.
The I/O interface supports a method by which data is transferred between internal storage and
external I/O devices. All the peripherals connected to a computer require special
communication connections for interfacing them with the CPU.
I/O Bus and Interface Modules
The I/O bus is the route used for peripheral devices to interact with the computer processor.
A typical connection of the I/O bus to I/O devices is shown in the figure.

The I/O bus includes data lines, address lines, and control lines. In any general- purpose
computer, the magnetic disk, printer, and keyboard, and display terminal are commonly
employed. Each peripheral unit has an interface unit associated with it. Each interface
decodes the control and address received from the I/O bus.
It can describe the address and control received from the peripheral and supports signals for

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 the peripheral controller. It also conducts the transfer of information between peripheral and
processor and also integrates the data flow.
The I/O bus is linked to all peripheral interfaces from the processor. The processor locates a
device address on the address line to interact with a specific device. Each interface contains
an address decoder attached to the I/O bus that monitors the address lines.
When the address is recognized by the interface, it activates the direction between the bus
lines and the device that it controls. The interface disables the peripherals whose address does
not equivalent to the address in the bus.

Interface performs the following:

o Decodes the device address (device code)

o Decodes the commands (operation)
o Provides signals for the peripheral controller
o Synchronizes the data flow and supervises the transfer rate between peripheral and
CPU or Memory
An interface receives any of the following four commands −

 Control − A command control is given to activate the peripheral and to inform its
next task. This control command depends on the peripheral, and each peripheral
receives its sequence of control commands, depending on its mode of operation.
 Status − A status command can test multiple test conditions in the interface and the
peripheral.
 Data Output − A data output command creates the interface counter to the command
by sending data from the bus to one of its registers.
 Data Input − The data input command is opposite to the data output command. In
data input, the interface gets an element of data from the peripheral and places it in its
buffer register.

Asynchronous Data Transfer

Internal operations in individual unit of digital system are synchronized by means of clock
pulse, means clock pulse is given to all registers within a unit, and all data transfer among
internal registers occur simultaneously during occurrence of clock pulse.Now, suppose any
two units of digital system are designed independently such as CPU and I/O interface.
And if the registers in the interface(I/O interface) share a common clock with CPU registers,
then transfer between the two units is said to be synchronous.But in most cases, the internal
timing in each unit is independent from each other in such a way that each uses its own
private clock for its internal registers.In that case, the two units are said to be asynchronous to
each other, and if data transfer occur between them this data transfer is said to be
Asynchronous Data Transfer.

But, the Asynchronous Data Transfer between two independent units requires that control
signals be transmitted between the communicating units so that the time can be indicated at
which they send data.

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 This asynchronous way of data transfer can be achieved by two methods:

1. One way is by means of strobe pulse which is supplied by one of the units to other
unit.When transfer has to occur.This method is known as “Strobe Control”.
2. Another method commonly used is to accompany each data item being transferred
with a control signal that indicates the presence of data in the bus.The unit receiving
the data item responds with another signal to acknowledge receipt of the data.This
method of data transfer between two independent units is said to be “Handshaking”.

The strobe pulse and handshaking method of asynchronous data transfer are not restricted to
I/O transfer.In fact, they are used extensively on numerous occasion requiring transfer of data
between two independent units.So, here we consider the transmitting unit as source and
receiving unit as destination.

As an example: The CPU, is the source during an output or write transfer and is the
destination unit during input or read transfer.

And thus, the sequence of control during an asynchronous transfer depends on whether the
transfer is initiated by the source or by the destination.

So, while discussing each way of data transfer asynchronously we see the sequence of control
in both terms when it is initiated by source or when it is initiated by destination.In this way,
each way of data transfer, can be further divided into parts, source initiated and destination
initiated.
We can also specify, asynchronous transfer between two independent units by means of a
timing diagram that shows the timing relationship that exists between the control and the data
buses.

Now, we will discuss each method of asynchronous data transfer in detail one by one.

1. Strobe Control:
The Strobe Control method of asynchronous data transfer employs a single control line to
time each transfer .This control line is also known as strobe and it may be achieved either by
source or destination, depending on which initiate transfer.

Source initiated strobe for data transfer:

The block diagram and timing diagram of strobe initiated by source unit is shown in figure
below:

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In block diagram we see that strobe is initiated by source, and as shown in timing diagram, the
source unit first places the data on the data bus.After a brief delay to ensure that the data settle
to a steady value, the source activates a strobe pulse.The information on data bus and strobe
control signal remain in the active state for a sufficient period of time to allow the destination
unit to receive the data.Actually, the destination unit, uses a falling edge of strobe control to
transfer the contents of data bus to one of its internal registers.The source removes the data from
the data bus after it disables its strobe pulse.New valid data will be available only after the
strobe is enabled again.

Destination-initiated strobe for data transfer:

The block diagram and timing diagram of strobe initiated by destination is shown in figure
below:

In block diagram, we see that, the strobe initiated by destination, and as shown in timing
diagram, the destination unit first activates the strobe pulse, informing the source to provide
the data.The source unit responds by placing the requested binary information on the data
bus.The data must be valid and remain in the bus long enough for the destination unit to
accept it.The falling edge of strobe pulse can be used again to trigger a destination
register.The destination unit then disables the strobe.And source removes the data from

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 data bus after a per determine time interval.

Now, actually in computer, in the first case means in strobe initiated by source - the strobe
may be a memory-write control signal from the CPU to a memory unit.The source, CPU,
places the word on the data bus and informs the memory unit, which is the destination, that
this is a write operation.

And in the second case i.e, in the strobe initiated by destination - the strobe may be a
memory read control from the CPU to a memory unit.The destination, the CPU, initiates the
read operation to inform the memory, which is a source unit, to place selected word into the
databus.
2. Handshaking:
The disadvantage of strobe method is that source unit that initiates the transfer has no way
of knowing whether the destination has actually received the data that was placed in the
bus.Similarly, a destination unit that initiates the transfer has no way of knowing whether the
source unit, has actually placed data on the bus. This problem can be solved by
handshaking method. Hand shaking method introduce a second control signal line that
provides a replay to the unit that initiates the transfer.
In it, one control line is in the same direction as the data flow in the bus from the source
to destination.It is used by source unit to inform the destination unit whether there are valid
data in the bus.The other control line is in the other direction from destination to the
source.It is used by the destination unit to inform the source whether it can accept data.And
in it also, sequence of control depends on unit that initiate transfer.Means sequence of control
depends whether transfer is initiated by source and destination.Sequence of control in both of
them are described below:
Source initiated Handshaking:

The source initiated transfer using handshaking lines is shown in figure below:

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 In its block diagram, we se that two handshaking lines are "data valid", which is
generated by the source unit, and "data accepted", generated by the destination unit.

The timing diagram shows the timing relationship of exchange of signals between the
two units.Means as shown in its timing diagram, the source initiates a transfer by placing data
on the bus and enabling its data valid signal.The data accepted signal is then activated by
destination unit after it accepts the data from the bus.The source unit then disable its data
valid signal which invalidates the data on the bus.After this, the destination unit disables its
data accepted signal and the system goes into initial state.The source unit does not send the
next data item until after the destination unit shows its readiness to accept new data by
disabling the data accepted signal.
This sequence of events described in its sequence diagram, which shows the above
sequence in which the system is present, at any given time.

Destination initiated handshaking:

The destination initiated transfer using handshaking lines is shown in figure below:

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 In its block diagram, we see that the two handshaking lines are "data valid", generated by
the source unit, and "ready for data" generated by destination unit.Note that the name of
signal data accepted generated by destination unit has been changed to ready for data to
reflect its new meaning.

In it, transfer is initiated by destination, so source unit does not place data on data bus
until it receives ready for data signal from destination unit. After that, hand shaking process
is some as that of source initiated.
The sequence of event in it are shown in its sequence diagram and timing relationship
between signals is shown in its timing diagram.

Thus, here we can say that, sequence of events in both cases would be identical.If we
consider ready for data signal as the complement of data accept.Means, the only difference
between source and destination initiated transfer is in their choice of initial state.

Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can be handled in generally three types
of modes which are given below:

1. Programmed I/O
2. Interrupt Initiated I/O

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 3. Direct Memory Access

Programmed I/O
Programmed I/O instructions are the result of I/O instructions written in computer program.
Each data item transfer is initiated by the instruction in the program.

Usually the program controls data transfer to and from CPU and peripheral. Transferring data
under programmed I/O requires constant monitoring of the peripherals by the CPU.

 In programmed I/O, each data transfer in initiated by the instructions in the CPU and
hence the CPU is in the continuous monitoring of the interface.
 Input instruction is used to transfer data from I/O device to CPU, store instruction is
used to transfer data from CPU to memory and output instruction is used to transfer
data from CPU to I/O device.
 This technique is generally used in very slow speed computer and is not a efficient
method if the speed of the CPU and I/O is different.

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  I/O device places the data on the I/O bus and enables its data valid signal.
 The interface accepts the data in the data register and sets the F bit of status register and
also enables the data accepted signal.
 Data valid line is disables by I/O device.
 CPU is in a continuous monitoring of the interface in which it checks the F bit of the
status register.
o If it is set i.e. 1, then the CPU reads the data from data register and sets F bit
to zero.
o If it is reset i.e. 0, then the CPU remains monitoring the interface.
 Interface disables the data accepted signal and the system goes to initial state where next
item of data is placed on the data bus.

Characteristics:

 Continuous CPU involvement

 CPU slowed down to I/O speed
 Simple
 Least hardware

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Polling, or polled operation, in computer science, refers to actively sampling the status of an
external device by a client program as a synchronous activity. Polling is most often used in
terms of input/output (I/O), and is also referred to as polled I/O or software driven I/O.

Interrupt Initiated I/O

 Polling takes valuable CPU time

 Open communication only when some data has to be passed -> Interrupt.
 I/O interface, instead of the CPU, monitors the I/O device
 When the interface determines that the I/O device is ready for data transfer, it generates
an Interrupt Request to the CPU
 Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches to the
service routine to process the data transfer, and then returns to the task it was performing

The problem with programmed I/O is that the processor has to wait a long time for the I/O
module of concern to be ready for either reception or transmission of data. The processor, while
waiting, must repeatedly interrogate the status of the I/O module. As a result, the level of the
performance of the entire system is severely degraded. An alternative is for the processor to
issue an I/O command to a module and then go on to do some other useful work. The I/O
module will then interrupt the processor to request service when it is ready to exchange data
with processor. The processor then executes the data transfer, and then resumes its former
processing. The interrupt can be initiated either by software or by hardware.

Interrupt Driven I/O basic operation

 CPU issues read command

 I/O module gets data from peripheral whilst CPU does other work
 I/O module interrupts CPU
 CPU requests data
 I/O module transfers data

Interrupt Processing from CPU viewpoint

 Issue read command

 Do other work
 Check for interrupt at end of each instruction cycle
 If interrupted:-
- Save context (registers)
- Process interrupt
- Fetch data & store

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 Direct Memory Access

 Large blocks of data transferred at a high speed to or from high speed devices, magnetic
drums, disks, tapes, etc.
 DMA controller Interface that provides I/O transfer of data directly to and from the
memory and the I/O device
 CPU initializes the DMA controller by sending a memory address and the number of
words to be transferred
 Actual transfer of data is done directly between the device and memory through DMA
controller -> Freeing CPU for other tasks

The transfer of data between the peripheral and memory without the interaction of CPU and
letting the peripheral device manage the memory bus directly is termed as Direct Memory
Access (DMA).
Removing the CPU from the path and letting the peripheral device manage the memory buses
directly would improve the speed of transfer. This technique is known as DMA.
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The two control signals Bus Request and Bus Grant are used to fascinate the DMA transfer. The
bus request input is used by the DMA controller to request the CPU for the control of the buses.
When BR signal is high, the CPU terminates the execution of the current instructions and then
places the address, data, read and write lines to the high impedance state and sends the bus grant
signal. The DMA controller now takes the control of the buses and transfers the data directly
between memory and I/O without processor interaction. When the transfer is completed, the bus
request signal is made low by DMA. In response to which CPU disables the bus grant and again
CPU takes the control of address, data, read and write lines.
The transfer of data between the memory and I/O of course facilitates in two ways which are
DMA Burst and Cycle Stealing.

DMA Burst: The block of data consisting a number of memory words is transferred at a time.

Cycle Stealing: DMA transfers one data word at a time after which it must return control of the
buses to the CPU.

 CPU is usually much faster than I/O (DMA), thus CPU uses the most of the memory
cycles
 DMA Controller steals the memory cycles from CPU
 For those stolen cycles, CPU remains idle
 For those slow CPU, DMA Controller may steal most of the memory cycles which may
cause CPU remain idle long time

DMA Controller

The DMA controller communicates with the CPU through the data bus and control lines.
DMA select signal is used for selecting the controller, the register select is for selecting the
register. When the bus grant signal is zero, the CPU communicates through the data bus to read
or write into the DMA register. When bus grant is one, the DMA controller takes the control of
buses and transfers the data between the memory and I/O.

The address register specifies the desired location of the memory which is incremented
after each word is transferred to the memory. The word count register holds the number of
words to be transferred which is decremented after each transfer until it is zero. When it is zero,
it indicates the end of transfer. After which the bus grant signal from CPU is made low and
CPU returns to its normal operation. The control register specifies the mode of transfer which is
Read or Write.

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DMA Transfer

 DMA request signal is given from I/O device to DMA controller.

 DMA sends the bus request signal to CPU in response to which CPU disables its current
instructions and initialize the DMA by sending the following information.

o The starting address of the memory block where the data are available (for read)
and where data to be stored (for write)
o The word count which is the number of words in the memory block
o Control to specify the mode of transfer
o Sends a bust grant as 1 so that DMA controller can take the control of the buses
o DMA sends the DMA acknowledge signal in response to which peripheral
device puts the words in the data bus (for write) or receives a word from the data
bus (for read).

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DMA Operation

 CPU tells DMA controller:-

o Read/Write
o Device address
o Starting address of memory block for data
o Amount of data to be transferred
 CPU carries on with other work
 DMA controller deals with transfer
 DMA controller sends interrupt when finished

Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards
and sound cards etc. It is also used for intra chip data transfer in multicore processors. In DMA,
CPU would initiate the transfer, do other operations while the transfer is in progress and receive
an interrupt from the DMA controller when the transfer has been completed.

Above figure shows block diagram of DMA

Input/Output Processor

An input-output processor (IOP) is a processor with direct memory access capability. In this, the
computer system is divided into a memory unit and number of processors.

A computer may incorporate one or more external processors and assign them the task of
communicating directly with the I/O devices so that no each interface need to communicate
with the CPU. An I/O processor (IOP) is a processor with direct memory access capability that
communicates with I/O devices. IOP instructions are specifically designed to facilitate I/O
transfer. The IOP can perform other processing tasks such as arithmetic logic, branching and
code translation.

Each IOP controls and manage the input-output tasks. The IOP is similar to CPU except that it
handles only the details of I/O processing. The IOP can fetch and execute its own instructions.
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These IOP instructions are designed to manage I/O transfers only.

Block Diagram Of I/O Processor

Below is a block diagram of a computer along with various I/O Processors. The memory unit
occupies the central position and can communicate with each processor by means of direct
memory access.

The CPU processes the data required for solving the computational tasks. The IOP provides a
path for transfer of data between peripherals and memory. The CPU assigns the task of
initiating the I/O program.
The IOP operates independent from CPU and transfer data between peripherals and memory.

The communication between the IOP and the devices is similar to the program control method
of transfer. And the communication with the memory is similar to the direct memory access
method.
In large scale computers, each processor is independent of other processors and any processor
can initiate the operation.
The CPU can act as master and the IOP act as slave processor. The CPU initiates the IOP and
after which the IOP operates independent of CPU and transfer data between the peripheral and
memory. For example, the IOP receives 5 bytes from an input device at the device rate and bit
capacity. After which the IOP packs them into one block of 40 bits and transfer them to
memory. Similarly the O/P word transfer from memory to IOP is directed from the IOP to the
O/P device at the device rate and bit capacity.
Instructions that are read from memory by an IOP are also called commands to distinguish them
from instructions that are read by CPU. Commands are prepared by programmers and are stored
in memory. Command words make the program for IOP. CPU informs the IOP where to find
the commands in memory.

CPU – IOP Communication

The memory unit acts as a message center where each processor leaves information for the
other. The operation of typical IOP is appreciated with the example by which the CPU and IOP
communication.

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  The CPU sends an instruction to test the IOP path.
 The IOP responds by inserting a status word in memory for the CPU to check.
 The bits of the status word indicate the condition of the IOP and I/O device, such as IOP
overload condition, device busy with another transfer or device ready for I/O transfer.
 The CPU refers to the status word in in memory to decide what to do next.
 If all right up to this, the CPU sends the instruction to start I/O transfer.
 The CPU now continues with another program while IOP is busy with I/O program.
 When IOP terminates the execution, it sends an interrupt request to CPU.
 CPU responds by issuing an instruction to read the status from the IOP.
 IOP responds by placing the contents to its status report into specified memory location.
 Status word indicates whether the transfer has been completed or with error.

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