We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
You are on page 1/ 15
1A
a2)
Logic Gates
Introduction
Boolean algebra, as defined in previous chapter, has two binary operators, AND
and OR, and one unary operator NOT. From the definition of these operators, we
have defined other binary operators in term of them. An electronic circuit which
performs a logic operations in called a logic gate. For example, the electronic circuit
which performs AND operation is called AND gate, which performs OR operation is
called OR gate, which performs NOT operations is known as NOT gate and so on.
A knowledge of logic gates is essential to understand the important digital circuit
used in computers.
Characteristics of Logic gates are :
4. Each logic gate has only one binary output.
2, Each logic gate has either one or more than one binary inputs).
Basic Gates
These are three basic gates, namely, AND, OR and NOT. Let us consider these
gates one by one.
7.2.1 AND Gate
An AND gate has two or more inputs and only one output. The output of an AND
gate is 1 only if all inputs are 1. The standard symbol for an AND gate with two
inputs is shown in fig. 7.1
|
|
o>
l esis
FIGURE 7.1
[165]12.3 NOT Gate
ANOT gate has oné input and one output. It is also known as inverter. The standard
symbols for eM gate is shown in fig 7.5
(A) (B)
FIGURE 7.5
The logic expression of a NOT gate is
F=A
The truth table for NOT gate with input A and output F is shown in table 7.3
TABLE 7.3
[167]7.3
Example 1
Design a circuit to realize the Boolean functions
x +y)(X+V)
FIGURE 7.6
Example 2
Design a circuit to realize the Boolean functions
Y =ABC+ABC + ABC
oO
Py 48
FIGURE 7.7
|
|
|
Universal Gates
We can implement all boolean expression with basic logic gates. Still, we try to
constuct other logic gates with the help of basic logic gates for practical interest:
While constructing other logic gates, we always consider the following factors.
(a) Feasibility and economy of producing the gate which physical components.
[168]pe (b) Possibility of extending the gate to more than two inputs.
| (e) Properties of the binary operator such as commutativity.
(d) Ability of the get to implement Boolean functions or expression alone or in
conjuction with other gates.
Auniversal gate is that gate which apart from its own logical function can also
perform the basic gate functions i.e. AND, OR and NOT. NAND and NOR are
universal gate.
Let us consider NAND and NOR gates
7.3.1 NAND gate
When AND gate is combined with an inverter, a NAND gate is obtained. In other
words, the NAND gate is a combination of NOT and AND gate. Logic symbol for
two-input NAND gate is shown in figure 7.8.
=
| et
FIGURE 7.8 [AND-INVERT]
The Logic expression
The truths table for a NAND gate with two inputs A,B and one output F is shown in
table 7.4
B
Other logic symbol of NAND gate is shown in fig 7.9
A
B
FIGURE 7.9 [OR-INVERT)
[ 169]Here F=A+B
=AB (By De Morgan's law)
7.3.2 NAND gate as an Universal Gate
“The logic opérations AND, OR and NOT can be implemented with NAND gates,
(a) NOT function ;
Sa ee
\| i |
xX x |
| |
= = — ed
FIGURE 7.10
Hence a single input NAND gate acts like an inverter.
‘(b) AND function
Hence using two NAND gates, we could get the AND output.
(c) OR function
FIGURE 7.12
Hence using three NAND gates, we could get the OR output.
7.3.3 The NOR gate
When an OR gate is combined with an inverter, a NOR gate is obtained. In other
words NOR gate is combination of NOT and OR gate. Logic symbol for two input
NOR gate is shown in figure 7.13
[170]FIGURE 7.13 [OR-INVERT] Ci oe
The logic expression of it is y
F=A+B
The truth table for a NOR gate with two inputs A, B and one output F is shown in
Table 7.5
TABLE 7.5
A
| 0 0 1
| 0 1 0 |
| 1 0 0 |
| 1 1 0 |
IEE ae
Other logic symbol of NOR gate is shown in figure 7.14
A
a: naa
7.3.4 NOR gate as an Universal Gate
The basic operations AND, OR and NOT can be implemented with NOR gate.
(a) NOT function
FIGURE 7.15
Hence a single input NOR gate acts like an inverter(b) OR function
|
FIGURE 7.16
Hence using two NOR gates, we could get the OR output
(c) AND function
ue
FIGURE 7.17
Hence using three NOR gates, we could get the OR output.
7.4 Exclusive - OR (XOR) gate
The Exclusive - OR operation is widely used in digital circuits. In this gate, If both
the inputs are same, output is 0 otherwise output is 1 Logic symbol of XOR gate is
shown in figure 7.18
A
B
FIGURE 7.18
The logic expression of it is
AB+AB
“=A@B
The truth table for XOR gate with two inputs A,B and output F is shown in Table 7.6
172)TABLE 7.6
B
~=4=oc O|F
=o=o
L
3 Exclusive - NOR (XNOR) gate
XNOR gate is also known as equivalence gate. It is the combination of KOR and
NOT gate. The logic symbol for XNOR is shown in figure 7.19
——
—<—$$—
The logic expression of it is
F=(AB+AB)
=AB+AB
=AoB
The truth table for XNOR gate with two inputs A, B and one output F is shown in
Table 7.7
TABLE 7.7
A B E |
0 0 a
0 1 0
1 0 0
1 1 1
Note that in this gate. if both inputs are same, output is 1 otherwise output is 0.
, [17317.6 NAND Implementation
We can implement any boolean function (or digital circuits) by using only NAND
gate. Rules to implement a boolean function by using NAND gate are :
4. Express the boolean functions is sum of products (SOP) form.
2. First Level: Draw a NAND gate for each product term of the boolean function
that has at least two variables. A term with a single variable needs an inverter
in the first level or may be complemented and applied as an input to the secong
level NAND gate.
3. Second Level : Drawa single NAND gate with inputs coming from outputs of
first level gates.
Example 3
Implement the following boolean function
Z F=AB+AB
using NAND gate.
Solution :
The given function
F=AB+AB
is already in sum of products form.
First Level
a> w >I
FIGURE 7.20 Be
Second Level
wD >I
o>
Po ‘
FIGURE 7.21
Hence NAND gate implementation has two level.Example 4
Implement the following boolean function.
Y= (A+C) (B+C+D) (D+ A+B)
using NAND gate.
Solution :
Given boolean functioni is in POS form. First convery this function is SOP form by
taking complement both sides, we get
Y= (A+C) (B+C+D) (D+ A+B)
= (A+C)+(B+C+D)+(0+A+B)
Y= AC+B.C.D+D.AB
The two level NAND gate for generating Y is:shown in figure 7.22 and 7.23.
First Level
oH
FIGURE 7.22
Second Level
Y
FIGURE 7.23
Note that Y is obtaining by using a inverter as shown in figure 7.23.
[175]Example 5
\mplement the following boolean expression
F=A+BC+DE
Using NAND gate
Solution :
Given expression is in sum of product form. The two - level NAND implementation
is shown in figure 7.24
.
FIGURE 7.24
7.7 NOR Implementation
We can implement any boolean function (or digital circuits) by using only NOR gate.
Rules‘to implement a boolean function by using NOR. gate are
1. _ Express the boolean function in product of sums (POS) form
2. First Level
Draw a NOR gate for each sum term of the boolean function that has at least
two variables. A term with a single variable needs an inverter in the first level
‘or may be complemented and applied as an input to the second level NOR
gate.
3. Second Level
Draw a single NOR gate with inputs coming from outputs of first level gates:
Example 6
Implement the following boolean function
Y = (A+C) (B+C+D) (D+A+B)
using NOR gate.
[176]A
é
g
c
5
.
A
6
|
|
|
pothesis
7-RasA8
=e) (08)
~(hs8) (BB)Aero
OPO or a
The two level NOR gate for generating F
using a inverter.
FIGURE 7.27
Exercise
What is a Logic Gate?
What are the characteristics of Logic Gates?
What is the purpose of AND, OR and NOT gate?
ing their symbols, boolean expression and
Explain various basic gates by drawi
truth table.
What do you mean by Universal Gate?
Explain NAND gate.
Explain NAND gate as an Universal Gate.
Explain NOR gate.
Explain NOR gate as an Universal Gate.
Explain XOR gate.
Explain XNOR gate.
Explain the rules to implement a Boolean functions by using NAND gate.
Explain the rules to implement a Boolean functions by using NOR. gate.
Design the circuit to realize the Boolean functions :
F=(A+B)(A+C)(C+D)
Design the circuit to realize the Boolean functions :
is shown in fig. 7.27 F In obtaining by |
p17 |