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    FDH Digital Logic Design

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    FDH Digital Logic Design

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    FDH Digital Logic Design

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    DEPARTMENT OF ELECTRICAL ENGINEERING

    Military College of Signals (MCS)


    National University of Sciences and Technology
    (NUST)

    EE-221 Digital Logic Design (3-1)

    1. Course Information
    Course No and Title: EE-221 Digital Logic Design
    Credits: 4 (3+1)
    Instructor(s)-in-charge: Assoc Prof Dr Muhammad Imran, Engr. Zeeshan Ahmed (Lab Engr)
    Course type: Lecture + Lab
    Required or Elective: Required
    Course pre-requisites -
    Degree and Semester BEE-60, semester 3
    Month and Year Fall 2024

    2. Course book and Related Course Material


    Textbooks: – M. Morris R. Mano and Michael D. Ciletti, Digital Design: With an
    Introduction to the Verilog HDL, VHDL, and System Verilog. 6th
    Edition, Pearson Education, Inc., 2018.
    Reference Books: – Digital Design: Principles and Practices,Author: John F.Wakerly,Publisher:
    PrenticeHall
    – Digital Fundamentals, Author: Thomas L.Floyd, Publisher: PrenticeHall
    – Digital Electronics Principles, Devices andApplications, Author: Anil K.Maini,
    Publisher: John Wiley & Sons,Ltd

    3. Course Description
    Digital Logic Design is a technological subject which is intended to make students familiar with different
    types of designs as sequential logic circuits, combinational logic circuits, trouble shooting of various digital
    systems, study of various digital systems. It is an introductory electronics course covering Basic Electron
    Theory, Resistors, Analog and Digital Wave forms, Number systems, Conversions, Logic Gates, Boolean
    Algebra, Combination Circuit Design, Flip-Flops, Shift Registers and Counters. After reading this course
    student would have complete understanding about the low level architecture of any digital system of diverse
    areas like computer systems, telephony, image/ data processing system, radar, navigation, military systems,
    medical instruments, process controls etc.

    4. Course Objectives
    Upon successful completion of the course, the student will demonstrate competency by being able to:
    1. Identify different number systems, their conversions and perform different operations on them.
    2. Apply the concepts of standard gates and minimization methods to analyze and design small scale combinational
    and sequential circuits
    3. Analyze the operation of simple synchronous sequential systems.
    4. Design a digital system using modern tools
    5. Demonstrate a solution to a real world problem and justify its time line and resource allocation

    5. Topics covered in the Course and Level of Coverage


    Introduction and motivation, Digital Systems, Binary Numbers, 1 week
    Number-base Conversions
    Octal and Hexadecimal Numbers, Complements of Numbers, Signed 1 week

    45
    DEPARTMENT OF ELECTRICAL ENGINEERING
    Military College of Signals (MCS)
    National University of Sciences and Technology
    (NUST)

    Binary Numbers, Binary Codes


    Binary Logic , Boolean Algebra, Axiomatic Definition, Basic Theorems 1 week
    and Properties of Boolean Algebra
    Boolean Functions, Canonical and Standard Forms, Logic Operations 1 week
    and Logic Gates
    Gate-level Minimization, The Map Method, Four-Variable K-map, 1 week
    Product-of-Sums Simplifications, Don’t-Care Conditions
    NAND and NOR Implementation, Two-level Implementations, 1 week
    Exclusive-OR Function
    Combinational Logic, Combinational Circuits, Analysis Procedure, 1 week
    Design Procedure
    Binary Adder-Subtractor, Decimal Adder, Binary Multiplier, Magnitude 1 week
    Comparator
    Decoders, Encoders, Multiplexers 1 week
    Synchronous Sequential Logic, Sequential Circuits, Storage Elements: 1 week
    Latches, Storage Elements: Flip-Flops
    Analysis of Clocked Sequential Circuits, State Reduction and 1 week
    Assignment, Design Procedure
    Registers, Shift Registers 1 week
    Ripple Counters, Synchronous Counters, Other Counters 1 week
    Random-Access Memory, Memory Decoding 1 week
    Read-only Memory, Programmable Logic Array, Programmable Array 1 week
    Logic

    6. Lab Experiments
    Lab 01 Introduction to Trainer IT 400, Digital Analog Training System
    Lab 02 Basic Gates implementation on IT 400 and Proteus
    Lab 03 Universal Gates implementation on IT 400 and Proteus
    Lab 04 Introduction to Modelsim Simulator and Verilog , a Simple Program in Verilog
    Lab 05 K Maps and Boolean function Simplification using IT 400 and Proteus
    Lab 06 Implementation of Adder and Subtractor on IT 400 and Proteus
    Lab 07 Level of Abstractions in Verilog using Modelsim , Introduction to Xilinx ISE , Spartan 3e Starter Board
    , Simple gates Implementation on FPGA
    Lab 08 Implementation of Decoder and Encoder on IT 400 , Decoder and Comparator RTL Synthesis on FPGA
    Lab 09 Implementation (RTL Synthesis) of Multiplexer and De Multiplexer on FPGA .
    Lab 10 Data Flow Level Modeling in Verilog using Xilinx ISE , Dataflow level RTL Synthesis on FPGA .
    Lab 11 Implementation of RS & D Latch and Flip Flop on IT 400 and Proteus
    Lab 12 Behavioral Level Programming in Verilog using Xilinx ISE , RTL synthesis on FPGA of Latches and
    Flipflops
    Lab 13 Implementation (RTL) of Serial Shift Register and Parallel Register on FPGA.
    Lab 14 Implementation (RTL Synthesis) of Clock divider circuit, Ripple counter and its variants on FPGA
    Lab 15 Design of Open-Ended Lab
    Lab 16 Lab Final Exam

    46
    DEPARTMENT OF ELECTRICAL ENGINEERING
    Military College of Signals (MCS)
    National University of Sciences and Technology
    (NUST)

    7. Course Outcomes and their Relation to Program Outcomes


    (Mapping CLO to PLO)
    Course Learning Outcome (CLOs) PLOs Learning Level
    Identify different number systems, their conversions and perform 1 C2
    CLO 1
    different operations on them.
    Apply the concepts of standard gates and minimization methods to 2 C3
    CLO 2
    analyze and design small scale combinational and sequential circuits
    CLO 3 Analyze the operation of simple synchronous sequential systems 3 C4

    Implement a digital system using modern tools 5 P3


    CLO 4

    Demonstrate a solution to a real world problem and justify its time line 11 A2
    CLO5
    and resource allocation

    8. Mapping of CLOs to Program Learning Outcomes


    PLOs / CLO CLO CLO CLO 4 CLO
    CLOs 1 2 3 5
    PLO:1 (Engineering Knowledge) C2
    PLO:2 (Problem Analysis) C3
    PLO:3 (Design/ Development of Solutions) C4
    PLO:4 (Investigation)
    PLO:5 (Modern Tool Usage) P3
    PLO:6 (The Engineer and Society)
    PLO:7 (Environment and Sustainability)
    PLO:8 (Professional Ethics)
    PLO:9 (Individual and Team Work)
    PLO:10 (Communication)
    PLO:11 (Project Management) A2
    PLO:12 (Lifelong Learning)

    47

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