Unit III

Register Transfer and Micro-operations: Register Transfer Language, Register Transfer, Bus and
Memory Transfers, Arithmetic Micro-Operations, Logic Micro-Operations, Shift Micro-Operations,
Arithmetic logic shift unit. Micro-programmed Control: Control Memory, Address Sequencing, Micro-
Program example, Design of Control Unit. Input Output: I/O interface, Programmed IO, Memory
Mapped IO, Interrupt Driven IO, DMA. Instruction level parallelism: Instruction level parallelism (ILP)-
over coming data hazards, limitations of ILP

REGISTER TRANSFER LANGUAGE:

 The symbolic notation used to describe the micro-operation transfer among registers is
called RTL(Register Transfer Language).
 The use of symbols instead of a narrative explanation provides an organized and concise
manner for listing the micro-operation sequences in registers and the control functions that
initiate them.
 A register transfer language is a system for expressing in symbolic form the microoperation
sequences among the registers of a digital module.
 It is a convenient tool for describing the internal organization of digital computers in concise
andprecise manner.

Registers:

 Computer registers are designated by upper case letters (and optionally followed by digits or
letters) to denote the function of the register.
 For example, the register that holds an address for the memory unit is usually called a
memoryaddress register and is designated by the name MAR.
 Other designations for registers are PC (for program counter), IR (for instruction register, and
R1 (for processor register).
 The individual flip-flops in an n-bit register are numbered in sequence from 0 through n-1,
startingfrom 0 in the rightmost position and increasing the numbers toward the left.
 Figure 4-1 shows the representation of registers in block diagram form.

 The most common way to represent a register is by a rectangular box with the name of the
register inside, as in Fig. 4-1(a).
 The individual bits can be distinguished as in (b).
 The numbering of bits in a 16-bit register can be marked on top of the box as shown in (c).
  16-bit register is partitioned into two parts in (d). Bits 0 through 7 are assigned the symbol L
(forlow byte) and bits 8 through 15 are assigned the symbol H (for high byte).
 The name of the 16-bit register is PC. The symbol PC (0-7) or PC (L) refers to the low-order
byteand PC (8-15) or PC (H) to the high-order byte.

Register Transfer:

 Information transfer from one register to another is designated in symbolic form by means of
a replacement operator.
 The statement R2← R1 denotes a transfer of the content of register R1 into register R2.
 It designates a replacement of the content of R2 by the content of R1.
 By definition, the content of the source register R 1 does not change after the transfer.
 If we want the transfer to occur only under a predetermined control condition then it can be
shown by an if-then statement.
if (P=1) then R2← R1

 P is the control signal generated by a control section.

 We can separate the control variables from the register transfer operation by specifying a
ControlFunction.
 Control function is a Boolean variable that is equal to 0 or 1.
 control function is included in the statement as
P: R2← R1
 Control condition is terminated by a colon implies transfer operation be executed by the
hardware only if P=1.
 Every statement written in a register transfer notation implies a hardware construction for
implementing the transfer.
 Figure 4-2 shows the block diagram that depicts the transfer from R1 to R2.

 The n outputs of register R1 are connected to the n inputs of register R2.

  The letter n will be used to indicate any number of bits for the register. It will be replaced by
anactual number when the length of the register is known.
 Register R2 has a load input that is activated by the control variable P.
 It is assumed that the control variable is synchronized with the same clock as the one
applied tothe register.
 As shown in the timing diagram, P is activated in the control section by the rising edge of a
clock pulse at time t.
 The next positive transition of the clock at time t + 1 finds the load input active and the data
inputsof R2 are then loaded into the register in parallel.
 P may go back to 0 at time t+1; otherwise, the transfer will occur with every clock pulse
transitionwhile P remains active.
 Even though the control condition such as P becomes active just after time t, the actual
transfer does not occur until the register is triggered by the next positive transition of the
clock at time t +1.
 The basic symbols of the register transfer notation are listed in below table

Symbol Description Examples

Letters(and Denotes a register MAR, R2

numerals)
Parentheses ( ) Denotes a part of a register R2(0-7), R2(L)

Arrow <-- Denotes transfer of R2 <-- R1

information
Comma , Separates two R2 <-- R1, R1 <--
microoperations R2

 A comma is used to separate two or more operations that are executed at the same time.
 The statement
T : R2← R1, R1← R2 (exchange operation)
denotes an operation that exchanges the contents of two rgisters during one common clock
pulseprovided that T=1.

Bus and Memory Transfers:

 A more efficient scheme for transferring information between registers in a multiple-

registerconfiguration is a Common Bus System.
 A common bus consists of a set of common lines, one for each bit of a register.
 Control signals determine which register is selected by the bus during each particular
registertransfer.
 Different ways of constructing a Common Bus System
 Using Multiplexers
 Using Tri-state Buffers

Common bus system is with multiplexers:

 The multiplexers select the source register whose binary information is then placed on the
bus.
 The construction of a bus system for four registers is shown in below Figure.

 The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and
twoselection inputs, S1 and S0.
 For example, output 1 of register A is connected to input 0 of MUX 1 because this input is
labelledA1.
 The diagram shows that the bits in the same significant position in each register are
connected tothe data inputs of one multiplexer to form one line of the bus.
 Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of
theregisters, and similarly for the other two bits.
 The two selection lines Si and So are connected to the selection inputs of all four
multiplexers.
 The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
 When S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the
outputsthat form the bus.
 This causes the bus lines to receive the content of register A since the outputs of this register
areconnected to the 0 data inputs of the multiplexers.
 Similarly, register B is selected if S1S0 = 01, and so on.
 Table 4-2 shows the register that is selected by the bus for each of the four possible binary
valueof the selection lines.
  In general a bus system has
 multiplex “k” Registers
each register of “n” bits
 to produce “n-line bus”
 no. of multiplexers required = n
 size of each multiplexer = k x 1
 When the bus is includes in the statement, the register transfer is symbolized as follows:
BUS← C, R1← BUS
 The content of register C is placed on the bus, and the content of the bus is loaded into
register R1 by activating its load control input. If the bus is known to exist in the system, it
may be convenientjust to show the direct transfer.
R1← C
Three-State Bus Buffers:
 A bus system can be constructed with three-state gates instead of multiplexers.
 A three-state gate is a digital circuit that exhibits three states.
 Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate.
 The third state is a high-impedance state.
 The high-impedance state behaves like an open circuit, which means that the output is
disconnected and does not have logic significance.
 Because of this feature, a large number of three-state gate outputs can be connected with
wires to form a common bus line without endangering loading effects.
 The graphic symbol of a three-state buffer gate is shown in Fig. 4-4.

 It is distinguished from a normal buffer by having both a normal input and a control input.
 The control input determines the output state. When the control input is equal to 1, the
output is enabled and the gate behaves like any conventional buffer, with the output equal
to the normal input.
 When the control input is 0, the output is disabled and the gate goes to a high-impedance
state,regardless of the value in the normal input.
 The construction of a bus system with three-state buffers is shown in Fig. 4
  The outputs of four buffers are connected together to form a single bus line.
 The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
 No more than one buffer may be in the active state at any given time. The connected buffers
must be controlled so that only one three-state buffer has access to the bus line while all
other buffers are maintained in a high impedance state.
 One way to ensure that no more than one control input is active at any given time is to use a
decoder, as shown in the diagram.
 When the enable input of the decoder is 0, all of its four outputs are 0, and the bus line is in
ahigh-impedance state because all four buffers are disabled.
 When the enable input is active, one of the three-state buffers will be active, depending on
thebinary value in the select inputs of the decoder.

Memory Transfer:

 The transfer of information from a memory word to the outside environment is called a read
operation.
 The transfer of new information to be stored into the memory is called a write operation.
 A memory word will be symbolized by the letter M.
 The particular memory word among the many available is selected by the memory address
duringthe transfer.
 It is necessary to specify the address of M when writing memory transfer operations.
 This will be done by enclosing the address in square brackets following the letter M.
 Consider a memory unit that receives the address from a register, called the address
register,symbolized by AR.
 The data are transferred to another register, called the data register, symbolized by DR.
 The read operation can be stated as follows:
Read: DR<- M [AR]
 This causes a transfer of information into DR from the memory word M selected by the
address inAR.
 The write operation transfers the content of a data register to a memory word M selected by
theaddress. Assume that the input data are in register R1 and the address is in AR.
 The write operation can be stated as follows:
Write: M [AR] <- R1

Types of Micro-operations:

 Register Transfer Micro-operations: Transfer binary information from one register to

another.
 Arithmetic Micro-operations: Perform arithmetic operation on numeric data stored in
registers.
 Logical Micro-operations: Perform bit manipulation operations on data stored in registers.
 Shift Micro-operations: Perform shift operations on data stored in registers.
 Register Transfer Micro-operation doesn’t change the information content when the binary
information moves from source register to destination register.
 Other three types of micro-operations change the information change the information
contentduring the transfer.
Arithmetic Micro-operations:

 The basic arithmetic micro-operations are

o Addition
o Subtraction
o Increment
o Decrement
o Shift
 The arithmetic Micro-operation defined by the statement below specifies the add micro-
operation.
R3 ← R1 + R2
 It states that the contents of R1 are added to contents of R2 and sum is transferred to R3.
 To implement this statement hardware requires 3 registers and digital component that
performsaddition
 Subtraction is most often implemented through complementation and addition.
 The subtract operation is specified by the following statement
R3 ← R1 + R2 + 1
 instead of minus operator, we can write as
 R2 is the symbol for the 1’s complement of R2
 Adding 1 to 1’s complement produces 2’s complement
 Adding the contents of R1 to the 2's complement of R2 is equivalent to R1-R2.

Binary Adder:

 Digital circuit that forms the arithmetic sum of 2 bits and the previous carry is called FULL
ADDER.
 Digital circuit that generates the arithmetic sum of 2 binary numbers of any lengths is called
BINARY ADDER.
 Figure 4-6 shows the interconnections of four full-adders (FA) to provide a 4-bit binary adder.

 The augends bits of A and the addend bits of B are designated by subscript numbers from
right to left, with subscript 0 denoting the low-order bit.
 The carries are connected in a chain through the full-adders. The input carry to the binary
adder is Co and the output carry is C4. The S outputs of the full-adders generate the required
sum bits.
 An n-bit binary adder requires n full-adders.
Binary Adder – Subtractor:

 The addition and subtraction operations can be combined into one common circuit by
including anexclusive-OR gate with each full-adder.
 A 4-bit adder-subtractor circuit is shown in Fig. 4-7.

 The mode input M controls the operation. When M = 0 the circuit is an adder and when M =
1 thecircuit becomes a subtractor.
 Each exclusive-OR gate receives input M and one of the inputs of B
 When M = 0, we have B xor 0 = B. The full-adders receive the value of B, the input carry is 0,
andthe circuit performs A plus B.
 When M = 1, we have B xor 1 = B' and Co = 1.
 The B inputs are all complemented and a 1 is added through the input carry.
 The circuit performs the operation A plus the 2's complement of B.

Binary Incrementer:

 The increment microoperation adds one to a number in a register.

 For example, if a 4-bit register has a binary value 0110, it will go to 0111 after it is
incremented.
 This can be accomplished by means of half-adders connected in cascade.
 The diagram of a 4-bit 'combinational circuit incrementor is shown in Fig. 4-8.

 One of the inputs to the least significant half-adder (HA) is connected to logic-1 and the
otherinput is connected to the least significant bit of the number to be incremented.
 The output carry from one half-adder is connected to one of the inputs of the next-higher-
orderhalf-adder.
 The circuit receives the four bits from A0 through A3, adds one to it, and generates the
 incremented output in S0 through S3.
 The output carry C4 will be 1 only after incrementing binary 1111. This also causes outputs S0
through S3 to go to 0.
 The circuit of Fig. 4-8 can be extended to an n -bit binary incrementer by extending the
diagram toinclude n half-adders.
 The least significant bit must have one input connected to logic-1. The other inputs receive
thenumber to be incremented or the carry from the previous stage.

Arithmetic Circuit:

 The basic component of an arithmetic circuit is the parallel adder.

 By controlling the data inputs to the adder, it is possible to obtain different types of
arithmeticoperations.
 The diagram of a 4-bit arithmetic circuit is shown in Fig. 4-9. It has four full-adder circuits
thatconstitute the 4-bit adder and four multiplexers for choosing different operations.
  There are two 4-bit inputs A and B and a 4-bit output D.
 The four inputs from A go directly to the X inputs of the binary adder.
 Each of the four inputs from B are connected to the data inputs of the multiplexers.
 The multiplexers data inputs also receive the complement of B.
 The other two data inputs are connected to logic-0 and logic-1.
 The four multiplexers are controlled by two selection inputs S1 and S0. The input carry Cin,
goes to the carry input of the FA in the least significant position. The other carries are
connected from onestage to the next.
 By controlling the value of Y with the two selection inputs S1 and S0 and making Cin equal to 0
or 1,it is possible to generate the eight arithmetic microoperations listed in Table 44.

Addition:

 When S1S0= 00, the value of B is applied to the Y inputs of the adder.
 If Cir, = 0, the output D =A+B.
 If Cin = 1, output D=A+B + 1.
 Both cases perform the add microoperation with or without adding the input carry.

Subtraction:

 When S1S0 = 01, the complement of B is applied to the Y inputs of the adder.
 If Cin = 1, then D = A + B + 1. This produces A plus the 2's complement of B,
which isequivalent to a subtraction of A -B.
 When Cin = 0 then D = A + B. This is equivalent to a subtract with borrow, that
is,A-B-1.

Increment:

 When S1S0 = 10, the inputs from B are neglected, and instead, all 0's are inserted into the Y
inputs. The output becomes D = A + 0 + Cin. This gives D = A when Cin = 0 and D = A + 1 when
Cin = 1.
 In the first case we have a direct transfer from input A to output D.
 In the second case, the value of A is incremented by 1.
Decrement:

 When S1S0= 11, all l's are inserted into the Y inputs of the adder to produce the decrement
operation D = A -1 when Cin = 0.
 This is because a number with all 1's is equal to the 2's complement of 1 (the 2's
complement of binary 0001 is 1111). Adding a number A to the 2's complement of 1
produces F = A + 2's complement of 1 = A — 1. When Cin = 1, then D = A -1 + 1=A, which
causes a direct transfer frominput A to output D.

Logic Micro-operations:

 Logic microoperations specify binary operations for strings of bits stored in registers.
 These operations consider each bit of the register separately and treat them as binary
variables.
 For example, the exclusive-OR microoperation with the contents of two registers RI and R2 is
symbolized by the statement

 It specifies a logic microoperation to be executed on the individual bits of the registers

providedthat the control variable P = 1.

List of Logic Microoperations:

 There are 16 different logic operations that can be performed with two binary variables.
 They can be determined from all possible truth tables obtained with two binary variables as
shown in Table 4-5.

 The 16 Boolean functions of two variables x and y are expressed in algebraic form in the first
column of Table 4-6.
 The 16 logic microoperations are derived from these functions by replacing variable x by the
binary content of register A and variable y by the binary content of register B.
 The logic micro-operations listed in the second column represent a relationship between the
binary content of two registers A and B.
Hardware Implementation:
 The hardware implementation of logic microoperations requires that logic gates be inserted
foreach bit or pair of bits in the registers to perform the required logic function.
 Although there are 16 logic microoperations, most computers use only four--AND, OR, XOR
(exclusive-OR), and complement from which all others can be derived.
 Figure 4-10 shows one stage of a circuit that generates the four basic logic microoperations.
 It consists of four gates and a multiplexer. Each of the four logic operations is generated
through agate that performs the required logic.
 The outputs of the gates are applied to the data inputs of the multiplexer. The two selection
inputs S1 and S0 choose one of the data inputs of the multiplexer and direct its value to the
output.
Some Applications:

 Logic micro-operations are very useful for manipulating individual bits or a portion of a word stored
in aregister.
 They can be used to change bit values, delete a group of bits or insert new bits values into a register.
 The following example shows how the bits of one register (designated by A) are manipulated by logic
microoperations as a function of the bits of another register (designated by B).
 Selective set
The selective-set operation sets to 1 the bits in register A where there are
corresponding l's in register B. It does not affect bit positions that have 0's in B. The
followingnumerical example clarifies this operation:

 The OR microoperation can be used to selectively set bits of a register.

 Selective complement
 The selective-complement operation complements bits in A where there are
corresponding 1's in B. It does not affect bit positions that have 0's in B. For example:

 The exclusive-OR microoperation can be used to selectively complement bits of a

register.
 Selective clear
 The selective-clear operation clears to 0 the bits in A only where there

arecorresponding l's in B. For example:

 The corresponding logic microoperation is

 Mask
 The mask operation is similar to the selective-clear operation except that the bits of A are
cleared only where there are corresponding O's in B . The mask operation is an AND micro
operation as seen from the following numerical example:

 Insert
 The insert operation inserts a new value into a group of bits. This is done by first masking the
bitsand then ORing them with the required value.
  For example, suppose that an A register contains eight bits, 0110 1010. To replace the four
leftmostbits by the value 1001 we first mask the four unwanted bits:

 The mask operation is an AND microoperation and the insert operation is an OR

microoperation.
 Clear
 The clear operation compares the words in A and B and produces an all 0's result if
the two numbers are equal. This operation is achieved by an exclusive-OR
microoperation as shownby the following example

Shift Microoperations:

 Shift microoperations are used for serial transfer of data.

 The contents of a register can be shifted to the left or the right.
 During a shift-left operation the serial input transfers a bit into the rightmost position.
 During a shift-right operation the serial input transfers a bit into the leftmost position.
 There are three types of shifts: logical, circular, and arithmetic.
 The symbolic notation for the shift microoperations is shown in Table 4-7.

 Logical Shift:
o A logical shift is one that transfers 0 through the serial input.
o The symbols shl and shr for logical shift-left and shift-right microoperations.
 o The microoperations that specify a 1-bit shift to the left of the content of register R
and a1-bit shift to the right of the content of register R shown in table 4.7.
o The bit transferred to the end position through the serial input is assumed to be 0
duringa logical shift.

 Circular Shift:
o The circular shift (also known as a rotate operation) circulates the bits of the register
around the two ends without loss of information.
o This is accomplished by connecting the serial output of the shift register to its serial
input.
o We will use the symbols cil and cir for the circular shift left and right, respectively.
 Arithmetic Shift:
o An arithmetic shift is a microoperation that shifts a signed binary number to the left
orright.
o An arithmetic shift-left multiplies a signed binary number by 2.
o An arithmetic shift-right divides the number by 2.
o Arithmetic shifts must leave the sign bit unchanged because the sign of the number
remains the same when it is multiplied or divided by 2.

Hardware Implementation:

 A combinational circuit shifter can be constructed with multiplexers as shown in Fig. 4-12.
 The 4-bit shifter has four data inputs, A0 through A3, and four data outputs, H0 through H3.
 There are two serial inputs, one for shift left (IL) and the other for shift right (IR).
 When the selection input S=0 the input data are shifted right (down in the diagram).
 When S = 1, the input data are shifted left (up in the diagram).
 The function table in Fig. 4-12 shows which input goes to each output after the shift.
 A shifter with n data inputs and outputs requires n multiplexers.
 The two serial inputs can be controlled by another multiplexer to provide the three possible
typesof shifts.
Arithmetic Logic Shift Unit:
 Instead of having individual registers performing the microoperations directly, computer
systems employ a number of storage registers connected to a common operational unit
called an arithmetic logic unit, abbreviated ALU.
 The ALU is a combinational circuit so that the entire register transfer operation from the
source registers through the ALU and into the destination register can be performed during
oneclock pulse period.
 The shift microoperations are often performed in a separate unit, but sometimes the shift
unit ismade part of the overall ALU.
 The arithmetic, logic, and shift circuits introduced in previous sections can be combined into
one ALU with common selection variables. One stage of an arithmetic logic shift unit is
shown in Fig. 4-13.
 Particular microoperation is selected with inputs S1 and S0. A 4 x 1 multiplexer at the output
chooses between an arithmetic output in Di and a logic output in Ei.
 The data in the multiplexer are selected with inputs S3 and S2. The other two data inputs to
the multiplexer receive inputs Ai-1 for the shift-right operation and Ai+1 for the shift-left
operation.
 The circuit whose one stage is specified in Fig. 4-13 provides eight arithmetic operation, four
logicoperations, and two shift operations.
 Each operation is selected with the five variables S3, S2, S1, S0 and Cin.
 The input carry Cin is used for selecting an arithmetic operation only.
 Table 4-8 lists the 14 operations of the ALU. The first eight are arithmetic operations and are
selected with S3S2 = 00.
 The next four are logic and are selected with S3S2 = 01.
 The input carry has no effect during the logic operations and is marked with don't-care x’s.
 The last two operations are shift operations and are selected with S3S2= 10 and 11.
 The other three selection inputs have no effect on the shift.