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VerilogHDL Assignment 3

verilog

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Chandu Chitti
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14 views

VerilogHDL Assignment 3

verilog

Uploaded by

Chandu Chitti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog HDL [18EC56]

Assignment – 3
1. With a neat flow chart explain Computer -Aided Logic Synthesis Process.
2. Define the term Logic Synthesis. Explain in detail the Impact of Logic Synthesis on
Digital Design Industry.
3. What will the following statement translate to when run on a logic synthesis tool.
assign y = (a & b) | (c & d); //out, a, b, c and d are 3bit vectors
if (s)
out = i1;
else
out = i0;
4. Write a short note on Functional Verification of Gate-Level Netlist.
5. With a neat flow chart explain Logic Synthesis Flow from RTL to Gates.
6. Write RTL description for Magnitude Comparator.
7. Define a function to design an 8-function ALU that takes two 4-bit numbers a and b
and computes a 5-bit result out based on a 3-bit select signal. Ignore overflow or
underflow bits.
Select, Signal Function Output
3’b000 a
3’b001 a+b
3’b010 a-b
3’b011 a/b
3’b100 a % 1 (remainder)
3’b101 a << 1
3’b110 a >> 1
3’b111 (a > b) (magnitude compare)
8. Write a Verilog code for Traffic Signal Controller with the following specification –

i. The traffic signal for the main highway gets highest priority because cars
are continuously present on the main highway. Thus, the main highway
signal remains green by default.
ii. Occasionally, cars from the country road arrive at the traffic signal. The
traffic signal for the country road must turn green only long enough to let
the cars on the country road go.
iii. As soon as there are no cars on the country road, the country road traffic
signal turns yellow and then red and the traffic signal on the main highway
turns green again.
iv. There is a sensor to detect cars waiting on the country road. The sensor sends
a signal X as input to the controller. X = 1 if there are cars on the country
road; otherwise, X= 0.
v. There are delays on transitions from S1 to 52, from S2 to S3, and from S4
to SO. The delays must be controllable.

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