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VerilogHDL Assignment 2

verilog

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Chandu Chitti
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12 views

VerilogHDL Assignment 2

verilog

Uploaded by

Chandu Chitti
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog HDL [18EC56]

Assignment – 2
1. Discuss AND, OR and NOT gates with respect to logic symbols, gate instantiation and
truth tables.
2. Design AOI based 4:1 multiplexer, write verilog description for the same and its
stimulus.
3. The logic diagram for an RS latch with delay is shown below

Write the Verilog description for the RS latch. Include delays of 1 unit when
instantiating the NOR gates. Write the stimulus module for the RS latch, using the
following table, and verify the outputs.
4. Write the verilog description of 4-bit ripple carry adder at gate level abstraction, with a
neat block diagram. Also, write stimulus block
5. A magnitude comparator checks if one number is greater than or equal to or less than
another number. A 4-bit magnitude comparator takes two 4-bit numbers, A and B, as
input. We write the bits in A and B as follows. Leftmost bit is the most significant bit.
A = A(3) A(2) A(1) A(0)
B = B(3) B(2) B(1) B(0)
The magnitude can be compared by comparing the numbers bit by bit, starting with the
most significant bit. If any bit mismatches, the number with bit 0 is the lower number.
To realize this functionality in logic equations, let us define an intermediate variable.
Notice that the function below is an xnor function.
x(i) = A(i).B(i) + A(i)`.B(i)`
The three outputs of the magnitude comparator are A_lst_B, A_lt_B, A_eq_B.
6. A synchronous counter can be designed by using master-slave JK Pip-Pops. Design a
4-bit synchronous counter. Circuit diagrams for the synchronous counter and the JK
flip-flop are given below. Clear signal is active low. Data gets latched on the positive
edge of clock, and the output of the flip-flop appears on the negative edge of clock.
Counting is disabled when count-enable signal is low. Write the dataflow description
for the synchronous counter. Write a stimulus file that exercises clear and count-enable.
Display the output count Q[3:0].

7. Write the verilog description of 4-bit ripple carry adder at gate level abstraction, with a
neat block diagram. Also, write stimulus block
8. Design a clock with period 40 and a duty cycle of 25% by using the always and initial
statement. The value of clock at tome = 0 is initiated at 0. Display the value.

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