ECEN 201 Electronics 1 Electronic Devices and Circuit

Republic of the Philippines
POLYTECHNIC UNIVERSITY OF THE PHILIPPINES

OFFICE OF THE VICE PRESIDENT FOR BRANCHES AND CAMPUSES
SANTA ROSA CAMPUS
City of Santa Rosa, Laguna
INSTRUCTIONAL MATERIAL FOR

ELECTRONICS 1: ELECTRONIC
DEVICES AND CIRCUITS
(ECEN 30014)
COMPILED BY:
Engr. ROSELITO E. TOLENTINO

Faculty
TABLE OF CONTENTS
UNIT I – INTRODUCTION TO SEMICONDUCTOR
Lesson 1 Classification of Materials ......... 1–2
Lesson 2 Atomic Structure of Semiconductor ......... 3–4
Lesson 3 Doping Process ......... 5-6
UNIT II – Diode Fundamentals and Biasing

Lesson 1 Diode Operation ......... 7-8
Lesson 2 Diode Equivalent Circuit ......... 8-10
UNIT III - Diode Application

Lesson 1 Rectification ......... 11-16
Lesson 2 Clipper ......... 17-18
Lesson 3 Clamper ......... 19-20
Lesson 4 Voltage multiplier ......... 20
Lesson 5 Zener Diode ........ 20-23
UNIT IV – BJT Fundamentals

Lesson 1 Types of BJT ......... 24 – 25
Lesson 2 Amplification factor ......... 25-26
Lesson 3 Transistor configuration ......... 26-27
Lesson 4 Region of operation ......... 28
UNIT V – BJT Biasing

Lesson 1 Fixed bias ......... 29 – 30
Lesson 2 Emitter Bias ......... 30 – 31
Lesson 3 Voltage divider bias ......... 32 – 34
UNIT VI – BJT Amplification

Lesson 1 re Model ......... 35 – 38
Lesson 2 Hybrid model ......... 38 - 48
UNIT VII – FET Fundamentals

Lesson 1 JFET ......... 49 - 53
Lesson 2 MOSFET ......... 54 - 55
UNIT VIII – BJT Biasing

Lesson 1 Fixed Bias ......... 56
Lesson 2 Self Bias ......... 57
Lesson 3 Voltage Divider Bias ......... 58
UNIT I X – BJT Amplification

Lesson 1 Fixed Bias ......... 60 - 65
Lesson 2 Self Bias ......... 66 -70
Lesson 2 Voltage Divider Bias ......... 71 -72
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Unit 1:
Introduction to Semiconductor
Lesson 1: Classification of Materials:
1. Conductor – a substance, body on materials w/c has more electrons that

are free to move (free electrons).
- w/c is a good conduction of electricity.
- w/c has a very low electrical resistance.
- w/c usually has one valence electron.
Example: metals (such as silver, copper, gold etc.) electrolytes and ionized
gases.
2. Insulator – a substance, body on materials w/c has characteristics that is

extremely opposite to that of a conductor w/c more than 4 valence
electrons but ideally it has 8 valence electrons.
Example: glass, mica, and hard rubber.
3. Semiconductor – a substance, body on materials that has a characteristics

in between a conductor and insulator.
- w/ four valence electrons.
Example:
1.) Elementary Semiconductor (IV A)

a. Silicon (Si)
b. Germanium (Ge)
2.) Compound Semiconductor (III A)

a. Gallium Arsenide (Ga As)
b. Aluminium Arsenide (Al As)
c. Gallium Phosphide (Ga P)
Composition/ Elementary Particles:
Particles Mass at test (kg) Charge Coulomb
Electron 9.1096 X 10 -23 - 1.6020 X 10-19

Proton 1.6726 X 10 -27 1.6020 X 10-19
Neutron 1.6726 X 10 -27 No charge
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Charge to mass kg to c/kg
1.6022 X 1011
9.8791 X 10 7
0
Important Terms:
1.) Atomic Mass or Weight ( A ) – approximately the sum of the number of

protons and neutrons of an atom.
2.) Atomic Number ( Z ) – the number of protons in the nucleus on the number
of electrons in an atom.
3.) Valence Electrons – electrons at the valence shell.
4.) Valence Shell – the outermost shell.
5.) Valence Band – the highest energy band of an atom w/c can be filled w/
electrons.
6.) Conduction Band – energy band in w/c electrons can move freely.
Energy gap – the energy different between the conduction band and the
valence band. It is the energy required to move or transfer a valence
electron at the valence band to the conduction band.
Energy Gap Comparison:
Energy Energy Energy
Conduction Band Conduction Band

Conduction Band
Eg > 5eV Eg
Valence Band
Valence Band
Valence Band
INSULATOR SEMICONDUCTOR CONDUCTOR
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Eg = 1.1 eV ( Si )
Eg = 067 eV ( Ge )
Eg = 1.41 eV ( GaAs )
Lesson 2: Atomic Structure Of Semiconductor:
Bonding Of atoms:
1. Ionic Bonds or Electrovalent Bonds – results from attractive forces between

positive and negative ions or between pairs of oppositely charges ion.
2. Metallic Bonds – attractive forces results from a group of positive ions and
electrons w/ are free to move about among its ions.
Covalent Bonds – (attractive forces) occurs when atoms shares two or more
electrons.
Covalent Bonding of Semiconductor:
Si Si Si
Si Si Si
Si Si Si
Covalent Bonding of the Silicon atom
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At 0 k absolute zero ( -273 ˚ C ) there are no free electrons in
semiconductor they locked at the valence bond however, at room temperature
( 300 K ) valence electrons can acquire sufficient energy and become free as
they move to the conduction band.
Intrinsic Carrier – free electrons in a material due only to natural causes,

example due to the increase in temperature.
- At room temperature, there are approximately 1.5X10 10
of free electrons in a cubic centimetre for intrinsic silicon
and 2.5X10 13 for Germanium materials.
Silicon Crystals – arrangement of silicon atoms to form a solid such that they
are now 8 electrons in the valence shell.
Ambient temperature – is the temperature of the surrounding air ( usually 27˚

or 25˚ C or 300 or 298 K )
Free Electron – the released electron dislodged from its original shell due to
increase in temperature w/c joins into a larger or bit.
Hole – refer to the vacancy left by free electrons when it departs from its original
shell.
Recombination – the merging of a free electrons and a hole inside a silicon

crystal.
lifetime – the amount of time between the creation and disappearance of a free
electron.
Lesson 3: DOPING PROCESS
Doping Process – adding a pentavalent or trivalent impurities to an intrinsic

materials.
Two Types Of Impurities:
1.) Pentavalent Impurities – w/ five valence electrons ( donor atom ) such as

Antimony ( Sb ), Arsenic ( As ), Phosphorus ( P ).
2.) Trivalent Impurities – w/ 3 valence electrons ( acceptor atom ) such as Boron

( B ), Gallium ( Ga ), Indium ( In ).
Two Types of Semiconductor:
1.) Intrinsic Semiconductor

- a pure conductor
- every atom in the crystal is a silicon atom.
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2.) Extrinsic Semiconductor
- a doped semiconductor
-result of adding an impurity atom to an intrinsic crystal to alter increase
it electrical conductivity.
Extrinsic Semiconductor can be
a.) N type – produced when a pentavalent atoms are added to the molten silicon
producing an excess of electrons.
b.) P type – produced when a trivalent atom are added to the molten silicon
produces an excess of holes.
Doped Semiconductors ( Extrinsic Materials)
Si - Antimony
Si Si Si
Fifth valence electron
2f Antimony
Si Sb Si
Si Si Si
- excess of electrons
- majority carrier is electrons
- resulting material is N type
- minority carrier is hole
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Si - Boron
Si Si Si
Void
Si B Si
Si Si Si Boron
Impurity
- excess of holes
- majority carrier is hole
- resulting material is P type
- minority carrier is electron
Si / Ge Semiconductor:
Some reasons why Si & Ge are mostly used:
1. Can be manufactured to a very high purity level.

2. Has the ability to change electrical characteristics from poor conductor to a
good conductor.
Si vs. Ge:
1. Si diode has higher PIV and currently rating and wider temperature rather
than Ge.
2. Si has forward-bias voltage required to reach conductor.
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Unit 2:
Diode Fundamentals and Biasing
Diode:
The junction diode is formed when a N-type and P-type materials are
brought together.
Construction & Symbol
P N
+ -
Electron Region
Symbol
A K
Operation:
A.) No Bias – no applied voltage
P N
Note:
1. Depletion Region – the region of

uncovered positive & negative
ions.
ID 2. In the absence of an applied
voltage, the net flow of charge
in any one direction for
VD semiconductor diode is zero.
B.) Reverse Bias – only minorily carrier ( reverse salvation current ) can flow.
P N
Reverse Salvation Current Is – the

current that exists under
reverse condition.
- +
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C.) Forward Bias – allows majorily carriers ( forward current ) to flow, a node
(A) must be positive w/ respect to the cathode (K).
P N
ID ID
+ -
VD
Diode Equivalent Circuit:
Type Model Characteristics
Precewise-linear ID rd
model`
rd
( 3 Approx. )
rd Ideal VT
VT Diode
Simplified model
( 2nd Approx. )
Ideal Device
Parallel & Series-Parallel Configuration:
0.33 KΩ
VO
ID1 ID2
I
E 10 V Si Si
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Determine Vo , I , I D1 and I D2
o.33 KΩ
10V .7 V .7 V VO = 0.7 V
For I : For I D1 :
by KVL: 10 – I ( 0.33 KΩ ) – 0.7 = 0
I D1 = I D2 = .I
I = 10 – 0.7 2
0.33 K I D1 = I D1 = 28.18 mA
2
I = 28.18 mA
I D1 = I D2 = 14.9 mA
Determine current I & VR

2.2 KΩ 0.7 V
+ +
20 V 4V
-
By KVL:
20 – I ( 2.2 KΩ ) – 0.7 – 4 = 0 VR = ( 6.95 mA )( 2.2 KΩ )
I = 20 – 0.7 – 4 VR = 15.29 V
2.2 KΩ
I = 6.95 mA
Determine I and VO of the network:

16 V
Si
By KVL:
16 – 1.4 V – 4.7 KΩ - 12 V = 0
Si Si I = 16 – 1.4 – 12
4.7 KΩ
VO I = 0.55 mA
4.7 KΩ
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12 V
VO = ?
VO
16 V 0.7 V 0.7 V By KVL:
12 – 0.55 ( 4.7 KΩ ) - VO = 0
4.7 KΩ
VO = 12 – 0.55 ( 4.7 KΩ )
VO = 9.42 V
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Unit 3:
Diode Application
Rectification – the process of converting alternating current to direct current
1. Half – Wave Rectifier
VO
VM
R
VI
Half Wave Rectifier using ideal diode
Half – wave Rectification

it is the process of removing one-half signal to establish a DC level.
Example:
VO
R = 4.6 KΩ
0 T
T
2
I= 4 VO = ( 0.87 mA )( 4.6 KΩ )
4.6 KΩ
VO = 4 V
= 0.87 mA
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2. Full – wave Rectifier
2 types:
a.) Bridge Network
b.) Center Tapped Transformer
VI
+ 0 T
T
VI 2
- VM
VO
Bridge Network
0 T T
2
VDC = 0.636 VM for Ideal
VDC = 0.636 (VM - 2 VT ) for Si or Ge diode
PIV > VM
+
+
VI -
-
Center – Tapped Transformer
VI
0 T
T
2
VO
0 T T
2
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Diode – Current Equation:
ID = IS ( e KVD / TK – 1 )
where:
ID = Diode current
IS = reverse saturation or leakage current
VD = forward voltage across the diode
TK = room temperature in ˚K
TK = T ˚C + 273 ˚K
K = 11600 / n for level of diode current
n = 1 for Germanium and n = 2 for Silicon
• For high level Diode Current n = 1 for both Si and Ge.
Temperature Effect on IS:
ISN = ISTO e K ( Ti - To )
where:
ISTI = saturation current at Temperature

ISTO = saturation current at room temperature K = 0.07 / ˚C.
Ti = new temperature
To = room temperature ( 27 ˚C or 300 K )
Temperature Effect on VTH:
VTHTI = VTHTO + K ( Ti – To )
where;
VTHTI = threshold voltage at new temperature
VTHTO = threshold voltage at room temperature
= 0.3 for Germanium
= 0.7 for Silicon
K = -2.5 mV / ˚C for Ge
= -2.0 mV / ˚C for Si
Example:
1. Determine the diode current at 20 ˚C for a silicon diode w/ IS = 50 mA applied

voltage of 0.6 V.
Given: T = 20 ˚C + 273
Tk = 293 K
IS = 50 mA
VD = 0.6 V
Sol’n: ID = IS ( e KVD / TK – 1 )
= 50 mA ( e 11600 / 2 ( 0.6 ) / 293 – 1 )
ID = 7.19 mA
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2. when a silicon diode is conducting at a temperature 25 ˚C, 0.7 V drops exists
across its terminals. What is the voltage at 100 ˚C.
Given: To = 25 ˚C Sol’n:
VTHTO = 100 ˚C VTHTI = VTHTO + K ( Ti – To )
Ti = 100 ˚C
VTHTI = ? = 0.7 + (-2.0 mV / ˚C )( 100 – 25 )
VTHTI = 0.55 V
DC Analysis:
VD less than 0.7 V V D less than 0.3 V
= =
Si Ge
VD > 0 V D > 0.7 V
= =
Si Si
“ off “ state of Si & Ge
VD > 0.3 V
Ge
“ on “ state of Si & Ge
In general, a diode is in the “ on “ state if the current established by
the applied voltage ( source ) is such that its direction matches that of the arrow
in the diode symbol.
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Series Diode Configuration w/ DC Inputs:
+ VD = VT VD = 0.7 for Si
E VD = 0.3 for Ge
R VR
- VR = E - VT
I D = I R = VR / R
Series Diode
0.7 V +
E VR
ID
-
Equivalent Model for “ on “ state
Sample Problem:
1. )
Si Determine: VD, VR and IR
0.5 V 12 KΩ
Sol’n: KVL:
+ - 0.5 - VD – VR = 0
VR = ID R
0.5 V I 12 KΩ ID = 0 , “ off “ state ( open ckt )
VR = 0 ( 12 K )
0.5 – VD – 0 = 0 VR = 0
VD = 0.5 V
2. ) + - + -
VD Determine: VO and ID
12 V Si Ge
5.6 KΩ
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VD1 VD2 KVL:
12 – 0.7 – 0.3 – VR = 0
VD
+
VR = 11 V
0.7 0.3
5.6 KΩ
ID VR = VO ( parallel )
-
VO = 11 V
VR = IR R
IR = ID ( series )
ID = VO / R = 11 V / 5.6 KΩ ID = 1.96 mA
3. ) VD1 VD2
Determine: ID and VO
VO
12 V Si Si
R = 5.6 KΩ
KVL:
12 – VD1 + VD2 – VR = 0
VR = ID R
12 V
VR = 0 ( 5.6 K )
ID = 0 5.6 KΩ
VR = 0 V
VR = VO
VO = 0 V
ID = 0 A open , off state
VD2 = 12 – 0 – 0
VD2 = 12 V
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4. )
VO Determine: I, V1 and V2
12 V 4.7 KΩ Si
2.2 KΩ KVL:
12 – I( 4.7 KΩ ) – 0.7 – I ( 2.2 KΩ ) + 5 V = 0
I = 12 – 0.7 + 5
5V 4.7 K + 2.2 K
I = 2.36 mA
VO
V1 = I R1
12 V 4.7 KΩ 0.7
V1 = 2.36 mA ( 4.7 KΩ )
2.2 KΩ
V1 = 11.092 V
I
5V
V2 = I R2
V2 = 2.36 mA ( 2.2 KΩ )
VO:
V2 = 5.192 V
-5 V+ I ( 2.2 KΩ ) – VO = 0
VO = -5 V + 2.36 mA ( 2.2 KΩ )
VO = 0.192 V
Clipper:
- a circuit or network that has the ability to “clip” of a portion of an input
signal w/out disturbing the remaining part of an alternating waveform.
Two General Categories:
1.) Series
2.) Parallel
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Series Clipper
+ VO
VM V
R
Vi
-
---------------------------- -----
Few thoughts to keep in mind as you work towards a network:
1.) Make a mental sketch of the response of the network based on the
direction of the diode and the applied voltage levels.
2.) Determine applied voltage ( transition voltage ) that will cause a charge
in state for the diode.
3.) Be continually aware of the defined terminals and polarity of V O.
4.) It can be helpful to sketch the input signal above the output and
determine the output instantaneous values of the input.
VI
VM - V
VO
Clamper:
- a network is one that will “clamp” a signal to a different DC level.
+ C +
VI R VO
- -
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Clamper:
Steps in analyzing a clamping network:
1.) Start the analysis of clamping network by considering the part of the
input that will forward bias the diode.
2.) During the period that the diode is in the “on” state, assume that the
capacitor will charge up instantaneously to a voltage level determined by
the network.
3.) Assume that during the period when the diode is in the “off ” state the
capacitor will hold on to its established voltage level.
4.) Throughout the analysis maintain a continual awareness of the location
and polarity for VO to ensure that the proper levels for VO are obtained.
5.) Keep in mind the general rule that the total swing of the total voltage
must matched the swing of the input signal.
Example 1:
+ -
+ C +
VI VO
- -
10 V 0–T/2: Positive Half
VO = 0
VI
VC = 10 V
- 10 V
T/2–T: Negative Half
By KVL Diode is “ off “

VO
-Vi – Vc – Vo = 0
- 20 V Vo = - ( Vi + Vc )
Vo = - ( 10 V + 10 V )
Vo = - 20 V
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Example 2:
+
4V
Vo
10 V VI Vo
4V
- -16 V
0–T/2: Positive Half T/2–T: Negative Half
- Vi – Vc – Vo = 0
Vo = 4 V Diode is “ on “ state
Vo = - Vi – Vc
By KVL for Vc: Vo = -10 – 6

- Vi – Vc – Vo = 0
Vo = -16 V
Vc = 6 V
Voltage Multiplier
Increase the magnitude of a given voltage a a factor of n.
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Zener Diode:
+ + +
Vz Vz V
- - -
( Vz > V > 0 V )
“ on ” state “ off ” state
Case I: Vi and R fixed R
+ +
IR
- - RL
Iz IL
2 Steps in Analyzing a Zener Diode
1.) Determine the state of the Zener diode by removing it from the network
and calculating the voltage across the resulting open circuit.
2.) Substitute the appropriate equivalent circuit and solve for the desired
unknowns.
By Voltage Divider:
V = VL = RL VI If V > Vz , the zener diode is “ on ”.
RL + R V L = Vz
If V < Vz , the zener diode is “ off “.

By KCL:
V = VL
IR = Iz + IL
IR = VR / R = V – VL
R
I L = VL Pz = Iz Vz
RL
Example no. 1
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1 KΩ
16 V
Vz = 100 RL = 1.2 KΩ
Pzm = 30 mW
Determine: IR , Iz , IL , VL, VR and Pz
V = ( 1.2 KΩ ) 16 V = 8.37 V V < Vz ; “ off “ state; VL = V VL = 8.37 V

1.2 KΩ + 1 KΩ
For IL: For Iz:

IL = VL = 8.37 V = IL = 7.26 mA IZ = I R – IL
RL 1.2 KΩ
= 7.27 mA – 7.26 mA
For VR: For IR:
VR = Vi - VL IR = VR / R Iz = 0.01 mA
= 16 V – 8.73 V = 7.27 V / 1 KΩ
For Pz:
VR = 7.27 V IR = 7.27 mA Pz = I R = ( 0 A ) 10 V
Case II: Fixed Vi , RL variable Pz = 0 W
VL = Vz = RL Vi
R RL R
Vi RL
RL min = R Vz
Vi - Vz
For IL max :
For IR :
RL = VL
IL IL min = VL
IL max = VL RL max
RL min
IL min = IR – Iz max
For IR :
IR = V R
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Example: 1 KΩ
a. Determine the range of RL and

IL that will maintain VL = 10 V
50 V RL b. determine the max. voltage

rating of the diode.
Sol’n :
IR = VR / R = Vi – VL
a. RL min = ( 1 KΩ ) ( 10 V ) R
50 V – 10 V = 50 V – 10 V
1 KΩ
RL min = 250 Ω
IR = 40 mA
For IL min :
IR = IL + Iz RL max = VL IL max = VL
IL min RL min
IL min = IR - Iz max
= 10 V = 10 V
IL min = 40 mA – 32 mA 8 mA 250 Ω
IL min
Range for R=L8: mA RL max
from 250 Ω to 1.25 KΩ= 1.25 KΩ IL max = 40 mA
Range for IL : from 8 mA to 40 mA
b. P max = ( IL max )2 ( RL max ) 2 Pz max = Vz Iz max
= ( 40 mA ) 2 ( 1.25 KΩ ) 2 = ( 10 ) ( 32 mA )
P max = 20 W Pz max = 320 mW
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Unit 4:
BJT Transistor Fundamentals
Transistor:
Definition:
• contraction of transfer and resistor
• a three terminal device w/c is capable of amplifying signal.
Short History:
• In 1904, the vacuum tube was introduced by J.A. Fleming
• In 1906, Lee De Forest added a third element called control grid to the
vacuum tube resulting in the first amplifier, the TRIODE.
• 1930’s, the four element tetrode and five elements punjode gained
prominence in the Electronic Industry.
• On December 23, 1947 the transistor was introduced
1.) Walter H. Brattain
2.) John Bardeen
Bipolar Junction Transistor ( BJT )

• “Bipolar” because they are two different types of semicon watts namely
N and P types and because they are opposite polarity biasing “voltage”.
• “Junction” because they use current carrying PN junction.
• It consist of a three-layer semiconductor device of either 2N and 1P type
layer of materials ( NPN ) or 2P and 1N type layer of materials (PNP
type).
Two types of Transistor

1. PNP Transistor
2. NPN Transistor
PNP Transistor
construction IE symbol IC IE IC
P P E C P N P
0.001 in IB IB
0.150 in B
NPN Transistor
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IE IC
N P N
IL
Basic Operation
• Forward – biased PN Junction is basically a low resistance path for
current to flow conversely a reverse biased PN Junction represents a
high resistance path.
P N P
VBE = 0.7 V
Three Transistor Current

1. IB = Base Current
2. IC = Collector Current
3. IE = Emitter Current
Majority and Minority flow of PNP Transistor

majority Icc minority
IE IC
Relationship
IB IE = IB + IC
Note: Collector Current is composed of two component

1. majority current
2. minority current IC = I majority + I minority
Amplification factor
1. Alpha , short circuit amplification factor
• The ratio of change in current collector to change in Emitter
Current.
 = ( ∆ IC / ∆ IE ) VCB = constant  = IC / IE
2. Beta β, common emitter-forward current amplification factor.
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β = IC / IB IC = β IB
Transistor Amplification Action
IE IC
P N P
IC ≈ IE
20 Ω 100 KΩ R = 5 KΩ IB = ( 1 + β ) IE
P = I2 R P = I2 R
❖ This is one basic principle of w/c power gain is produced by a transistor.

In effect, the transistor has transferred thru signal from low resistance (
input ) to a high resistance ( output ) thus, the word transistor relates the
concept of transfer and resistance.
Transistor Configuration
1) Common – Base Configuration ( CB )

➢ the base is common to both the input and the output side
of the circuit.
IE PNP IC IE NPN IC
E C E C
IB IB
B B
Basic Feature of Common – Base Configuration:

a) The input signal is introduced into the emitter and the output is taken
from the collector circuit.
b) The input circuit is very low impedance.
c) The output circuit is high impedance.
d) Current gain is always lesser than 1.
e) There is no phase reversal between the input and the output signal.
2) Common – Emitter Configuration ( CE )

➢ the emitter is common to both input and output circuit.
IC IC
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C C
IB IB
B B
IE IE
E E
NPN Transistor PNP transistor
Basic Feature of Common – Emitter Amplifier:

a) The input signal is introduced to the base and the output is taken from
the collector circuit.
b) The input circuit is low resistance.
c) The output circuit is medium to high impedance.
d) Current gain is always greater than 1.
e) There is 180˚ phase reversal between the input and the output signal.
3) Common – Collector Configuration

➢ the collector is common to both the input and the output
circuit.
E E
IB IE IB IE
B B
IC IC
C C
PNP Transistor NPN Transistor
Basic Feature of Common – Collector Configuration:

a) The input signal is introduced into the base circuit and the output is taken
from the emitter circuit.
b) Input Impedance is very low.
c) Output Impedance is relationally low.
d) Voltage gain is less than 1.
e) No phase reversal between the input and output.
Relationship between  and β
 = β β = 
1+β 1–
3 Transistor Regions of Operation:
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1.) Saturation – is the condition in w/c voltage across the device is as small
as possible with the current in the device path reaching a limiting or
saturating value.
Condition:
B – E = Forward Bias
B – C = Forward Bias
2.) Cut-off – is the condition in w/c the device no longer conducts.

Condition:
B – E = Reverse Biased
B – C = Reverse Biased
3.) Linear – is the condition in w/c the device conducts at normal operator,
that is an amplifying action occurs, a common region of operation when
a transistor is used as an amplifies.
Condition:
B – E = Forwad Biased
B – C = Reversed Biased
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Unit 5:
BJT Transistor Biasing
DC Biasing of BJT :
Reason for Biasing:

• To turn the devices for amplification and place it in operation in the region
of its characteristics w/ in the device operates most linearly.
• To locate the Q. Point ( Quiescent Point ).
1.) Fixed Biased
Vcc VB E = 0.7 V
IC = β IB
IC IE = ( 1 + β ) IB
IB
RB RC For IC :
For IB :
KVL at input side: IC = β IB
Vcc - IB RB - VBE = 0
IB = Vcc – VBE For IE :

IE
RB I E = ( 1 + β ) IB
For VCE : For VE : For Vc : For V B :

KVL at output side
Vcc – IC RC - VCE = 0 VE = IE RE Vc = VCE + VE VB = VBE + VE
VCE = Vcc - IC RC VE = 0 V Vc = VCE VB = VBE
Example:
12 V Determine all parameters value: IB , VCE,
IC , IE , VE and VB .
For IB :
12 – IB ( 240 K ) – VBE = 0
240 KΩ 2.2 KΩ
IB = 12 – 0.7
β = 100 240 K
IB = 47.08 mA
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For IC : For IE : For V E :
IC = 100 ( 47.08 mA ) IE = ( 1 + 100 )( 47.08 mA ) VE = IE RE
IC = 4.7 mA IE = 4.75 mA VE = 0 V
For VCE : For V B :

KVL at output: V B = VBE + VE
12 – ( 4.7 mA )( 2.2 K ) – VCE = 0
VB = VBE
VCE = 12 – 10.34
VB = 0.7 V
VCE = 1.66 V
2.) Emitter – Stabilizer Ckt :
Vcc For IB :
KVL at input side:
Vcc - IB RB - VBE – IE RE = 0
RB RC I E = ( 1 + β ) IB
Vcc - IB RB - VBE – ( 1 + β ) IB RE = 0
Vcc - VBE = IB ( RB + ( 1 + β ) RE
IB = Vcc - VBE
RE RB + ( 1 + β ) RE
For IC : For Vc :
Vc = VCE + VE
IC = β I B
Vc = Vcc – IC RC
For VCE : For VB : For VE :

By KVL:
Vcc - IC RC - VCE - IE RE = 0 VB = VBE + VE VE = IE RE
VCE = Vcc - IC RC - IE RE
Example:
20 V Determine: IB , IC , IE ,VBE , VC , VB and VE
For IB : By KVL
20 – IB ( 430 KΩ ) - VBE – IE ( 3 KΩ ) = 0
430 KΩ 5 KΩ
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IE = ( 1 + β ) IB
β = 50
20 – IB (430 KΩ ) - VBE – ( 1 + β ) IB (3 KΩ ) = 0
20 – 0.7 = IB (430 KΩ + ( 1 + 50 ) ( 3 KΩ )
IB = 20 – 0.7
3 KΩ (430 K )+ ( 51 )( 3 K )
IB = 33.1 µA
For IE : For VCE :

IE = ( 1 + β ) IB 20 – IC ( 5 K ) – VCE – IE ( 3 K ) = 0
= ( 51 ) ( 33. 1 µA ) VCE = 20 – ( 1.66 mA )( 5 K ) – ( 1.69 mA )( 3 K )
IE = 1.69 mA VCE = 6.63 V
For IC : For VC :
IC = β IB VC = VCE + VE
= 50 ( 33. 1 µA ) = 6.63 + ( 1.66 mA )(3 K )
IC = 1.66 mA VC = 11.7 V
For VB : For VE :
VB = VBE + VE VE = IE RE
VB = 0.7 + ( 1.69 mA )( 3 K ) = ( 1.69 mA )( 3 K )
VB = 5.77 V VE = 5.07 V
Determine: RC , RB , RE , V CE and VB
12 V
RE = VE / IE = 2.4 V / 2.03 mA
2 mA
RE = 1.2 KΩ
RB RC
Vc = 8 V For IB :
IC = β I B
β = 80
2.4 V IB = IC / β = 2 mA / 80
IB = 25 µA
RE
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For RC :
For IE : For V CE : VC = Vcc – IC RC
IE = ( 1 + 80 )(25 µA ) VCE = VC - VE
RC = 12 - 8
IE = 2.03 mA = 8 V – 2.4 V 2 mA
VCE = 5.6 V RC = 2 KΩ
By KVL:
12 – IB RB – VBE – 2.4 = 0 For VB :
VB = VCC - IB RB
RB = 12 – 0.7 – 2.4
25 µA V B = 3.1 V
RB = 356 KΩ
3.) Voltage – Divider Bias

Vcc Vcc
R1 RC
RT
R2 RE
VR2
For VR2 : For R T :

By Voltage – Divider
RT = R1 ( R2 ) RT = R1 R2
VR2 = Vcc R2 R1 + R2
R1 + R2
R2 For IC :
VR2 = VB = Vcc
R1 + R2 IC = β IB
For IB : By KVL : For IE :

VR2 - IB RT – VBE – IB RE = 0
IE = ( 1 + β ) IB
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IE = ( 1 + β ) IB
IE = IB + IC
VR2 - IB RT – VBE – ( 1 + β )IB RE =0
IB = VR2 – VBE For VCE :

RT + ( 1 + β ) RE Vcc – IC RC - VCE – IE RE = 0
IC ≈ IE
For VC :
VCE = Vcc – IC ( RC + RE )
VC = VCE + VE
VC = VCC - IC RC For VB : For VE :
VB = VBE + VE VE = IE RE
Example :
18 V
Determine: IB , VCE , VC and IC
R2
39 KΩ 3.3 KΩ VR2 = Vcc
R1 + R2
8.2 K
β = 120 = 18
8.2 K + 39 K
VR2 = 3.13 V
8.2 KΩ 1 KΩ
RT = R1 ( R2 ) For IB : For IC :
R1 + R2 IB = VR2 – VBE IC = β IB
RT + ( 1 + β ) RE
= 39 K ( 8.2 K ) = 120 ( 19 µA )
39 K + 8.2 K = 3.13 – 0.7
6.78 K + ( 1 + 120 ) 1 K IC = 2.28 mA
RT = 6.78 KΩ
IB = 19 µA
IE = ( 1 + β ) IB For VCE :
VCE = Vcc – IC ( RC + RE )
= ( 1 + 120 ) 19 µA
= 18 – 2.28 mA ( 3.3 K + 1K )
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IE = 2.3 mA
VCE = 8.2 V
For VC :
VC = VCC - IC RC
= 18 – ( 2.28 mA )( 3.3 K )
VC = 10.48 V
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Unit 6:
BJT Transistor Amplification
A model is the combination of circuit elements, properly chosen, that best
approximates the actual behavior of a semiconductor device under specific operating
condition
Models:
a. Re model
b. Hybrid equivalent
Steps:
1. Short all DC Sources to the ground
2. Replace all the capacitors w/ a short circuit
3. Replace an open circuit for the resistor w/c is parallel w/ the capacitor
4. Replace the transistor w/ its equivalent model
5. Solve for the different AC parameters
AC Parameters:
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1. Input Impedance (Zi) = The impedance seen at the input side.
Vi
Zi = ----
Ii
2. Output Impedance (Zo) = The impedance seen at the output side.
Vo
Zo = ----
Io
3. Voltage gain (Av) = The ratio of the output voltage and the input voltage.
Vo
Av = ----
Vi
4. Current Gain (Ai) = The ration of the output and input current.
Io
Ai = ----
Ii
5. Power Gain (Ap) = The product of the voltage gain and current gain.
Ap = AvAi
For DC Analysis:
re Transistor Model:
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re transistor modeling
CB BJT Transistor
Re model for CB configuration
ID = IS [ e KVD / TK – 1]
dID = dIS [ e KVD / TK –
1]
dVD dV
dID = k
dVD TK
TK = 273k + TC
@room
Temp.
AC Equivalent TC = 25ºC or
27ºC
k = 11,600 n=1
n
k = 11,600
TK = 300k or 298k
dID = 11,600
dVD 298
1 V
38.93 I
RAC = VD
ID
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= 1
38.93
The subscript e of re to emphasize that it is the DC level of Emitter Current

that determine the AC level of the diode resistance.
Common Emitter Configuration
CE Transistor
Using KVL:
IE = I B + I C
IC = βIB
IE = IB + βIB
IE = IB(1+ β)
IE ≈ βIB
For Zi:
Re Equivalent Model Vi Vi = IE re
Ii Vi = βIBre
Ii = IB
βIBre
IB
Zi = βre
Approximate Equivalent Circuit
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AC Equivalent Circuit
For Equation 1:
If we set Vo = 0 (short circuit the output terminal)
h11 = Vi/Ii
hii = is an impedance parameter with the unit ohm
= also called short circuit input, impedance parameter
11 = defined the fact that the parameter is determined by the ratio of the
quantities measured at the input terminal
if we set io = 0
h12 = Vi/Vo unit less
h12 = called the open circuit reverse transfer quantity determine by a
ratio of input and output measurements
for equation 2
if we set Vo = 0 (shorting the output terminal)
h21 = Io/Ii unit less
h21 = also called the short circuit forward transfer current ratio parameter
21 = indicates that it is a transfer parameter
22 = reveals that it is determine by the ratio of the output parameters
HYBRID EQUIVALENT CIRCUIT

h11 = input resistance (hi)
h12 = reverse transfer voltage ratio (hr)
h21 = forward transfer current ratio (hf)
h22 = output conductance (ho)
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Since hr is normally relatively small quantity its removed is approximately by
hr = 0 hrVo = 0, resulting in a short Ckt. Equivalent for the feedback elements
1/ho is often large enough permitting its replacement by an open circuit.
AC EQUIVALENT CIRCUIT COMPARISON
1. COMMON BASE CONFIGURATION
2. COMMON EMITTER CONFIGURATION
BJT SMALL SIGNAL ANALYSIS
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1.Common – Emitter Fixed Bias Configuration
Solve Zi, Zo, Av, Ai, Ap For Zi:

Zi = 470k  // (100) (10.79)
re = 26mv/Ie = 1.08 k 
= 26 mv/241mA For Zo:
re = 10.79  Zo = 3k 
For Av:
KVL : Av = Vo/Vi
12V – Ib(470 k  ) – 0.7V = 0 = -3k  /10.79
IB = 12.07V/470k  = 24.05  A For Ai:
IE = Ic Ai = Io/Ii
IE =  Ib = 100[1 + 100(10.79
 )]
= 100 (24.05  A) = 99.77 = 100
IE = 2.41mA For Ap:
Ap = AiAv
= (99.77)(-278)
= -27,736 .06
VOLTAGE DIVIDER CONFIGURATION
For Zi: For Zo:

Zi = Rb1//Rb2//  re Zo = Rc
For Ap: For Ai:
Ap = IiAv [BR1/R1 +  re][-Rc/Re] Ai = Io/Ii
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Solution from DC analysis For Zi:
 re > Io Rb2 Zi = 36k  //8.2  //1.04k 
90 (1.5k) >10 (8.2k) Zi = 899.87 
135 k > 82k(satisfy)
VB = Vcc [Rb2/Rb2 + Rb1] For Av:
VB = 22[8.2k  /8.2k  +36k  ] Av = -Rc/re
VB = 4.08 = 6.8k  /11.5
= -591.30
VE = VB – VBE
= 4.08 – 0.7V For Ai:
VE = 3.38V Ai = Io/Ii
= 90(6.7k  )/6.7k 
re = 26mV/IE = 77.91
= 26mV/2.25mA
re = 11.5  For Ap:
Ap = AiAv
 re = 90(11.5) = (77.91) (-591.3)
 re = 1.04 k  = -46, 068.2
CE – EMITTER BIAS CONFIGURATION
For Zi:
By KVL
Vi - IB  re – IERE = 0
IE =  IB
VI - IB  re -  IBRE = 0
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VI/IB =  (re + RE)
Zi = RB//Zb
For Av:
Ai = Io/Ii
Ai =  [RB/RB+ZB]
For Zo:
Zo = Rc
For Av:
Av = -  Rc/ZB
For Ap:
Ap = AiAv
= -  [RB/RB+Zb] [  Rc/Zb]
EXAMPLE :
re = 26mV/IE For Zi:

= 26mV / 4.31mA Zi = 470k  //Zb
re = 6  = 470k  /67.9k 
Zi = 59.33k 
 re = (120)(6)
= 720  For Zo:
Zo = 2.2 k
For Av: For Ap:

Av = -  [1/Zb] RL Ap = AiAv
= -120 [2.2k/67.9k] = (104.85) (-3.89)
Av = -3.89 Ap = 407.87
EMITTER FOLLOWER CONFIGURATION
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For Zi: For Zo:
Zi = Rb//Zb Zo = RE//re
Zb =  (re + RE)
For Av:
For Ai: Av = Vo/Vi
Ai = Io/Ii Av = RE/(RE+re)
Ai = [Rb/Rb+Zb] [-  ]
EXAMPLE:
AC ANALYSIS:
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DC ANALYSIS:
 RE > Io R2 Zb = 200(27.9 + 2k)
200(2k) > Io(8.2k) = 405.58k 
400k > 82k(satisfy)
VR2 = VB = 20 [8.2k/8.2k+56k] For Zi:
VB = 2.55V Zi = 7.15k  //405.58k 
= 7.03k 
VE = VB – VBE
= 2.56V – 0.7 For Zo:
= 1.857 Zo = RE//re
= 2k//27.9 
IB = IE /  = 27.52 
= 4.65  A For Av:
Av = 2k/2k + 27.9k
re = 26mV/ IE = 0.986
= 26mV/ 0.93mA
= 27.9  For Ai:
Ai = [7.15k/7.15 + 405.58k] –
200
= -3.47
COMMON BASE CONFIGURATION
For Zi: For Ai:

Zi = RE/re Ai = -  [RE/RE+re]
For Zo:
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Zo = Rc
For Av:
Av =  Rc/re
EXAMPLE:
DC ANALYSIS:
5V – 0.7V – IE(3.9) = 0 For Av:

IE = 5V – 0.7V / 3.9k Av =  Rc / Re
= 1.1mA = 150.28
re = .26mV / 1.1mA For Ai:

= 23.64  Ai =  [RE / RE + re]
= 0.99 [3.9/3.9k +23.64 ]
COLLECTOR FEEDBACK CONFIGURATION
For Zi: KCL @ mode A

Zi = Vi/Ii IB = Ii + If
By KVL From input to Output Vo= - [  Ib]Rc
Vi + IfRf – Vo = 0
If = Vo – Vi / Rf KCL @ mode B
If = Vo – Vi / Rf Io = Ic + If
If = -Vi /Rf [Rc/re+1] Io =  Ib
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Zi =  re / 1 +  re/Rf(Rc/re+1) For Zo:
Zo = Rf // Rc
For Av:
Av = -Rc/re
EXAMPLE:
By KVL: KCL @ mode A

12V – Ic (3.9k) – Ib(220) – 0.7 = 0 IB = Ii + If
but Ic =  Ib
12V -  Ib(3.9k) – Ib(220) – 0.7 = 0 KCL @ mode B
IB = 12 – 0.7 / 120 (3.9k)+220k Io = Ic + If
= 16.42mA Io =  Ib + If
If = -Vi/Rf [Rc/re+1]
IE = Ic
Ic =  IB
IE = 1.97mA
For Zi:
Zi =  re/1+  re/Rf(Rc/re+1)
= 120(13.2)/1+120(13.2)/20k(3.9k/13.2+1)
= 505.32
For Zo: For Ai:

Zo = Rf/Rc Ai =  Rf /  re+RF+  Rc
= 220k//3.9k =
120(220k)/120(13.2)+220k+120(3.9k)
= 3.8 k = 38.28
For Ai:
Ai = -Rc/re
= -295.45
PARAMETER Common Base Common Emitter

Common Collector
Ap Moderate Highest
Moderate
Av Highest Moderate
Highest
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Zi Lowest Lowest Highest
Zo Lowest Lowest Lowest
Phase Inversion Highest 180
None
Application Rf Amp. Universal
Isolation Amp.
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Unit 7:
FET Transistor Fundamentals
Field Effect Transistor:
FET
• Field Effect Transistor
• Unipolar device
• Three terminal device containing one basic PN junction.
The FET’s terminals are:

1. gate – equivalent to the base of the transistor.
2. drain – equivalent to the collector terminal of the transistor.
3. source – equivalent to the emitter of the transistor.
2 Types
1. J FET ----------- junction FET
2. MOSFET ------- Metal Oxide Semiconductor FET
a. Depletion Mosfet
b. Enhancement Mosfet
General Comparisons between FET and BJT:

1. The FET has extremely high input resistance with about 100 M ohms
typical ( BJT input resistance typically 2 K ohms ).
2. The FET has no offset value when used as a switch.
3. The FET is relatively immune to radiation, but the BJT is very sensitive.
4. The FET is less noisy than BJT.
5. The FET can be operated to provide greater thermal stability than BJT.
6. FET is smaller than BJT.
7. FET has smaller gain bandwidth than BJT.
8. FET has greater susceptibility to damage in handling the FET.
JFET construction and symbols
1. N channel : construction and symbol

S D
Gate ( G )
G
P
Source ( S ) Drain ( D )
n - material
P
Ohmic contact
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Shockley’s Formula:
2
VGS
ID = IDSS 1 -
Vp
2. P channel : construction and symbol

S D
Gate ( G )
G
N
Source ( S ) Drain ( D )
p - material
Basic Operation of JFET:

- VDS + VDD = VDS
S D VGS = - VGG
ID
ID ID
VGS - VDD
VGG
+
The supply voltage , VDD , provides a voltage across drain source , VDS , which
results in current ID , from drain to source ( electrons in an n channel actually
move from the source ). This drain current passes through the channel
surrounded by the p type gate. A voltage between gate and source, VGS , is to
be set by a voltage supply, VGG. Since the polarity of this gate – source voltage
will reverse bias the gate – source junction, no gate current will result. The effect
of the gate – source voltage will be to create a depletion region in the channel
and thereby reduce the channel which to increase the drain – source resistance
resulting in less drain current.
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Pinch – off action due to channel current
Back – biased
depletion region
n P +
S ID + D
+
+
ID P ID
+
Current VDD
through VGS = 0 V -
n - channel
Pinch off of channel

occurs when depletion
region is completed
n P across channel.
S D
ID
ID P ID
+
VDD
-
Drain – Source characteristics
• a plot of drain current versus the drain – source voltage.
a. N – channel b. P – channel
ID ( mA ) VGS = 0 V D
ID ( mA ) G
IDSS VDD ID = IDSS
S
VGS = 0 V
VDS IDSS
+1V
VGS = 0 V
+2V
0 V DS ( volts ) 0 V DS ( volts )
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JFET Transfer characteristics
• plot of drain current as a function of gate – source voltage
a. n – channel ID ( mA )
2
VGS curve represents IDSS
ID = IDSS 1-
VP
less than VP
IDS = 0 A
VP 0 VGS ( volts )
JFET Parameters
IDSS ------ drain – source saturation current.

VP ------ VGS ( off ) , pinch – off or gate source voltage.
B VGSS --- device breakdown voltage.
Gm ------ Gfs , device transconductance.
rds ------- drain – source resistance when the device is turned on.
Gm = Gfs = ( ∆ ID / ∆ VGS ) I VDS = 0
= Gmo ( 1 – VGS / VP ) = 2 IDSS

I VP I
where Gmo is the maximum ac gain parameter of the JFET.
Examples:
1. Determine the drain current of an n channel JFET having a pinch off
voltage VP = -4 volts and drain – source saturation current = 12 mA
at VGS = 0 V and VGS = -3 volts at VGS = -5 V
Sol’n :
VP = -4 V For VGS = -3 V
IDSS = 12 mA
For VGS = 0 V ID = 12 mA ( 1 – -3 )2
-4
ID = 12 mA ( 1 – 0 )2
-4 ID = 0.75 mA
ID = 12 mA
2. Calculate the transconductance , Gmo , of a JFET with IDSS = 12 mA

and VP = -4 volts at bias point VGS = -1.5 V.
Sol’n:
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Gm = 2 IDSS VGS
1-
I VP I VP
= 2 ( 12 mA ) ( 1 - - 1.5 )
4 -4
Gm = 3.75 mS
3. What is the value of IDSS for an n channel JFET with Gmo = 4.5 mS
and VP = -3 volts.
Sol’n:
Gmo = 4.5 mS IDSS = Gmo ( I VP I )
VP = -3 V 2
= 4.5 ( 3 )
2
IDSS = 6.75 mA
4. What is the value of VP of a p channel JFET having IDSS = 12 mA

and Gmo = 6500 µS.
Sol’n:
VP = ? Gmo = 2 IDSS .
IDSS = 12 mA I VP I
Gmo = 6.5 mS VP = 2 IDSS .
Gmo
= 2 ( 12 mA )
6.5 mS
VP = 3.69 V
5. Determine the value of Gmo for a p channel JFET having VP = -3.8 V

and IDSS = 6.8 mA.
Sol’n:
VP = 3.8 V Gmo = 2 IDSS .
IDSS = 6.8 mA I VP I
= 2 ( 6.8 mA )
3.8 V
Gmo = 3.58 mS
6. A p – channel JFET with IDSS = 13.5 mA , VP = 5 volts is operated at

ID = 9.5 mA. What is the value of Gm at this operation point.
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Sol’n:
IDSS = 13.5 mA ID = IDSS ( 1 - VGS )2 Gm = 2 IDSS ( 1 - VGS )2
VP = 5 V VP VP VP
ID = 9.5 mA VGS = VP ( 1 - √ ID ) = 2 ( 13.15 mA ) (1 – 0.81 )2
Gm = ? IDSS 5 5
= 5 ( 1 - √ 9.5 mA )
13.15 mA
Gm = 4.53 mS
VG = 0.81 V
7. What is the maximum value of transconductance of a JFET ( VP = -

4 volts if the transconductance is 4500 µS when operated at V GS = -
1 volts.
Sol’n:
VP = -4 V Gm = 2 IDSS . ( 1 - VGS )2 Gmo = 2 IDSS .
Gm = 4.5 µS I VP I VP I VP I
VGS = -1 V IDSS = Gm I VP I = 2 ( 12 mA )
2 ( 1 - VGS )2 4
VP
= ( 45 mS )( 4 V ) Gmo = 6 mS
2 ( 1 - -1 )2
-4
IDSS = 12 mA
MOSFET
• Metal Oxide Semiconductor FET
• Gate terminal insulated from the channel
Depletion MOSFET
• channel is physically constructed and current between drain and source
will result if a voltage is connected across the drain source.
Enhancement MOSFET
• no channel is formed when the device is constructed. A voltage must be
applied to the gate to develop a channel so that a current results when
a voltage is applied across the drain – source terminal.
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Constructions:
a. depletion b. enhancement
Gate S D
Source (G) Drain G
(S) (D)
SiO2
( isolating
Dielectric )
p – substrate P - substrate
Symbols:
a. depletion ( n channel ) b. enhancement ( n channel )
D D
G G
S S
FET Biasing ( DC Analysis )
IQ = 0 A
ID = IS
For JFET and D – MOSFET

Shockley’s Formula:
ID = IDSS ( 1 - VGS )2
VP
For E – MOSFET
ID = K ( VGS – VTH )2 w/r: K= ID ( on )

(VGS on – VTH )2
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Unit 9:
FET Transistor Biasing
1. ) Fixed Bias
VDD
For VGS : For VG :
- VGG – VGS = 0 VG = VGS + VS
RD
D VGS = - VGG VG = VGS
G
For ID : For VD :
RG S
ID = IDSS ( 1 - VGS )2 VD = VDD - ID RD
VP
VGG For VS : For VDS :

VDS = VD – VS
VS = 0 V
VDS = VD
Ex. Let RD = 2 KΩ VGG = -2 V VP = -8 V

VDD = 16 V IDSS = 10 mA
Determine: VGSQ , IDQ , VDS , VD , VG and VS
Sol’n:
For VGS : For IDQ : For V S :

-2 V – VGS = 0 IDQ = IDSS ( 1 - VGS )2
VP VS = 0 V
VGS = -2 V = 10 mA ( 1 - -2 V ) 2
-8 V
IDQ = 5.63 mA
For VDS : For V D : For VG :

VDD – ID RD – VDS = 0 VD = VDS VG = VGS + VS
VDS = VDD – ID RD = -2 V + 0 V
= 16 – ( 5.63 mA )( 2 KΩ ) VD = 4.74 V
VG = -2 V
VDS = 4.74 V
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2. ) Self – Bias
For VGS : For VDS :
VDD - VGS – IS RS = 0 VDD – ID RD – VDS – IDRS = 0
VGS = IS RS
ID = IS VDS = VDD – ID ( RD + RS )
RD
D VGS = ID RS
G
For ID : For VS :
S ID = IDSS ( 1 - VGS )2 VS = ID RS
VP
RG RS
For VD : For VG :
VD = VDD – ID RD VG = VGS + VS
or = ID RS + ID RS
VD = VDS + VS
VG = 0 V
Examples:
Given: VDD = 16 V VD = -6 V IDSS = 8 mA
RD = 3 KΩ RS = 1 KΩ RG = 1 MΩ
Determine: ID , VGS , VD , VS and VDS
Sol’n:
For ID : For V S :
ID = 8 mA ( 1 - - ID RS )2 VS = 2.6 mA ( 1 KΩ )
-6
ID = ( 6 - ID RS )2 VS = 2.6 V
8 mA 6
36 ( ID ) = 36 – 12 ID ( 1 KΩ ) + [ ID ( 1 KΩ )2 ]
8 mA For V GS :
4.5x10 ID = 36 – 12x10 ID + 1x10 ID
3 2 3 6 2 VGS = ( 2.6 mA )( 1 KΩ )
1x106 ID2 – 16. 5x103 ID + 36 = 0
VGS = -2.6 V
ID = - b - √ b2 – 4ac
2a
ID = (16. 5x103 ) - √ (16. 5x103 )2 – 4 (1x106 )( 36 )
2 (1x106 )
ID = 2.6 mA For VDS :

VDS = VD – VS
= 8.2 V – ( 2.6 mA )( 1 KΩ )
For VD :
VD = 16 – 2.6 mA ( 3 KΩ ) VDS = 5.6 V
VD = 8.2 V
57
st
3. Voltage Divider
VDD VDD
RD
+
IR1 R1 VR1 RD
RT
+
RS
R2 VR2 RS VG
IR2
For VG : By KVL:
For VGS:
VG = VR2 = VDD ( R2 ) VG – VGS – ID RS = 0
R1 + R2
VGS = VG – ID RS
For RT :
RT = R1 // R2 For VD : For VDS :
VD = VDD - ID RD VDS = VDD = ID ( RD + RS )

For ID : V D = VDS + ID RD
ID = IDSS ( 1 - VGS )2
VP For VS :
For IR1 and IR2 VS = ID RS
IR1 = IR2 = VDD

R1 + R2
Example:
Given: R1 = 2.1 MΩ R2 = 270 KΩ R D = 2.4 KΩ

RS = 1.5 KΩ VP = -4 V IDSS = 10 mA
Determine: IDSS , VGS , VP , VS , VDS and VG
58
st
For VG : For VD :
VG = VDD ( R2 ) VD = VDD – ID RD
R1 + R2 = 16 – 2.25 mA ( 2.4 K )
= 16 ( 270 K )
2.1 M + 270 K V D = 9.88 V
VG = 1.82 V
For ID :
ID = 10 mA [ 1 – 1.82 – ID ( 1.5 K ) ]2
-4
ID = [ 1 – ( 1.82 ) – ID ( 1.5 K ) ]2
10 mA -4 -4
ID = [ 1.46 – ID ( 1.5 K ) ]2
10 mA 4
16 ID = [ 5.84 – ID ( 1.5 K ) ]2
10 mA
1.6x103 ID = 34.11 – 17.52x103 ID + 2.25x106
2.25x106 – 19.12x103 ID + 34.11 = 0
ID = (19.12x103 ) - √ (19.12x103 )2 – 4 (2.25x106 )( 34.11 )

2 ( 2.25x106 )
ID = 2.55 mA For VDS :

VDS = VD – VS
= 9.88 – 3.83
For VGS :
VGS = 1.82 – 2.25 mA ( 1.5 K ) V DS = 6.05 V
VGS = -2.01 V
59
st
Unit 10:
FET Transistor Amplification
FET Small Signal Analysis
- The gate to source voltage controls the drain to source (channel)
current of an FET.
- The change in drain current that will result from the change in gate-
to-source voltage can be determined using the trans-conductance
factor Gm in the following manner:
ID = gmVGS
- The word “trans” reveals that it established relationship between the
output and input quantity.
- The root word “conductance” is determined by a voltage to current
ratio. G = 1 ; G = I
R V
 ID
gm =
VGS
Mathematical Definitions of gm:
ID d   VGS  
2
dID
gm = = =  IDSS1 −  
VGS dVGS dVGS   VP  
2
d  VGS 
= IDSS 1 − 
dVGS  VP 
2 IDSS  VGS 
gm = 1 −
VP VP 
For MAX value of gm:

Set VGS=0
2 IDSS  0
gmo = 1− 
VP  VP 
gmo =
2 IDSS
1 = 2 IDSS
VP VP
2 IDSS
gmo =
VP
Substituting the value of gm:
60
st
 VGS 
gm = gmo 1 − 
 VP 
gm = Yfs
Impact of ID on gm:
From Shockley’s Formula:
2
 VGS 
ID = IDSS1 − 
 VP 
2
ID  VGS 
= 1 − 
IDSS  VP 
ID  VGS 
= 1 − 
IDSS  VP 
 VGS 
gm = gmo 1 − 
 VP 
 ID 
gm = gmo  

 IDSS

If:
a.) ID=IDSS VGS = 0
gmo = gmo
IDSS
b.) ID =
2
IDSS / 2 1
gm = gmo = gmo =
2 IDSS 2
gm = gmo (0.707 gmo )
c.) ID = IDSS
4
IDSS / 4
gm = gmo
IDSS
1
gm = gmo
4
gm = gmo (0.5 gmo )
FET AC Parameters:
1. Input Impedance Zi = 
1
2. Output Impedance Zo = rd =
Yos
3. Voltage Gain Av
FET AC Equivalent Circuit:

61
“THE COUNTRY’S 1 POLYTECHNICU” st
G D
gm VGS
rd
VGS
S S
JFET Fixed-Bias Configuration:

VDD
RD
Vo
Vi
RG
VGG
G
Vo
gm VGS
RG VGS
rd RD
62
st
Determine: Zi, Zo and Av

For Zi:
Zi = RG
For Zo:
Zo = rd // RD
For Av:
Vo Vo = (gmV GS )(rd // RD )
Av =
Vi Vi = VGS
− ( gmV GS )(rd // RD )
Av =
VGS
Av = − gm(rd // RD )
Example:
VDD
Given: VDD = 20V
RD = 2 k 
IDSS = 10Ma
VP = -8V
Yos = 40 s
RD
RG = 1M  Vo
VGG = 2V
Vi
RG
Solution:
DC Analysis (KVL at input)

VGG
VGS = 0
− 2V − VGS = 0
VGSQ = −2V
63
st
2 G
 VGSQ  Vo
IDQ = IDSS1 − 
 VP 
gm VGS
RG VGS
rd RD
 −2
2
= 10 mA 1 − 
 −8
2
3
= 10 mA  
4
= 10 mA (0.5625 )
IDQ = 5.63mA
Solving for gm:
Formula:
2 IDSS  VGS 
gm = 1−
VP  VP 
2(10 mA )  − 2V 
= 1−
− 8V  − 8V 
10 mA  3 
=
4  4 
gm = 1.875 mS
For Maximum Trans conductance Factor:
Formula:
2 IDSS
gmo =
VP
2(10 mA )
=
−8
10 mA
=
4
64
st
gmo = 2.5ms
Solving for rd:
Formula:
1 1
rd = =
Yos 40 
rd = 25 k
Determine Zi , Zo & Av
Vi Vo
gm VGS
1M
VGS
rd = 25k 2k
Solution: Zi
Zo
For Zi:
Zi = 1M
For Zo: Set Vi = 0
Zo = rd // RD
1 1
= +
2k 25 k
Zo = 1851 .8 Zo  2k
For Av:
Vo = −(1.8ms )(− 2)(2k )

Vo Vo = 7.2
Av =
Vi
Vi = −2V
65
st
− (1.8ms )(− 2V )(2k )
Av =
− 2V
Av = −(1.8ms )(2k )
Av = −3.6
JFET Self-Bias Configuration:
1. Bypassed
VDD
RD
CD
Vo
CG
Vi
CS
RG RS
gm VGS
RG
rd RD
66
st
Determine Zi , Zo & Av :
Solution:
For Zi:
Zi = RG
For Zo:
Zo = rd // RD
For Av:
Vo Vo = − gmVGS (rd // RD )
Av =
Vi Vi = VGS
− gmV GS (rd // RD )
Av =
VGS
Av = − gm(rd // RD )
Example:
67
st
Given: VDD
VDD = 20V
RD = 3.3k
RD
RS = 1k
RG = 1M CD
Vo
IDSS = 8mA
VP = −6V
CG
Vi
Solution: CS
RG RS
Solving for gm:
Formula:
2 IDSS  VGS 
gm = 1−
VP  VP 
DC Analysis ( By KVL )
− VGS − IDRS
VGS = − IDRS
VGS = − ID (1k )
Solving for ID:
Formula:
2
 VGS 
ID = IDSS 1 − 
 VP 
68
st
 − ID (1k ) 
2
ID = 8mA 1 − 
 − 6V 
= 6 − ID (1k )
36 ID 2
8mA
4.5kID = 36 − 12000 ID + 1x10 6 ID 2

1x10 6 ID 2 − 16 .5kID + 36 = 0
Solving for ID1 and ID2:
16 .5k  (16 .5)2 − 4(1x10 6 )(36 )

ID =
(
2 1x10 6 )
16 .5 + 128 .25 x10 6

ID1 =
2 x10 6
ID1 = 13 .91mA
16 .5k − 128 .25 x10 6

ID 2 =
2 x10 6
ID 2 = 2.59 mA
Solving for VGS1 and VGS2:
VGS1 = −(13 .91mA )(1k )

VGS1 = −13 .91V
VGS 2 = −(2.59 mA )(1k )

VGS 2 = −2.59V
IDQ = −2.59 mA
VGSQ = −2.59V
Solving for gm:
69
st
2(8mA )  − 2.59V 
gm = 1−
− 6  − 6V 
gm = −1.52 m
Solving for gmo:
Since VGS = ON
2(8mA )
gm =
−6
gm = 2.67 m
gm VGS
RG
rd RD
For Zi:
Zi = 1M
For Zo:
70
st
Zo = (rd // RD )
Zo = 3.3k
For Av:
Vo Vo = − gmVGS(RD )
Av =
Vi Vi = VGS
Av = −1.52 ms (3.3k)
Av = −5.02
2. Un Bypassed
VDD
By KCL:
Set Vi = 0
gmV GS = ID + IO
RD
− ID = IO
VO = − IORD Vo
VO = − IORD
Vi
RG RS
For Zi:
Zi = RG
For Zo:
71
st
Vo
Zo =
Io
− IDRD gm VGS
Zo =
− Io
Zo = RD RG
ID
RD
Vo
RS
Io + ID Io
For Av:
Vo = − IDRD
Vo Vi = VGS + VRS
Av =
Vi Vi − VGS − VRS = 0
Vi = VGS + gmV GSRS
− gmRD
Av =
1 + gmRS
72
st

ECEN 201 Electronics 1 Electronic Devices and Circuit

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Republic of the Philippines

POLYTECHNIC UNIVERSITY OF THE PHILIPPINES

INSTRUCTIONAL MATERIAL FOR

Engr. ROSELITO E. TOLENTINO

UNIT II – Diode Fundamentals and Biasing

UNIT III - Diode Application

UNIT IV – BJT Fundamentals

UNIT V – BJT Biasing

UNIT VI – BJT Amplification

UNIT VII – FET Fundamentals

UNIT VIII – BJT Biasing

UNIT I X – BJT Amplification

Lesson 1: Classification of Materials:

1. Conductor – a substance, body on materials w/c has more electrons that

2. Insulator – a substance, body on materials w/c has characteristics that is

Example: glass, mica, and hard rubber.

3. Semiconductor – a substance, body on materials that has a characteristics

1.) Elementary Semiconductor (IV A)

2.) Compound Semiconductor (III A)

Composition/ Elementary Particles:

Particles Mass at test (kg) Charge Coulomb

Electron 9.1096 X 10 -23 - 1.6020 X 10-19

1.) Atomic Mass or Weight ( A ) – approximately the sum of the number of

3.) Valence Electrons – electrons at the valence shell.

4.) Valence Shell – the outermost shell.

Energy Gap Comparison:

Energy Energy Energy

Conduction Band Conduction Band

INSULATOR SEMICONDUCTOR CONDUCTOR

Lesson 2: Atomic Structure Of Semiconductor:

1. Ionic Bonds or Electrovalent Bonds – results from attractive forces between

Covalent Bonding of Semiconductor:

Covalent Bonding of the Silicon atom

Intrinsic Carrier – free electrons in a material due only to natural causes,

Ambient temperature – is the temperature of the surrounding air ( usually 27˚

Recombination – the merging of a free electrons and a hole inside a silicon

Lesson 3: DOPING PROCESS

Doping Process – adding a pentavalent or trivalent impurities to an intrinsic

Two Types Of Impurities:

1.) Pentavalent Impurities – w/ five valence electrons ( donor atom ) such as

2.) Trivalent Impurities – w/ 3 valence electrons ( acceptor atom ) such as Boron

Two Types of Semiconductor:

1.) Intrinsic Semiconductor

Extrinsic Semiconductor can be

Doped Semiconductors ( Extrinsic Materials)

Some reasons why Si & Ge are mostly used:

1. Can be manufactured to a very high purity level.

Construction & Symbol

A.) No Bias – no applied voltage

1. Depletion Region – the region of

Reverse Salvation Current Is – the

Diode Equivalent Circuit:

Type Model Characteristics

Parallel & Series-Parallel Configuration:

Determine current I & VR

Determine I and VO of the network:

Rectification – the process of converting alternating current to direct current

1. Half – Wave Rectifier

Half Wave Rectifier using ideal diode