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Paper / Subject Code: 51222 / Electronics Devices and Circuits

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June 6, 2024 02:30 pm - 05:30 pm 1T01033 - S.E.(Electronics and Telecommunication )

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(SEM-III)(Choice Base Credit Grading System ) (R- 19) (C Scheme) / 51222 - Electronics

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Devices and Circuits QP CODE: 10057487

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Time: 3 hour Max. Marks: 80

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=====================================================================

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Q1 is compulsory.

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Attempt any three from Q2 to Q6.

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Q1 Solve any Four 5 marks each

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A Explain the operation of a semiconductor pn junction diode with the help of VI

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1
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C

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characteristics.

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Explain Miller’s capacitance theorem.

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C What is the effect of coupling and bypass capacitors on the frequency response of
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a single stage amplifier?

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D What is crossover distortion in Class B power amplifiers?

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E Explain the working of a two transistor constant current source using E-MOSFET.

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5

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10 marks each

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A Draw the voltage divider biasing circuit for JFET and derive the quiescent point

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(VDSQ,IDQ) equations.
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1

B Draw a small signal equivalent circuit of the given circuit in fig. 1 and derive the
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expression for voltage gain, input impedance and output impedance.

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A
A

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A

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A0
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1

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AX
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5
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A

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52

Fig. 1
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AX

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25

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AX

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52

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57487 Page 1 of 3
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X525Y1A0C0AX525Y1A0C0AX525Y1A0C0AX525Y1A0C0A
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25

1A

52
 AX A0 5Y 25 0A
52 C0 1A Y1 X5
5Y A X5 0C A 0C 25
25 0A 1A 0A Y1
Y1 X5 0C 25 A0
Y1 X5 C0
A0
C0
25
Y1
0A
X5 A 0C 2 5Y AX
AX A0 25 0A 1A 52
1A 52 C0 Y1 X5 0C 5Y
0C 5Y AX A0 25 0A 1A
0A 1A 52 C0 Y1 X5 0C
25 0A

B
5Y

A
0C AX A0

B
A

57487
X5

Q4
Q3
25 0A 1A 52 C0 Y1 X5
Y X 0 C 5 Y AX A0 25
0A 1A 52 0 1 5 C 0 Y1
X5 0C 5Y AX A0
C0
25
Y1 A X5 A0
25 0A 1A 52 C0
Y1 0C 5Y AX A0 25
A0
X5
25 0A 1A 52 C 0 Y 1
AX
52 C0 Y1 X5 0C 5Y A X A 0
52
5Y
5Y AX A0 25 0A 1A 52 C0 1A
5Y
efficiency.
1A 52 C0 Y1 X5 0C AX 0C
0C 5Y AX A 0 25 0 A 1 A 5 2 0A
0A 1A 52 C0 Y1 X5 0C 5 Y X5
X5 0C 5Y AX A0 25 0A 1A 25
25 0A 1A 52 C0 Y1 X5 0C Y1
Y1 0C 5Y A X A 0 2 5 0
X5 C Y AX A0
circuit given in fig. 2

A0 25 0A 1A 52
5Y 0 1 A 5 25 C0
C0 Y1 X5 0C
0A 1A
AX
52 0 C0 Y1 AX
AX A0 25 52
C0 Y1 X5 0C 5Y AX A0 5Y
52
5Y AX A0 25 0A 1A 52 C 0 1A
1A 52 C0 Y1 X5 0C 5Y AX 0C
0C 5Y AX A0 25 0A 1A 52 0A
C Y 1 X 0 C 5
0A 1A 52 0 A 5 0 Y1
A
X5
X5 0C 5Y AX 0 25
Y A 0 25
25 0A 1A 52 C0 1 X5
25 C 0A Y1
Y1 X5 0C 5Y AX A0 A0

Page 2 of 3
A0 25 0A 1A 52 C0 Y1 X5 C0
Y1 0C 5Y AX A0 25
Y

Fig. 2
C0 X5 C AX
AX A0 25
Y1
0A 1A
0C
52
5Y 0 AX 1 A 52
52 C0 X5
1 0C 5Y
5Y A X A 0 25 0 A A 5 2 0 1
Y 0 C 5 Y A X
1A
0C
52
5Y
C0
AX 1 A0
X5
25 0A 1 52
A0 5Y
0A 1A 52 C0 Y1 X5
25 C 0A 1A
X5 0C 5Y AX A0
25 0A 1A 52 C0 Y1 X5 0C
0

X525Y1A0C0AX525Y1A0C0AX525Y1A0C0AX525Y1A0C0A
0C 5Y AX A0 25

and waveforms and derive the expression of power efficiency.

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A0 25 0A 1A 52 C0
C0 Y1 X5 0C 5Y AX A0
C0
Paper / Subject Code: 51222 / Electronics Devices and Circuits

AX A0 25 0A 1A 52
0C 5Y AX

Draw and explain high frequency model for BJT in CE configuration.

52 C0 Y1 X5
5Y AX A0 25 0A 1A 5
1A 52 C0 Y1 X5 0C
0C 5Y AX A0 25 0A
0A 1A 52 C0 Y1 X5
Calculate low cutoff frequencies due to coupling and bypass capacitors of the

X5 0C 5Y AX A0 25
25 0A 1A 52 C0 Y1
power supply of VCC = 30 V, determine the input power, output power and circuit

Y1 X5 0C 5Y AX
10 marks each

10 Marks each

Draw and explain a series fed class A power amplifier with the help of neat diagram
1A
For a Class B amplifier providing a 20 V peak signal to a 16 Ω load (speaker) and a

A0 25 0A 52
C0 Y1 X5 0C 5Y
AX A0 25 0A 1A
52 C0 Y1 X5 0C
5Y AX A0 25
1A 52 C0 Y1
0C 5Y AX A0
C
 AX A0 5Y 25 0A
52 C0 1A Y1 X5
5Y A X5 0C A 0C 25
25 0A 1A 0A Y1
Y1 X5 0C 25 A0
Y1 X5 C0
A0
C0
25
Y1
0A
X5 A 0C 2 5Y AX
AX A0 25 0A 1A 52
1A 52 C0 Y1 X5 0C 5Y
0C 5Y AX A0 25 0A 1A
0A 1A 52 C0 Y1 X5 0C
25 0A

B
B
5Y

A
A
0C AX A0

57487
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Q6
Y1
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25 0A 1A 52 C0 X5
Y X 0 C 5 Y AX A0 25
0A 1A 52 0 1 5 C 0 Y1
X5 0C 5Y AX A0
C0
25
Y1 A X5 A0
25 0A 1A 52 C0
Y1 0C 5Y AX A0 25
A0
X5
25 0A 1A 52 C 0 Y 1
AX

signal.
52 C0 Y1 X5 0C 5Y A X A 0
52
5Y
5Y AX A0 25 0A 1A 52 C0 1A
1A 52 C0 Y1 X5 0C 5Y AX 0C
0C 5Y AX A 0 25 0 A 1 A 5 2 0A
0A 1A 52 C0 Y1 X5 0C 5 Y X5
X5 0C 5Y AX A0 25 0A 1A 25
0C

circuit. Refer fig. 4

25 0A 1A 52 C0 Y1 X5 Y1
Y1 0C 5Y A X A 0 2 5 0
A0
X5
25 0A 1A 52 C 0 Y 1
AX
5
A0
C0
C0 Y1 X5 0C 5Y AX A 0 25 AX
AX A0 25 0A 1A 52 C0 Y1 52
C0 Y1 X5 0C 5Y AX A0 5Y
52
5Y AX A0 25 0A 1A 52 C 0 1A
Y1 0C 5Y AX

VGSQ = 1.872 V, IDSQ = 0.94 mA

1A 52 C0 X5 0C
0C 5Y AX A0 25 0A 1A 52 0A
C Y 1 X 0 C 5
0A 1A 52 0 A 5 0 Y1
A
X5
X5 0C 5Y AX 0 25
Y A 0 25
25 0A 1A 52 C0 1 X5
25 C 0A Y1
Y1 X5 0C 5Y AX A0 A0

Page 3 of 3
A0 25 0A 1A 52 C0 Y1 X5 C0
5Y AX A0 25

Fig. 4
Fig. 3
C0 Y1 X5 0C Y AX
A0 25 0A 1A 52 C 0 1
AX
C0 Y1 X5 0C 5Y AX A 0C
52
5Y

_____________________
52 A 0 1 5
5Y A X 0 25 A A 2 0 A 1
1A 52 C0 Y 1 X5 0 C 5 Y X
0C 5Y AX A0 25 0A 1 A0 52
0A 1A 52 C0 Y1 X5 C 5Y
X5 0C 5Y AX A0 25 0A 1A
25 0A 1A 52 C0 Y1 X5 0C
0

X525Y1A0C0AX525Y1A0C0AX525Y1A0C0AX525Y1A0C0A
Y1 X5 0C 5Y AX A0 25
A0 25 0A 1A 52 C0 Y1
C0 Y1 X5 0C 5Y AX A0
C0
Paper / Subject Code: 51222 / Electronics Devices and Circuits

AX A0 25 0A 1A 52
52 C0 Y1 X5 0C 5Y AX

Derive the equation of CMRR for the MOS differential pair amplifier.
5Y AX A0 25 0A 1A 5
1A 52 C0 Y1 X5 0C
0C 5Y AX A0 25 0A
0A 1A 52 C0 Y1 X5
X5 0C 5Y AX A0 25
Design a voltage divider bias circuit to operate at the given conditions. Refer Fig. 3

0A 1A 52 C0 Y1
Determine the input impedance, output impedance and voltage gain for the given

25

Explain the operation of a MOS differential amplifier with differential mode input
Y1 X5 0C 5Y AX

10 Marks each
10 Marks each

A0 25 0A 1A 52
C0 Y1 X5 0C 5Y
AX A0 25 0A 1A
52 C0 Y1 X5 0C
5Y AX A0 25
1A 52 C0 Y1
0C 5Y AX A0
C