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 Basic Block Diagram Of Computer

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Input Unit
All the data received by the computer goes through the input unit. The input unit comprises
different devices like a mouse, keyboard, scanner, etc. In other words, each of these devices
acts as a mediator between the users and the computer.

CPU – Central Processing Unit

CPU, is the brain of the computer. It works the same way a human brain works. As the brain
controls all human activities, similarly the CPU controls all the tasks.
Now the CPU comprises of two units, namely –
ALU (Arithmetic Logic Unit) and CU (Control Unit).

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ALU – Arithmetic Logic Unit
The Arithmetic Logic Unit is made of two terms, arithmetic and logic. There are two primary
functions that this unit performs.
1. Data is inserted through the input unit into the primary memory. Performs the basic
arithmetical operation on it. Like addition, subtraction, multiplication, and division. It
performs all sorts of calculations required on the data. Then sends back data to the storage.
2. The unit is also responsible for performing logical operations like AND, OR, Equal to, Less
than, etc. In addition to this it conducts merging, sorting, and selection of the given data.

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CU – Control Unit
The control unit as the name suggests is the controller of all the activities/tasks and
operations. All this is performed inside the computer.

Memory Unit
All the data that has to be processed or has been processed is stored in the memory unit.
The memory unit acts as a hub of all the data. It transmits it to the required part of the
computer whenever necessary.
Output Unit
All the information sent to the computer once processed is received by the user through the
output unit. Devices like printers, monitors, projectors, etc. all come under the output unit.

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Microprocessor
A microprocessor is basically the brain of the computer. We can also call it simply a processor
or CPU. Furthermore, a microprocessor is basically a computer processor that is mounted on a
single IC (Integrated Circuit). It means that all the functions of the processor are included on a
single chip.

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Evolution of Microprocessor

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Microprocessor Operation
Microprocessor follows the following cycles or operations during program execution.
1. Fetch Cycle
2. Decoding Cycle
3. Execute Cycle

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Features of 8085 Microprocessor

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 8085 Microprocessor Architecture
• The architecture of 8085 consists of three main sections, ALU (Arithmetic and Logical Unit),
timing and control unit and Registers.
 Arithmetic and Logic Unit (ALU)
The ALU performs numerical and logical operations. ALU performs the following arithmetic
and logical operations.
Addition, Subtraction
Logical AND, Logical OR, Logical Ex - OR
Complement (logical NOT)
Increment, Decrement
Left shift, Right shift etc.
ALU includes the accumulator, the temporary register, the arithmetic and logic circuits and
flags. It always stores the results of operations in an Accumulator.

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 Timing & Control Unit
• It generates timing and control signals, which are necessary for the execution of instructions.
• It controls data flow between the CPU and peripherals (including memory).
• It provides status, control and timing signals required to operate memory and I/O devices.
 Program Counter (PC): This 16-bit register deals with sequencing the execution of
instructions. The microprocessor uses this register to sequence the execution of the
instructions. The function of the program counter is to point to the memory address from
which the next byte is to be fetched.
 Stack Pointer (SP): The stack pointer is a 16-bit register used as a memory pointer. It points
to a memory location in read-write memory called the stack.

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 Instruction Register/Decoder: Temporary store for the current instructions of a program. The
latest instruction was sent here from memory before execution. The decoder then takes
instruction and decodes or interprets the instruction. Decoded instructions are then passed
to the next stage.

 8085 System Bus: The microprocessor communicates with memory and other devices (input
and output) using three buses: Address Bus, Data Bus and Control Bus.

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 Address Bus: The Address bus consists of 16 wires. The address bus's size determines the
memory size, which can be used. To communicate with memory, the microprocessor sends
an address on the address bus to the memory. The address bus is
unidirectional, i.e., numbers are only sent from the microprocessor to memory.
 Data Bus: Bus is bidirectional. The size of the data bus determines what arithmetic can be
done. The data bus also carries instructions from memory to the microprocessor.
Memory size = 2A x D were, A denotes the address lines, and D denotes the data lines.
 Control Bus: Control buses are various lines that have specific functions for coordinating and
controlling μP operations. The control bus carries control signals partly unidirectional and
partly bidirectional. Control signals are things like reading or writing.

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 General Purpose Registers: μP requires extra registers for versatility. It can be used to store
additional data during a program.
 Registers: 8085 has six general-purpose registers to store 8-bit data, identified as B, C, D, E,
H and L. They can be combined as register pairs BC, DE and HL to perform 16-bit
operations.
 Accumulator: The accumulator is an 8-bit register included as a part of the Arithmetic Logic
Unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical
operations. The result of an operation is stored in the accumulator.
 Flag Register: The ALU includes five flip-flops. They are called Zero (Z), Carry (CY), Sign (S),
Parity (P) and Auxiliary Carry (AC) flags. The microprocessor uses these flags to test data
conditions. The software instructions test the flags' conditions (set or reset).
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 Bit Position of Various Flags in Flag Register of 8085
The combination of the flag register and the accumulator is called Program Status Word (PSW),
and PSW is the 16-bit unit for stack operation.

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Pin Diagram Of 8085 Microprocessor

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1. Address Bus and Data Bus:

The address bus is a group of sixteen lines i.e A0-A15. The address bus is
unidirectional, i.e., bits flow in one direction from the microprocessor unit to the
peripheral devices and uses the high order address bus.

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2. Control and Status Signals:

ALE – It is an Address Latch Enable signal. It goes high during first T state of a
machine cycle and enables the lower 8-bits of the address, if its value is 1 otherwise
data bus is activated.
IO/M’ – It is a status signal which determines whether the address is for input-
output or memory. When it is high(1) the address on the address bus is for input-
output devices. When it is low(0) the address on the address bus is for the memory.

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SO, S1 – These are status signals. They distinguish the various types of operations
such as halt, reading, instruction fetching or writing.
IO/M’ S1 S0 Data Bus Status

0 1 1 Opcode fetch

0 1 0 Memory read

0 0 1 Memory write

1 1 0 I/O read

1 0 1 I/O write

1 1 1 Interrupt acknowledge

0 0 0 Halt

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RD’ – It is a signal to control READ operation. When it is low the selected memory or
input-output device is read.
WR’ – It is a signal to control WRITE operation. When it goes low the data on the
data bus is written into the selected memory or I/O location.
READY – It senses whether a peripheral is ready to transfer data or not. If READY is
high(1) the peripheral is ready. If it is low(0) the microprocessor waits till it goes
high. It is useful for interfacing low speed devices.

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3. Power Supply and Clock Frequency:

Vcc – +5v power supply

Vss – Ground Reference
XI, X2 – A crystal is connected at these two pins. The frequency is internally divided by
two, therefore, to operate a system at 3MHZ the crystal should have frequency of
6MHZ.
CLK (OUT) – This signal can be used as the system clock for other devices.

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4. Interrupts and Peripheral Initiated Signals:
The 8085 has five interrupt signals that can be used to interrupt a program execution.
(i) INTR
(ii) RST 7.5
(iii) RST 6.5
(iv) RST 5.5
(v) TRAP
The microprocessor acknowledges Interrupt Request by INTA’ signal. In addition to
Interrupts, there are three externally initiated signals namely RESET, HOLD and READY. To
respond to HOLD request, it has one signal called HLDA.

INTR – It is an interrupt request signal.

INTA’ – It is an interrupt acknowledgement sent by the microprocessor after INTR is
received.

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5. Reset Signals:

RESET IN’ – When the signal on this pin is low(0), the program-counter is set to
zero, the buses are tristated and the microprocessor unit is reset.
RESET OUT – This signal indicates that the MPU is being reset. The signal can be
used to reset other devices.

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6. DMA Signals:

HOLD – It indicates that another device is requesting the use of the address and
data bus. Having received HOLD request the microprocessor relinquishes the use of
the buses as soon as the current machine cycle is completed. Internal processing
may continue. After the removal of the HOLD signal the processor regains the bus.
HLDA – It is a signal which indicates that the hold request has been received after
the removal of a HOLD request, the HLDA goes low.

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7. Serial I/O Ports:

Serial transmission in 8085 is implemented by the two signals,

SID and SOD – SID is a data line for serial input where as SOD is a data line for serial
output.

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• Bus Structure of 8085 Microprocessor

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Address bus:
• An address bus is a group of 16 lines generally called A0 – A15 to carry a 16-bit address
of memory location.
• In a computer system, each peripheral or memory location is identified by a
Hexadecimal number called an address. It represents 0000 H to FFFF H . H means
hexadecimal no. This is similar to the postal address of a house.
• The address bus is unidirectional, which means bit flow in only one direction from MPU
to the peripheral.
• MPU carries 16-bit address i.e. 216 = 65,536 or 64K memory locations.

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Data Bus:
A data bus is a group of eight bidirectional lines used for data flow in both the directions
between MPH and peripheral devices. The 8 data lines are manipulating 8-bit data ranging
from 00 to FF i.e. (28 = 256) numbers from 0000 0000 -1111 1111. This 8-bit data is called
word length and the register size of a microprocessor and MPH is called an 8-bit
microprocessor.

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Control bus:
The control bus is having various single lines used for sending control signals in the form of
the pulse to the memory and I/O devices. The MPU generates specific control signals to
perform a particular operation. Some of these control signals are memory read, memory
write, I/O read and I/O write.

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8085 Microprocessor Instructions:
An instruction of a computer is a command given to the computer to perform a specified operation on
given data. In microprocessor, the instruction set is the collection of the instructions that the
microprocessor is designed to execute.
These instructions have been classified into the following groups:
• Data Transfer Group
• Arithmetic Group
• Logical Group
• Branch Control Group

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Addressing Modes of 8085 Microprocessor:-
• The different methods to select (address) the operands are called the Addressing Modes.
• Types of addressing modes of 8085 microprocessor :
• Immediate Addressing
• Register Addressing
• Direct Addressing
• Indirect Addressing
• Implied Addressing

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• Immediate Addressing Mode:
• In immediate addressing mode, the data (8 / 16 bit) is specified in the instruction itself.
• The immediate addressing instructions are either 2 bytes or 3 bytes long.
• In 2 byte instruction, the first byte is OPCODE, and the second byte is the 8-bit data.
• In 3 byte instruction, the first byte is OPCODE, second and third bytes are 16-bit data.
• The instruction containing the letter “I” indicate immediate addressing mode.
• Examples:
• MVI A, A0 H : This instruction transfers immediate data (A0 H ) to A register.
• LXI H, C200 H : This instruction transfer 16-bit immediate data C200 to HL register pair.
Lower order data(00H) to L register and high order data (C2 H) to H register.
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Register Addressing Mode:
• In register addressing mode the source and destination operands are general-purpose
registers.
• The register addressing instructions are generally of 1 byte i.e OPCODE only.
• The OPCODE specifies the operation and registers to be used to perform the operation.
Examples:
MOV D, B : This instruction copies the contents of register B to the D register. The source and
destination operands are both registers.
ADD B : This instruction adds the content of B register and A register, The data is present in
both B and A registers. The result is stored in the accumulator.

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Direct Addressing Mode:
• In direct addressing mode, the 16-bit address of the operand is given within the instruction
itself.
• The instruction in the direct addressing mode is 3-byte instructions. The first byte is OPCODE,
the second slower order address mode and the third is the higher-order address mode.
• For I/O instruction that uses direct addressing mode are 2-byte as the address if I/O is one
byte.
Examples: LDA C200 H : Load accumulator directly from the memory location. In this
instruction, the contents of C200 memory location are transferred to the accumulator.
STA C200 H : Store accumulator directly to memory location. In this instruction, the content of
the accumulator are store at memory location C200 H.
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Indirect Addressing Mode:
In indirect addressing mode the instruction reference the memory through a register pair.
i.e. the memory address where the operand is located is specified by the content of a register
pair.
Examples:
MOV A, M : In this case, M is a memory pointer specifying the HL register pair where the
address is stored. The contents of the HL pair are used as addresses and the content of that
memory location is transferred to the accumulator.
LDAX B : In this case, the BC register pair is used as an address and the content of the memory
location specified by the BC register pair is copied to the accumulator.

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Implied Addressing or Implicit Addressing Mode:
The implied mode of addressing does not require any operand.
The data is specified within OPCODE itself.
Generally, the implied addressing mode instruction is a 1-byte instruction.
The data is supposed to be present generally in the accumulator.
Examples:
RAL : Rotate accumulator left, it operates on the data in accumulator only. So whenever RAL is
used it is implied that the data to be operated on is available in the accumulator only.
CMC : Complement carry flag.

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• Assembler Directives

• Assembler directives are the instructions used by the assembler at the time of assembling

a source program. More specifically, we can say, assembler directives are the commands

or instructions that control the operation of the assembler.

• Assembler directives are the instructions provided to the assembler, not the processor as

the processor has nothing to do with these instructions. These instructions are also

known as pseudo-instructions or pseudo-opcode.

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• Assembler Directives of 8085
The assembler directives given below are used by 8085 assemblers:
DB: Define Byte
This directive is used for the purpose of allocating and initializing single or multiple data
bytes.

Memory name AREA has three consecutive locations where 30H, 52H and 35H are to be
stored.

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DW: Define Word
It is used for initialising single or multiple data words (16-bit).

These two 16-bit data 1020H and 4216H are stored at 4 consecutive locations in the memory
MARK.

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END: End of program
This directive is used at the time of program termination.
EQU: Equate
It is used to assign any numerical value or constant to the variable.

Variable name ‘DONE’ has value 10H

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ORG: Origin
This directive is used at the time of assigning starting address for a module or segment.

By this instruction, the assembler gets to know that the statements following this instruction,
must be stored in the memory location beginning with address 1050H.

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• Machine Cycle in 8085 Microprocessor
The time needed for completing one operation of accessing memory, I/O or acknowledging
an external request is termed as Machine cycle. It is comprised of T-states. One subdivision
of the operation completed in one clock period is termed as T-state. The following are the
various machine cycles of 8085 microprocessor.
1. Opcode Fetch (OF)
2. Memory Read (MR)
3. Memory Write (MW)
4. I/O Read (IOR)
5. I/O Write (IOW)

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Signal Representation

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• Opcode Fetch (OF) machine cycle of 8085:

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S. No T state Operation
1 T1 The
.
microprocessor places the higher order 8-bits of the memory address on A15 – A8
address bus and the lower order 8-bits of the memory address on AD7 – AD0 address /
data bus.

2 The microprocessor makes the ALE signal HIGH and at the middle of T1 state, ALE signal
goes LOW.
3 The status signals are changed as IO/𝑀’ = 0, S1 =1 and S0 = 1. These status signals do not
change throughout the OF machine cycle.

4 T2 The microprocessor makes the RD’ line LOW to enable memory read and increments the
Program Counter.

5 The contents on D7 – D0 (i.e. the Opcode) are placed on the address / data bus.

6 T3 The microprocessor transfers the Opcode on the address / data bus to Instruction
Register (IR).
7 The microprocessor makes the RD’ line HIGH to disable memory read.

8 T4 The microprocessor decodes the instruction.

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• Memory Read Machine Cycle of 8085:

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S. No T state Operation
1 T1 The microprocessor places the higher order 8-bits of the memory address on
A15 – A8 address bus and the lower order 8-bits of the memory address on
AD7 – AD0 address / data bus.
2 The microprocessor makes the ALE signal HIGH and at the middle of T1 state,
ALE signal goes LOW.
3 The status signals are changed as IO/𝑀’ = 0, S1 =1 and S0 = 0. These status
signals do not change throughout the memory read machine cycle.
4 T2 The microprocessor makes the RD’ line LOW to enable memory read and
increments the Program Counter.
5 The contents on D7 – D0 (i.e. the data) are placed on the address / data bus.

6 T3 The data loaded on the address / data bus is moved to the microprocessor.

7 The microprocessor makes the RD’ line HIGH to disable the memory read
operation.
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• Memory Write Machine Cycle of 8085:

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S. No T state Operation
1 T1 The microprocessor places the higher order 8-bits of the memory address on
A15 – A8 address bus and the lower order 8-bits of the memory address on
AD7 – AD0 address / data bus.
2 The microprocessor makes the ALE signal HIGH and at the middle of T1 state,
ALE signal goes LOW.
3 The status signals are changed as IO/𝑀’ = 0, S1 =0 and S0 = 1. These status
signals do not change throughout the memory write machine cycle.

4 T2 The microprocessor makes the 𝑊𝑅’ line LOW to enable memory write.

5 The contents of the specified register are placed on the address / data bus.

6 T3 The data placed on the address / data bus is transferred to the specified
memory location.
7 The microprocessor makes the 𝑊𝑅’ line HIGH to disable the memory write
operation.
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• I/O Read Machine Cycle of 8085

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S. No T state Operation
1 T1 The microprocessor places the address of the I/O port specified in the
instruction on A15 – A8 address bus and also on AD7 – AD0 address / data bus.

2 The microprocessor makes the ALE signal HIGH and at the middle of T1 state,
ALE signal goes LOW.
3 The status signals are changed as IO/𝑀’ = 0, S1 =1 and S0 = 0. These status
signals do not change throughout the I/O read machine cycle.

4 T2 The microprocessor makes the 𝑅𝐷’ line LOW to enable I/O read.

5 The contents on D7 – D0 (i.e. the data) are placed on the address / data bus.

6 T3 The data loaded on the address / data bus is moved to the microprocessor ie.,
to the accumulator.
7 The microprocessor makes the 𝑅𝐷’ line HIGH to disable the I/O read operation.

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• I/O Write Machine Cycle of 8085

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S. No T state Operation
1 T1 The microprocessor places the address of the I/O port specified in the
instruction on A15 – A8 address bus and also on AD7 – AD0 address / data
bus.
2 The microprocessor makes the ALE signal HIGH and at the middle of T1 state,
ALE signal goes LOW.
3 The status signals are changed as IO/𝑀’ = 0, S1 =0 and S0 = 1. These status
signals do not change throughout the I/O write machine cycle.

4 T2 The microprocessor makes the 𝑊𝑅’ line LOW to enable I/O write.

5 The contents of the Accumulator are placed on the address / data bus.

6 T3 The data placed on the address / data bus is transferred to the specified I/O
port.
7 The microprocessor makes the 𝑊𝑅’ line HIGH to disable the I/O write
operation

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