ASSIGMENT 1:

Explain the following combinational logic circuit with their logic diagram
 Adders circuit
 Subtractor circuit
 Encoder circuit
 Decoder circuit
 Multiplexer circuit
 De-multiplexer circuit

MULTIPLEXER CIRCUIT.
Multiplexers: A multiplexer (MUX) also known as data selector, is a logic circuit which
allows the digital information from multi-inputs to a single output line.
The selection of the input data to be routed to the output line is done by the select terminals.
The number of select terminals depends on the number of input lines to be routed to
output line, given by the general formula as:
2K=N
where N is the number of input lines and K is the number of select terminals. In other
words, if there are 4 input lines to be routed to output line, then two select terminals are
needed as 22 = 4
The block diagram for 4:1 multiplexer is shown in figure below

In which X0, X1, X2, X3 are the 4 input lines and S1, S0 are the select terminals
and X is the output terminal. Normally a strobe terminal or enable terminal
(G) is provided in the MUXs which is normally active-low. The active-low
means it performs the operation when it is low; it also helps to cascade the
MUXs. The Boolean function to perform the multiplexing action is given as:

X = X0 ⋅S1 ⋅S0 + X1 ⋅S1 ⋅S0 + X2 ⋅S1 ⋅S0 + X3 ⋅S1 ⋅S0

 The output X will follow the input data depending on the select terminals S1,S0 , as
given in the table 6.1.

Table 6.1

Select terminals Output

S1 S0 X
0 0 X = X0
0 1 X = X1
1 0 X = X2
1 1 X = X3

Note that only one of the inputs X0, X1, X2, X3 is routed to the output X
(one at a time). The realization of the Boolean function X with NAND gates only is
shown in figure 6.2.

Fig. 6.2

The MUXs are available in the form of the following IC’s:

74157 quadruple two – input multiplexer/data selector.
74151A eight - input multiplexer/data selector.
74150 sixteen - input multiplexer/data selector.
Quadruple two – input multiplexer/data selector: The internal logic diagram of the
IC 74157 is given in figure 6.3. It consists of four two input multiplexers on a single
chip. Each of the four multiplexers has a common data select line S and a common
chip enable terminal G. A low signal to the chip enables terminal G allows the
selected input data to rout to the output. Since there are only two inputs to be
selected from each multiplexer, a single data select terminal is sufficient.

Fig. 6.3

74151A Eight - input multiplexer/data selector: Figure 6.4 shows the logic
block diagram for a 8 – input multiplexer/ data selector IC 74151A. It has 8 data
inputs X0 through X7, three data select terminals S2 S1, & S0 and an enable terminal
G. when enable terminal G is high, the multiplexer is disabled and output X is zero
irrespective of the select input terminal. However, when the enable terminal G is
low the input data is routed to the output as per data select terminals S 2 S1, & S0
as illustrated in table 6.2.
 Fig. 6.4

74150 Sixteen - input multiplexer/data selector: The IC 74150 is 16:1

multiplexer having 16 input lines and one output line. It has four select terminals
S3, S2, S1& S0 and one enable terminal G which is kept low for multiplexing action.
The block diagram of the 16:1 MUX is given in figure 6.5.

Fig. 6.5
 Expansion of Multiplexers: For the expansion of number of input terminals of
the multiplexers two MUXs may be cascaded. Two 4:1 MUXs may be cascaded to
form 8:1 MUX. Similarly, two 8:1 MUXs may be cascaded to have a 16:1
multiplexer and so on. Figure 6.6 illustrates how two 4:1 MUXs are cascaded to
form 8:1 MUX. The enable terminal G of the MUXs in-conjunction with a NOT gate
provides the third select terminal. When S2 is zero the first MUX will be enabled
and inputs X0 through X3 will be routed to its output; and when S2 is 1, the second
MUX will be enabled, X4 through X7 will be routed to the output of the second
MUX. The outputs of the two MUXs are connected to the inputs of an OR gate
which then gives the final output (ref. fig. below).

Fig.

Applications of Multiplexers: Primary aim of the MUXs is the multiplexing

operation, that is, the selected input is routed to the output. In addition to this,
Implementation of Boolean function can easily be done with MUXs, since MUXs
are available in the form of integrated circuits. The method of implementing the
Boolean function is that the truth table is first constructed for the given function
to be implemented. Then logic 1 is connected to each data input of the
multiplexer corresponding to each combination of the input variables which has 1
in the output column of the truth table. The logic 0 is, however, connected to the
remaining inputs of the MUX. The variables are connected to the data select
inputs of the multiplexer.
The Boolean functions of N – variables can also be implemented by the
Multiplexers of (N – 1) select lines. A function of 4 variables can be implemented
with 8:1 multiplexer having 3 select lines. Let A, B, C, D are the input variables of
the function F, which is to be implemented with a multiplexer. The variable A is
the most significant bit and D is the least significant bit. Variables B, C, D are
assumed to be the select terminals for the multiplexer. The truth table is drawn
for the given function. It is well known that in the truth table variables BCD
progresses twice through the sequence 000, 001…. 111; once with A = 0 and
other with A = 1. The connections to be made to the data inputs of the
multiplexer, following rules are observed.
1. A logical 0 is connected to the data input of MUX, if the 0 occurs
at the output in the truth table, both times when MSB is 0 and 1
(other variables having the same value).
2. A logical 1 is connected to the data input of MUX, if the 1 occurs
at the
output in the truth table, both times when MSB is 0 and 1 (other variables
having the same value).
3. MSB is connected to the data input of MUX, if the output in the
truth table is different both times when MSB is 0 and 1(other
variables having the same value); and also, output is the same as
the MSB.
4. The complement of the MSB is connected to the data input of
MUX, if the output in the truth table is same both times when
MSB is 0 and 1(other variables having the same value); and also,
output is the same as the complement of MSB.

EXAMPLE OF QUESTIONS INVOLVING MULTICOMPLEXERS

Example 6.1: Realize the following function of three variables with 8:1 MUX.

F (A, B, C) = ∑ (0,1,3,4,7 )
Solution: The truth table of the given function is drawn as shown in table 6.3. To
realize the given function using 8:1 MUX, the variable A, B, C are assumed to be
the three select terminals as shown in figure 6.7. The logic 1 is connected to each
data input of the multiplexer corresponding to each combination of the input
variables which has 1 in the output column of the truth table. The logic 0 is
connected to the remaining inputs of the MUX. The inputs X0, X1, X3, X4, X7 are,
therefore, connected to the logic 1 and X2, X5, X6 are connected to logic 0.
Example 6.2: Use Multiplexers to implement of Full adder.

Solution: It is well known that a full adder adds three bits of information. Let A B
C are three bits to be added. Let augend bit is A, addend bit is B and C is the carry
from the previous column; SUM and CARRY to the next bit are given in the table
6.4. Implementation of SUM and CARRY is shown in figure below
 Fig

Example 6.3: Realize the following function of four variables with 8:1 MUX.

F ( A, B , C , D ) = ∑ (0,1,3,5,7,11 ,13 ,15 )

Solution: The truth table for the given function is first of all drawn (table 6.5) and
YZW are assumed to be the select terminals of the 8:1 MUX. The inputs to the
multiplexer are obtained from the truth table as given below.

X0 = A X1 = A
X2 = 0 X3 = 1

X4 = 0 X5 = 1

X6 = 0 X7 = 1
Figure 6.9 shows the implementation of the given function.