Digital Logic Design, Second Year B. Tech.

E&TC

Date of Performance: 7/8/14

Experiment No. 2.

Aim: To construct basicgates

(AND,OR, NOT)using universal
verify their truth tables.
gates (NAND & NOR)and thus

Components: IC 7400, IC 7402, DC Power supply, Breadboard,

Digital Multimeter
Connecting Wires and

Theory:

A universalgate is a gate which

can implement any Boolean function without need
other gate type. The NAND and NOR gates are universal gates.
to use any
since NANDand NOR gates are economical andcsier In practice, this is
advantageous
to fabricate and are the basicgates used
in all IC digital logic families.

1. NAND Gate:
The NOT-AND Operation is known as the NAND operation. The NAND gate is made up off N
(N>2)inputs given to the AND gate followed by a NOT gate. The logical operation of NAND
gate can be shown as:

Y= A.B (fora two input NAND gate)

The standard symbol of the NAND gate and its truth table is as shown below. Here, the bubble
represents NOT operation, inversion or complementation.

Input Input Output

A B Y

A 1

Y=AB 1 1

B 1 1

1 1

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 Digital Logic Design, Second Year B. Tech. E&TC 2
The NAND (Not -AND) gate
has an
"LOW" to logic level 0"when ALLoutput that is normally at logic level 1" and only goes
of its inputs are at
Gate is the reverse or logic level *1". The Loge
"Complementary" form ofthe AND gate
we have seen previoUsiy -

2. NOR Gate:

The NOT-OR operation is known as the NOR operation, The NOR gate made up of N (N2)
inputs to the OR gate followed by a NOT The
is

as:
gate. logical operation ofNOR gate can be shown

Y=A+B (for a two inputNOR gate)oteL

The standard symbol of NOR gate and its truth table is shown below. The
NOT operation, inversion.
bubble represents the

Input Output
A A B A+B
Y-A+B
B 1 0
1

The inclusiveNOR (Not-OR)gate has an output that normally at logic level

"LOW *1" and only goes
is

to logic
level 0"when ANY of its inputs are at logic level 1". The Logic NOR Gate is
the reverse or "Complementary" form of the inclusive OR gate.

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 2
Pin djagram: DigitalLogic Design, Second Year B. Tech. E&TC

Truth Tables: (Theoretical and in Volts)

Practical values) CReadings are

IC74 00 1) AND using NAND

Theoetical Proctieal

i/p i/p o/p i/p i/p O/p

A-B A B A-B

NAND GATE (IC7400) o o-36

Construction of Rosir Gotes Usina NAND GATE

o O-43

) AND Using

A
NAND:
2) OR using NAND
O-78
L4.58

o/p i/p i/p

A.B i/P i/e
y
A AtB A A+B
0-26
2) OR using NAND 3-48
4-05
A 5 4-42

A.B- 3) NOT using NAND

B
4
o/P

i/P o/P
A
2) NOT NAND: 4.49
O.07

A
y= A
Institute, Mumbai - 400019
Veermata Jijabai Technological
Rn duoqrami

Digital Logic
Design, Second Year B. Tech.
E&TC

Tables: (Theoretical I and Practical

Truth values) CRe adings
nIC7402 1) AND using
NOR are n
vols )
Thuotetical
Peactical

i/p o/p
GND
A i/p o/p
A P AB
NOR GATE (IC7402) o O-18
o O.37
Conctruction of Bosic Gatea
ng NOR GATE
u 0.78

AND using NORi 4.90

2) OR using NOR
A

A
A+B A i/p
A+B
B
= AB
4-82
2) 4.88
OR NOR:

Noon
using

oonL)
4.99
3) NOT using NOR
A+B A+B y A+B

i/p o/p
A O/p
A A
B) NOT uSing NOR :
4.95
5 O.36

y- A

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Veermata Jijabai Technological Institute,Mumbai

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 Digital Logic
Design, Second Year B. Tech. E&TC

Procedure:

1. The IC (7400- NAND, 7402-NOR) is firstly

connected on the breadboard
both upper and lower such that it
oonnects parts of the breadboard
Erom the supply(V)nign mput 1s given to the top section of the breadboard and the lower
section is given ground connection.
As ner thepin diagram of each gate, the
wires are connected on respective input and output
of the IC gates such that NAND is
sections
connected as NOT. AND & OR gates and the
respective truth tables are verified.

AThe sameprocedure is followed for verifying the NOR gate truth table.
E According to the truth table requirements, respective inputs are given to the gates and the
correspondingoutput is analyzed using a digital multi meter.
6 Therefore, the theoretical and practical truth tables are cross verified.

Conclusion:

t. Jhus the tuth taltes o wiweual gau,CNAND&NOR)

aele voutid
2: he nivesal gate was
use od mplemented by

c&nthuting the kasic gats o AND, OR, NoT by

d NoR
usung the NAND ony
encluawrely

Sign. & Date:

- 400019
Technological Institute, Mumbai
VeermataJijabal