Scribd
Upload
522 views3 pages

Block-Level OCC Insertion With A Top-Level PLL

synopsys dft for occ

Uploaded by

thsim85
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
522 views3 pages

Block-Level OCC Insertion With A Top-Level PLL

synopsys dft for occ

Uploaded by

thsim85
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Recent Searches:

mbist vclp message reference -xg


(/s/) Cases (/s/case-list) STARs (/s/star-list) Articles (/s/knowledge) Help (/s/help-info)

Dec 11, 2019 • Knowledge

Title
Block-Level OCC Insertion with a Top-Level PLL

Description

Block-Level OCC Insertion with a Top-Level PLL


Question:

In the Hierarchical Scan Synthesis (HSS) or Hierarchical Adaptive Scan Synthesis (HASS) flow, we would like to insert block-level OCC controllers
TO control a single top-level PLL clock that propagates into each block.

How can this be accomplished?

Answer:

In the D-2010.12-SP2 and earlier releases, only internal leaf pins (and not ports) were permitted for the definition of PLL clock sources. To satisfy
this requirement, users had to manually buffer the incoming PLL clock at the block level, and declare this buffer's output as the PLL clock source.
However, these buffers could get removed during place and route, rendering the SPF useless with the post-layout netlist.

In the D-2010.12-SP3 release, an enhancement was introduced to support this flow. With this enhancement, an input port can be specified as a
PLL clock source. The set_dft_signal command should be used to define the PLL clock input port as type ScanClock, rather than as type
Oscillator:

dc_shell> set_dft_configuration -clock_controller enable

# Note the PLL clock signal type. It's declared as ScanClock


# instead of Oscillator clock.
dc_shell> set_dft_signal -view existing_dft -type ScanClock -port pll_clk \
-timing {45 55} -test_mode all

dc_shell> set_dft_clock_controller -cell_name OCC_U1 \


-design snps_clk_mux \
-pllclocks {pll_clk} \
-ateclocks {ate_clk}
The enhancement allows this port-sourced ScanClock clock to be referenced in the list of PLL clocks provided to the set_dft_clock_controller
command.

You should keep the following points in mind:

1. After a block-level OCC is inserted using this enhancement, post-insertion DRC is not supported in DFT Compiler due to a top-level port being
defined as PLL clock. Attempting to run post-insertion DRC results in the following error:

prompt> dft_drc
In mode: Internal_scan...
Design has scan chains in this mode
Design is scan routed
Post-DFT DRC enabled

Information: Starting test design rule checking. (TEST-222)


Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking vector rules...
Error: Line 599 (/tmp/__dft_drc.spf.module.userid.11908),
unresolved reference (No such net "I_1/\**inside** "). (V5-1)
Error: Line 610 (/tmp/__dft_drc.spf.module.userid.11908),
unresolved reference (PLL source for internal clock I_2283/Z does not exist). (V5-2)
Error: Could not perform design rule checking. (TEST-1311)
0

However, you can run post-insertion DRC in PLL-bypass mode.

prompt> set_dft_drc_configuration -pll_bypass enable


prompt> dft_drc

Use TetraMAX to perform the DRC in the PLL-enabled mode.

2. Once an OCC controller is inserted at the block level, another OCC controller should not be inserted in a higher-level module between the PLL
and this block. Otherwise, the design will be incorrect and the test patterns will fail. DFTMAX cannot check for this condition to prevent
double OCC controller insertion.

3. During ATPG, users must issue set_build -portfaults_box OCC_module_name for all OCC-inserted modules. This ensures that the PLL clock
name is preserved during design flattening in the TetraMAX build step.

4. TetraMAX can generate patterns for OCC-inserted blocks, but these patterns will have default timing for the PLL clocks. The patterns should
be updated for block level simulation. Ensure that the PLL clock is free-running in the simulation testbench.

Workaround

Product L1 Additional Product(s)


TestMAX DFT (/s/detail/01t1U000003IXzUQAW)

Article Number Last Published Date


000005039 12/11/2019, 9:10 AM
Article Record Type URL Name
How To Block-Level-OCC-Insertion-with-a-Top-Level-PLL-1576002497531

Was this article helpful? 0 0

Recommended Articles

Error when using the write_timing_constraints command in OCC block-level flow

Inserting OCC Controller Alongside an Existing OCC Controller in the Same Design

Using OCC Test Models During Hierarchical Scan Insertion

Using 8:1 or 16:1 Frequency Ratios with the DFT-Inserted Synchronized OCC Controller

Why Isn't My Existing OCC Controller Clock Chain Identified?

Related Files (0)

Article Comments (0) (/s/relatedlist/ka01U000001dji5QAA/Article_Comments__r) New

Saved Articles (0) (/s/relatedlist/ka01U000001dji5QAA/Saved_Articles__r) New

You might also like