EXPERIMENT-2 : STUDY OF FLIP FLOP

2.1. OBJECTIVE

2.2. APPARATUS

2.3. INTRODUCTION

2.4. PROCEDURE

2.5. OBSERVATIONS

2.6. RESULTS

2.7. VIVA VOCE

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2.1. OBJECTIVE: Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR
gates.

2.2. APPARATUS: Flip flop box, connecting wires.

2.3. INTRODUCTION: In electric circuit any device or circuit has two stable states called Bistable
statas. For example toggle switch has bistable states. Switch can be considered as memory device as it
will remains as set until some one change its position. A flip-flop (or latch) is a circuit that has two stable
states. For example its output may be 0 or 1(0 or +5V). The flip flop also has memory since it output will
remains as it set until some one change its, and can be used as memory device. Flip-flops are
fundamental building blocks of digital electronics systems used in computers, communications, and
many other types of systems. The circuit can be made to change state by signals applied to one or more
control inputs and will have one or two outputs.

Figure 2.1: Basic Flip Flop

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A flip flop is an electronic circuit with two stable states that can be used to store binary data. The
stored data can be changed by applying varying inputs. Flip-flops and latches are fundamental building
blocks of digital electronics systems used in computers, communications, and many other types of
systems.

1) R-S flip flop

2) D flip flop

3) J-K flip flop

4) T flip flop

1) R-S flip flop: The basic NAND gate RS flip flop circuit is used to store the data and thus
provides feedback from both of its outputs again back to its inputs. The RS flip flop actually has
three inputs, SET, RESET and its current output Q relating to its current state as shown in figure
below.

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Figure 2.3

2) D flip flop:

A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop by
connecting the R input through an inverter, and the S input is connected directly to data input. The
modified clocked SR flip-flop is known as D-flip-flop and is shown below. From the truth table of SR
flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs are same
and high. In many practical applications, these input conditions are not required. These input conditions
can be avoided by making them complement of each other.

Figure 2.4

3) J-K flip flop: In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop
circuit may be re-joined if both inputs are 1 than also the outputs are complement of each other as shown
in characteristics table below.

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Figure-2.5: Circuit diagram of J-K flip flop

4) T flip flop:

T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop. Both the
JK inputs of the JK flip – flop are held at logic 1 and the clock signal continuous to change as shown
in table below.

Figure2.6: Circuit diagram of T flip

flop
2.4. PROCEDURE:

1) RS flip flop

Step-1: Connect the supply (+5V) to the circuit.

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Step-2: First press "ADD" button to add basic state of your output in the given table. Step-3:

Press the switches to select the required inputs "S" and "R" and apply the clock pulse.

Step-4: Press "ADD" button to add your inputs and outputs in the given table and their corresponding
graph.

Step-5: Repeat steps 3&4 for next state of inputs and their corresponding outputs.

Step-6: Press the "Print" button after completing your simulation to get your

results. 2) D flip flop

Step-1: Connect the supply(+5V) to the circuit.

Step-2: First press "ADD" button to add basic state of your output in the given

table. Step-3: Press the switches to select the required inputs "D" and "Clock".

Step-4: Press "ADD" button to add your inputs and outputs in the given table and their corresponding
graph.

Step-5: Repeat step 3 & step 4 for next state of inputs and their corresponding outputs.

Step-6: Press the "Print" button after completing your simulation to get your results.

3) J-K flip flop

Step 1: Connect the supply (+5V) to the circuit.

Step-2: First press "ADD" button to add basic state of your output in the given table. Step-3:

Press the switches to select the required inputs "S" and "R" and apply the clock pulse.

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Step-4: Press "ADD" button to add your inputs and outputs in the given table and their corresponding
graph.
Step-5: Repeat step 3 & step 4 for next state of inputs and their corresponding outputs.

Step-6: Press the "Print" button after completing your simulation to get your

results. 4) T flip flop

Step-1: Connect the supply(+5V) to the circuit.

Step-2: First press "ADD" button to add basic state of your output in the given table.

Step-3: Press the switches to select the required inputs "T" and apply the clock

pulse.

Step-4: Press "ADD" button to add your inputs and outputs in the given table and their corresponding
graph.

Step-5: Press the "Print" button after completing your simulation to get your results.

2.5. OBSERVATIONS:

Truth Table of RS Flip flop

S R Q Action

0 0 No Change Previous

0 1 0 Reset

1 0 1 Set

1 1 - Forbidden

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Truth Table of D Flip flop

Truth Table of JK flip flop

Truth Table of T flip flop

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2.6. RESULTS:

The truth table of different flip flops are verified.

2.7. VIVA VOCE:

1. Which of the following is correct for a gated D-type flip-flop?

A) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
B) The output complement follows the input when enabled
C) Only one of the inputs can be HIGH at a time
D) The output toggles if one of the inputs is held HIGH

2. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
A) AND or OR gates B) Ex-OR or Ex-NOR gates C) NOR or NAND gates C) AND or
NOR gate

3. The truth table for an S-R flip-flop has how many valid entries?
A) 1 B) 2
C) 3 D) 4

4. The flip-flops which has not any invalid states are _____________

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A) : S-R, J-K, D B) S-R, J-K, T

B) J-K, D, S-R D) J-K, D, T

5. Both the J-K & the T flip-flop are derived from the basic _____________
A) S-R flip-flop B) S-R latch
C) D latch D) D flip-flop
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