Concurrent Ternary Galois-Based Computation Using Nano-Apex Multiplexing Nibs of Regular Three-Dimensional Networks, Part I: Basics
Concurrent Ternary Galois-Based Computation Using Nano-Apex Multiplexing Nibs of Regular Three-Dimensional Networks, Part I: Basics
Concurrent Ternary Galois-Based Computation Using Nano-Apex Multiplexing Nibs of Regular Three-Dimensional Networks, Part I: Basics
Anas N. Al-Rabadi
ABSTRACT
New implementations within concurrent processing using three-dimensional lattice networks via nano
carbon-based field emission controlled-switching is introduced in this article. The introduced nano-based
three-dimensional networks utilize recent findings in nano-apex field emission to implement the concurrent
functionality of lattice networks. The concurrent implementation of ternary Galois functions using nano three-
dimensional lattice networks is performed by using carbon field-emission switching devices via nano-apex
carbon fibers and nanotubes. The presented work in this part of the article presents important basic
background and fundamentals with regards to lattice computing and carbon field-emission that will be
utilized within the follow-up works in the second and third parts of the article. The introduced nano-based
three-dimensional lattice implementations form new and important directions within three-dimensional
design in nanotechnologies that require optimal specifications of high regularity, predictable timing, high
testability, fault localization, self-repair, minimum size, and minimum power consumption.
KEYWORDS
Carbon nano-apex, Concurrent processing, Field emission, Lattice network, Regularity, Symmetric function.
1. INTRODUCTION
With future logic realization in technologies that are scaled down rapidly in size, the emphasis will
be increasingly focused on the mutually linked issues of regularity, predictable timing, high
testability, fast fault localization and self-repair [2], [3], [7], [31].
For the current leading technologies with the active-device count reaching the hundreds of millions,
and more than 80% of circuit areas are occupied by local and global interconnects, the delay of
interconnects is responsible for up to 50% or more of the total delay associated with a circuit [2],
[31]. Interconnects will take even higher percent of area and delay within future technologies,
which creates rising and increasing interests in cellular and regular circuits especially for deep sub-
micron and nanotechnologies. For example, Fig. 1 illustrates trends for electrical signal delays for
global interconnects with repeaters and without repeaters versus the local interconnects [2], [31].
DOI : 10.5121/vlsic.2020.11501 1
International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 1/2/3/4/5, October 2020
Figure 1. Delays for local and global interconnects versus the utilized feature size.
Lattice circuits [2], [3] generalize the ideas from the well-known regular circuits such as Fat Trees,
Generalized PLAs, Maitra Cascades and Akers Arrays [1], into a more systematic framework which
is closely related to the symmetry of functions and symmetric networks [2], [3], [28]. Realization of
logic circuits in three-dimensional space can be very important for future technologies, as it shows
that the best way is to synthesize combinational logic functions in a three-dimensional space where
all local interconnections are of the same length and global interconnections are only inputs on
parallel oblique planes (cf. Section 3). Moreover, three-dimensional cubical lattice circuits have
special importance since three-dimensional crystal lattices exist where inter-related atoms that exist
in a potential field are spaced on the corners of three-dimensional cubes, and thus the real potential
of the physical implementation of the logically synthesized three-dimensional lattice networks using
three-dimensional crystal lattices.
Nanotechnology is a new interdisciplinary field of research that cuts across several fields of
engineering, chemistry, physics and biology, that analyzes and synthesizes systems in the nano
scale (equal or less than 10-9 m) such as nanoparticles, nanowires, nanosheets and carbon nanotubes
(CNTs) [4], [5]-[7], [10], [11], [15]-[19], [22], [26], [29], [34], [36]-[38]. For example,
nanocapsules that contain charged particles for better medical delivery has been proposed [34],
methods for logic design that can be useful in nano integrated circuits have been presented [35],
utilizing CNT field emission for scanning electron microscopy has been shown [11], the
investigation of nanoelectronics has been presented [29], the potential uses of nanotubes in
important future applications have been demonstrated [10], and the introduction of the important
upcoming era of nanotechnology applications has been deeply manifested [19]. The CNT
technology is one of several cutting-edge emerging technologies within nanotechnology that is
showing high efficiency and very wide range of applications in several various fields in science and
technology, where recent examples of such applications include TVs based on field-emission of
CNTs that consume much less power, thinner and are of much higher resolution, and nanocircuits
based on CNTs such as CNT Field Effect Transistors (FETs) that show high potential for
consuming less power and to be much faster than the available silicon-based FETs.
Recently, carbon nanotubes have attracted much attention not only for their unique morphologies
and relatively small dimensions, but also for their potential implementations in many current and
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emerging technologies [10], [16]-[18]. The CNT is made of graphite, where it has been observed
that graphite can be formed within nano-scale in three different forms: (1) Carbon nanoball (or
buckyball) which is a molecule that consists of 60 carbon atoms (C60) that are arranged in the form
of a soccer ball, (2) Carbon nanotube (CNT) which is a narrow strip of tiny sheet of graphite that
comes mainly in two types of multi-wall CNT (MWCNT) where each CNT contains several hollow
cylinders of carbon atoms nested inside each other and single-wall CNT (SWCNT) that is made of
just a single layer of carbon atoms, and (3) Carbon nanocoil. Electrical implementations of basic
logic gates such as the logic inverter using CNTs have been demonstrated [18], engineering CNT
circuits using electrical breakdown has been shown [17], the utilization of CNT films for cathode-
based implementations has been demonstrated [30], designing CNT multiplexer-based circuits and
actuators has been shown [4]-[6], and the potential importance of CNTs for designing electronic
circuits and systems has been proposed [16].
This first part of the article introduces basic background in concurrent processing using three-
dimensional lattice networks and basic carbon-based field emission characteristics that will be used
in the second and third parts of the article within concurrent processing via field emission-based
three-dimensional lattice networks. Figure 2 illustrates the hierarchical layout of the introduced
system design methodology where layer 1 shows the underlying utilized fundamental Galois field
algebra, layer 2 illustrates the field-emission physics which is used in the operation of the utilized
devices, layer 3 shows the carbon-based technology which is used in the synthesis of the field
emission – based switching devices, and layers 4 - 5 show the corresponding hierarchical
implementation into the system level.
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f (x1, x2,…, xn) = 1∙ f0(x1, x2,…, xn) x1∙ f2(x1, x2,…, xn) (2)
f (x1, x2,…, xn) = 1∙ f1(x1, x2,…, xn) x1∙ f2(x1, x2,…, xn) (3)
Where f0(x1, x2,…, xn) = f(0, x2,…, xn) = f0 is the negative cofactor of variable x1, f1(x1, x2,…, xn) =
f(1, x2,…, xn) = f1 is the positive cofactor of variable x1, and f2(x1, x2,…, xn) = f(0, x2,…, xn) f(1,
x2,…, xn) = f0 f1. All operations in Equations (1) - (3) are performed using Boolean algebra, i.e.,
is Boolean XOR, and ∙ is Boolean multiplication.
Multiple-valued spectral methods are used in many applications in synthesis, analysis, testing,
classification and verification of logic circuits and systems [27]. Because Galois field proved to
possess desired properties in many applications such as test, communications and signal processing,
the developments of three-dimensional lattice networks will be conducted on the corresponding
Galois field (GF) algebraic structures. Radix three Galois field (GF(3)) addition and multiplication
are defined in Tables 1(a) and 1(b), respectively.
Table 1. Third radix Galois field (a) GF(3) addition, and (b) GF(3) multiplication.
(a) (b)
+ 0 1 2 * 0 1 2
0 0 1 2 0 0 0 0
1 1 2 0 1 0 1 2
2 2 0 1 2 0 2 1
A literal is a function of a single variable. 1-Reduced Post literal (1-RPL) is defined as:
i
x = 1 iff x =i else ix = 0 (4)
For example 0x, 1x, and 2x are the zero, first, and second polarities of the 1-RPL, respectively [2].
Also, the ternary shifts of variable x are defined as: x with no shift, x' with one shift and x" with two
shifts (i.e., x = x + 0, x’ = x +1, and x” = x + 2, respectively), and x can take any value in the set {0,
1, 2}. Ternary 1-RPL will be used in Section 3 to construct three-dimensional lattice networks by
controlling the propagation of sub-functions in three-dimensions.
The concept of lattice networks for switching functions [2] involves three components: (1)
expansion of a function that corresponds to the root (initial node) in the lattice which creates several
successor nodes of the expanded node, (2) joining of several nodes of a decision tree level to a
single node which is the reverse operation of the expansion process, and (3) regular geometry to
which the nodes are mapped that guides which nodes of the level are to be joined.
While the realization of Boolean non-symmetric functions in Akers arrays requires an exponential
growth of the repetition of variables in the worst case [1]-[2], the realization of Boolean non-
symmetric functions in lattice networks requires a linear growth of repetition of variables, and
consequently one does not need to repeat the variables of non-symmetric functions too many times
to realize such functions in lattice networks for most practical benchmarks [2].
Figure 3 illustrates, as an example, the geometry of a four-neighbor lattice network and joining
operations on the nodes where each cell has two inputs and two outputs (i.e., four neighbors). The
construction of the lattice network in Fig. 3 implements the following one possible convention of
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top-to-bottom expansion and left-to-right joining (i.e., left-to-right propagation of the corresponding
correction functions in Figs. 3(c) and 3(d), respectively).
Definition 1. The function that is generated by joining two nodes (sub-functions) in a lattice
network is called the joined function. The function that is generated in nodes other than the joining
nodes, to preserve the functionality within the lattice network, is called the correction function.
Note that the lattices shown in Fig. 3 preserve the functionality of the corresponding sub-functions f
and g. This can be observed, for instance, in Fig. 3(b) as the negated variable {a’} will cancel the
un-complemented variable {a}, when propagating the cofactors from the lower levels to the upper
levels or vice versa, without the need for any correction functions to preserve the output
functionality of the corresponding lattice network. This simple observation cannot be seen directly
in Figs. 3(c) and 3(d), as the correction functions are involved to cancel the effect of the new joining
nodes for the preservation of the functionality of the new lattice networks (these correction
functions are shown in the extreme right leaves of the second level in Figs. 3(c) and 3(d),
respectively).
It is shown [2], [28] that every function that is not symmetric can be symmetrized by repeating
variables, and that a totally symmetric function can be obtained from an arbitrary non-symmetric
function by the repetition of variables. Consequently, lattice networks and the symmetry of
functions are very much related to each other. Example 1 will illustrate such very close relationship.
Example 1. For the following non-symmetric three-variable Boolean function F = a∙b + a’∙c, by
utilizing the joining rule that was presented in Fig. 3(b) for two-dimensional lattice network with
binary Shannon nodes, one obtains the lattice network shown in Fig. 4.
One can note that without the repetition of variable(s) (e.g., variable b in Fig. 4) F cannot be
produced by any lattice network. It is also to be noted that all internal nodes in Fig. 4 are two-to-one
multiplexers (i.e., selectors). In Fig. 4, if one multiplies each leaf value, from left to right, with all
possible bottom-up paths (from the leaves to the root F) and add them over Boolean algebra then
one obtains the function F (i.e., the root) as follows:
One can observe that in order to represent the non-symmetric function in Example 1 in the two-
dimensional lattice network, variable b is repeated, where the nodes in Fig. 4 are Shannon nodes,
which are merely two-input one-output multiplexers, whose output goes in two directions, with the
set of variables {a, b, c} operate as control signals.
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c f g
a’ a a’ a
d
f0 af1 + a’g0 g1
v1 v2 v3 v4 v5
vi {0,1}
(a) (b)
f g f g
1 a 1 a 1 a’ 1 a’
Figure 3. Two-dimensional binary lattice networks: (a) A two-dimensional 4-neighbor lattice network, (b)
Shannon lattice network, (c) positive Davio lattice network, and (d) negative Davio lattice network.
a
0 1
b
0 1 0 1
c
0 1 0 1 0 1
b
0 1 0
1 1
0 1
0 1
Figure 4. Two-dimensional Shannon lattice network for the corresponding non-symmetric function
F = a∙b + a’∙c.
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The results from this section will be generalized to the ternary logic in Section 3, and thus from
two-dimensional space to three-dimensional space. It is important to prove that the repetition of
variables will have an end in the process of the symmetrization of the non-symmetric functions.
An intuitive proof is as follows: For totally symmetric functions the number of variables are equal
to the number of levels of the lattice network, as there is no need to repeat variables, and as it is
known that by the repetition of variables every non-symmetric function is symmetrized, then this
must result in definite number of levels in the corresponding lattice network and as a consequence
in certain number of total variables, repeated and non-repeated, that will result in the termination
of the process of symmetrization. One method to define the symmetry of a Boolean function is by
using symmetry indices Si [28].
Definition 2. A symmetry index (Si) has superscript i equals to the count of the number of “1”
values in the states of variables in the corresponding cell in a Karnaugh map.
Example 2 illustrates the concept of symmetry indices for a two-variable Boolean function, and
shows the close relationship between two-dimensional lattice networks and symmetry indices.
Example 2. For the binary non-symmetric implication function F = a’ + b, Fig. 5 illustrates the
relationship between the karnaugh map with non-conflicting symmetry indices Si and the two-
dimensional lattice network with non-conflicting leaves, which is achieved by repeating variable
{a} twice in the two-dimensional lattice network.
(a) (b)
(c) (d)
i
Figure 5. Using symmetry indices S : (a) non-symmetric implication Boolean function, (b) symmetrization
by the repetition of variable {a}, (c) two-dimensional lattice network that corresponds to Fig. 5(a) with
conflicting leaf (in dark box), and (d) two-dimensional lattice network that corresponds to Fig. 5(b) with
non-conflicting leaves.
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It is to be noted that all internal nodes in Fig. 5 are two-to-one multiplexers (i.e., selectors), where
if one multiplies each leaf value (from left to right) with all possible bottom-up paths (from the
leaves to the root F) and add them over Boolean algebra then one obtains the required function F
in the root.
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0 1 2
0 0 1 2
1 1 2 0
2 2 0 1
Figure 6 shows the logic circuit of the ternary 3-digit full adder that implements the ternary
addition operation presented in Table 2.
The following ternary maps in Fig. 7 represent the ternary Sum (S) and the ternary output Carry
(Cout) functions that appear in the logic circuit in Fig. 6. The presented representation is
performed by using 1-RPLs for variables a, b and c, and using the corresponding Galois field
addition and multiplication operations.
The lattice architectures that are shown in Figs. 8 and 9 show the corresponding three-
dimensional lattice realizations of the ternary maps in Fig. 7 which represent the Sum and output
Carry ternary functions.
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(a) (b)
Figure 7. Ternary maps for (a) ternary Sum: F1 = 0a0b1c + 0a1b0c + 2∙0a1b1c + 2∙0a2b0c + 1a0b0c + 2∙1a0b1c +
2∙1a1b0c + 1a2b1c + 2∙2a0b0c + 2a1b1c + 2a2b0c + 2∙2a2b1c, and (b) ternary Carry: F2 = 0a2b1c + 1a1b1c + 1a2b0c
+ 1a2b1c + 2a0b1c + 2a1b0c + 2a1b1c + 2a2b0c + 2a2b1c.
Figure 8. The Sum function F1 of the ternary 3-digit full adder, where – is a ternary don’t care (0, 1, or 2).
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Figure 9. The Carry function F2 of the ternary 3-digit full adder, where – is a ternary don’t care (0, 1, or 2).
As observed in Example 3, Figs. 8 and 9 represent a fully regular lattice network in three-
dimensions. Each dimension corresponds to a value of the corresponding control variable: value
zero of the control variable propagates along the x-axis, value one of the control variable
propagates along the y-axis, and value two of the control variable propagates along the z-axis.
Since the ternary function in Example 3 is fully symmetric, no variables are needed to be repeated
in the corresponding lattice network. In three-dimensional space, each control variable spreads in
a plane to control the corresponding nodes (these parallel planes are represented using the
corresponding dotted triangles in Figs. 8 and 9), in contrast to the binary case where each control
variable spreads in a line to control the corresponding nodes (these control signals are represented
in the corresponding horizontal lines in Fig. 3(a)). Each node in Figs. 8 and 9 represents a three-
input one-output multiplexer whose output goes in three directions.
All internal nodes in Figs. 8 and 9 are three-to-one multiplexers (i.e., selectors), where if one
multiplies each leaf value, going counter clock wise, with all possible out-to-in paths (from the
leaves to the root) and add them over Galois field (in Table 1) then one obtains the maps in Fig.
7(a) (F1) and Fig. 7(b) (F2), respectively. Also, one notes that internal nodes in Figs. 8 and 9 lay
on the corners of three-dimensional cubes, which is in contrast to the binary case (e.g., Fig. 4)
where nodes lay on the corners of two-dimensional squares. From Figs. 8 and 9, one observes that
the Sum and Carry functions are both symmetric, since there is no conflict in leaf values, and
consequently there is no need to repeat variables to make the ternary functions realizable in the
corresponding three-dimensional lattice networks. In ternary non-symmetric functions, at least
one leaf has conflict values, and one needs to repeat variables to symmetrize the corresponding
non-symmetric functions, in order to realize such functions in the corresponding three-
dimensional lattice networks. Example 4 shows the realization of a ternary non-symmetric
function in a three-dimensional lattice through the process of repeating variables.
Example 4. For the non-symmetric two-variable ternary-input ternary-output function F = ab +
a’b’’, and by adopting the right-hand rule of the Cartesian coordinate system, Fig. 10 illustrates
the three-dimensional logic network to implement such non-symmetric function. In Figs. 10(c)
and 10(d), if one multiplies each leaf value, going counter clock wise, with all possible out-to-in
paths (from the leaves to the root) and add them over Galois field (in Table 1), then one obtains
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the maps in Figs. 10(a) and 10(b), respectively, where {0a, 1a, 2a} are the zero, first and second
polarities of the 1-RPL of variable a, {0b, 1b, 2b} are the zero, first and second polarities of the 1-
RPL of variable b, and ternary-valued variables a and b can take any value in the set {0,1,2}.
(a) (b)
(c) (d)
Figure 10. Three-dimensional lattice networks for non-symmetric functions: (a) Ternary non-symmetric
function, (b) symmetrization by repeating variable a, (c) three-dimensional lattice network that corresponds
to Fig. 10(a) with conflicting leaves (in dark boxes), and (d) final three-dimensional lattice network that
corresponds to Fig. 10(b) with non-conflicting leaves.
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-V +V
F O2
PMMA
Gold Gold
Gold Gold
n-FET p-FET SiO2
Si back-gate Si back-gate
A
Figure 11. The NOT (inverter) logic gate using two nanotube-based FETs.
Figure 12 shows solid-state CNT-based multiplexer [4], [6] where CNT is used as a channel in a
Field Effect Transistor (FET). As was shown in Fig. 11, the use of CNT as a channel in FET has
been shown and a simple inverter that works exactly the same way as an ordinary CMOS inverter
was built. Here, we use the same principle of using CNT as a channel but in a different device
that uses two CNT n-FETs and two CNT p-FETs with different topologies of interconnects that
are used for inputs A and B, controls C and C’, and the output F. In Fig. 12, silicon (Si) is used as
back-gate in the device, silicon dioxide (SiO2) is used as an insulator, and gold is used as
electrodes (conductors). Four metallic catalyst islands with each pair located at the facing ends of
each pair of gold electrodes can be also used to grow CNTs between each pair of gold electrodes,
rather than just placing CNTs in contact with the gold electrodes. The PMMA is a cover that
protects anything beneath it from being exposed to oxygen (O2) where oxygen is used to convert
an n-CNTFET to a p-CNTFET.
The fabrication of each sub-device in Fig. 12 is done as follows [18]: Initially the two CNTFETs
are p-type. After vacuum annealing both CNTFETs are converted to n-type. The two CNTFETs
are exposed to oxygen (10-3 Torr of oxygen for three minutes), and the unprotected n-CNTFET
converts back to the original p-type, while the protected CNTFET remains n-type. Another
method to form p-type and n-type CNTFETs has been reported as follows: CNT channel dopped
with potassium (K) produces an n-type CNTFET, while a CNT without dopping produces p-type
CNTFET. Dopping produces n-type CNTFET by shifting the Fermi energy level to the
conduction band that results in an increase of electron concentration in the conduction band
which increases the conductance of the FET for a given positive gate voltage.
The function of the device in Fig. 12 can be analyzed as follows [6]: If C = “1” then the upper
transmission gate (t-gate) is activated and A is passed to F while the lower t-gate is deactivated
and B is not passed to F, and if C = “0” then the lower t-gate is activated and B is passed to F
while the upper t-gate is deactivated and A is not passed to F. Thus, the solid-state CNT
multiplexer functions exactly as a 2-to-1 multiplexer. Intra-molecular CNTFET technology [18]
can be used instead of each sub-device in Fig. 12 in which a single CNT bundle is placed on top
of three gold electrodes to produce an n-type and a p-type CNTFETs on the same substrate using
the exact procedure that is used for the inter-molecular CNTFET in Fig. 12.
Figure 13 shows the magnetic CNT-based multiplexer [4], [6]. The numbers on the parts of the
device in Fig. 13 indicate the following: (#1, #2, #3, #4, #5, #6) are CNTs, (#7, #8, #9, #10, #11)
are electrical current directions, (#12) is the body of the device which is an electrical insulator
such as glass, SiO2, plastics or any other type of electrical insulator, and (#13) is a hollow space
with structural walls in two opposite sides (sides of CNTs #1 and #2) made of an electrical
insulator.
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A
O2
PMMA Gold Gold
Gold Gold
n-FET p-FET SiO2
F
Si back-gate Si back-gate
B
O2 C C’
PMMA
Gold Gold Gold Gold
p-FET n-FET SiO2
Si back-gate Si back-gate
The device in Fig. 13 operates as follows: electrical current (#7) is input B and can have two
levels x and y that indicate logics “0” and “1”, respectively. Electrical current (#8) is input A and
can have two levels x and y that indicate logics “0” and “1”, respectively. The two electrical
currents (#7, #8) are flowing in the directions indicated in Fig. 13 in CNTs (#1) and (#2),
respectively. The flow of these currents will produce magnetic fields around CNTs (#1, #2)
according to Ampere’s (circuital) law in the Maxwell’s equations [33] that relates the magnetic
field around a closed loop to the electric current passing through the loop, for which the
differential form representation in terms of the total charge and current takes the formulation as
shown in Equation (5).
10
4 6 11
8 2
3 9
13
7
1
12
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E
xB 0 J 0 0 (5)
t
where B H is the magnetic field (magnetic flux density; magnetic field density), H is the
magnetizing field (or magnetic field intensity), xB is the curl of the magnetic field, 0 is
D
permeability, 0 is permittivity, J is current density, E is the electric field, D is the
E
electric displacement field (or electric flux density), and is the time derivative of the electric
t
field. The direction of such magnetic fields follows the conventional right-hand thumb rule [33].
The CNT (#3) initially is in contact with either CNT (#1) or CNT (#2), and thus a current would
be running in CNT (#3) in the same direction as currents (#7, #8). An electrical current is pumped
through CNTs (#4, #5, #6), and this current can be pumped either in clock wise (CW) direction
(#10) or counter clock wise (CCW) direction (#11). The electrical current (#10) flowing in CNTs
(#4, #5, #6) will produce a magnetic field according to Maxwell’s equations in a direction
according to the right-hand thumb rule, and if current (#11) flows in CNTs (#4, #5, #6) a
magnetic field will be produced in an opposite direction of that which is produced by current
(#10). The direction of the current flowing in CNTs (#4, #5, #6) and thus the direction of the
magnetic fields plays the role of the control signal in a regular multiplexer as follows: if current
(#11) is flowing in CNTs (#4, #5, #6) then an attractive Lorentz force occurs [33]:
FI x B (6)
where I xB is the cross product between current I in a conductor that lays in magnetic field B ,
and F is the Lorentz force between two current-carrying conductors that occurs between CNT
(#5) and CNT (#3) that causes CNT (#3) to move in the space (#13) towards CNT (#5) and thus
makes a contact with CNT (#2) which means that current (#8) or input A is selected to flow to the
output. On the other hand, if current (#10) is flowing in CNTs (#4, #5, #6) then a repulsive
Lorentz force occurs between CNT (#5) and CNT (#3) that causes CNT (#3) to move in the space
(#13) away from CNT (#5) and thus makes a contact with CNT (#1) which means that current
(#7) or input B is selected to flow to the output. Thus, the nano mechanical device in Fig. 13
implements a two-to-one logic multiplexer (selector). It has to be noted that one has to wait a
period of time equal to T in order to obtain the result at the output. This time indicates the
traveling (or displacement) time needed for CNT (#3) to make a contact with either CNT (#1) or
CNT (#2) depending on the direction of the electrical current flowing in CNTs (#4, #5, #6).
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model, and λL is the local pre-exponential correction factor where it takes into account all of the
other factors that influence the emission. The factors νF and λL depend on the applied field F.
This section presents important functional modeling of field emitters and the corresponding
experimental setups and measurements that characterize their time-dependent response. In order
to perform the static modeling of CNT field emitters, four field emission carbon nanotubes, which
are shown in Figs. 14(b)-14(e), were manufactured by Xintek, Inc. The copper anode is at the
right and the CNT emitter is mounted on a tungsten wire attached to the copper cylinder at the left
as shown in Fig. 14(a). Figures 14(b)-14(e) show the images of CNT emitters for each carbon
nanotube, taken with a JEOL Ltd. model JEM 6300 SEM [24]. Carbon nanotubes M-1 and M-4
have a single MWCNT as the emitter, and carbon nanotubes C-3 and C-6 have a single SWCNT
as the emitter. The used CNTs were formed in bundles that have diameters of 10-30 nm, but in
each carbon nanotube the field emission is from the one CNT at the end of the bundle where the
electric field is most intense.
(d) (e)
Figure 14. Carbon nanotube – based field emission: (a) structure of the field emission carbon nanotubes
manufactured by Xintek Inc. and (b) - (e) Scanning Electron Microscopy (SEM) images of the CNT
emitters in the four utilized carbon nanotubes.
The DC current-voltage characteristics were measured for these four carbon nanotubes, as well as
a field emitter tube from Leybold Didactic GmbH, which has an etched single crystal of tungsten
as the emitter. All of the measurements that were made with the five tubes were performed at
room temperature. The tungsten tip is mounted on a filament so that this tip is heated for cleaning
shortly before each session of measurements. However, it is not possible to clean the CNT, which
probably causes the “switch-on” effect in which the supply voltage must be momentarily
increased well beyond the operating point to initiate field emission with the CNT. The data from
the DC measurements were reduced by the Fowler-Nordheim analysis which is based on the
following simplified form of the Fowler-Nordheim equation that provides the magnitude of the
current density as a function of the applied static field for the field emission from a specific
material:
J = A E2 e (-B/E) (8)
where J and E are the magnitudes of the current density and the electric field intensity, A = 1.541
x 10-6/Φ, and B = 6.831 x 109 Φ3/2. The work function values are Φ = 4.5 eV for tungsten and (for
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International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 1/2/3/4/5, October 2020
the CNT) was set to Φ = 4.9 eV for graphene. In order to apply the Fowler-Nordheim equation to
the DC current-voltage data, the following equation was also used which is valid for a given
carbon nanotube, where I is the field emission current and V is the potential applied between the
anode and the cathode:
I = CV2 e (-D/V) (9)
Equations (8) and (9) can be combined to obtain the following equations for the parameters S and
R, which are used to characterize the field emitters:
S = CD2/AB2 (10)
R ≡ V/E = D/B (11)
where parameter S refers to the effective emitting area which would be the physical area of the
emitter if the current density were uniform over a fixed area and zero elsewhere, and parameter R
refers to the effective radius of curvature of the emitter but also includes the effects of local
intensification of the electric field caused by elongation of the emitter or the reduction of the field
which may be caused by shielding due to adjacent structures.
The Fowler-Nordheim plots of the DC current-voltage data were conducted using ln(I/V2) as the
ordinate and (1/V) as the abscissa. Equation (9) requires that these plots should be straight lines
and typically with correlation c - 0.998. Linear regressions based on these Fowler-Nordheim
plots typically have a standard variance 0.08, and the probability for the null-hypothesis, that
no linear relationship exists, is less than 0.0001. The values of the parameters {C, D, S, R} were
determined from the linear regressions. A series ballast resistor of 100 MΩ was typically used in
the measurements. However, when the series ballast resistor was increased to 2.575 GΩ with
carbon nanotube C-6, the obtained data were not consistent with the Fowler-Nordheim equation
(c = - 0.846, = 0.738) even though the emitted current was stable at each value of the applied
static potential. Figure 15 shows the anomalous data which were obtained using the 2.575 GΩ
ballast resistor. In order to explain this effect, it is hypothesized that for currents greater than 500
nA, field emission with a single CNT may be intermittent, fluctuating at a high frequency. Thus,
the average current, as measured by the DC microammeter, may be much greater with a large
ballast resistor and this is because at those times when the current is momentarily low, the voltage
drop across the ballast resistor is at minimum so that high voltage occurs across the CNT, and this
voltage causes a short-duration surge in the current.
The values of parameter R, the effective radius of curvature of the emitter, were found to vary
within 77-110 nm for the four carbon nanotubes with CNT emitters. This suggests that values of
the local electric field at the emitting sites were as high as 14 V/nm in some of these
measurements. Others studying the field emission from various CNTs have provided approximate
values for the electric field by dividing the applied voltage by the distance between the anode and
the emitting tip, noting that this field would be intensified by the shape of the CNT, but not
estimating the local electric field at the emitting sites [30]. The Fowler-Nordheim analysis gave a
value of 91 nm for the effective radius of curvature of the emitter in the Leybold tube, suggesting
that the local electric field was as high as 5 V/nm in some of the performed measurements [24].
Current densities as high as 109 and 1012 A/m2 may be drawn from a tungsten emitter in steady-
state and pulsed operation, respectively, and the corresponding values of the applied static field
are 4.7 and 8.6 V/nm which may be considered as limiting field strengths for tungsten under these
conditions. Thus, the value of the parameter R which was obtained for the Leybold tube appears
to be reasonable.
The Fowler-Nordheim analysis also showed that the parameter S, the effective emitting area,
varied within 81-230 nm2 for the four carbon nanotubes with CNT emitters. If the current density
was uniform, this would correspond to circular emitting spots having radii of approximately 5-9
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International Journal of VLSI design & Communication Systems (VLSICS) Vol 11, No 1/2/3/4/5, October 2020
nm. Others have used Lorenz microscopy to directly observe the emitting sites for field emission
from MWCNT, and they found one or more sites having radii of several nm, and their data were
in reasonable agreement with other performed experiments.
-27
-28
-29
ln(I/V )
2
-30
-31
-32
Figure 15. The obtained Fowler-Nordheim plot for CNT C-6 with 2.575 GΩ ballast resistor.
The Fowler-Nordheim analysis also showed that the effective emitting area for the tungsten tip in
the Leybold tube would correspond to a hemisphere with a radius of 290 nm. This result and the
value of 91 nm for the effective radius of curvature of the emitter in the Leybold tube were in
reasonable agreement with the radius of 100-200 nm which was specified by Leybold.
Recently conducted simulations and experiments had shown that photomixing (i.e., optical
heterodyning) in laser-assisted field emission could be used as a new microwave or terahertz
(THz) source with a multi-octave bandwidth [9], [12], [14], [25]. The field emitter tip used is
much smaller than the wavelength of the incident optical radiation so quasi-static conditions
require that the electric field of the radiation is superimposed on the applied static field to
modulate the height of the energy barrier. Electrons tunnel from the tip into vacuum with a delay
of less than 2 fs. Therefore, because the current-voltage characteristics of field emission are
extremely nonlinear, it is shown that if two lasers are focused on the tip, the mixer current would
follow each cycle of the difference frequency of the two lasers from DC up to 500 THz (which is
equal to 1/). It is also shown that the tip will withstand applied static fields as high as 9 V/nm, so
that incident laser radiation with comparable field strengths could produce a bright source of
microwave or THz radiation.
surface which are afterwards being ultrasonically cleaned using an ultrasonic cleaning device and
mounted in a standard field emission microscopy (FEM) with a tip screen distance of 10 mm. The
anode is formed as phosphored screen to allow recording of the emission images.
The FEM was evacuated to ultra high vacuum (UHV) conditions using rotary pump that produce
pressures of about 10−3 mbar and a diffusion pump system in addition to a liquid nitrogen (LN2)
trap that lead to finally reaching a base pressure of about 10-9 mbar. Then, the tips received
sample conditioning which consists of an initial baking of the system for 12 hours at 170 °C, a
follow up baking of the system for 12 hours, thermal relaxation for 12 hours at 170 °C, and
finally cooling the sample by liquid nitrogen – while studying emission behavior [8]. This
allowed the recording of the effects of these conditioning processes on carbon fiber tips.
To record the emission behavior, the voltage applied from extra high tension (EHT) to the tip is
slowly increased until the emission current rises to about one microampere on the picoammeter
device, and then the voltage is slowly decreased until the emission current was vanished. Within
this range, a linear Fowler-Nordheim plot is expected. Figure 16 presents the scanning electron
micrograph of a produced very sharp carbon fiber tip at about 10,000 x magnification.
Figure 16. Scanning electron micrograph of a very sharp carbon fiber tip at 10,000 × magnification.
The apex radii of carbon fiber tips have been measured as the average of the graphically best-
fitting circles. The latter ones are used to interpret the experimental data and extract relevant
information such as the apex radii. During the experiments, electronic emission images have been
recorded by a standard digital camera to study the spatial distribution and stability of the emission
current. Stability as well as brightness are important factors for judging the quality of the electron
source for practical applications. During the sample conditioning treatment, it was discovered that
there were statistical variations in the electronic emission of the various tip microemitters under
the corresponding UHV conditions. One of the very sharp carbon fiber tips has been tested during
sample conditioning treatment [8] where the apex radius of this tip was around 57 nm.
Figures 17-20 show the emission characteristics that are derived as the I-V characteristics and the
corresponding Fowler-Nordheim plots.
Figure 17. The I-V characteristics (left) and FN plot (right) of very sharp tip after initial baking for 12
hours at temperature of 170°C.
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Figure 18. The I-V characteristics (left) and FN plot (right) of very sharp tip after follow-up baking for 12
hours at temperature of 170°C.
Fig. 19. The I-V characteristics (left) and FN plot (right) of very sharp tip after thermal relaxation process
for 12 hours.
Fig. 20. The I-V characteristics (left) and FN plot (right) of very sharp tip during cooling process.
After initial baking, as was shown in Fig. 17, the FN plot shows a non-linear behavior and
emission current was unstable. The follow up baking, as shown in Fig. 18, shows a disconnected
plot because the voltage drops from 66 V to 5.5 V where this drop is due to hysterical current.
After the sample conditioning, the emission current stability becomes much higher as shown in
Figs. 19 and 20.
As previously mentioned, the presented background and fundamentals in this section with regards
to carbon nanotubes and nanotips and their corresponding field-emission will be further utilized,
in addition to the basic background on lattice networks that was presented in Sections 2 and 3,
within the follow-up works in the second and third parts of the article for designing concurrent
nano-based three-dimensional lattice networks, where the new implementation of ternary Galois
functions using carbon field-emission switching devices will be performed.
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5. CONCLUSIONS
Fundamentals of concurrent processing using three-dimensional lattice networks are presented,
and basic characteristics of carbon-based field-emission are also shown. This includes the newly
investigated Fowler-Nordheim and I-V characteristics for carbon nanotip-based field emitters.
The presented basics in this first part will be utilized within the second and third parts of the
article for the synthesis of nano-based three-dimensional networks to implement ternary Galois
functions in three-dimensions using carbon field-emission switching devices that are based on the
presented carbon nanotube and nanotip field-emission characteristics.
The two-to-one controlled switch is a basic building block in switch logic, which is proven to be
of fundamental practical importance in cost-effective modern logic design within wide variety of
circuits and systems. The concept of switch logic is that logic circuits are implemented as
combination of switches rather than a combination of gates as in gate logic, where it has been
shown that this type of synthesis possesses direct one-to-one mapping from the design layer into
physical layer for wide range of applications including lattice networks. As previously stated, the
presented field-emission basics in this first part will be further utilized in the second and third
parts of the article which form new and interesting design directions via the synthesis of
emission-based controlled-switching within concurrent three-dimensional lattice systems.
ACKNOWLEDGEMENT
This research was performed during sabbatical leave in 2019-2020 granted to the author from The
University of Jordan and spent at Isra University, Jordan.
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AUTHOR
Anas N. Al-Rabadi is currently a Professor in the Department of Computer Engineering at The University
of Jordan. He received his Ph.D. in Computer Design and Advanced Logic Synthesis from the Electrical
and Computer Engineering Department at Portland State University in 2002, received his M.Sc. in
Feedback Control Systems and Power Electronics Systems Design from the Electrical and Computer
Engineering Department at Portland State University in 1998, and was a Research Faculty at the Office of
Graduate Studies and Research (OGSR) at Portland State University. He is the author of the first
comprehensive graduate-level book and the first published title on Reversible Logic Synthesis, Reversible
Logic Synthesis: From Fundamentals to Quantum Computing (Springer-Verlag, 2004). Currently, Prof. Al-
Rabadi is the author of more than 130 international scholarly articles that are published in international
books, book chapters, journals and conferences, in addition to a registered U.S.A. nanotechnology patent.
His current research includes parallel and distributed computing, systolic architectures, regular circuits and
systems, reversible logic, quantum computing, multiple-valued logic, soft computing and computational
intelligence, machine learning, optical computing, reconstructability analysis, signal processing, testing and
design for testability, nanotechnology, robotics, optimal robust control, and digital error-control coding.
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