European Journal of Scientific Research ISSN 1450-216X Vol.23 No.4 (2008), pp.626-638 EuroJournals Publishing, Inc. 2008 http://www.eurojournals.com/ejsr.

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The Design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function
Keivan Navi Department of Electrical & Computer Engineering and Microelectronics Research Center, Shahid Beheshti University Email: {navi, mrc-ecef}@sbu.ac.ir Tel: (+98)21-29902286; Fax: (+98)21-22431804 Neda Khandel Microelectronics Research Center, Shahid Beheshti University and IAU Tel: (+98)21-29902286; Fax: (+98)21-22431804 Abstract In this paper, two high performance adder cells are proposed. We simulated these two full adder cells using HSPICE in 0.18 m, CMOS technology and at 25-degree of temperature with supply voltage range from 0.5v to 3.3v with 0.1v steps. Results show that the proposed adders operate successfully when connected to a 0.5 V power supply. The two adders differ in the technology applied to their gates. While the first circuit applies CMOS technology, the second and optimal one uses Past Transistor Logic. The average power dissipation of the optimum is 4.3269*10-7 watt, which illustrates an amazing performance. This paper demonstrates the PDP and Power Consumption of the proposed adders, and the comparison results among another six full adders. Keywords: Adder Circuits, Low-Power Logic Style, Pass Transistors, CMOS Logic

1. Introduction
Adder is one of the most important components of a CPU (central processing unit). Arithmetic logic unit (ALU), floating-point unit and address generation like cache or memory access unit use it. In addition, Full-adders are important components in other applications such as digital signal processors (DSP) architectures and microprocessors [1-5]. Arithmetic functions such as addition, subtraction, multiplication and division are some examples, which use adder as a main building block. As a result, design of a high-performance full-adder is very useful and important [2, 3, 6-8]. On the other hand, increasing demand for portable equipments such as cellular phones, personal digital assistant (PDA), and notebook personal computer, arises the need of using area and power efficient VLSI circuits[2, 9-12]. Low-power and high-speed adder cells are used in battery-operation based devices [13-15]. In this paper, we present two different 1-bit full-adder cells, with suitable power consumption, delay and performance. We have simulated these two Full-adders and compared the Power dissipation, time delay, and power delay product (PDP) of the proposed cells with six other adders. The results show a lower Power Consumption and PDP among the other ones.

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The remainder of the paper is as follows: The related work is briefly described in the next section. Then, we focus on the design of the adders in detail. In simulation results section, the simulation results are demonstrated. Conclusion is the last section of the paper.

2. Related Works
Some designs of adder cells can be found in the figures 1 to 6. These six different adder cells are simulated in 0.18 m CMOS technology and tested separately. All these cells are optimum in power dissipation and Power delay product (PDP). The conventional adder shown in figure 1 is implemented with 28 Transistors in CMOS technology. Conventional adder circuits do not function well below one V supply [16]. Figure 2 shows the Complementary Pass-transistor Logic (CPL) adder. Among the passtransistor logic styles, CPL has the best performance and the lowest power delay product[17]. The Transmission Function full Adder (TFA), which is shown in figure 3, uses 16 transistors. Pull-up and pull-down logic is used to drive the load the same as the complementary pass logic [18]. Figure 4 shows the Transmission Gate full adder (TG). TG adder includes 20 transistors, and generates a+b and its complement to produce the sum and carry signals. It uses complementary input signals (a,b,c) as the complementary CMOS full adder [19, 20]. This full adder uses only 14 transistors to make the adder function. The circuit occupies less area in comparison with other CMOS full adder cells[20]. At end, another full adder with 26 transistors is presented in figure 6 [21].
Figure 1: Conventional CMOS full adder

The design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function
Figure 2: Complementary pass-transistor logic (CPL) adder

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Figure 3: Transmission function adder (TFA)

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Figure 4: Transmission Gate (TG) CMOS adder

Figure 5: Fourteen Transistor (14T) adder

The design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function
Figure 6: 26 Transistor adder

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3. Circuit Design
A full adder has three inputs, i.e., a, b, and c (carry in), and two outputs sum and carry. The basic operation of full adder is expressed as:

which the operators and. are respectively logic exclusive OR and AND functions. Figure 7 shows the design of the new full adder. In this section, we show how the majority function can generate the carry signal, by the same time; sum signal can be produced by majorityNOT. The majority function returns logic 1, only if there is more logic 1s than logic 0s given at the input. Obviously, the majorityNOT is the reverse of the majority function. Therefore, by extending the above equations of sum and carry, they are changed to:

Table 1 depicts the truth table of sum and majorityNOT. It can be seen that the sum is not exactly the same as the majorityNOT. The value of these two functions are not equal at a=b=c=0 and a=b=c=1. Therefore, we correct these two states by using a PMOS and an NMOS transistor. These transistors must be arranged in such a way that ensures the correctness of the circuit. Three capacitors are used to generate the majority function. The proposed Full-adders include two three-input NAND and NOR gates. The two adders differ in the designing of these gates. The first adders gates are designed in standard CMOS logic (Figure 8); however, Pass-Transistor (PT) logic is chosen to implement the gates in the second one. The change is in order to improve the performance of CMOS circuits and decrease the number of transistors. The gates designed with pass-transistor logic styles have less power dissipation and delay than standard CMOS logic. Figure 9 shows the design of the latter adder.

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Figure 7: The new full adder cell

Keivan Navi and Neda Khandel

Table 1:
a 0 0 0 0 1 1 1 1

The truth table of the sum and majorityNOT equations

b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 MajorityNOT 1 1 1 0 1 0 0 0

Figure 8: Full adder cell with CMOS gates

The design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function
Figure 9: Full adder cell with PT gates

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4. Simulation Results
All the adders are simulated in 0.18 m standard CMOS technology at the room temperature. The simulations are done with HSPICE, which is an acceptable simulator. In the simulations, the circuits are connected to a range of 0.5 V to 3.3 V power supply, with the steps of 0.1 V. The adder designed by PT Logic shows a better performance in terms of power and PDP in comparison with the other one which uses CMOS technology. The simulations results of the two new full adders are illustrated in table 2. Table 3 depicts the simulation results of the suggested full-adder's performance with PT gates under the mentioned circumstances. In this table, VDD shows the supply voltage that maintains the correct functionality of the full adder cell. POW indicates the average of the power dissipation. The PDP is the power delay product. Delay illustrates the worst-case of delay. Figure 11 shows the sum and carry output waveforms of the suggested full-adder with PT gates, for an input pattern corresponding to the transitions that cover all input combinations showed in Figure 10. This figure shows that all simulated designs have properly responded to the different input patterns. In Figure 12, the average of power consumption curves for six other adders are presented. As illustrated in it, the transmission function adder (TFA), in the terms of power consumption, is better than the other adders unless one; therefore, power consumption of the suggested full adder with PT gates is compared with power consumption of TFA in Figure 13. Our adder shows better performance in power consumption in comparison with TFA. Figure 14 shows the PDP amount for the six tested full adders. TFA has the best performance in PDP than the other five adders, with which are compared, but the suggested adder with PT gates is better than TFA (This point is shown in figure 15). The figures show that the suggested adder with PT gates consumes 97.6% less power compared to TFA adder, which has the best power consumption results among the six tested full adders. Powerdelay product of the proposed adder is less than other compared adders. The results show 90% improvement in regards of PDP of our adders, when being compared with the TFA adder. In addition, the power dissipation and PDP of the six full adders and the new adder with PT gates at three different VDDs are listed in Table 4 and 5. As a result, the new adder is better than the other adders in terms of power consumption and PDP.

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Table 2: Simulation results of two new full adder
New adder with CMOS gates POW(w) PDP(J) 1.08E-06 3.62E-16 1.88E-05 4.03E-15 1.88E-05 1.36E-14

Keivan Navi and Neda Khandel

VDD(v) 0.5 1.8 3.3

New adder with PT gates POW(w) PDP(J) 4.33E-07 1.79E-16 4.14E-06 1.81E-15 1.38E-05 9.54E-15

Table 3:

Simulation results of Full-Adder with PT gates

VDD(V) 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 POW(w) 1.38E-05 1.28E-05 1.20E-05 1.12E-05 1.05E-05 9.79E-06 9.11E-06 8.45E-06 7.82E-06 7.22E-06 6.45E-06 6.08E-06 5.56E-06 5.06E-06 4.59E-06 4.14E-06 3.72E-06 3.31E-06 2.94E-06 2.58E-06 2.25E-06 1.95E-06 1.66E-06 1.40E-06 1.15E-06 9.37E-07 7.42E-07 5.73E-07 4.33E-07 PDP(J) 9.54E-15 7.16E-15 6.59E-15 6.07E-15 5.58E-15 5.08E-15 4.65E-15 4.23E-15 3.84E-15 3.48E-15 2.96E-15 2.83E-15 2.54E-15 2.27E-15 2.03E-15 1.81E-15 1.59E-15 1.40E-15 1.22E-15 1.07E-15 9.22E-16 7.90E-16 6.69E-16 5.64E-16 4.63E-16 3.78E-16 3.02E-16 2.33E-16 1.79E-16 Delay(t) 6.93E-10 5.60E-10 5.50E-10 5.40E-10 5.31E-10 5.20E-10 5.10E-10 5.00E-10 4.91E-10 4.83E-10 4.59E-10 4.65E-10 4.56E-10 4.49E-10 4.43E-10 4.36E-10 4.27E-10 4.21E-10 4.16E-10 4.14E-10 4.09E-10 4.06E-10 4.03E-10 4.04E-10 4.01E-10 4.03E-10 4.06E-10 4.07E-10 4.15E-10

The design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function
Figure 10: Simulation input patterns

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Figure 11: Output (carry and sum) signals form, for the new adder

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Figure 12: Average power consumption of six tested full adders

Figure 13: Average power consumption curves

The design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function
Figure 14: PDP of six tested full adders

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Figure 15: The PDP curves

Table 4:
VDD(v) 0.5 1.8 3.3

The Power dissipation (watt)

Conventional(W) 3.68E-05 2.46E-04 8.62E-04 CPL(w) 6.11E-05 4.12E-04 1.30E-03 TFA(w) 1.81E-05 1.38E-04 4.53E-04 TG(w) 2.42E-05 1.82E-04 5.47E-04 14T(w) 4.01E-04 1.53E-04 4.91E-04 26T(w) 5.02E-05 4.26E-04 1.32E-03 Suggested(w) 4.33E-07 4.14E-06 1.38E-05

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Table 5:
VDD(v) 0.5 1.8 3.3

Keivan Navi and Neda Khandel

The PDP (J)
Conventional(J) 1.35E-14 2.17E-14 7.11E-14 CPL(J) 1.93E-14 3.29E-14 9.16E-14 TFA(J) 1.85E-15 9.30E-15 2.55E-14 TG(J) 2.47E-13 1.22E-14 3.14E-14 14T(J) 2.91E-14 1.22E-14 3.56E-14 26T(J) 7.99E-15 2.81E-14 7.82E-14 Suggested(J) 1.79E-16 1.81E-15 9.54E-15

5. Conclusion
In this paper, we have proposed two new full adder designs by combining common digital gates and majority functions. We have compared the performance of the better one with six other full adders. The proposed full adders have shown a better performance in average power consumption and power delay product as being compared to the other full adders. This circuit has been tested in 0.18 m CMOS technology and operates successfully at different supply voltages and 25-degree temperature. According to HSPICE simulation, an improvement of 97.6% in power consumption compared to the best analyzed adder is gathered. At end, the proposed full adder shows 90% degradation in power delay product.

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