EFFICIENT POLYPHASE DECOMPOSITION OF COMB DECIMATION ANALOG-TO-DIGITAL CONVERTERS.

FILTERS IN
H. Aboushady, Y. Dumonteix, M. M. Lou rat and H. Mehrez e Universit Paris VI, Laboratoire LIP6/ASIM e 4, Place Jussieu, 75252 Paris Cedex 05, France
Email: [email protected] , [email protected]

A power efcient multi-rate multi-stage Comb decimation lter for mono-bit and multi-bit A/D converters is presented. Polyphase decomposition in all stages, with high decimation factor in the rst stage, is used to signicantly reduce the sampling frequency of the Comb lter. Several implementations indicate that proper choice of the rst stage decimation factor can considerably improve power consumption, A/Ds, area and maximum sampling frequency. In multibit this optimum rst stage decimation factor is function of the input wordlength. I. I NTRODUCTION Nowadays, power consumption of decimation lters in A/D converters is receiving an increasing attention [1][2][3]. Comb lters, shown in Fig.1(a), are widely used in the decimation lter of A/D converters. These lters operate at maximum sampling frequency before any decimation takes place. The power consumption of Comb lters is then very high. The transfer function of a Comb lter of order and for a decimation ratio is dened by

(1)

II. P REVIOUS W ORK C OMPARISON In the IIR-FIR structure, shown in Fig.1(b), the FIR lter, , operates at a sampling frequency times lower

$7 4 " 8T 1

t$XT R `P &

' c b`YW a

In this paper, we present a different representation of the Comb lter. This representation allows us to exploit the Polyphase decomposition in order to perform higher decimation factors at the input of the rst stage. Although coefcients, resulting from this decomposition, require expensive multiplication operations and larger wordlength, the overall power consumption is lower. This is due to the signicant reduction of the operating frequency. We show that, an optimum decimation factor exists that compromises the added complexicity of the Polyphase decomposition with the reduction of the operating frequency. This optimum decimation factor depends on the output wordlength of the modulator.

Applying the commutative rule [6], we get the FIR2 structure shown in Fig.1(c). In this structure, the Comb lter is realized identical FIR lters, , each by cascading decimating by 2. The POLY-FIR2 structure [5], illustrated in Fig.1(d), is obtained by applying Polyphase decomposition [7], to the FIR2 structure. In this case, the decimation occurs at the input of each lter, thus reducing by 2 the sampling frequency of each stage. The FIR2 and the POLY-FIR2 structures have the advantage of not having any stability problems and the wordlength of each stage is limited to bits. The average power consumption of a digital signal processing system is proportional to: the number of operations performed per sample, the wordlength and the sampling frequency. In Comb lters, we will assume that the number of operations is equal to the number of partial products to be added.

R y B@ c 4 T 1 84X6 vxu tsrqpih)%#"! " 7 w g ($

These lters were usually implemented using the IIR-FIR technique [4], Fig.1(b). Recently lower power consumption has been achieved using the FIR2 [3], and the POLY-FIR2 [5], implementations, shown in Fig.1(c) and Fig.1(d) respectively.

than the IIR lter, . In order to ensure stability of the IIR lter, the wordlength of the IIR lter has to be equal to bits [4], where is the number of bits at the lter input. The major drawback of this architecture is that the IIR lter is operating at maximum sampling frequency and with a very large wordlength. Equation (1) can be written in the following form:

R fP

I G F7 4 $ %H5E7

$ 'ca W & T R ebdb`YXVUSQP

 

 

&

'

 

B)A284 " @97 ($ 64 5" 31 )%#"! 31 20 '

 

$ %#"!

 

  @

x[n]

(
1

1 - z -M 1 - z -1

y[n]

(a)
x[n]

1 - z -1

M (b)

(1 - z )
-1

y[n]

x[n]

(1 + z )
-1

(1 + z )
-1

2 (c)

(1 + z )
-1

y[n]

x[n]

2 2

E0 ( z )
z
-1

2 2

E0 ( z )
z
-1

2 2

E0 ( z ) E1 ( z )

y[n]

-1

E1 ( z )

E1 ( z )
(d)

Fig. 1. (a) Comb lter. (b) IIR-FIR implementation. (c) FIR2: cascade of FIR lters each decimating by 2. (d) POLY-FIR2: Polyphase decomposition applied to FIR2.

(2)

$7 4 3 E8D" C1

350 300
IIRFIR

x[n]

H1 ( z )

M1

(1 + z )
-1

2 (a)

(1 + z )
-1

y[n]

Power Consumption

250 200 150 100

x[n]
-1

M1 M1

E0 ( z )
z
-1

2 2

E0 ( z )
z
-1

2 2

E0 ( z ) E1 ( z )

y[n]

E1 ( z )

E1 ( z )

z-1 z
-1

M1

E-1 ( z ) M
1

(b)

50 1

(3)

The coefcients of this lter are integers and symmetrical , where . Applying Polyphase decomposition on the lter of equation (7), we get

. . .
w y 2 w v DS f g2 d

(4)

where,

Efcient Polyphase implementation of is shown in Fig.3(b). As we can see, decimation takes place before ltering, so multiplications and additions are performed at a samtimes lower than the frequency of the input pling frequency signal. The subsequent lters decimating by 2 are nothing but a special case of the general case described above. Higher values of will signicantly reduce the sampling frequency of the rst stage which can be interesting for power consumption. On the other hand, we can see, from equation (5), that higher values of will increase the order of the lter , which implies more complex coefcients and a higher number of partial products. Note also that the wordlength of the polyphase lter will increase since it is equal to bits.

$ %#" 7 

7 '

r p s7i

$ 7 ' c b`YW T R QP a &

b c`

7 '

7 '

$ %#" 7 

As shown in Fig.3(a), we propose to decompose the Comb decimation lter into a rst stage FIR lter with a decimation factor , followed by a cascade of FIR lters with a decimation factor 2. The reason behind choosing this representation is that we would like to decimate as much as possible in the rst stage. The following stages are kept with the minimum decimation ratio 2 because, when the wordlength of the input signal is high, reducing the sampling frequency does not compensate for the added complexity of the Polyphase decomposition. In the following, we will explain how Polyphase decompostion is applied to Comb decimation lters. Equation (1) can be written in the following form:

d g0 U V

b` cY

f g2

III. P ROPOSED C OMB F ILTER A RCHITECTURE

$ 1h3 7 ' & (  $ P Ah3 31 H IR B ($ 4 "$ QP `w84 I  G 6 g @ )%#" 7  7

d g0yxDS U V 2 w v

d gyxDS U V 2 w v

f g2

r p sqi

t usqi r p

` I h cbY 2 d U

f g2

d e h

b` caY

d U

W XTDT2 V US

$1 3 7 ' &

( $

P Q

where is the number of partial products to be added in stage , the input wordlength of stage , the decimation factor in stage and the total number of decimation stages. Equation (3) is used to compare the power consumption for different implementations of a order Comb lter, with a decimation factor of . Fig.2 shows that power consumption of POLY-FIR2 is signicantly lower than the two other techniques. All three implementations have the same number of partial product per stage . The very large wordlength, in the rst stage of the IIR-FIR technique , is the reason behind its considerably higher power consumption. POLY-FIR2 requires exactly the same hardware as FIR2, but operates at half the sampling frequency. In the next section, we will introduce a different architecture that reduces even more power consumption, especially for low input wordlength.

The expansion of

7 

( %#" 7  $ ( %#" c  $

The power consumption, , can then be dened by the following relation:

$" R y B@ c 4 "T 1 8Q4w I FxEE Es q ig 7 u R py @ y 4 " 84 I  6 B 7

results in an FIR lter of order

Fig. 2. Estimation of power consumption for different implementations of a order Comb lter with a decimation factor of ( and ).

2 A

2 3

2 3 4 5 Input Wordlength Wo (bits)

Fig. 3. (a) Cascade of FIR with high decimation factor in the 1st stage. (b) Polyphase decomposition of the 1st stage lter decimating by and the subsequent lters decimating by .

@ 86 2 09754

$7 4 E8" T 1 7 $ %#" 



$ 01 ( y )

'

$  %#" c f$ " 7  ( %#"! $

' 7  7 i y  ( y P y y    
  % # $" ' (&

7 '

$"' P d$1T R h( y QP

y P

(5)

(6)

(7)

(8)

x[n]

M1

z-1

E0 (z)

z-1

TABLE I

Adder Tree
(Wallace tree) y[n]

M1

z-1

z-1

Fig. 4. Direct-form implementation of one stage of the Comb lter using one adder-tree.

 

To study the effect of the decimation factor of the rst stage on the overall performance of the circuit, several order Comb lters, with a total decimation factor of have been implemented. Each lter had: a different decimation factor in the rst stage , and a different input wordlength bits . These lters have been realized using the proposed system architecture described in
% # (" ' &

'

V. P ERFORMANCES E VALUATION

where is the number of combinational logic layers necessary to sum the partial products of stage . The estimated circuit performances, based on equations (3), (9) and (10), are shown in Fig.5. The circuits have been implemented in a standard low-cost technology. Simulation results of the circuit performances are shown in Fig.6. Comparing Fig.5 and Fig.6, we see that equation-based estimations are very close to the simulations. Analyzing these gures, we can see that, for mono-bit , minimum power consumption and area are achieved for a decimation factor . The worst performances are obtained when , which is in fact nothing but the POLY-FIR2 structure. Comparing the two implementations for and : the power consumption is reduced by 30%, the area is reduced by 20%, and the maximum sampling frequency is 5 times higher. In fact, the sampling frequency is limited by the intrinsic propagation delay of the D Flip-Flop. For multi-bit (6-bit) , minimum power consumption and area are achieved for a decimation factor and . Since higher frequency of operation can be achieved with , the implementation with is more interesting. In general, for multi-bit , we can see that, as the number of bits at the input of the Comb lter decrease, the proposed architecture becomes more interesting. Although the main purpose from this architecture was to achieve low-power consumption, signicant improvements regarding area and maximum sampling frequency have also been obtained.

7 1 ( '

 

(7 '

$ P  db`YW ca i y y  6 8 6 @8 98 77 9 '7 1 ) ( $" $ y P  y  y   c a #YW 0 A 20'5 43y (1 A%#& '

(7 '

$ " %#!

(7 '

C B " D%(&

 

7 ' ' ( 7 7 ' ( ' 1 ( '

The choice of the FIR architecture to implement the polyphase lters has an important impact on power consumption. FIR lters are implemented either in a transposed-form or a direct-form. Each of these two forms has one main drawback. The transposed-form requires larger wordlength for the intermediate registers, which can increase power consumption. The direct-form has a long critical path which limits the maximum sampling frequency of the lter. Since the use of Polyphase decomposition has highly reduced the operating frequency of the lter, the critical path is no longer a problem. Thus we have chosen the direct-form implementation. Fig.4 shows the general architecture for one stage of the comb , , ..., , redecimation lter. All the sublters, sulting from the polyphase decomposition are operating at the same sampling frequency. One way of reducing the required hardware is to gather all additions from the different sublters into one adder tree. This adder tree is also used in the multipliers to sum all the partial products. In fact, partial products resulting from different multiplications is gathered with the addition operations in the same adder tree. The Wallace tree [8] is an efcient realization of the adder tree. This technique is usually used in the implementation of high speed multipliers [8][9]. Note that, we have only one Wallace tree for the complete polyphase lter. This has signicantly reduced the overall power consumption.

The maximum operating frequency, mated by

IV. F ILTER I MPLEMENTATION

, can also be esti-

that achieves minIn order to nd the decimation factor imum power consumption, several implementations with different values for have been implemented and are presented in the following section.

-1

E -1 (z) M

section III. and with the implementation described in section IV.. Table I lists the number of partial products for all possible decimation factors . Three criteria have been chosen for evaluation: power consumption, area and maximum sampling frequency. Power consumption is estimated using equation (3). A similar equation can be deduced to estimate the area of the circuit. We assume, as in section II., that the hardware required to add the multiplication partial products is dominant. The area, , can then be dened as


B P y y

&

 &

7 '

i py V ( 

z-1

  1
(9) (10)

' (&

1 1

'

1 7

M1

7  ' (7 ' 7 84 I 6

z-1

E 1 (z)

z-1

-1

FOR ALL VALUES OF

 

ORDER

C OMB ).

7 R

'

7 '

$ & UR QP " ' ( $ d' & 1 ' ( 7 1 #'

7 '

7 '

180 160

140

6bit

Power Consumption (W/Hz))

6bit

120 100

Power Consumption

140 120 100 80 60 40

5bit

5bit

4bit

4bit

80
3bit

3bit

60
2bit

2bit

40
1bit

1bit

20 2 6000

4 8 16 First Stage Decimation Factor M1

32

20 2 9

4 8 16 First Stage Decimation Factor M1

32
6bit 5bit

6bit

8 7

5000
5bit 4bit

Area (m )

4000

6 5 4 3 2

4bit

Area

3000 2000 1000 0 2 3.5 3

3bit 2bit 1bit

3bit

2bit 1bit

1 4 8 16 First Stage Decimation Factor M1 32

0 2 2500

4 8 16 First Stage Decimation Factor M1

32

1bit

Maximum Frequency (MHz)

Maximum Frequency

2000

2bit 3bit 4bit 5bit 6bit

2.5 2 1.5 1 0.5 0 2 4 8 16 First Stage Decimation Factor M1

1500

1000
Technology Limit

500

32

0 2

4 8 16 First Stage Decimation Factor M1

32

VI. C ONCLUSION Low-power implementations of a Comb decimation lter for A/D converters have been premono-bit and multi-bit sented. A multi-stage polyphase structure with maximum decimation factor in the rst stage has been used. The proper choice of this rst stage decimation factor can signicantly improve power consumption, area and maximum sampling frequency. In order to nd this optimum rst stage decimation factor, simple equations have been developed to estimate circuit performances of the proposed architecture. Gathering all the partial products additions into one adder tree has also considerably reduced the required hardware for the circuit. R EFERENCES
[1] C.J. Pan. A Stereo Audio Chip Using Approximate Processing for Decimation and Interpolation Filters.. IEEE Journal of Solid-State Circuits, vol. SC-35(No. 1):4555, January 2000. [2] P.C. Maulik, M.S. Chadha, W.L. Lee, and P.J. Crawley. A 16-bit 250kHz Delta-Sigma Modulator and Decimation Filter.. IEEE Journal of Solid-State Circuits, vol. SC-35(No. 4):458467, April 2000.

Fig. 5. Calculation of Polyphase Comb lters performances using equations (3), (9) and (10).

Fig. 6. Simulation results of the Polyphase Comb lters implemented in a technology. [3] Y. Gao, L. Jia, J. Isoaho, and H. Tenhunen. A Comparison Design of Comb Decimators for Sigma-Delta Analog-to-Digital Converters. Analog Integrated Circuits and Signal Processing, vol. 22(No. 1):5160, January 2000. [4] E. B. Hogenauer. An Economical Class of Digital Filters for Decimation and Interpolation. IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-29(No. 2):155162, April 1981. [5] Y. Gao, L. Jia, and H. Tenhunen. Low-Power Implementation of a FifthOrder Comb Decimation Filter for Multi-Standard Transceiver Applications. International Conference on Signal Processing Applications & Technology, ICSPAT, October 1999. [6] S. Chu and C. S. Burrus. Multirate Filter Designs Using Comb Filters. IEEE Transactions on Circuits and Systems, vol. CAS-31:913924, November 1984. [7] M. G. Bellanger, G. Bonnerot, and M. Coudreuse. Digital Filtering by Polyphase Network: Application to sample-Rate Alteration and Filter Banks. IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-24(No. 2):109114, April 1976. [8] J-M. Muller. Elementary Functions, Algorithms and Implementations. Birkhauser Boston, 1997. [9] Y. Dumonteix and H. Mehrez. A Family of Redundant Multipliers Dedicated to Fast Computation For Signal Processing. International Symposium on Circuits & System, ISCAS, May 2000.